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    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>reference design</h1>
    </td>
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# Introduction

AMD-Xilinx has provided various hardware IP overlays to fulfill different hardware architecture and the changing task requirement. 
Please find the IP suits best based on the following tables. 


## Edge IP


<table>
<thead>
  <tr>
    <th width="10%" align="center"><h3><b>IP Name</b></hr></th>
    <th width="5%" align="center"><h3><b>Supported Platforms</b></hr></th>
    <th width="50%" align="center"><h3><b>Description</b></hr></th>
    <th width="30%" align="center"><h3><b>Download Link</b></hr></th>
    <th width="5%" align="center"><h3><b>Product Guide</b></hr></th>
  </tr>
</thead>
<tbody>
  <tr>
    <td align="center">DPUCZDX8G</td>
    <td align="center">MPSoC</td>
    <td align="center">General purpose CNN inference 16nm DPU to support full Vitis AI ModelZoo. DPU core is fully built with FPGA programming logic. Support Vitis flow and Vivado flow on edge devices.</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCZDX8G.tar.gz">Download</a></td>
    <td align="center"><a href="https://docs.xilinx.com/r/en-US/pg338-dpu?tocId=~72l0MosWV8p9MbkDlnw8Q">PG338</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8G</td>
    <td align="center">VCK190</td>
    <td align="center">General purpose CNN inference 7nm DPU for ACAP platform to support full Vitis AI ModelZoo. DPU core is fully built with FPGA AIE cores and programming logic. Support Vitis flow on edge devices.</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8G.tar.gz">Download</a></td>
    <td align="center"><a href="https://docs.xilinx.com/r/en-US/pg389-dpucvdx8g/Introduction">PG389</a></td>
  </tr>
</tbody>
</table>

## Cloud IP

<table>
<thead>
  <tr>
    <th width="10%" align="center"><h3><b>IP Name</b></hr></th>
    <th width="5%" align="center"><h3><b>Supported Platforms</b></hr></th>
    <th width="50%" align="center"><h3><b>Description</b></hr></th>
    <th width="30%" align="center"><h3><b>Download Link</b></hr></th>
    <th width="5%" align="center"><h3><b>Product Guide</b></hr></th>
  </tr>
</thead>
<tbody>
  <tr>
    <td align="center">DPUCAHX8H</td>
    <td align="center">U50/U50lv/U280/U55c</td>
    <td align="center">High throughput CNN inference 16nm DPU. Optimized with high bandwidth memory. DPU core is fully built with FPGA programming logic. Support Xilinx shell integration.</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCAHX8H.tar.gz">Download</a></td>
    <td align="center"><a href="https://docs.xilinx.com/r/en-US/pg367-dpucahx8h">PG367</a></td>
  </tr>
  <tr>
    <td align="center">DPUCADF8H</td>
    <td align="center">U200/U250</td>
    <td align="center">High throughput CNN inference 16nm DPU. Optimized with DDR. DPU core is fully built with FPGA programming logic. Support Xilinx shell integration.</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCAHX8H.tar.gz">Download</a></td>
    <td align="center"><a href="https://docs.xilinx.com/r/en-US/pg400-dpucadf8h">PG400</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8H_2pe_miscdwc</td>
    <td rowspan="5" align="center">VCK5000</td>
    <td rowspan="5" align="center">High throughput CNN inference 7nm DPU for ACAP platform. All computing engines are implemented with FPGA AIE cores.  Support Xilinx shell integration.</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8H_2pe_miscdwc.tar.gz">Download</a></td>
    <td rowspan="5" align="center"><a href="https://docs.xilinx.com/r/en-US/pg403-dpucvdx8h">PG403</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8H_4pe_miscdwc</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8H_4pe_miscdwc.tar.gz">Download</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8H_6pe_misc</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8H_6pe_misc.tar.gz">Download</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8H_6pe_dwc</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8H_6pe_dwc.tar.gz">Download</a></td>
  </tr>
  <tr>
    <td align="center">DPUCVDX8H_8pe_normal</td>
    <td align="center"><a href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCVDX8H_8pe_normal.tar.gz">Download</a></td>
  </tr>
</tbody>
</table>
