0. old reports waiting for ACK =============================================

1. Upcoming release ====================================================

2. Later releases ==========================================================
- librnd4.1 API upgrade:
	- lib_plot/plot_preview.c: LIBRND41 TODOs: e->coord_per_pix is available
		-> see bug_files/TODO/sim.patch
- needs librnd4.2 API upgrade:
	- library window "Use selected" should have a tooltip on what exactly it does (for devmap: returns name only, does not update loclib); API: close buttons can't have tooltips [report: aron]
- TEST+DOC:
	- can load a project file TODO: pool node
		-> export project from GUI
		-> -x with multiple sheet names
		-> -x with project.lht
- FEATURE: font2:
	- check calls to rnd_font_fix_v1(); don't call it if ->height is loaded; maybe not needed at all with font2, multiline is handled in librnd
	- baseline: probably a bad idea, skip it (incompatible with multiline and bbox placement, adds a random offset for term lables)
- FEATURE: BoM template language: concat'd lists:
		- use case: v1.1 should have color and tolerance in the value
		- allow creating new attributes (or rather macros) using the same template
		- create one with: %escape.sym.a.color|% %escape.sym.a.value|% %escape.sym.a.tolerance|%
		- print it as %escape.macro|(unknown)% for the value column
- FEATURE: implement attribute symlinks (see design doc)
	- BUG: altium had a =Device or =Footprint attribute somewhere, that should be a symlink [report: aron]
- FEATURE: arrow key navigation [report: Vuokko]
- FEATURE: symbol meta layer drawing: draw lines from floaters back to their parent?
- FEATURE: io_geda: multiple net= attributes (e.g. in stock 7400) -> should be an array
- FEATURE: librnd svg export upgrade (enum: color, grayscale, b&w): allow svg schematic export with option of monochrome [report: Erich]
- FEATURE: integrity check: wirenet consists of floaters only: list floater object id paths or coords [report: Vuokko]
- FEATURE: DRC (requires query() on the abstract model):
	- noslot or rather uniq attribute (e.g. for resistors)
	- figure if fully overlapping ports (or symbols) can be or should be detected (see: two gnd symbols on top of eachother) [report: Erich]
	- it is easy to accidentally add a footprint to a terminal on a symbol instead of the symbol itself. This is not flagged on netlist export. Should it be harder to do this, or maybe a netlist exporter could indicate if footprints associated with terminals in symbols were not included in the export? [report: Erich]
	- accidentally adding a name to a rail exports a connection in the netlist with no associated component. Perhaps this would benefit from some sort of DRC check, like the "footprint attribute put on non-symbol" issue above. [report: Erich]
	- component pcb pinnum: check if pins are numbered from 1 (or 0) without discontinuities; could catch typos in footprint creation (example: Aron's orange pi zero usb pins on edakrill) [report: aron]
	- move drc/require_graphical_conn check from compiler to DRC, see TODO#rgc
	- DRC dialog in sch_dialogs
	- DRC menu and hotkey
- FEATURE: export of the schematic as a pcb-rnd/tedax subcircuit/footprint for placement on the PCB as a graphical element? For simpler circuits, this would be good for "documentation on the silk layer". [report: Erich]
- BUG: csch_grp_ref_embed(), used in sym loclib paste and right click symbol context menu toref (to loclib) conversion is not undoable [report: Igor2]
- file format version bump cschem-sheet-v2:
	- a connection object should have x;y displacement for the graphical object to be useful (or is it a grp_ref?); at the moment we are not drawing it at all
	- text flag for &entity;
		- implement new text flag/attr for &entity; (similar to dyntext)

3. NLnet ==========================================================
- hierarchic design [3]:
	- figure how to handle aux sheets from library (prefix?)
	- more generally: how to handle files from a different directory
		- BUG: bug_files/TODO/unl; sch-rnd project.lht; file/project/new unlisted; file name "/tmp/new.rs"; new sheet goes into a new, unnamed project [report: aron]
	- doc/usr/07_io/export_spice/pinout.html: look for TODO, verify
- extensions:
	- multiline font: switch over to librnd multiline/alignment rendering
		- implement the halign property (watch out for x mirror: start is always toward the origin)
		- {e T} for multiline edit of single line text; {e t} should also do this if text has \n's
		- propedit should get a button for invoking the same {e T} popup
		- maybe cache whether text is multiline in an unsaved struct field
		- FEATURE: text vertical alignment (add in design doc and code); same rules as in halign [report: Ade]
	- easyeda:
		- sch
		- pcb
		- see work/alien/easyeda/testread:
			- names are from sphash so strcmp can be avoided during dom parse
			- easyeda_low parses the strings after it uses the generic json bridge
	- bxl symbols
		- devmap is probably impossible as slotted symbols are just drawn multiple times, once per slot
		- needs API for multiple symbols from a single file (see pcb-rnd bxl footprint load)
	- eagle xml schematics
	- eagle xml libraries (lbr)
	- high level sim:
		- sim-to-spice compilation:
			- autodetect net type from pin types
			- auto-bridge as needed for mixed mode digital+analog
			- DOC: port type attributes (e.g. analog, ttl), also consider DRC, check coraleda std 2
			- lib_sim: elect network type (default is analog)
			- API? set port attributes for bridges where needed
		- BUG: stance is set temporarily using sch_sim_set_test_bench() for the compilation only but csch_stance_set() prints the permanent setting
		- BUG: womit_no_test_bench is not really implemented, see TODO#womit

4. Low prio ==========================================================
- FEATURE: check feasability: use non-graphical fawk sheet as calculator
	- e.g. voltage divider of R1 and R2 with input and output voltages specified, fawk calculates value for R1 and R2
	- how to query attributes of existing things?
	- how to guarantee the data sheet is compiled after the graphical sheets?
	-> probably better to have this in a "target script"
- BUG: enable multiport_net_merge, then bug_files/multiconn0.rs; move TP2 1k or 2k to the left; more than one connection is created because the vertical ports are overlapping and when the horizontal port is connected, but it figures connections only one by one so it doesn't dare to extend existing connections [report: Igor2]
- BUG: {e t} over a non-dyntext, resize window larger: entry remains small [report: aron]
- FEATURE: view window: open once, single perview widget, copy current zoom+pan, close when parent sheet closed; consider the same for pcb-rnd and camv-rnd [report: Vuokko]
- FEATURE: consider dangling wire end indication (see pool node)
- FEATURE: support for protel format? (.asc, differerent syntax and data model from io_altium) [report: Scott]
- FEATURE: tooltip on toolbar icons should also show the hotkey (librnd?) [report: rudolfii]
- TODO#38: rethink grp-ref-in-grp-ref with child xforms, maybe cache=1 is a bad idea
	- problem: ref1 -> ref2 -> grp -> text; ref2 is floater; if whole ref2 is rotated, we won't update anything in ref1's central xform list
- BUG: wirenet in group should work: load symnet.rs. select terminal and adjacent vertical line using negative selection box; convert selection to symbol. connect test point 1 to wire net. export netlist. do not assume wirenet is directly under the &direct in the tree [report: Erich]
- BUG: back annotation: abstract model: abstract model UUIDs are not implemented, annotation doesn't use them; either figure persistent uuids or use CMRs [report: Igor2]
- BUG: rewrite get_prjname() in dytext render
	- figure the path of the project file
	- project name change runtime (save-as); inalidate text objects (->rtext = NULL using csch_text_dyntext_inval()) to re-render the new name
- OPTIMIZE: do not re-create views multiple times in sch_rnd_prj_conf2prj(): start 'sch-rnd A.rs B.rs' from the same dir [report: Igor2]
- CLEANUP: code dups with pcb-rnd, consider moving some code to src_3rd/rnd_inclib:
	- query
	- propedit
	- undodialog
	- rename csch_ symbols to sch_rnd_ in plugins/
	- act_read
- librnd4.0.0:
	- remove the whole project loading plug io: project files will be handled by librnd
	- once multi is moved over:
		- extend oidpath to generate and accept sheet prefix with $uuid/
		- act_draw should be able to use it as scope
		- act_draw should be able to return oidpath with $uuid/
		- query() should be able to return/convert lists like that for scripting

6. TODO() tags ==========================================================
	- bitmap:     needed for bitmap objects
	- fungw:      may need fungw API change
	- multi:      multiple sheet support
	- hierarchic: needed for hierarchic projects
