digraph g {
	rankdir=LR
	subgraph cluster_0 {
		label="graphical schematics sheet"

		subgraph cluster_01 {
			label="drawing primitives\n(chapter 3)"

			at1 [label="\"bus-segment\":\natoms, e.g. lines"]
			at2 [label="\"wire-segment\":\natoms, e.g. lines"]
			at3 [label="atoms\nand groups"]
			at4 [label="atoms\ne.g. lines"]
			at5 [label="atoms\ne.g. lines"]
			at6 [label="atoms\ne.g. arc, polygon"]
			at7 [label="connection gfx\ne.g. arc, polygon"]

			gr1 [label="group\nrole=bus-net"]
			gr2 [label="group\nrole=wire-net"]
			gr3 [label="group\nrole=symbol"]
			gr4 [label="group\nrole=bus_terminal"]
			gr5 [label="group\nrole=terminal"]
			gr6 [label="group\nrole=hub_point"]

			connection
		}

		subgraph cluster_02 {
			label="concrete model\n(chapter2)"
			symbol
			terminal
			bus_terminal [label="bus-terminal"]
			wire_net [label="wire-net"]
			hub_point [label="hub-point"]
			bus_net [label="bus-net"]
			attribute [label="attribute\nof wire-nets, bus-nets, symbols,\n hubs and terminals" shape=octagon]
		}
	}

	subgraph cluster_1 {
		label="abstract model\n(chapter 2)"

		network [shape=box height=1.875]
		bus [shape=box]
		component [shape=box]
		port [shape=box]
		bus_port  [label="bus-port" shape=box]
		hub [shape=box]
	}

	subgraph cluster_2 {
		label="real world\nexample: PCB"
		bgcolor="#cccccc"
		pcb_component [label="component"]
		pcb_pin [label="pin or pad\nof a\ncomponent"]
		pcb_net [label="copper tracks\ncopper polygons"]
		pcb_pair [label="copper tracks/polygons with\nconstraints (e.g. diff pair)"]
		pcb_hub [label="specific point on copper\nwith geometry constraints\n(e.g. star point gnd)"]
	}

	at1 -> gr1
	at2 -> gr2
	at3 -> gr3
	at4 -> gr4
	at5 -> gr5
	at6 -> gr6
	at7 -> connection [dir=back]

	connection -> wire_net [label="Note 2" weight=20]
	connection -> bus_net [label="Note 2" weight=20]

	gr1 -> bus_net
	gr2 -> wire_net
	gr3 -> symbol
	gr4 -> bus_terminal
	gr5 -> terminal
	gr6 -> hub_point

	symbol -> component
	terminal -> port
	bus_terminal -> bus_port
	wire_net -> network
	bus_net -> bus
	hub_point -> hub
	attribute -> network [label="Note 1" color=blue]

	symbol:e -> attribute:se [constraint=0 color=blue]
	wire_net:e -> attribute:se [constraint=0 color=blue]
	bus_net:e -> attribute:se [constraint=0 color=blue]
	terminal:e -> attribute:se [constraint=0 color=blue]
	bus_terminal:e -> attribute:se [constraint=0 color=blue]

	component -> pcb_component
	port -> pcb_pin
	bus_port -> pcb_pin
	network ->  pcb_net
	bus ->  pcb_net
	bus ->  pcb_pair
	hub -> pcb_net
	hub -> pcb_hub

	bus_port-> pcb_component [style=invis]

}
