diff -ruN linux/drivers/net/sk98lin/flashfun.c linux-new/drivers/net/sk98lin/flashfun.c
--- linux/drivers/net/sk98lin/flashfun.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/flashfun.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1474 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/flashfun.c#5 $
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools
+ * Version:	$Revision: #5 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains FLASH-PROM functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include <stdio.h>
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include "h/flash.h"
+#ifdef MRVL_UEFI
+#include "unistd.h"
+#endif /* MRVL_UEFI */
+
+#if defined MSDOS && !defined DJGPP && !defined DO_PROTO
+#include <dos.h>
+#endif	/* MSDOS && !DJGPP && !DO_PROTO */
+
+/* defines ******************************************************************/
+
+#if defined DJGPP || !defined MSDOS
+#define	FP_OFF(x)	(short *)(&(x))[0]
+#define	FP_SEG(x)	(short *)(&(x))[1]
+
+#define far
+#define huge
+#endif /* DJGPP || !MSDOS */
+
+/*
+ * commands for AMD Am28F010
+ */
+#define	FC_READ			0x00		/* read memory */
+#define FC_AUTO			0x90		/* read auto select */
+#define FC_SETUP_ERASE	0x20		/* setup erase */
+#define FC_ERASE_VERIFY	0xa0		/* erase verify */
+#define FC_SETUP_PROGRAM 0x40		/* setup program */
+#define FC_PRGRAM_VERIFY 0xc0		/* program verify */
+#define FC_RESET		0xff		/* reset state machine */
+
+/*
+ * definitions for Intel 28F001BX-B
+ */
+
+/*
+ * status register definitions
+ */
+#define FP_WSMR			(1<<7)		/* wait state machine */
+#define FP_ES			(1<<6)		/* erase suspended */
+#define FP_EF			(1<<5)		/* erase failure */
+#define FP_PF			(1<<4)		/* program failure */
+#define FP_VPPL			(1<<3)		/* Vpp low detect */
+
+#define FP_CM_ARRAY		0xff		/* read array command */
+#define FP_CM_IDENT		0x90		/* intelligent identifier */
+#define FP_CM_RSTATUS	0x70		/* read status register */
+#define FP_CM_CSTATUS	0x50		/* clear status register */
+#define FP_CM_ERASE		0x20		/* erase setup */
+#define FP_CM_CONFIRM	0xd0		/* erase confirm */
+#define FP_CM_SUSPEND	0xb0		/* erase suspend */
+#define FP_CM_RESUME	0xd0		/* erase resume */
+#define FP_CM_PROGRAM	0x40		/* program setup */
+
+/*
+ * definitions for AMD Am29F010
+ */
+#define F29_5555		0x5555		/* first address */
+#define F29_AA			0xaa		/* first data */
+#define F29_2AAA		0x2aaa		/* 2nd address */
+#define F29_55			0x55		/* 2nd data */
+#define F29_RESET		0xf0		/* read/reset */
+#define F29_SELECT		0x90		/* autoselect */
+#define F29_PROGRAM		0xa0		/* byte program */
+#define F29_ERASE		0x80		/* erase */
+#define F29_CERASE		0x10		/* chip erase */
+#define F29_SERASE		0x30		/* sector erase */
+
+#define	F29_SEC_SIZE	0x4000		/* sector size of the Am29F010 */
+
+#define TIMEOUT_ERASE	200000
+#define TIMEOUT_PROGRAM	30
+
+#define TIMEOUT(IoC, x)	\
+	for (timeout = (x); timeout && !(fl_in(pAC, IoC, 0) & FP_WSMR); timeout--)
+
+extern void bank_select(SK_IOC IoC, long lp);
+extern void vpp_on(SK_AC *pAC, SK_IOC IoC);
+extern void vpp_off(SK_AC *pAC, SK_IOC IoC);
+#if !defined(HASE) && !defined(MRVL_UEFI)
+extern int  spl5();
+extern void splx(int);
+#endif /* !HASE && !MRVL_UEFI */
+
+#ifdef FLASH_ACC_EXT
+
+/*
+ *	define	FLASH_ACC_EXT
+ *
+ *	If this define is set, the user of this module has to write his
+ *	own flash access functions. Those functions must be named:
+ *
+ *	fl_out(SK_AC *pAC, SK_IOC IoC, long a, unsigned char x);
+ *	- Write a byte into the flash without bank select
+ *
+ *	fl_in(SK_AC *pAC, SK_IOC IoC, long a);
+ *	- Read a byte out of the flash without bank selecting
+ *
+ *	fl_set(SK_AC *pAC, SK_IOC IoC, long a, unsigned char x);
+ *	- Write into the flash, but select the bank before
+ *
+ *	fl_get(SK_AC *pAC, SK_IOC IoC, long	a);
+ *	- Read a byte out of the flash, but select the bank before
+ */
+extern unsigned char fl_out(SK_AC *pAC, SK_IOC IoC, long a, unsigned char x);
+extern unsigned char fl_in(SK_AC *pAC, SK_IOC IoC, long a);
+extern unsigned char fl_set(SK_AC *pAC, SK_IOC IoC, long a, unsigned char x);
+extern unsigned char fl_get(SK_AC *pAC, SK_IOC IoC, long a);
+
+#else	/* !FLASH_ACC_EXT */
+
+/*
+ * macros for ROM read/write
+ */
+#define fl_out(pAC, IoC, a, x)	(pAC->spi.fprom[a] = (x))
+#define fl_in(pAC, IoC, a)		(pAC->spi.fprom[a])
+/* fl_get is a static function */
+#define fl_set(pAC, IoC, a, x)	(bank_select(IoC, (a) / pAC->spi.max_faddr), \
+								pAC->spi.fprom[(a) % pAC->spi.max_faddr] = (x))
+
+/*****************************************************************************
+ *
+ * fl_get - Gets a byte out of the flash
+ *
+ * Description:
+ *	This function gets a byte out of the flash.
+ *
+ * Returns:
+ *	byte read out of the flash
+ */
+static unsigned char fl_get(
+SK_AC	*pAC,
+SK_IOC	IoC,
+long	addr)	/* address of the byte */
+{
+	bank_select(IoC, addr / pAC->spi.max_faddr);
+
+	return (pAC->spi.fprom[addr % pAC->spi.max_faddr]);
+}
+
+#endif /* !FLASH_ACC_EXT */
+
+/*
+ * delay macros
+ * WARNING: use braces after IF-statement
+ */
+
+#ifdef	FLASH_DELAY_EXT
+
+/*
+ * In the powerPC firmware environment we cannot use assembler statements
+ */
+#define DELAY6uS()	utl_sleep(6)
+#define DELAY10uS()	utl_sleep(10)
+#define DELAY10mS()	utl_sleep(10000)
+
+#endif	/* FLASH_DELAY_EXT */
+
+#ifdef	MSDOS
+
+extern void fl_print(char *str, ...);
+extern void fl_err(char *str, ...);
+
+#ifndef DJGPP
+
+/*
+ * calibrate extension
+ */
+int	mul_loop_cnt = 1;
+
+#define DELAY6uS()	delay(1,del_6us)
+#define DELAY10uS()	delay(1,del_10us)
+#define DELAY10mS()	delay(del_10ms_out,del_10ms_in)
+
+#else	/* DJGPP */
+
+#define DELAY6uS()	delay(1)
+#define DELAY10uS()	delay(2)
+#define DELAY10mS()	delay(10)
+
+#endif	/* DJGPP */
+
+#endif	/* MSDOS */
+
+#ifdef Core
+
+#define fl_print	pAC->Gui.WPrint
+#define fl_err		pAC->Gui.WPrint
+
+#define DELAY6uS()	SkDgDelayMs(6)
+#define DELAY10uS()	SkDgDelayMs(10)
+#define DELAY10mS()	SkDgDelayMs(10)
+
+#endif	/* Core */
+
+#ifdef VCPU
+
+#define fl_print	c_print
+#define fl_err		c_print
+
+#define DELAY6uS()
+#define DELAY10uS()
+#define DELAY10mS()
+
+#endif	/* VCPU */
+
+#ifdef USE_DGLIB
+
+extern void fl_print(char *msg, ...);
+extern void fl_err(char *msg, ...);
+extern int SkDgDelayMs(unsigned long ms);
+
+#define DELAY6uS()	SkDgDelayMs(6)
+#define DELAY10uS()	SkDgDelayMs(10)
+#define DELAY10mS()	SkDgDelayMs(10)
+
+#endif	/* USE_DGLIB */
+
+#ifdef MRVL_UEFI
+#define DELAY6uS()	usleep(6)
+#define DELAY10uS()	usleep(10)
+#define DELAY10mS()	usleep(10000)
+#define fl_err w_print
+extern void fl_print(char *str, ...);
+#endif /* MRVL_UEFI */
+
+/* typedefs ******************************************************************/
+
+/* global variables **********************************************************/
+
+/* local variables **********************************************************/
+
+/*
+ * command options
+ */
+int	verbose = 0;
+int	wait_for_erase = 0;
+
+#if defined(MSDOS) && !defined(DJGPP)
+/*
+ * timing parameters
+ */
+static unsigned int del_6us;					/* timing constant   6 usec */
+static unsigned int del_10us;					/* timing constant  10 usec */
+static unsigned int del_10ms_out, del_10ms_in;	/* timing constants 10 msec */
+#endif	/* MSDOS && !DJGPP */
+
+static struct {
+	char	*man_name;
+	int		man_code;
+	char	*dev_name;
+	int		dev_code;
+	int		dev_id;
+} dev_table[] = {
+	{ "AMD",		0x01,	"Am29F010",		0x20,	FT_29		},
+	{ "AMD",		0x01,	"Am29LV010B",	0x6e,	FT_29		},
+	{ "AMD",		0x01,	"Am29LV040",	0x4f,	FT_29		},
+	{ "AMD",		0x01,	"Am29F040",		0xa4,	FT_29		},
+	{ "AMD",		0x01,	"Am28F010",		0xa7,	FT_AMD		},
+	{ "Intel",		0x89,	"iN28F010",		0xb4,	FT_AMD		},
+	{ "Intel",		0x89,	"iN28F001BX-T",	0x94,	FT_INTEL	},
+	{ "Intel",		0x89,	"iN28F001BX-B",	0x95,	FT_INTEL	},
+	{ "Catalyst",	0x31,	"CAT28F010",	0xb4,	FT_AMD		},
+	{ "STM",		0x20,	"M29W010B90N1",	0x23,	FT_29		},
+	{ "SST",		0xbf,	"SST39VF010",	0xd5,	FT_29		},
+	{ "Atmel",		0x1f,	"AT49BV001N",	0x05,	FT_29		},
+};
+
+#define MAX_DEVS	(sizeof(dev_table) / sizeof(dev_table[0]))
+
+/* function prototypes *******************************************************/
+
+/* local functions ***********************************************************/
+
+#if defined MSDOS && !defined DJGPP
+
+/*****************************************************************************
+ *
+ * delay - Delay loop in assembler
+ *
+ * Description:
+ *	ASM delay loop for calibration.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void	delay(
+int	outer,	/* outer loop value */
+int	inner)	/* inner loop value */
+{
+	_asm {
+		mov	ax, outer
+		mov	bx, inner
+	oloop:
+		mov	cx, bx
+	iloop:
+		push	ax
+		push	dx
+		push	cx
+
+		mov	cx, mul_loop_cnt
+		cmp	cx, 0
+		jz	ml_end
+	mloop:
+		mul	ax
+		loop	mloop
+	ml_end:
+		pop	cx
+		pop	dx
+		pop	ax
+		loop	iloop
+		dec	ax
+		jne	oloop
+	}
+}
+
+#endif /* MSDOS */
+
+/*****************************************************************************
+ *
+ * apply_vpp - Turns on Vpp and waits
+ *
+ * Description:
+ *	This function turns on Vpp and waits 10 msec
+ *	(capacitor charge time is about 1 msec).
+ *
+ * Returns:
+ *	Nothing
+ */
+static void apply_vpp(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	if (pAC->spi.fl_type == FT_29 ||
+		pAC->spi.fl_type == FT_SPI ||
+		pAC->spi.fl_type == FT_SPI_Y2)
+		return;
+
+	vpp_on(pAC, IoC);
+
+	if (pAC->spi.vpp)
+		return;
+
+	DELAY10mS();
+	pAC->spi.vpp = 1;
+}
+
+/*****************************************************************************
+ *
+ * off_vpp - Turns off Vpp and waits
+ *
+ * Description:
+ *	This function turns off Vpp and wait 3 sec
+ *	(capacitor discharge time is about 2 sec).
+ *
+ * Returns:
+ *	Nothing
+ */
+static void off_vpp(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	int	i;
+
+	if (pAC->spi.fl_type == FT_SPI || pAC->spi.fl_type == FT_SPI_Y2)
+		return;
+
+	bank_select(IoC, 0);
+
+	if (pAC->spi.fl_type == FT_29)
+		return;
+
+	vpp_off(pAC, IoC);
+
+	if (!pAC->spi.vpp)
+		return;
+
+	for (i = 0; i < 300; i++) {
+		DELAY10mS();		/* 3 sec. */
+	}
+	pAC->spi.vpp = 0;
+}
+
+/*****************************************************************************
+ *
+ * amd_flash_erase - Erases AMD-type flashes
+ *
+ * Description:
+ *	This function erases AMD-type flashes.
+ *
+ * Returns:
+ *	0	O.K., chip erased
+ *	1	error occured during erase
+ */
+static int amd_flash_erase(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	long	bank;
+	long	addr;
+	int		x;
+	int		cycles;
+	int		fl;
+
+	fl = spl5();
+
+	/* reset state machine */
+	fl_out(pAC, IoC, 0, FC_RESET);
+	fl_out(pAC, IoC, 0, FC_RESET);
+
+	/* 1st cycle: setup erase */
+	fl_out(pAC, IoC, 0, FC_SETUP_ERASE);
+	/* 2nd cycle: erase */
+	fl_out(pAC, IoC, 0, FC_SETUP_ERASE);
+
+	DELAY10mS();
+
+	/* verify erase */
+	cycles = 1;
+
+	for (bank = 0; bank < pAC->spi.max_pages; bank++) {
+		bank_select(IoC, bank);
+		for (addr = 0; addr < pAC->spi.max_faddr; ) {
+			/* verify erase : address is memory address */
+			fl_out(pAC, IoC, addr, FC_ERASE_VERIFY);
+			DELAY6uS();
+			if ((x = fl_in(pAC, IoC, addr)) != 0xff) {
+				if (cycles++ >= 1000) {
+					fl_out(pAC, IoC, 0, FC_READ);
+					splx(fl);
+					fl_err("E001: erase verify error at address %lx, is %x, "
+						"should be %x\n", bank * pAC->spi.max_faddr + addr, x, 0xff);
+					return (1);
+				}
+				/* 1st cycle: setup erase */
+				fl_out(pAC, IoC, 0, FC_SETUP_ERASE);
+				/* 2nd cycle: erase */
+				fl_out(pAC, IoC, 0, FC_SETUP_ERASE);
+
+				DELAY10mS();
+			}
+			else
+				addr++;
+		}
+	}
+	bank_select(IoC, 0);
+	fl_out(pAC, IoC, 0, FC_READ);
+	pAC->spi.erase_cycles += cycles;
+	splx(fl);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * fprom_erase - Erases a block in the flash
+ *
+ * Description:
+ *	This function erases a block in the flash.
+ *
+ * Returns:
+ *	0	Everything O.K.
+ *	pointer	to error message in case of an error
+ */
+static char *fprom_erase(
+SK_AC	*pAC,
+SK_IOC	IoC,
+long	addr)
+{
+	int	status;
+	long	timeout;
+
+	fl_out(pAC, IoC, addr, FP_CM_ERASE);
+	fl_out(pAC, IoC, addr, FP_CM_CONFIRM);
+	TIMEOUT(IoC, TIMEOUT_ERASE);
+	if (!timeout) {
+		fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+		return ("WSMR ERASE timeout");
+	}
+
+	/* read status */
+	fl_out(pAC, IoC, 0, FP_CM_RSTATUS);
+	status = fl_in(pAC, IoC, 0);
+
+	/* clear status */
+	fl_out(pAC, IoC, 0, FP_CM_CSTATUS);
+	if (status & (FP_EF | FP_VPPL)) {
+		fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+		return ("Failure in Block Erase");
+	}
+
+	fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * intel_flash_erase - Erases Intel-type flashes
+ *
+ * Description:
+ *	This function erases Intel-type flashes.
+ *
+ * Returns:
+ *	0	O.K., flash erased
+ *	1	Error occured in block erase
+ */
+static int intel_flash_erase(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	int		i;
+	char	*error;
+
+	static struct {
+		char	*name;
+		long	start;
+	} blocks[4] = {
+		{ "Boot-Block",			0L		},
+		{ "Parameter Block 1",	0x2000	},
+		{ "Parameter Block 2",	0x3000	},
+		{ "Main Block",			0x3000	},
+	};
+	for (i = 0; i < 4; i++) {
+		bank_select(IoC, blocks[i].start / pAC->spi.max_faddr);
+		error = fprom_erase(pAC, IoC, blocks[i].start % pAC->spi.max_faddr);
+		if (error) {
+			fl_err("error in block erase : %s\n", blocks[i].name);
+			return (1);
+		}
+	}
+
+	bank_select(IoC, 0);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * fl_29 - Sends a command to a type F29 flash
+ *
+ * Description:
+ *	This function sends a command to a type F29 flash.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void	fl_29(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		c)	/* command that shall be sent to the flash */
+{
+	fl_set(pAC, IoC, F29_5555, F29_AA);
+
+	fl_set(pAC, IoC, F29_2AAA, F29_55);
+
+	fl_set(pAC, IoC, F29_5555, (unsigned char)c);
+
+	bank_select(IoC, 0);
+}
+
+/*****************************************************************************
+ *
+ * f29_flash_erase - Erases a type F29 flash
+ *
+ * Description:
+ *	This function erases a type F29 flash. To be sure that only
+ *	the specified sectors are erased, a sector count is computed
+ *	out of pAC->spi.max_pages and pAC->spi.max_faddr
+ *
+ * Returns:
+ *	0	Everything O.K.
+ *	1	Cannot erase the chip
+ */
+static int f29_flash_erase(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	long	timeout;
+	int	i;
+	int	sec_count;
+
+	if (verbose) {
+		fl_print("erase FLASH ");
+	}
+	/* First compute the number of sectors to be erased */
+	/* Note: max_faddr doesn't need to be equal to F29_SEC_SIZE */
+	sec_count = (int) ((pAC->spi.max_pages * pAC->spi.max_faddr / F29_SEC_SIZE) & 0xffff);
+
+	/*
+	 * bug fix: write erase preamble once, than just give
+	 * the sector addresses and the Sector Erase command (MA)
+	 */
+	fl_29(pAC, IoC, F29_ERASE);
+	fl_set(pAC, IoC, F29_5555, F29_AA);
+	fl_set(pAC, IoC, F29_2AAA, F29_55);
+
+	/* Erase all sectors one by one */
+	for (i = 0; i < sec_count; i++) {
+		/* erase concurrently all sectors that are not protected */
+		fl_set(pAC, IoC, (long) i * F29_SEC_SIZE, F29_SERASE);
+	}
+
+	/* The timeout need only be used after the last Sector erase */
+
+	/*
+	 * changed because of timeout problems in Genesis production
+	 *
+	for (timeout = 5000000; timeout && !(fl_in(pAC, IoC, 0) & 0x80); timeout--)
+	 */
+	i = 0;
+	for (timeout = 20000000;;timeout--) {
+		if ((fl_in(pAC, IoC, 0) & 0x80) != 0) {
+			break;
+		}
+		if (timeout == 0) {
+			if (wait_for_erase) {
+				/* restart and wait for unlimited time */
+				timeout = 20000000;
+			}
+			else {
+				break;
+			}
+		}
+		if ((timeout % 100000) == 0) {
+			if (verbose) {
+				fl_print(".");
+			}
+		}
+	}
+	if (!timeout) {
+		fl_err("\nerror in chip erase (timeout)\n");
+		return (1);
+	}
+
+	if (verbose) {
+		fl_print(" finished\n");
+	}
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * flash_erase - Erases flash
+ *
+ * Description:
+ *	This function is the main flash erase routine (called by erase_flash)
+ *	It erases flashes using the appropriate flash erase algorithm.
+ *
+ * Returns:
+ *	error code
+ */
+static int flash_erase(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+#ifdef SK_DIAG
+	int Rtv;
+#endif
+
+	switch (pAC->spi.fl_type) {
+	case FT_AMD:
+		return (amd_flash_erase(pAC, IoC));
+	case FT_INTEL:
+		return (intel_flash_erase(pAC, IoC));
+	case FT_29:
+		return (f29_flash_erase(pAC, IoC));
+	case FT_SPI:
+	case FT_SPI_Y2:
+#ifndef SK_DIAG
+		return (spi_flash_erase(pAC, IoC, 0, (unsigned long)
+			pAC->spi.max_pages * pAC->spi.max_faddr));
+#else	/* SK_DIAG */
+		if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_EX &&
+			pAC->spi.max_faddr == 0x1000) {
+			Rtv = spi_flash_erase(pAC, IoC, 0, SPI_PIG_OFF);
+			if (Rtv == 0 &&
+				(pAC->spi.max_pages * pAC->spi.max_faddr) - SPI_CHIP_SIZE > 0) {
+				return (spi_flash_erase(pAC, IoC, SPI_CHIP_SIZE, (unsigned long)
+					(pAC->spi.max_pages * pAC->spi.max_faddr) - SPI_CHIP_SIZE));
+			}
+			return (Rtv);
+		}
+		else {
+			return (spi_flash_erase(pAC, IoC, 0, (unsigned long)
+				pAC->spi.max_pages * pAC->spi.max_faddr));
+		}
+#endif	/* SK_DIAG */
+		break;
+	}
+	return (1);
+}
+
+/*****************************************************************************
+ *
+ * normal_flash_verify - Verifies the contents of the flash
+ *
+ * Description:
+ *	This function compares the contents of the flash with the Data.
+ *
+ * Returns:
+ *	0	Verify O.K.
+ *	1	Verify error
+ */
+static int normal_flash_verify(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)	/* pointer to the DATA that shall be verified */
+{
+	long	bank;
+	long	addr;
+	int		x;
+	int		byte;
+
+#ifdef	FLASH_VPP_READ
+	/*
+	 * read access to flash
+	 * only with vpp on
+	 */
+	apply_vpp(pAC, IoC);
+
+	DELAY10mS();
+	fl_out(pAC, IoC, 0, FC_RESET);
+	DELAY10mS();
+#endif
+
+	for (bank = 0; bank < pAC->spi.max_pages; bank++) {
+		bank_select(IoC, bank);
+		for (addr = 0; addr < pAC->spi.max_faddr; addr++,data++) {
+			byte = data ? *data : 0;
+			if ((x = fl_in(pAC, IoC, addr)) != byte) {
+				fl_err("*** data verify error at address %lx, is %x, "
+					"should be %x\n", bank * pAC->spi.max_faddr + addr, x, byte);
+#ifdef	FLASH_VPP_READ
+				off_vpp(pAC, IoC);
+#endif
+				return (1);
+			}
+		}
+	}
+	bank_select(IoC, 0);
+
+#ifdef	FLASH_VPP_READ
+	off_vpp(pAC, IoC);
+#endif
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * flash_verify - Verifies flash contents
+ *
+ * Description:
+ *	This function compares the flash contents with the Data.
+ *
+ * Returns:
+ *	0	Verify O.K.
+ *	1	Verify error
+ */
+int	flash_verify(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)
+{
+	if (pAC->spi.fl_type == FT_SPI || pAC->spi.fl_type == FT_SPI_Y2) {
+		return (spi_flash_manage(pAC, IoC, data, 0, (unsigned long)
+			pAC->spi.max_pages * pAC->spi.max_faddr, SPI_VERIFY));
+	}
+
+	return (normal_flash_verify(pAC, IoC, data));
+}
+
+/*****************************************************************************
+ *
+ * fprom_program - Programs a byte
+ *
+ * Description:
+ *	This function programs a byte into a ???-type flash.
+ *
+ * Returns:
+ *	0	byte successfully programmed
+ *	pointer	to error message otherwise
+ */
+static char *fprom_program(
+SK_AC	*pAC,
+SK_IOC	IoC,
+long	addr,	/* address where byte shall be programmed */
+char	data)	/* character to be programmed */
+{
+	int		status;
+	long	timeout;
+
+	fl_out(pAC, IoC, addr, FP_CM_PROGRAM);
+	fl_out(pAC, IoC, addr, data);
+
+	TIMEOUT(IoC, TIMEOUT_PROGRAM);
+
+	if (!timeout) {
+		fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+		return ("WSMR PROGRAM timeout");
+	}
+
+	/* read status */
+	fl_out(pAC, IoC, 0, FP_CM_RSTATUS);
+	status = fl_in(pAC, IoC, 0);
+
+	/* clear status */
+	fl_out(pAC, IoC, 0, FP_CM_CSTATUS);
+	if (status & (FP_PF | FP_VPPL)) {
+		fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+		return ("Failure in Byte Program");
+	}
+	fl_out(pAC, IoC, 0, FP_CM_ARRAY);
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * amd_flash_program - Programs AMD-type flashes
+ *
+ * Description:
+ *	This function programs an AMD-type flash.
+ *	If data == NULL, program all zeros.
+ *
+ * NOTE
+ *	The length is given by pAC->spi.max_pages * pAC->spi.max_faddr.
+ *
+ * Returns:
+ *	0	successfully programmed
+ *	1	error occured
+ */
+static int amd_flash_program(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)	/* pointer to the data that shall be programmed */
+{
+	long	bank;
+	long	addr;
+	int		cycles;
+	int		x;
+	int		byte;
+	int		max;
+	int		retries;
+	int		fl;
+
+	fl = spl5();
+
+	/* reset state machine */
+	fl_out(pAC, IoC, 0, FC_RESET);
+	fl_out(pAC, IoC, 0, FC_RESET);
+
+	/* program and verify loop */
+	cycles = 0;
+	retries = 0;
+	max = 0;
+	for (bank = 0; bank < pAC->spi.max_pages; bank++) {
+		bank_select(IoC, bank);
+		for (addr = 0; addr < pAC->spi.max_faddr; ) {
+			byte = data ? *data : 0;
+			fl_out(pAC, IoC, 0, FC_SETUP_PROGRAM);
+			/* program data: address is memory address */
+			fl_out(pAC, IoC, addr, (char)byte);
+			DELAY10uS();
+			fl_out(pAC, IoC, 0, FC_PRGRAM_VERIFY);
+			DELAY6uS();
+			if ((x = fl_in(pAC, IoC, addr)) != byte) {
+				if (cycles++ >= 25) {
+					fl_out(pAC, IoC, 0, FC_READ);
+					splx(fl);
+					fl_err("*** program verify error at address %lx, is %x, "
+						"should be %x\n", bank * pAC->spi.max_faddr + addr, x, byte);
+					return (1);
+				}
+			}
+			else {
+				addr++;
+				if (data)		/* incr. only if !0 */
+					data++;
+				retries += cycles;
+				if (cycles > max)
+					max = cycles;
+				cycles = 0;
+			}
+		}
+	}
+	bank_select(IoC, 0);
+	fl_out(pAC, IoC, 0, FC_READ);	/* clear command */
+	pAC->spi.prog_retries += retries;
+	if (max > pAC->spi.max_retries)
+		pAC->spi.max_retries = max;
+	splx(fl);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * intel_flash_program - Programs Intel-type flashes
+ *
+ * Description:
+ *	This function programs an Intel-type flash.
+ *
+ * NOTE
+ *	The length is given by pAC->spi.max_pages * pAC->spi.max_faddr.
+ *
+ * Returns:
+ *	0	successfully programmed
+ *	1	error occured
+ */
+static int intel_flash_program(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)	/* pointer to the data that shall be programmed */
+{
+	long	bank;
+	long	addr;
+	char	*error;
+
+	for (bank = 0; bank < pAC->spi.max_pages; bank++) {
+		bank_select(IoC, bank);
+		for (addr = 0; addr < pAC->spi.max_faddr; addr++) {
+			error = fprom_program(pAC, IoC, addr, *data);
+			if (error) {
+				fl_err("*** program verify error at address %lx, is %x, "
+					"should be %x\n", bank * pAC->spi.max_faddr + addr,
+					fl_in(pAC, IoC, addr), *data);
+				return (1);
+			}
+			data++;
+		}
+	}
+	bank_select(IoC, 0);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * f29_program - Programs a byte into F29-type flashes
+ *
+ * Description:
+ *	This function programs a byte into an F29-type flash.
+ *
+ * Returns:
+ *	0	successfully programmed
+ *	pointer	to error message in case of an error
+ */
+static char *f29_program(
+SK_AC			*pAC,
+SK_IOC			IoC,
+long 			a,	/* address where the byte shall be written */
+unsigned char	c)	/* byte that shall be written */
+{
+	long	addr;
+	long	timeout;
+
+	addr	= a % pAC->spi.max_faddr;
+
+	fl_29(pAC, IoC, F29_RESET);
+	fl_29(pAC, IoC, F29_PROGRAM);
+	fl_set(pAC, IoC, a, c);
+	for (timeout = 500000; timeout && (fl_in(pAC, IoC, addr) != c); timeout--)
+		;
+	return (timeout ? 0 : "timeout during byte programming");
+}
+
+/*****************************************************************************
+ *
+ * f29_flash_program - Programs F29-type flashes
+ *
+ * Description:
+ *	This function programs an F29-type flash.
+ *
+ * NOTE
+ *	The length is given by pAC->spi.max_pages * pAC->spi.max_faddr.
+ *
+ * Returns:
+ *	0	successfully programmed
+ *	1	error occured
+ */
+static int f29_flash_program(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)	/* pointer to the data that shall be programmed */
+{
+	long	i;
+	char	*error;
+	long	end;
+
+	end = pAC->spi.max_pages * pAC->spi.max_faddr;
+
+	for (i = 0; i < end; i++) {
+
+		error = f29_program(pAC, IoC, i, *data);
+
+		if (error) {
+			fl_err("*** program verify error at address %lx, is %x, "
+				"should be %x\n", i, fl_in(pAC, IoC,
+				(int) (i % pAC->spi.max_faddr)), *data);
+
+			fl_29(pAC, IoC, F29_RESET);
+			return (1);
+		}
+		data++;
+	}
+	fl_29(pAC, IoC, F29_RESET);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * flash_program - Programs a flash
+ *
+ * Description:
+ *	This function programs an F29-type flash.
+ *	If data == NULL
+ *		If flash type is AMD, program all zeros
+ *		else do nothing.
+ *
+ * NOTE
+ *	The length is given by pAC->spi.max_pages * pAC->spi.max_faddr.
+ *
+ * Returns:
+ *	0	successfully programmed
+ *	1	error occured
+ */
+static int flash_program(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data)	/* pointer to the data that shall be programmed */
+{
+	switch (pAC->spi.fl_type) {
+	case FT_AMD:
+		return (amd_flash_program(pAC, IoC, data));
+	case FT_INTEL:
+		if (data == NULL) {
+			return (0);
+		}
+		return (intel_flash_program(pAC, IoC, data));
+	case FT_29:
+		if (data == NULL) {
+			return (0);
+		}
+		return (f29_flash_program(pAC, IoC, data));
+	case FT_SPI:
+	case FT_SPI_Y2:
+		if (data == NULL) {
+			return (0);
+		}
+		return (spi_flash_manage(pAC, IoC, data, 0, (unsigned long)
+			pAC->spi.max_pages * pAC->spi.max_faddr, SPI_WRITE));
+	}
+	return (1);
+}
+
+/*****************************************************************************
+ *
+ * flash_check_f29 - Checks whether a flash is of type F29
+ *
+ * Description:
+ *	This function checks whether a flash is of type F29.
+ *	If so it sets pAC->spi.fl_type.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void flash_check_f29(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		*pManId,
+int		*pDevId)
+{
+	unsigned	i;
+	int			fl_man;		/* flash manufacturer */
+	int			fl_dev;		/* flash device ID */
+
+	/* set-up for Am29 */
+	fl_29(pAC, IoC, F29_SELECT);
+	fl_man = fl_in(pAC, IoC, 0);	/* read manufacturer code */
+	fl_dev = fl_get(pAC, IoC, 1L);	/* read device code */
+	fl_29(pAC, IoC, F29_RESET);
+
+#ifdef SK_DIAG
+	c_print("\nFLASH found: man=%02X, dev=%02X\n",
+		fl_man, fl_dev);
+#endif /* SK_DIAG */
+
+	for (i = 0; i < MAX_DEVS; i++) {
+		if (dev_table[i].dev_id == FT_29 &&
+			dev_table[i].man_code == fl_man &&
+			dev_table[i].dev_code == fl_dev) {
+
+			pAC->spi.fl_type = FT_29;
+			if (pManId != NULL) {
+				*pManId = fl_man;
+			}
+			if (pDevId != NULL) {
+				*pDevId = fl_dev;
+			}
+			break;
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * flash_man_code - Reads device and manufacturer code from flash
+ *
+ * Description:
+ *	This function reads device and manufacturer code from flash.
+ *
+ * Returns:
+ *	0	Device found and pAC->spi.fl_type set correctly
+ *	1	Device could not be identified or found
+ */
+int	flash_man_code(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned	i;
+	int			fl_man;		/* flash manufacturer */
+	int			fl_dev;		/* flash device ID */
+
+	if (pAC->spi.fl_type == FT_SPI || pAC->spi.fl_type == FT_SPI_Y2) {
+		return (0);
+	}
+
+	/* reset state machine */
+	bank_select(IoC, 0);
+
+	/* check for Am29 */
+	flash_check_f29(pAC, IoC, &fl_man, &fl_dev);
+
+	if (pAC->spi.fl_type != FT_29) {
+
+		apply_vpp(pAC, IoC);
+
+		if (pAC->spi.fl_type != FT_INTEL) {
+			fl_out(pAC, IoC, 0, FC_RESET);
+			fl_out(pAC, IoC, 0, FC_RESET);
+		}
+
+		/* command auto-select */
+		fl_out(pAC, IoC, 0, (char) (pAC->spi.fl_type == FT_INTEL ? FP_CM_IDENT : FC_AUTO));
+		fl_man = fl_in(pAC, IoC, 0);	/* read manufacturer code */
+		fl_dev = fl_get(pAC, IoC, 1L);	/* read device code */
+		/* clear command */
+		fl_out(pAC, IoC, 0, (char) (pAC->spi.fl_type == FT_INTEL ? FP_CM_ARRAY : FC_READ));
+
+		off_vpp(pAC, IoC);
+	}
+
+	for (i = 0; i < MAX_DEVS; i++) {
+		if (fl_man == dev_table[i].man_code &&
+			fl_dev == dev_table[i].dev_code) {
+			break;
+		}
+	}
+
+	if (i == MAX_DEVS) {
+		fl_err("E002: UNKNOWN device: manufacturer '%02X' device '%02X'\n",
+			fl_man, fl_dev);
+		return (1);
+	}
+
+	fl_print("FLASH Device: '%s' (%02X) '%s' (%02X)\n",
+		dev_table[i].man_name, fl_man, dev_table[i].dev_name, fl_dev);
+
+	return (0);
+}
+
+#if defined(MSDOS) && !defined(DJGPP)
+
+/*****************************************************************************
+ *
+ * tsync - Waits for timer to advance
+ *
+ * Description:
+ *	This function waits for the OS timer to advance.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void tsync(
+SK_AC	*pAC)
+{
+	unsigned long	time;
+
+	time = (unsigned long) SkOsGetTime(pAC);
+	while ((unsigned long) SkOsGetTime(pAC) == time)
+		;
+}
+
+#endif	/* MSDOS && !DJGPP */
+
+/*****************************************************************************
+ *
+ * calibrate - Calibrates timing parameters
+ *
+ * Description:
+ *	This function calibrates timing parameters:
+ *		wait 1 clock tick and count loop delay
+ *		calculate nsecs per loop
+ *		calculate delay parameters for 10 usec loop
+ *		verify parameters for 1 second
+ *
+ * Returns:
+ *	0	O.K.
+ *	1	error occured (can't calibrate clock)
+ */
+int calibrate(
+SK_AC	*pAC)
+{
+#if defined(MSDOS) && !defined(DJGPP)
+	unsigned long	start;
+	unsigned long	ns;
+	unsigned		i;
+	unsigned		n;
+	unsigned		us10;
+	unsigned		ticks;
+
+	if (pAC->spi.fl_type == FT_29) {
+		return (0);
+	}
+
+	fl_print("Calibrating Timer ...\n");
+
+	/* try to calibrate 3 times */
+	for (n = 0; n < 3; n++) {
+		tsync(pAC);
+		start = (unsigned long) SkOsGetTime(pAC);
+		for (i = 0; start == (unsigned long) SkOsGetTime(pAC); i++) {
+			delay(1, 1000);
+		}
+		ns = 54945054;		/* 1/18.2 */
+		ns /= i * 1000L;
+		us10 = (unsigned) (20000/ns);	/* 10 min 25 max -> 20 */
+
+		tsync(pAC);
+		start = (unsigned long) SkOsGetTime(pAC);
+		for (i = 0; i < 10; i++) {
+			delay((int) 5000, us10);	/* 100 mS */
+		}
+
+		ticks = (unsigned) ((unsigned long) SkOsGetTime(pAC) - start);
+		if (verbose) {
+			fl_print("us10 = %u, ticks = %u\n",us10,ticks);
+		}
+		if (ticks >= 17 && ticks <= 24) {
+			break;	/* complete calibration successfully */
+		}
+		if (mul_loop_cnt == 0) {
+			break;	/* terminate, calibration impossible */
+		}
+		if (ticks > 24) {
+			mul_loop_cnt = 0;
+		}
+		if (ticks < 17) {
+			mul_loop_cnt += 50;
+		}
+	}
+
+	if (ticks < 17 || ticks > 24) {
+		fl_err("E003: can't calibrate clock, ticks = %u, us10 = %u\n",
+			ticks, us10);
+		return (1);
+	}
+	del_10us = us10;
+	del_6us = (unsigned) (12000 / ns);			/* 6 min no max -> 12 */
+	del_10ms_in = (unsigned) (100000L / ns);	/* 100 uS */
+	del_10ms_out = 100;							/* 100 *100uS = 10mS */
+	DELAY10uS();
+#endif	/* MSDOS && !DJGPP */
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * init_flash - Initializes flash parameter values
+ *
+ * Description:
+ *	This function initializes flash parameter values.
+ *
+ * Returns:
+ *	Nothing
+ */
+void init_flash(
+SK_AC		*pAC,
+SK_IOC		IoC,
+unsigned	rombase,	/* base address of memory access to the flash */
+long		pages,		/* number of pages that can be selected */
+long		faddr)		/* page size (0..faddr-1) are directly */
+						/* addressable in rombase-window */
+{
+	unsigned long flash_size;
+
+#if (defined MSDOS) && (!defined linux)
+	FP_SEG(pAC->spi.fprom) = rombase;
+	FP_OFF(pAC->spi.fprom) = 0;
+#endif /* MSDOS */
+
+	pAC->spi.max_pages = pages;
+	pAC->spi.max_faddr = faddr;
+
+	flash_check_spi(pAC, IoC, &flash_size);
+	if (pAC->spi.fl_type == FT_SPI || pAC->spi.fl_type == FT_SPI_Y2) {
+		return;
+	}
+
+	flash_check_f29(pAC, IoC, NULL, NULL);
+}
+
+/*****************************************************************************
+ *
+ * erase_flash - Erases the whole flash contents
+ *
+ * Description:
+ *	This function erases the whole flash contents.
+ *
+ * Returns:
+ *	0	Flash is successfully erased
+ *	10	Flash cannot be programmed with all zeros before erasing
+ *	11	Flash cannot be erased
+ */
+int	erase_flash(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	apply_vpp(pAC, IoC);
+
+	if (flash_program(pAC, IoC, NULL)) {
+		off_vpp(pAC, IoC);
+		return (10);
+	}
+
+	if (flash_erase(pAC, IoC)) {
+		off_vpp(pAC, IoC);
+		return (11);
+	}
+	off_vpp(pAC, IoC);
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * program_flash - Programs the contents of the flash
+ *
+ * Description:
+ *	This function programs the contents of the flash.
+ *
+ * Returns:
+ *	0	Successfully programmed
+ *	6	Flash cannot be programmed with all zeros
+ *	7	Flash cannot be erased before programming
+ *	8	Flash cannot be programmed
+ */
+int	program_flash(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*prom_data)	/* pointer to the programming area */
+{
+	apply_vpp(pAC, IoC);
+
+	if (flash_program(pAC, IoC, NULL)) {
+		off_vpp(pAC, IoC);
+		return (6);
+	}
+	if (flash_erase(pAC, IoC)) {
+		off_vpp(pAC, IoC);
+		return (7);
+	}
+
+	fl_print("\nStarting FLASH programming ");
+
+	if (flash_program(pAC, IoC, prom_data)) {
+		off_vpp(pAC, IoC);
+		return (8);
+	}
+	off_vpp(pAC, IoC);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * read_from_flash - Reads contents of the flash
+ *
+ * Description:
+ *	This function reads contents of the flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int	read_from_flash(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* pointer to the data buffer */
+unsigned long	offs,	/* start offset to read from */
+unsigned long	size)	/* number of bytes to read */
+{
+	unsigned long	i;
+
+	if (pAC->spi.fl_type == FT_SPI || pAC->spi.fl_type == FT_SPI_Y2) {
+		return (spi_flash_manage(pAC, IoC, data, offs, size, SPI_READ));
+	}
+
+	for (i = offs; i < offs + size; i++) {
+		*data = fl_get(pAC, IoC, i);
+		data++;
+	}
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * bank_protected - Determines whether a particualar sector is protected
+ *
+ * Description:
+ *	This function determines whether a particualar sector is protected.
+ *
+ * Returns:
+ *	0	Unprotected or unknown protection algorithm
+ *	1	Protected sector
+ */
+int	bank_protected(
+SK_AC	*pAC,
+SK_IOC	IoC,
+long	addr)	/* address in the sector to be analyzed */
+{
+	int	protection;
+
+	if (pAC->spi.fl_type != FT_29) {
+		/* unknown detection algorithm for that type */
+		/* -> default: this sector is not protected */
+		return (0);
+	}
+
+	/* Autoselect function */
+	fl_29(pAC, IoC, F29_SELECT);
+
+	protection = fl_get(pAC, IoC, addr / F29_SEC_SIZE * F29_SEC_SIZE + 2L);
+	/* protection now: 00: unprotected, 01: protected sector */
+
+	/* Reset the Flash now! */
+	fl_29(pAC, IoC, F29_RESET);
+
+	return (protection);
+}
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/fwapp.c linux-new/drivers/net/sk98lin/fwapp.c
--- linux/drivers/net/sk98lin/fwapp.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwapp.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,898 @@
+/******************************************************************************
+ *
+ * Name:    fwapp.c
+ * Project: Gigabit Ethernet Adapters, Common Modules
+ * Version: $Revision: #6 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: Embedded SDK firmware application code.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+"$Header: //Release/Yukon_1G/Shared/fw_interface/V1/embedded_sdk/fwapp.c#6 $" ;
+#endif
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/******************************************************************************
+		Local Variables
+******************************************************************************/
+
+/******************************************************************************
+		Global Variables
+******************************************************************************/
+
+/******************************************************************************
+		Local Functions
+******************************************************************************/
+static void   FwRestartCpu(SK_AC *, SK_IOC);
+static void   FwInitRmt(SK_AC *);
+static int    FwFillRmt(SK_AC *, SK_U32, char *, SK_U32);
+#ifdef FW_RMT_VERBOSE_DEBUG
+static void   FwPrintRmt(SK_AC *);
+#endif
+
+/******************************************************************************
+		Global Functions
+******************************************************************************/
+
+extern SK_U32 SendFwCommand(SK_AC *, SK_U32, char *, SK_U32);
+
+/*****************************************************************************
+ *
+ *  @brief This function initializes the FW application
+ *         code at level 0.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @param IoC      IO context handle 
+ *  @return         SK_TRUE or SK_FALSE
+ */
+int FwAppInit0(SK_AC *pAC, SK_IOC IoC)
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit0 ==>\n", SK_DRV_NAME));
+
+	/* Set structure to zero */
+	SK_MEMSET((char *)&(pAC->FwApp), 0, sizeof(SK_FWAPP));
+
+	pAC->FwApp.ActivePort   = 0;
+	pAC->FwApp.DualMode     = SK_GEASF_Y2_SINGLEPORT;
+	pAC->FwApp.OpMode       = SK_GEASF_MODE_UNKNOWN;
+	pAC->FwApp.ChipMode     = SK_GEASF_CHIP_UNKNOWN;
+	pAC->FwApp.InitState    = ASF_INIT_UNDEFINED;
+	pAC->RamAddr = 0;
+	pAC->RamSelect = 0;
+
+	/* Allocate and initialize RMT */
+#ifdef FW_RMT_DEBUG
+	SK_DBG_PRINTF("%s: FwAppInit0: Allocate pAC->FwApp.pRMT\n", SK_DRV_NAME);
+#endif
+	pAC->FwApp.pRMT = (FW_RMT *)FwOsAllocMemory(pAC, sizeof(FW_RMT));
+	if (pAC->FwApp.pRMT == NULL) {
+		SK_DBG_PRINTF("%s: FwAppInit0: Memory allocation error!\n", SK_DRV_NAME);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+			("%s: FwAppInit0 <==\n", SK_DRV_NAME));
+
+		return SK_FALSE;
+	}
+	FwInitRmt(pAC);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit0 <==\n", SK_DRV_NAME));
+
+	return SK_TRUE;
+
+} /* FwAppInit0 */
+
+/*****************************************************************************
+ *
+ *  @brief This function initializes the FW application
+ *         code at level 1.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @param IoC      IO context handle 
+ *  @return         SK_TRUE or SK_FALSE
+ */
+int FwAppInit1(SK_AC *pAC, SK_IOC IoC)
+{
+	int RetCode = SK_TRUE;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit1 ==>\n", SK_DRV_NAME));
+
+	/* Check chip ID and set appropriate flash offsets, */
+	/* operational modes and chip modes depending on Chip ID. */
+	switch (pAC->FwCommon.ChipID) {
+	case CHIP_ID_YUKON_SUPR:
+		pAC->FwApp.ChipMode        = SK_GEASF_CHIP_SU;
+		pAC->FwApp.FlashSize       = ASF_FLASH_SU_SIZE;
+
+		SK_STRNCPY(pAC->FwApp.DriverVersion, FW_API_VERSION, FW_API_VERSION_SIZE);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+			("%s: FwAppInit1: pAC->FwApp.DriverVersion: %s!\n",
+			SK_DRV_NAME, pAC->FwApp.DriverVersion));
+
+		break;
+	default:
+		/* Chip ID does not match! */
+		pAC->FwApp.InitState = ASF_INIT_ERROR_CHIP_ID;
+		printk("%s: FwAppInit1: Chip ID does not match!\n", SK_DRV_NAME);
+
+		RetCode = SK_FALSE;
+		break;
+	}
+
+	if (RetCode != SK_TRUE) {
+		pAC->FwApp.InitState = ASF_INIT_ERROR_CHIP_ID;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+			("%s: FwAppInit1 <==\n", SK_DRV_NAME));
+
+		return RetCode;
+	}
+
+	SetRamAddr(pAC, SK_ST_FIFOTYPE, HOST_READ_QWORD, SK_ST_BUFADDR_HIGH);
+	pAC->FwApp.OpMode = SK_GEASF_MODE_EMBEDDED_SDK;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit1 <==\n", SK_DRV_NAME));
+
+	return RetCode;
+
+} /* FwAppInit1 */
+
+/*****************************************************************************
+ *
+ *  @brief This function initializes the FW application
+ *         code at level 2.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @param IoC      IO context handle 
+ *  @return         SK_TRUE or SK_FALSE
+ */
+int FwAppInit2(SK_AC *pAC, SK_IOC IoC)
+{
+	int RetCode = SK_TRUE;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit2 ==>\n", SK_DRV_NAME));
+
+	/* FW initialization ok */
+	pAC->FwApp.InitState = ASF_INIT_OK;
+
+	/* Check if CPU is running */
+	if (FwCpuState(pAC, IoC) != ASF_CPU_STATE_RUNNING) {
+		SK_DBG_PRINTF("%s: FwAppInit2: CPU is NOT running! Start CPU!\n", SK_DRV_NAME);
+
+		/* If not, start CPU */
+		FwStartCpu(pAC, IoC);
+	}
+	pAC->FwApp.CpuAlive = 1;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppInit2: INIT OK pAC->FwApp.InitState: %d pAC->FwApp.OpMode: %d\n",
+		SK_DRV_NAME, pAC->FwApp.InitState, pAC->FwApp.OpMode));
+
+	/* Otherwise the transmitter and the receiver will be */
+	/* deactivated if we shut down the network interface. */
+	FwAsfEnable(pAC, IoC);
+
+	SK_DBG_PRINTF("%s: Checking Driver <-> FW communication ...", DRV_NAME);
+	if (FwHciSendCommand(pAC, IoC, YASF_HOSTCMD_CHECK_ALIVE, 0, 0, 0, ASF_HCI_WAIT, 0) != HCI_EN_CMD_READY) {
+		SK_DBG_PRINTF(" FAILED!\n");
+		pAC->FwState = SK_FALSE;
+	} else {
+		SK_DBG_PRINTF(" working!\n");
+		pAC->FwState = SK_TRUE;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,("%s: FwAppInit2 <==\n", SK_DRV_NAME));
+
+	return RetCode;
+
+} /* FwAppInit2 */
+
+/*****************************************************************************
+ *
+ *  @brief This function prepares the patches for the FW image.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @param IoC      IO context handle 
+ *  @return         SK_TRUE or SK_FALSE
+ */
+int FwAppPatchImage(SK_AC *pAC, SK_IOC IoC)
+{
+	int RetCode;
+
+	/* Nothing to patch... */
+	pAC->FwCommon.PatchNumber = 0;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppPatchImage: pAC->FwCommon.PatchNumber: %d\n",
+		SK_DRV_NAME, pAC->FwCommon.PatchNumber));
+
+	RetCode = SK_TRUE;
+	return RetCode;
+
+} /* FwAppPatchImage */
+
+/*****************************************************************************
+ *
+ *  @brief This function returns the full pathname
+ *         of the FW image file.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @return         Pointer to full FW file pathname
+ */
+char *FwAppGetImageName(SK_AC *pAC)
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppGetImageName: pAC->FwOs.pFilePathName: %s\n",
+		SK_DRV_NAME, pAC->FwOs.pFilePathName));
+
+	return pAC->FwOs.pFilePathName;
+
+} /* FwAppGetImageName */
+
+/*****************************************************************************
+ *
+ *  @brief This function compares the required FW version
+ *         with the version found in the FW image file.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @return         SK_TRUE or SK_FALSE
+ */
+SK_BOOL FwAppIsVersionOk(SK_AC *pAC)
+{
+	SK_BOOL RetCode = SK_TRUE;
+	int     i;
+
+	/*
+	 * Compare file firmware version with
+	 * required firmware version.
+	 */
+	for (i = 0; i < FW_API_VERSION_SIZE; i++) {
+		if (pAC->FwApp.DriverVersion[i] != pAC->FwCommon.FileVersion[i]) {
+			RetCode = SK_FALSE;
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwAppIsVersionOk: RetCode: %d\n", SK_DRV_NAME, RetCode));
+
+	return RetCode;
+
+} /* FwAppIsVersionOk */
+
+/*****************************************************************************
+*
+* FwMainStateMachine - general ASF  timer
+*
+* Description:
+*
+* Returns:
+*   Always 0
+*/
+void FwMainStateMachine(
+SK_AC  *pAC,	/* Pointer to adapter context */
+SK_IOC IoC)		/* IO context handle */
+{
+	SK_EVPARA EventParam;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+		("%s: FwMainStateMachine() called!\n", SK_DRV_NAME));
+
+	if (pAC->FwApp.GlHciState == 0) { /* idle */
+
+		SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+		SkTimerStart(pAC, IoC, &pAC->FwApp.AsfTimer,
+					1000000, SKGE_ASF, SK_ASF_EVT_TIMER_EXPIRED,
+					EventParam);
+	}
+	else {
+		SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+		SkTimerStart(pAC, IoC, &pAC->FwApp.AsfTimer,
+					30000, SKGE_ASF, SK_ASF_EVT_TIMER_EXPIRED,
+					EventParam);
+	}
+
+	return;
+
+} /* FwMainStateMachine */
+
+/*****************************************************************************
+*
+* FwDriverHello - Hand over control from firmware to driver
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+void FwDriverHello(
+SK_AC  *pAC,	/* Pointer to adapter context */
+SK_IOC IoC)		/* IO context handle */
+{
+	SK_U8   Result;
+	SK_U8   TmpBuffer[4];
+
+	/* Set OS Present Flag in ASF Status and Command Register */
+	FwSetOsPresentBit(pAC, pAC->IoBase);
+
+	TmpBuffer[0] = YASF_HOSTCMD_DRV_HELLO;
+	TmpBuffer[1] = 3; /* Length */
+	TmpBuffer[2] = 0; /* Original handling */
+	TmpBuffer[3] = 0;
+
+	/* Set the FW queue handling values */
+	if (pAC->SdkQH == SK_TRUE) {
+		if (pAC->Suspended)
+			TmpBuffer[2] = 3; /* Suspend/new handling */
+		else
+			TmpBuffer[2] = 1; /* New handling */
+	} else {
+		if (pAC->Suspended)
+			TmpBuffer[2] = 2; /* Suspend */
+	}
+
+	Result = FwHciSendData(pAC, pAC->IoBase, TmpBuffer, 0, ASF_HCI_WAIT, 0);
+	if (Result == HCI_EN_CMD_ERROR) {
+		printk("%s: FwDriverHello: YASF_HOSTCMD_DRV_HELLO NOT in FW!\n",
+			SK_DRV_NAME);
+		pAC->FwState = SK_FALSE;
+	} else {
+		printk("%s: FwDriverHello: YASF_HOSTCMD_DRV_HELLO in FW!\n",
+			SK_DRV_NAME);
+	}
+
+	return;
+
+} /* FwDriverHello */
+
+/*****************************************************************************
+*
+* FwDriverGoodbye - Hand over control from driver to firmware
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+void FwDriverGoodbye(
+SK_AC  *pAC,	/* Pointer to adapter context */
+SK_IOC IoC)		/* IO context handle */
+{
+	SK_U8   Result;
+	SK_U8   TmpBuffer[4];
+
+	/* Reset OS Present Flag in ASF Status and Command Register */
+	FwResetOsPresentBit(pAC, pAC->IoBase);
+
+	/* Inform the FW that the driver will be unloaded */
+	TmpBuffer[0] = YASF_HOSTCMD_DRV_GOODBYE;
+	TmpBuffer[1] = 3; /* Length */
+	TmpBuffer[2] = 0; /* Original handling */
+	TmpBuffer[3] = 0;
+
+	/* Set the FW queue handling values */
+	if (pAC->SdkQH == SK_TRUE) {
+		if (pAC->Suspended)
+			TmpBuffer[2] = 3; /* Suspend/new handling */
+		else
+			TmpBuffer[2] = 1; /* New handling */
+	} else {
+		if (pAC->Suspended)
+			TmpBuffer[2] = 2; /* Suspend */
+	}
+
+	Result = FwHciSendData(pAC, pAC->IoBase, TmpBuffer, 0, ASF_HCI_WAIT, 0);
+	if (Result == HCI_EN_CMD_ERROR) {
+		printk("%s: FwDriverGoodbye: YASF_HOSTCMD_DRV_GOODBYE NOT in FW!\n",
+			SK_DRV_NAME);
+		pAC->FwState = SK_FALSE;
+	} else {
+		printk("%s: FwDriverGoodbye: YASF_HOSTCMD_DRV_GOODBYE in FW!\n",
+			SK_DRV_NAME);
+	}
+
+	return;
+
+} /* FwDriverGoodbye */
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+/*****************************************************************************
+*
+* FwCheckLinkState - Check the link state
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+void FwCheckLinkState(
+SK_AC  *pAC,	/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int    Port,
+SK_U16 *pPhyStat)
+{
+	*pPhyStat = 0x0;
+
+	/* Check link state */
+	GM_IN16(IoC, Port, GM_GP_CTRL, pPhyStat);
+	*pPhyStat &= ~(GM_GPCR_AU_SPD_DIS | GM_GPCR_AU_FCT_DIS | GM_GPCR_AU_DUP_DIS | 
+		GM_GPCR_FC_RX_DIS | GM_GPCR_FL_PASS | GM_GPCR_PART_ENA | 
+		GM_GPCR_LOOP_ENA | BIT_10S | GM_GPCR_FC_TX_DIS | GM_GPCR_RMII_LB_ENA |
+		GM_GPCR_RMII_PH_ENA);
+}
+
+/*****************************************************************************
+*
+* FwCheckLinkMode - Check the firmware link state and link mode
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+void FwCheckLinkMode(
+SK_AC  *pAC,	/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int    Port)
+{
+	SK_U16 PhyStat;
+	SK_U32 PhyCtrl;
+
+	PhyStat = 0x0;
+	PhyCtrl = 0x0;
+
+	pAC->GIni.GIDontInitPhy = SK_FALSE;
+
+	if (pAC->LinkInfo[Port].LinkMaintenance == SK_TRUE) {
+
+		/* Check if link is up */
+		SK_IN32(pAC->IoBase, MR_ADDR(Port, GPHY_CTRL), &PhyCtrl);
+
+		if ((PhyCtrl & GPC_PHY_LINK_UP) == 0) {
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+			printk("FwCheckLinkMode: No link on port %d\n", Port);
+#endif
+			return;
+		}
+		else {
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+			printk("FwCheckLinkMode: Link up on port %d\n", Port);
+#endif
+			/* Check link state */
+			FwCheckLinkState(pAC, pAC->IoBase, Port, &PhyStat);
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+			printk("FwCheckLinkMode: GM_GP_CTRL:  0x%x\n",
+				PhyStat);
+#endif
+			if (pAC->DriverLinkStat != PhyStat) {
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+				printk("FwCheckLinkMode: Link status changed\n");
+				printk("FwCheckLinkMode: pAC->DriverLinkStat:     0x%x\n",
+					pAC->DriverLinkStat);
+#endif
+				return;
+			}
+
+			/* Store link state */
+			pAC->DriverLinkStat = PhyStat;
+
+			/* Enable link maintenance */
+			pAC->GIni.GIDontInitPhy = SK_TRUE;
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+			printk("FwCheckLinkMode: Link match, GIDontInitPhy: %d\n",
+				pAC->GIni.GIDontInitPhy);
+#endif
+		}
+	}
+	else {
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+		printk("FwCheckLinkMode: UseLinkMaintenance not set!\n");
+#endif
+	}
+
+	return;
+
+} /* FwCheckLinkMode */
+#endif
+
+/*****************************************************************************
+*
+* FwRestartCpu - Reset and start firmware CPU
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+static void FwRestartCpu(
+SK_AC	*pAC,	/* Pointer to adapter context */
+SK_IOC	IoC)	/* IO context handle */
+{
+#ifdef FW_RMT_DEBUG
+	SK_BOOL RetCode;
+
+	/* Check CPU state. */
+	RetCode = FwCpuState(pAC, IoC);
+
+	SK_DBG_PRINTF("%s: FwRestartCpu: CPU State: 0x%x\n", DRV_NAME, RetCode);
+#endif
+
+	/* Reset CPU. */
+	SK_DBG_PRINTF("%s: FwRestartCpu: Reset CPU\n", DRV_NAME);
+	FwResetCpu(pAC, IoC);
+
+	/* Start CPU. */
+	SK_DBG_PRINTF("%s: FwRestartCpu: Start CPU\n", DRV_NAME);
+	FwStartCpu(pAC, IoC);
+
+	FwAsfEnable(pAC, IoC);
+	pAC->FwState = SK_TRUE;
+
+	return;
+
+} /* FwRestartCpu */
+
+/*****************************************************************************
+*
+* FwRecoverFirmware - Restart firmware and trigger RMT update
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+void FwRecoverFirmware(
+SK_AC	*pAC,	/* Pointer to adapter context */
+SK_IOC	IoC)	/* IO context handle */
+{
+	if (pAC->FwState == SK_TRUE) {
+		return;
+	}
+
+	FwRestartCpu(pAC, IoC);
+	FwOsSleep(FW_RECOVER_DELAY_VALUE);
+	FwDriverHello(pAC, IoC);
+
+	if (pAC->FwState == SK_TRUE) {
+
+		/* Trigger FW message recovery (RMT). */
+		if (pAC->FwApp.pRMT->RmtFilled == SK_TRUE) {
+			pAC->FwApp.pRMT->RecoverMessageTable = SK_TRUE;
+		}
+	}
+	else {
+		SK_DBG_PRINTF("%s: FwRecoverFirmware: Unable to restart FW\n",
+			DRV_NAME);
+	}
+
+} /* FwRecoverFirmware */
+
+/*****************************************************************************
+*
+* FwHandleRmt - Handle RMT (Recovery Message Table)
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+int FwHandleRmt(
+SK_AC	*pAC,			/* Pointer to adapter context */
+SK_U32	ID,
+char	*pMemBuf,
+SK_U32	Length)
+{
+	if (ID != RMT_MSG_ID_DEFAULT) {
+		if (ID == RMT_MSG_ID_RESET) {
+#ifdef FW_RMT_DEBUG
+			SK_DBG_PRINTF("%s: FwHandleRmt: Receive RMT_MSG_ID_RESET: 0x%x\n",
+				DRV_NAME, ID);
+#endif
+			FwInitRmt(pAC);
+		}
+		else {
+#ifdef FW_RMT_DEBUG
+			SK_DBG_PRINTF("%s: FwHandleRmt: Receive RMT_MSG_ID: 0x%x\n",
+				DRV_NAME, ID);
+#ifdef FW_RMT_VERBOSE_DEBUG
+			PrintDataBuffer("sk98lin: FwHandleRmt",
+				(char *)pMemBuf, Length);
+#endif
+#endif
+			if (FwFillRmt(pAC, ID, (char *)pMemBuf, Length)) {
+#ifdef FW_RMT_DEBUG
+				SK_DBG_PRINTF("%s: FwHandleRmt: ERROR: RMT full.\n",
+					DRV_NAME);
+#endif
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+
+} /* FwHandleRmt */
+
+/*****************************************************************************
+*
+* FwInitRmt - Initialize RMT (Recovery Message Table)
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+static void FwInitRmt(
+SK_AC	*pAC)	/* Pointer to adapter context */
+{
+	int	i;
+
+#ifdef FW_RMT_DEBUG
+	SK_DBG_PRINTF("%s: FwInitRmt: Clear and initialize RMT\n", DRV_NAME);
+#endif
+
+	/* Clear and initialize RMT. */
+	SK_MEMSET((char *)pAC->FwApp.pRMT, 0, sizeof(FW_RMT));
+	pAC->FwApp.pRMT->RmtFilled = SK_FALSE;
+	pAC->FwApp.pRMT->RecoverMessageTable = SK_FALSE;
+	for (i = 0; i < FW_RMT_ARRAY_SIZE; i++) {
+		pAC->FwApp.pRMT->RmtMessage[i].MessageIndex = i;
+	}
+
+} /* FwInitRmt */
+
+/*****************************************************************************
+*
+* FwFillRmt - Fill RMT (Recovery Message Table)
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+int FwFillRmt(
+SK_AC	*pAC,			/* Pointer to adapter context */
+SK_U32	ID,
+char	*pMemBuf,
+SK_U32	Length)
+{
+	SK_BOOL	MessageHandled;
+	int		i;
+
+	/* Check the message length. */
+	if (Length > FW_RMT_MESSAGE_SIZE) {
+
+		SK_DBG_PRINTF("%s: FwFillRmt: WARNING: Message too long. ID: 0x%x not stored\n",
+			DRV_NAME, ID);
+
+		return 1;
+	}
+
+	MessageHandled = SK_FALSE;
+	for (i = 0; i < FW_RMT_ARRAY_SIZE; i++) {
+		if (pAC->FwApp.pRMT->RmtMessage[i].MessageID == ID) {
+#ifdef FW_RMT_DEBUG
+			SK_DBG_PRINTF("%s: FwFillRmt: Index: %d REPLACE ID 0x%x with length 0x%x\n",
+				DRV_NAME, pAC->FwApp.pRMT->RmtMessage[i].MessageIndex,
+				ID, Length);
+#endif
+			/* Replace message. */
+			SK_MEMSET((char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+				0, FW_RMT_MESSAGE_SIZE);
+			SK_MEMCPY((char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+				(char *)pMemBuf, Length);
+			pAC->FwApp.pRMT->RmtMessage[i].MessageLength = Length;
+			pAC->FwApp.pRMT->RmtFilled = SK_TRUE;
+			MessageHandled = SK_TRUE;
+			break;
+		}
+	}
+
+	/* If MessageHandled is FALSE, the message was not replaced. */
+	if (MessageHandled == SK_FALSE) {
+		for (i = 0; i < FW_RMT_ARRAY_SIZE; i++) {
+			if (pAC->FwApp.pRMT->RmtMessage[i].MessageID == RMT_MSG_ID_DEFAULT) {
+#ifdef FW_RMT_DEBUG
+				SK_DBG_PRINTF("%s: FwFillRmt: Index: %d STORE ID 0x%x with length 0x%x\n",
+					DRV_NAME, pAC->FwApp.pRMT->RmtMessage[i].MessageIndex,
+					ID, Length);
+#endif
+				/* Store message. */
+				pAC->FwApp.pRMT->RmtMessage[i].MessageID = ID;
+				SK_MEMSET((char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+					0, FW_RMT_MESSAGE_SIZE);
+				SK_MEMCPY((char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+					(char *)pMemBuf, Length);
+				pAC->FwApp.pRMT->RmtMessage[i].MessageLength = Length;
+				pAC->FwApp.pRMT->RmtFilled = SK_TRUE;
+				MessageHandled = SK_TRUE;
+				break;
+			}
+		}
+	}
+
+#ifdef FW_RMT_VERBOSE_DEBUG
+	FwPrintRmt(pAC);
+#endif
+
+	/* If MessageHandled is FALSE, the RMT is full. */
+	if (MessageHandled == SK_FALSE) {
+
+		SK_DBG_PRINTF("%s: FwFillRmt: ERROR: RMT full. ID: 0x%x not stored\n",
+			DRV_NAME, ID);
+
+		return 1;
+	}
+
+	return 0;
+
+} /* FwFillRmt */
+
+/*****************************************************************************
+*
+* FwWriteRmt - Write RMT (Recovery Message Table) to firmware
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+int FwWriteRmt(
+SK_AC	*pAC)	/* Pointer to adapter context */
+{
+	int			i;
+	int			RetCode = 1;
+	SK_U8		RdTry = FW_MAX_READTRY;
+	FwCmdResult	*FwCommandResult;
+
+	if (pAC->FwApp.pRMT->RecoverMessageTable == SK_FALSE) {
+#ifdef FW_RMT_DEBUG
+		SK_DBG_PRINTF("%s: FwWriteRmt: No need to write RMT\n", DRV_NAME);
+#endif
+		return RetCode;
+	}
+
+	if (pAC->FwApp.pRMT->RmtFilled == SK_FALSE) {
+		SK_DBG_PRINTF("%s: FwWriteRmt: RMT empty\n", DRV_NAME);
+		pAC->FwApp.pRMT->RecoverMessageTable = SK_FALSE;
+		return RetCode;
+	}
+
+	SK_DBG_PRINTF("%s: FwWriteRmt: Write RMT to FW START\n", DRV_NAME);
+
+	for (i = 0; i < FW_RMT_ARRAY_SIZE; i++) {
+		if (pAC->FwApp.pRMT->RmtMessage[i].MessageID != RMT_MSG_ID_DEFAULT) {
+#ifdef FW_RMT_DEBUG
+			SK_DBG_PRINTF("%s: FwWriteRmt: Write MessageIndex %d to FW\n",
+				DRV_NAME,
+				pAC->FwApp.pRMT->RmtMessage[i].MessageIndex);
+#endif
+			SendFwCommand(pAC, SKGE_DGRAM_MSG2FW,
+				(char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+				pAC->FwApp.pRMT->RmtMessage[i].MessageLength);
+
+			/* Try to read the result. */
+			RetCode = 2;
+			for (RdTry = 0; RdTry < FW_MAX_READTRY; RdTry++) {
+
+				/* Wait for result. */
+				FwOsSleep(FW_READ_DELAY_VALUE);
+
+				/* Check if we have a result. */
+				if ((pAC->pFwBuffer) && (pAC->FwBufferLen)) {
+					FwCommandResult = (FwCmdResult *)pAC->FwApp.pRMT->RmtMessage[i].Message;
+#ifdef FW_RMT_DEBUG
+					SK_DBG_PRINTF("%s: FwWriteRmt: Result in loop %d for MessageIndex %d: 0x%x\n",
+						DRV_NAME, RdTry,
+						pAC->FwApp.pRMT->RmtMessage[i].MessageIndex,
+						FwCommandResult->Result);
+#ifdef FW_RMT_VERBOSE_DEBUG
+					PrintDataBuffer("sk98lin: FwWriteRmt",
+						(char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+						pAC->FwApp.pRMT->RmtMessage[i].MessageLength);
+#endif
+#endif
+					if (FwCommandResult->Result != FW_RESULT_OK) {
+
+						SK_DBG_PRINTF("%s: FwWriteRmt: ERROR: RMT ID 0x%x"
+							" at INDEX %d with result 0x%x from FW\n",
+							DRV_NAME,
+							pAC->FwApp.pRMT->RmtMessage[i].MessageID,
+							pAC->FwApp.pRMT->RmtMessage[i].MessageIndex,
+							FwCommandResult->Result);
+
+						RetCode = 0;
+					}
+					else {
+						RetCode = 1;
+					}
+					pAC->FwBufferLen = 0;
+					FwOsFreeMemory(pAC, (SK_U8 *)pAC->pFwBuffer);
+					pAC->pFwBuffer = NULL;
+					break;
+				}
+			}
+
+			/* ERROR: No result after 200 milliseconds. */
+			if (RetCode == 2) {
+				SK_DBG_PRINTF("%s: FwWriteRmt: ERROR: RMT ID 0x%x"
+					" at INDEX %d without result from FW\n",
+					DRV_NAME,
+					pAC->FwApp.pRMT->RmtMessage[i].MessageID,
+					pAC->FwApp.pRMT->RmtMessage[i].MessageIndex);
+				pAC->FwApp.pRMT->RecoverMessageTable = SK_TRUE;
+				return RetCode;
+			}
+			else if (RetCode == 0) {
+				pAC->FwApp.pRMT->RecoverMessageTable = SK_TRUE;
+				return RetCode;
+			}
+		}
+	}
+
+	/* Recovery successful, set RecoverMessageTable to false. */
+	pAC->FwApp.pRMT->RecoverMessageTable = SK_FALSE;
+
+	SK_DBG_PRINTF("%s: FwWriteRmt: Write RMT to FW END\n", DRV_NAME);
+
+	return RetCode;
+
+} /* FwWriteRmt */
+
+#ifdef FW_RMT_VERBOSE_DEBUG
+/*****************************************************************************
+*
+* FwPrintRmt - Print RMT (Recovery Message Table) to console
+*
+* Description:
+*
+* Returns:
+*   Nothing
+*/
+static void FwPrintRmt(
+SK_AC	*pAC)	/* Pointer to adapter context */
+{
+	int	i;
+
+	SK_DBG_PRINTF("\n%s: FwPrintRmt: Print RMT START\n\n", DRV_NAME);
+
+	for (i = 0; i < FW_RMT_ARRAY_SIZE; i++) {
+		if (pAC->FwApp.pRMT->RmtMessage[i].MessageID != RMT_MSG_ID_DEFAULT) {
+			SK_DBG_PRINTF("%s: FwPrintRmt: MessageIndex:  %d\n",
+				DRV_NAME, pAC->FwApp.pRMT->RmtMessage[i].MessageIndex);
+			SK_DBG_PRINTF("%s: FwPrintRmt: MessageID:     0x%x\n",
+				DRV_NAME, pAC->FwApp.pRMT->RmtMessage[i].MessageID);
+			SK_DBG_PRINTF("%s: FwPrintRmt: MessageLength: 0x%x\n",
+				DRV_NAME, pAC->FwApp.pRMT->RmtMessage[i].MessageLength);
+			PrintDataBuffer("sk98lin: FwPrintRmt",
+				(char *)pAC->FwApp.pRMT->RmtMessage[i].Message,
+				pAC->FwApp.pRMT->RmtMessage[i].MessageLength);
+		}
+	}
+
+	SK_DBG_PRINTF("%s: FwPrintRmt: Print RMT END\n\n", DRV_NAME);
+
+} /* FwInitRmt */
+#endif
+
diff -ruN linux/drivers/net/sk98lin/fwfunctions.c linux-new/drivers/net/sk98lin/fwfunctions.c
--- linux/drivers/net/sk98lin/fwfunctions.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwfunctions.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Name:        fwfunctions.c
+ * Project:     Yukon/Yukon2, PCI Gigabit Ethernet Adapter
+ * Purpose:     All functions regarding firmware handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	    (C)Copyright 1998-2002 SysKonnect GmbH.
+ *	    (C)Copyright 2002-2011 Marvell.
+ *
+ *	    Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	    Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include "h/skversion.h"
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+extern SK_U32 SendFwCommand (SK_AC *pAC, SK_U32 DatagramType, char *pFwDataBuff, SK_U32 FrameLength);
+unsigned int inet_addr(char *str);
+
+/******************************************************************************
+ *
+ *	SetFwIpAddr() - set the Firmware IP address
+ *
+ * Description:
+ *	Set the Firmware IP address.
+ *
+ * Returns:
+ *	nothing
+ */
+int SetFwIpAddr(
+	SK_AC	*pAC,			/* Adapter context */
+	SK_U32	InetAddress,	/* IPv4 address */
+	SK_U32	InetNetmask,	/* IPv4 netmask */
+	SK_U32	InetGateway)	/* IPv4 gateway */
+{
+
+	SK_U16					DatagramLength;
+	CmdSetIpv4Config		Ipv4ConfigDatagram;
+	char					*pMsgBuff = NULL;   /* Message buffer */
+	printk("Set IP: 0x%x\n", InetAddress);
+	printk("Set NM: 0x%x\n", InetNetmask);
+
+	/* Check tha data */
+	if (InetAddress == 0) {
+		printk("%s: SetFwIpAddr  No IPv4 address given!\n", DRV_NAME);
+		return (-1);
+	}
+	else if (InetNetmask == 0) {
+		printk("%s: SetFwIpAddr  No IPv4 netmask given!\n", DRV_NAME);
+		return (-1);
+	}
+	else if (InetGateway == 0) {
+		printk("%s: SetFwIpAddr  No IPv4 gateway given!\n", DRV_NAME);
+		return (-1);
+	}
+
+	/* Allocate internal message buffer */
+	DatagramLength = sizeof(Ipv4ConfigDatagram);
+	pMsgBuff = kmalloc(DatagramLength, GFP_KERNEL);
+
+	if (pMsgBuff == NULL) {
+		printk("%s: SetFwIpAddr  Memory allocation failed!\n", DRV_NAME);
+		return (-1);
+	}
+	memset(pMsgBuff, 0, DatagramLength);
+
+	/* ENDIANESS */
+	Ipv4ConfigDatagram.Hdr.Cmd = FW_CMD_SET_IPV4_CONFIG;
+	Ipv4ConfigDatagram.Hdr.Len = FW_CMD_SET_IPV4_CONFIG_LENGTH;
+	Ipv4ConfigDatagram.Ip = InetAddress;
+	Ipv4ConfigDatagram.Mask = InetNetmask;
+	Ipv4ConfigDatagram.Gateway = InetGateway;
+
+	memcpy(pMsgBuff, &Ipv4ConfigDatagram, DatagramLength);
+
+
+	/* SEND */
+	SendFwCommand(pAC, SKGE_DGRAM_MSG2FW, pMsgBuff, FW_CMD_SET_IPV4_CONFIG_LENGTH);
+
+	/* Free internal message buffer */
+	if (pMsgBuff != NULL) {
+		kfree(pMsgBuff);
+	}
+	return 0;
+}
+
+
+/* Helper functions */
+unsigned int inet_addr(char *str)
+{
+	int a,b,c,d;
+	char arr[4];
+	sscanf(str,"%d.%d.%d.%d",&a,&b,&c,&d);
+	arr[3] = a; arr[2] = b; arr[1] = c; arr[0] = d;
+	return *(unsigned int*)arr;
+}
+#endif
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/fwhci.c linux-new/drivers/net/sk98lin/fwhci.c
--- linux/drivers/net/sk98lin/fwhci.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwhci.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,906 @@
+/******************************************************************************
+ *
+ * Name:    fwhci.c
+ * Project: fwcommon
+ * Version: $Revision: #5 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware host communication interface
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+void FwHciStateMachine(
+	SK_AC  *pAC,
+	SK_IOC IoC,
+	SK_U8  ToEna);
+
+static SK_U8 FwHciSendMessage(
+	SK_AC  *pAC,
+	SK_IOC IoC,
+	SK_U8  *message,
+	SK_U8  length,
+	SK_U8  ExpectResponse,
+	SK_U8  Wait);
+
+#ifdef DASH_APP
+/******************************************************************************
+ *
+ *	Converting functions for HCI communication (network byte order)
+ *
+ * Description:
+ *
+ *  static SK_U16 FwfRaw16ToPlain16(SK_U8 *data)
+ *  static void FwPlain16ToRaw16(SK_U16 val, SK_U8 *data)
+ *  static SK_U32 FwRaw32ToPlain32(SK_U8 *data)
+ *  static void FwPlain32ToRaw32(SK_U32 val, SK_U8 *data)
+ *  static SK_U64 FwfRaw64ToPlain64(SK_U8 *data)
+ *  static void FwPlain64ToRaw64(SK_U64 val, SK_U8 *data) 
+ *
+ * Returns:
+ *
+ */
+
+static SK_U16 FwRaw16ToPlain16(SK_U8 *data)
+{
+	SK_U16 TmpVal16 = 0x0000;	
+	TmpVal16  = ((SK_U16) *(data+0) << 8);
+	TmpVal16 |= ((SK_U16) *(data+1) << 0);
+	return NTOHS(TmpVal16);
+}
+
+static void FwPlain16ToRaw16(SK_U16 val, SK_U8 *data)
+{
+	SK_U16 TmpVal = NTOHS(val);	
+	*(data++) = (SK_U8) ((TmpVal >>  8) & 0xFF);
+	*(data++) = (SK_U8) ((TmpVal >>  0) & 0xFF);
+}
+
+static SK_U32 FwRaw32ToPlain32(SK_U8 *data)
+{
+	SK_U32 TmpVal32 = 0x00000000;
+	TmpVal32  = ((SK_U32) *(data+0) << 24);
+	TmpVal32 |= ((SK_U32) *(data+1) << 16);
+	TmpVal32 |= ((SK_U32) *(data+2) << 8);
+	TmpVal32 |= ((SK_U32) *(data+3) << 0);
+	return NTOHL(TmpVal32);
+}
+
+static void FwPlain32ToRaw32(SK_U32 val, SK_U8 *data)
+{
+	SK_U32 TmpVal = NTOHL(val);
+	*(data++) = (SK_U8) ((TmpVal >> 24) & 0xFF);
+	*(data++) = (SK_U8) ((TmpVal >> 16) & 0xFF);
+	*(data++) = (SK_U8) ((TmpVal >>  8) & 0xFF);
+	*(data++) = (SK_U8) ((TmpVal >>  0) & 0xFF);
+}
+
+static SK_U64 FwRaw64ToPlain64(SK_U8 *data)
+{
+	SK_U64 TmpVal64 = 0;
+#ifdef SK_LITTLE_ENDIAN
+	TmpVal64  = ((SK_U64) *(data+7) << 56);
+	TmpVal64 |= ((SK_U64) *(data+6) << 48);
+	TmpVal64 |= ((SK_U64) *(data+5) << 40);
+	TmpVal64 |= ((SK_U64) *(data+4) << 32);
+	TmpVal64 |= ((SK_U64) *(data+3) << 24);
+	TmpVal64 |= ((SK_U64) *(data+2) << 16);
+	TmpVal64 |= ((SK_U64) *(data+1) << 8);
+	TmpVal64 |= ((SK_U64) *(data+0) << 0);
+#else
+	TmpVal64  = ((SK_U64) *(data+0) << 56);
+	TmpVal64 |= ((SK_U64) *(data+1) << 48);
+	TmpVal64 |= ((SK_U64) *(data+2) << 40);
+	TmpVal64 |= ((SK_U64) *(data+3) << 32);
+	TmpVal64 |= ((SK_U64) *(data+4) << 24);
+	TmpVal64 |= ((SK_U64) *(data+5) << 16);
+	TmpVal64 |= ((SK_U64) *(data+6) << 8);
+	TmpVal64 |= ((SK_U64) *(data+7) << 0);
+#endif	
+	return TmpVal64;
+}
+
+static void FwPlain64ToRaw64(SK_U64 val, SK_U8 *data)
+{
+#ifdef SK_LITTLE_ENDIAN
+	*(data+0) = (SK_U8) ((val >> 56) & 0xFF);
+	*(data+1) = (SK_U8) ((val >> 48) & 0xFF);
+	*(data+2) = (SK_U8) ((val >> 40) & 0xFF);
+	*(data+3) = (SK_U8) ((val >> 32) & 0xFF);
+	*(data+4) = (SK_U8) ((val >> 24) & 0xFF);
+	*(data+5) = (SK_U8) ((val >> 16) & 0xFF);
+	*(data+6) = (SK_U8) ((val >>  8) & 0xFF);
+	*(data+7) = (SK_U8) ((val >>  0) & 0xFF);
+#else
+	*(data+7) = (SK_U8) ((val >> 56) & 0xFF);
+	*(data+6) = (SK_U8) ((val >> 48) & 0xFF);
+	*(data+5) = (SK_U8) ((val >> 40) & 0xFF);
+	*(data+4) = (SK_U8) ((val >> 32) & 0xFF);
+	*(data+3) = (SK_U8) ((val >> 24) & 0xFF);
+	*(data+2) = (SK_U8) ((val >> 16) & 0xFF);
+	*(data+1) = (SK_U8) ((val >>  8) & 0xFF);
+	*(data+0) = (SK_U8) ((val >>  0) & 0xFF);
+#endif	
+}
+
+static void FwPrintIpData(
+	SK_AC   *pAC,
+	SK_U32	Modules,
+	SK_U32	Categories)  {
+	SK_U16 i;
+	TAsfDashIpInfoExt *IpConfig	=  &pAC->FwApp.Mib.IpInfoExt;
+
+	SK_DBG_MSG(pAC, Modules, Categories, ("\nIP Configuration\n"));
+	for( i=0; i<IpConfig->NumIpAddresses; i++  )  {
+		if( i < ASF_DASH_IP_INFO_NUM_IPADDR )  {
+			SK_DBG_MSG(pAC, Modules, Categories, ("  IP %d       Addr:0x%x Mask:0x%x\n", 
+					i+1, IpConfig->IpAddress[i].Address, IpConfig->IpAddress[i].SubnetMask));
+		}
+	}
+	
+	for( i=0; i<IpConfig->NumIpGateways; i++  )  {
+		if( i < ASF_DASH_IP_INFO_NUM_IPADDR )  {
+			SK_DBG_MSG(pAC, Modules, Categories, ("  Gateway %d: 0x%x\n", 
+					i+1, IpConfig->IpGateway[i] ));
+		}
+	}
+
+	SK_DBG_MSG(pAC, Modules, Categories,         ("  DHCP Server %d: 0x%x\n", 
+					i+1, IpConfig->DhcpServer ));
+}
+#endif /*DASH_APP*/
+
+/*****************************************************************************
+*
+* FwHciGetData
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciGetData(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_U8 **pHciRecBuf ) {
+
+	*pHciRecBuf = pAC->FwCommon.Hci.ReceiveBuf;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("FwHciGetData\n"));
+	SK_DBG_DMP(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, pAC->FwCommon.Hci.ReceiveBuf, pAC->FwCommon.Hci.ReceiveBuf[1] );
+	return( 1 );
+}
+
+/*****************************************************************************
+*
+* FwHciGetState
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciGetState(
+	SK_AC *pAC) {  /* Pointer to adapter context */
+
+	SK_U8	Stat;
+	SK_U64	DiffTime;
+
+	Stat = pAC->FwCommon.Hci.Status;
+	if ( Stat == HCI_EN_CMD_READY ) {
+
+		pAC->FwCommon.Hci.Status = HCI_EN_CMD_IDLE;
+		DiffTime = SkOsGetTime(pAC) - pAC->FwCommon.Hci.Time;
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    *** Ready -> Cycles:%d Time:%lums\n",
+													   pAC->FwCommon.Hci.Cycles, DiffTime / (10*1000) ));
+	}
+	if ( Stat == HCI_EN_CMD_ERROR ) {
+		DiffTime = SkOsGetTime(pAC) - pAC->FwCommon.Hci.Time;
+
+		pAC->FwCommon.Hci.To = 0;		
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    *** Error -> Cycles:%d Time:%lums\n",
+													   pAC->FwCommon.Hci.Cycles, DiffTime / (10*1000) ));
+	}
+	return( Stat );
+}
+
+/*****************************************************************************
+*
+* FwHciFinishCommand
+*
+* Description:
+*	Waits some time if the current command finishes.
+*
+* Returns:
+*
+*/
+SK_U8 FwHciFinishCommand(
+	SK_AC *pAC,    /* Pointer to adapter context */
+	SK_IOC IoC) {  /* IO context */
+	
+	SK_U64  StartTime;
+	SK_U64  CurrTime;
+	SK_U64  TmpTime;
+	SK_U8   RetCode;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwHciFinishCommand\n"));
+	StartTime = SkOsGetTime(pAC);
+	TmpTime = StartTime + ASF_HCI_WAIT_TICKS;
+
+	do {
+		CurrTime = SkOsGetTime(pAC);
+
+		/* mlindner: Fix for a MVista timer problem */
+		/* if ( CurrTime > TmpTime ) { */
+
+			FwHciStateMachine( pAC, IoC, 0 );
+			TmpTime = CurrTime + ASF_HCI_WAIT_TICKS;
+		/* } */
+		RetCode = FwHciGetState( pAC );
+		if ( (CurrTime - StartTime) > (SK_TICKS_PER_SEC*5) ) {
+
+			RetCode = HCI_EN_CMD_ERROR;
+			break;
+		}
+	} while( (RetCode != HCI_EN_CMD_READY) && (RetCode != HCI_EN_CMD_ERROR) );
+
+	if ( (RetCode != HCI_EN_CMD_READY) ) {
+
+		pAC->FwCommon.Hci.Status = HCI_EN_CMD_IDLE;
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Command not confirmed RetCode:0x%x\n", RetCode ));
+	}
+
+	return( RetCode );
+}
+
+/*****************************************************************************
+*
+* FwHciSendMessage
+*
+* Description:
+*
+* Returns:
+*
+*/
+static SK_U8 FwHciSendMessage(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context */
+	SK_U8  *message,
+	SK_U8  length,
+	SK_U8  ExpectResponse,
+	SK_U8  Wait ) {
+
+	SK_U8 RetCode;
+	SK_U8 i;
+
+	RetCode = 0;
+
+	if ( length > ASF_HCI_TRA_BUF_SIZE ) {
+
+		return( RetCode );
+	}
+
+	if ( pAC->FwCommon.Hci.Status == HCI_EN_CMD_IDLE ) {
+
+		/*  SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Send Message\n" )); */
+
+		SK_OUT32( IoC, ASF_HCI_CMDREG, (SK_U32) 0 );
+		SK_OUT32( IoC, ASF_HCI_DATAREG, (SK_U32) 0 );
+
+		for( i=0; i<length; i++ ) {
+			pAC->FwCommon.Hci.TransmitBuf[i] = message[i];
+		}
+		pAC->FwCommon.Hci.SendLength = length;
+		if( ExpectResponse ) {
+			pAC->FwCommon.Hci.ExpectResponse = 1;
+		}
+		else {
+			pAC->FwCommon.Hci.ExpectResponse = 0;
+		}
+		pAC->FwCommon.Hci.Status = HCI_EN_CMD_WRITING;
+		pAC->FwCommon.Hci.OldCmdReg = 0;
+		pAC->FwCommon.Hci.SendIndex = 0;
+		pAC->FwCommon.Hci.Cycles = 0;
+		pAC->FwCommon.Hci.To = 0;
+		pAC->FwCommon.Hci.Time = SkOsGetTime( pAC );
+		RetCode = 1;  /*  successfull */
+	}
+	else {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Send Message -> Not Idle\n" ));
+	}
+
+	if ( !Wait ) {
+
+		/*  SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Send Message -> Start Timer\n" )); */
+		/*SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+		SkTimerStart(pAC, IoC, &pAC->FwCommon.Hci.AsfTimerHci,
+					 10000, SKGE_ASF, SK_ASF_EVT_TIMER_HCI_EXPIRED,
+					 EventParam);*/
+
+		/* Start state machine immediatetly (dr)*/
+		FwHciStateMachine(pAC, IoC, 1);
+	}
+	else {
+		/* Added (ts) */
+		FwHciStateMachine(pAC, IoC, 0);
+	}
+	return( RetCode );
+}
+
+#ifdef DASH_APP
+/*****************************************************************************
+*
+* FwfHciPrepareMessage
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciPrepareMessage(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_U8  Cmd,
+	SK_U8  *pBuf,
+	SK_U8  BufLen ) {
+	SK_U8  *pBufTmp;
+	SK_U16 i;
+	SK_U8  CalcLen = 0;
+	SK_U8  Len = 0;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+		("FwHciPrepareMessage: Cmd:%d L:%d\n", Cmd, BufLen));
+
+	if ( BufLen < 2 ) {
+		return 0;
+	}
+
+	pBufTmp = pBuf;
+	*(pBuf++) = Cmd;
+	*(pBuf++) = 0;  /*    will be filled in later */
+	CalcLen += 2;
+	switch( Cmd ) {
+		case YASF_HOSTCMD_CFG_SET_EXT_IP_INFO:
+
+			CalcLen += 	(pAC->FwApp.Mib.IpInfoExt.NumIpAddresses*sizeof( SK_U32)*2)+
+						(pAC->FwApp.Mib.IpInfoExt.NumIpGateways*sizeof(SK_U32))+
+						(pAC->FwApp.Mib.IpInfoExt.NumDnsServer*sizeof(SK_U32))+
+						(2*sizeof(SK_U32))+ (2*sizeof(SK_U64))+4;
+
+			if ( BufLen < CalcLen ) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+					("    ERROR: BufLen (%d) < CalcLen (%d)\n", BufLen, CalcLen ));
+				break;
+			}
+
+			/*   write IP addresses */
+			*(pBuf++) = pAC->FwApp.Mib.IpInfoExt.NumIpAddresses;
+
+			for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpAddresses; i++ ) {
+				FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.IpAddress[i].Address, pBuf );
+				pBuf += sizeof( SK_U32 );
+			}
+			/*   write IP subnet masks				 */
+			*(pBuf++) = pAC->FwApp.Mib.IpInfoExt.NumIpAddresses;
+
+			for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpAddresses; i++ ) {
+
+				FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.IpAddress[i].SubnetMask, pBuf );
+				pBuf += sizeof( SK_U32 );
+			}
+			/*   write IP Gateways */
+			*(pBuf++) = pAC->FwApp.Mib.IpInfoExt.NumIpGateways;
+
+			for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpGateways; i++ ) {
+
+				FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.IpGateway[i], pBuf );
+				pBuf += sizeof( SK_U32 );
+			}
+			FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.DhcpEnabled, pBuf );
+			pBuf += sizeof( SK_U32 );
+			FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.DhcpServer, pBuf );
+			pBuf += sizeof( SK_U32 );
+			FwPlain64ToRaw64( pAC->FwApp.Mib.IpInfoExt.DhcpLeaseObtained, pBuf );
+			pBuf += sizeof( SK_U64 );
+			FwPlain64ToRaw64( pAC->FwApp.Mib.IpInfoExt.DhcpLeaseExpires, pBuf );
+			pBuf += sizeof( SK_U64 );
+			/*   write DNS server */
+			*(pBuf++) = pAC->FwApp.Mib.IpInfoExt.NumDnsServer;
+			for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumDnsServer; i++ ) {
+				FwPlain32ToRaw32( pAC->FwApp.Mib.IpInfoExt.DnsServer[i], pBuf );
+				pBuf += sizeof( SK_U32 );
+			}
+			Len = (SK_U8) (pBuf-pBufTmp);
+			*(pBufTmp+1) = Len;
+			break;
+			
+	}
+
+	if ( Len > 0 )
+		SK_DBG_DMP( pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, pBufTmp, Len );
+
+	return Len;
+}
+
+/*****************************************************************************
+*
+* FwHciProcessData
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciProcessData(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_U8 Cmd,
+	SK_U8 *pBuf ) {
+
+	SK_U8  RetVal = 0;
+	SK_U8  RecCmd, Length;
+	SK_U16 i;
+
+	RecCmd = *(pBuf++);
+	Length = *(pBuf++);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, 
+		("FwHciProcessData: Cmd:%d RecCmd%d L:%d\n", Cmd, RecCmd, Length ));
+
+	if ( Cmd == RecCmd ) {
+		switch( RecCmd ) {
+
+			case YASF_HOSTCMD_CFG_GET_EXT_IP_INFO:
+
+					/*   read IP addresses */
+				pAC->FwApp.Mib.IpInfoExt.NumIpAddresses = *(pBuf++);
+				Length--;
+				if ( Length >= (pAC->FwApp.Mib.IpInfoExt.NumIpAddresses*sizeof(SK_U32)) ) {
+
+					for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpAddresses; i++ ) {
+
+						if ( i < ASF_DASH_IP_INFO_NUM_IPADDR ) {
+
+							pAC->FwApp.Mib.IpInfoExt.IpAddress[i].Address = FwRaw32ToPlain32( pBuf ); 
+						}
+						pBuf+=sizeof(SK_U32);
+						Length-=sizeof(SK_U32);
+					}
+				}
+				else {
+					break;  /*   failure */
+				}
+
+				/*   read IP subnet masks */
+				if ( pAC->FwApp.Mib.IpInfoExt.NumIpAddresses == *(pBuf) ) {
+					
+					pBuf++;
+					Length--;
+
+					if ( Length >= (pAC->FwApp.Mib.IpInfoExt.NumIpAddresses*sizeof(SK_U32)) ) {
+
+						for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpAddresses; i++ ) {
+
+							if ( i < ASF_DASH_IP_INFO_NUM_IPADDR ) {
+
+								pAC->FwApp.Mib.IpInfoExt.IpAddress[i].SubnetMask = FwRaw32ToPlain32( pBuf );
+							}
+
+							pBuf+=sizeof(SK_U32);
+							Length-=sizeof(SK_U32);
+						}
+					}
+					else {
+						break;
+					}
+				}
+				else {
+					break;  /*   failure */
+				}
+
+				/*   read IP gateways */
+				pAC->FwApp.Mib.IpInfoExt.NumIpGateways = *(pBuf++);
+				Length--;
+
+				if ( Length >= (pAC->FwApp.Mib.IpInfoExt.NumIpGateways*sizeof(SK_U32)) ) {
+
+					for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumIpGateways; i++ ) {
+						
+						if ( i < ASF_DASH_IP_INFO_NUM_IPADDR ) {
+
+							pAC->FwApp.Mib.IpInfoExt.IpGateway[i] = FwRaw32ToPlain32( pBuf );
+						}
+
+						pBuf+=sizeof(SK_U32);
+						Length-=sizeof(SK_U32);
+					}
+				}
+				else {
+					break;  /*   failure */
+				}
+
+				/*   read DHCP enable */
+				if ( Length >= sizeof(SK_U32) ) {
+
+					pAC->FwApp.Mib.IpInfoExt.DhcpEnabled = FwRaw32ToPlain32( pBuf );
+					pBuf+=sizeof(SK_U32);
+					Length-=sizeof(SK_U32);
+				}
+				else 
+					break;  /*   failure */
+
+				/*   read DHCP server */
+				if ( Length >= sizeof(SK_U32) ) {
+					pAC->FwApp.Mib.IpInfoExt.DhcpServer = FwRaw32ToPlain32( pBuf );
+					pBuf+=sizeof(SK_U32);
+					Length-=sizeof(SK_U32);
+				}
+				else 
+					break;  /*   failure */
+
+				/*   read DHCP Lease Obtained */
+				if ( Length >= sizeof(SK_U64) ) {
+					pAC->FwApp.Mib.IpInfoExt.DhcpLeaseObtained = FwRaw64ToPlain64( pBuf );
+					pBuf+=sizeof(SK_U64);
+					Length-=sizeof(SK_U64);
+				}
+				else 
+					break;  /*   failure */
+
+				/*   read DHCP Lease Expires */
+				if ( Length >= sizeof(SK_U64) ) {
+					pAC->FwApp.Mib.IpInfoExt.DhcpLeaseExpires = FwRaw64ToPlain64( pBuf );
+					pBuf+=sizeof(SK_U64);
+					Length-=sizeof(SK_U64);
+				}
+				else 
+					break;  /*   failure */
+
+				/*   read DNS servers */
+				pAC->FwApp.Mib.IpInfoExt.NumDnsServer = *(pBuf++);
+				Length--;
+				if ( Length >= (pAC->FwApp.Mib.IpInfoExt.NumDnsServer*sizeof(SK_U32)) ) {
+					for( i=0; i<pAC->FwApp.Mib.IpInfoExt.NumDnsServer; i++ ) {
+						if ( i < ASF_DASH_IP_INFO_NUM_IPADDR ) {
+							pAC->FwApp.Mib.IpInfoExt.DnsServer[i] = FwRaw32ToPlain32( pBuf ); 
+						}
+						pBuf+=sizeof(SK_U32);
+						Length-=sizeof(SK_U32);
+					}
+				}
+				else 
+					break;  /*   failure */
+
+				FwPrintIpData( pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL);
+				RetVal = 1;  /*   receive cmd successfully parsed */
+				break;
+
+			default:
+				break;
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+				("FwHciProcessData: YASF_HOSTCMD_CFG_GET_EXT_IP_INFO: >"));
+
+	return RetVal;
+}
+#endif /*DASH_APP*/
+
+/*****************************************************************************
+*
+* FwfHciSendCommand
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciSendCommand(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context */
+	SK_U8  Command,
+	SK_U8  Par1,
+	SK_U8  Par2,
+	SK_U8  ExpectResponse,
+	SK_U8  Wait,
+	SK_U8  Retry ) {
+
+	SK_U8 Message[4];
+	SK_U8 RetCode;
+
+	if ( Wait && ( pAC->FwCommon.Hci.Status != HCI_EN_CMD_IDLE )) {
+
+		/* NOTE: This may take some time. */
+		(void) FwHciFinishCommand(pAC, IoC);
+	}
+
+	do {
+		if ( pAC->FwCommon.Hci.Status == HCI_EN_CMD_IDLE ) {
+			
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Send Command cmd:0x%x p1:0x%x p2:0x%x wait:%d Retry:%d\n",
+															Command, Par1, Par2, Wait, Retry ));
+			Message[0] = Command;
+			Message[1] = 2;  /*   Length */
+			Message[2] = Par1;
+			Message[3] = Par2;
+			RetCode = FwHciSendMessage(pAC, IoC, Message, 4, ExpectResponse, Wait );
+		}
+
+		if ( Wait ) {
+
+			RetCode = FwHciFinishCommand(pAC, IoC);
+		}  /*   if ( wait... */
+		else {
+			RetCode = FwHciGetState( pAC );
+			if ( (RetCode == HCI_EN_CMD_ERROR) ) {
+
+				pAC->FwCommon.Hci.Status = HCI_EN_CMD_IDLE;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Command not confirmed RetCode:0x%x\n", RetCode ));
+			}
+		}
+
+		if ( Retry > 0 )
+			Retry--;
+		else {
+			break;
+		}
+
+	} while ( Wait && (RetCode != HCI_EN_CMD_READY) );
+
+	if ( (RetCode == HCI_EN_CMD_READY) ) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Command successfully conveyed\n"));
+	}
+
+	return( RetCode );
+}
+
+/*****************************************************************************
+*
+* FwfHciSendData
+*
+* Description:
+*
+* Returns:
+*
+*/
+SK_U8 FwHciSendData(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context */
+	SK_U8  *Buffer,
+	SK_U8  ExpectResponse,
+	SK_U8  Wait,
+	SK_U8  Retry ) {
+
+	SK_U8 RetCode;
+	SK_U8 Length;
+	SK_U8 Command;
+
+	do {
+		if ( pAC->FwCommon.Hci.Status == HCI_EN_CMD_IDLE ) {
+			Command = *(Buffer + 0 );
+			Length =  *(Buffer + 1);
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Send Data cmd:0x%x Length:%d wait:%d Retry:%d\n",
+															Command, Length, Wait, Retry ));
+			SK_DBG_DMP(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, Buffer, Length );
+			RetCode = FwHciSendMessage(pAC, IoC, Buffer, Length, ExpectResponse, Wait );
+		}
+		if ( Wait ) {
+			RetCode = FwHciFinishCommand(pAC, IoC);
+		}  /*   if ( wait... */
+		else  {
+			RetCode = FwHciGetState( pAC );
+			if ( RetCode == HCI_EN_CMD_ERROR ) {
+				pAC->FwCommon.Hci.Status = HCI_EN_CMD_IDLE;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Data not confirmed RetCode:0x%x\n", RetCode ));
+			}
+		}
+		if ( Retry > 0 ) {
+			Retry--;
+		}
+		else
+			break;
+	} while ( Wait && (RetCode != HCI_EN_CMD_READY) );
+
+	if ( RetCode == HCI_EN_CMD_READY ) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    Data successfully conveyed\n"));
+	}
+
+	return( RetCode );
+}
+
+/*****************************************************************************
+*
+* FwHciStateMachine
+*
+* Description:
+*
+* Returns:
+*
+*/
+void FwHciStateMachine(
+	SK_AC  *pAC,   /* Pointer to adapter context */
+	SK_IOC IoC,    /* IO context */
+	SK_U8  ToEna ) {
+
+	SK_EVPARA EventParam;
+	SK_U32    Cmd;
+	SK_U32    SendValue;
+	SK_U32    RecValue;
+	SK_U32    TmpVal32;
+
+	if (pAC->FwCommon.Hci.Status == HCI_EN_CMD_IDLE) {
+		return;
+	}
+
+	pAC->FwCommon.Hci.Cycles++;
+
+	/* Check, whether there is something to do */
+	SK_IN32( IoC, ASF_HCI_CMDREG, &Cmd );
+
+	if ( pAC->FwCommon.Hci.OldCmdReg != Cmd ) {
+
+		pAC->FwCommon.Hci.OldCmdReg = Cmd;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ,("FwHciStateMachine CmdReg: 0x%x\n", Cmd ));
+	}
+
+	if ((Cmd & (ASF_HCI_READ | 
+				ASF_HCI_WRITE | 
+				ASF_HCI_CMD_RD_READY | 
+				ASF_HCI_CMD_WR_READY | 
+				ASF_HCI_UNSUCCESS)) == 0) {
+
+		/*  SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwHciStateMachine State: 0x%x\n", pAC->FwCommon.Hci.Status )); */
+		switch( pAC->FwCommon.Hci.Status ) {
+
+			case HCI_EN_CMD_WRITING:
+				SendValue = 0;
+				if (pAC->FwCommon.Hci.SendLength > 0) {
+
+					pAC->FwCommon.Hci.SendLength--;
+					SendValue = ((SK_U32)pAC->FwCommon.Hci.TransmitBuf[pAC->FwCommon.Hci.SendIndex +0]) << 24;
+
+					if (pAC->FwCommon.Hci.SendLength > 0) {
+
+						pAC->FwCommon.Hci.SendLength--;
+						SendValue += ((SK_U32)pAC->FwCommon.Hci.TransmitBuf[pAC->FwCommon.Hci.SendIndex +1]) << 16;
+						
+						if (pAC->FwCommon.Hci.SendLength > 0) {
+
+							pAC->FwCommon.Hci.SendLength--;
+							SendValue += ((SK_U32)pAC->FwCommon.Hci.TransmitBuf[pAC->FwCommon.Hci.SendIndex +2]) << 8;
+							if (pAC->FwCommon.Hci.SendLength > 0) {
+
+								pAC->FwCommon.Hci.SendLength--;
+								SendValue += ((SK_U32)pAC->FwCommon.Hci.TransmitBuf[pAC->FwCommon.Hci.SendIndex +3]) << 0;
+							}
+						}
+					}
+				}
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ,("        SendValue: 0x%x l:%d\n",
+															  SendValue, pAC->FwCommon.Hci.SendLength ));
+				SK_OUT32( IoC, ASF_HCI_DATAREG, SendValue);
+
+				if (pAC->FwCommon.Hci.SendLength == 0) {
+
+					SK_OUT32( IoC, ASF_HCI_CMDREG, ASF_HCI_WRITE | ASF_HCI_CMD_WR_READY | ASF_HCI_UNSUCCESS | (pAC->FwCommon.Hci.SendIndex/4));
+					pAC->FwCommon.Hci.Status = HCI_EN_CMD_WAIT;
+				}
+				else {
+					SK_OUT32( IoC, ASF_HCI_CMDREG, ASF_HCI_WRITE | ASF_HCI_UNSUCCESS | (pAC->FwCommon.Hci.SendIndex/4));
+					pAC->FwCommon.Hci.SendIndex += 4;
+				}
+
+				/*  report command to FW (interrupt wakes CPU from sleep mode) */
+				SK_IN32( IoC, HCU_CCSR, &TmpVal32);
+				SK_OUT32( IoC, HCU_CCSR, TmpVal32 | HCU_CCSR_SET_IRQ_HCU);
+
+				break;
+
+			case HCI_EN_CMD_WAIT:
+
+				if ( pAC->FwCommon.Hci.ExpectResponse ) {
+
+					pAC->FwCommon.Hci.Status = HCI_EN_CMD_READING;
+					pAC->FwCommon.Hci.ReceiveIndex = 0;
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("        Wait for response\n" ));
+					SK_OUT32( IoC, ASF_HCI_CMDREG, ASF_HCI_READ | ASF_HCI_UNSUCCESS | (pAC->FwCommon.Hci.ReceiveIndex/4));
+				}
+				else  {
+					pAC->FwCommon.Hci.Status = HCI_EN_CMD_READY;
+					pAC->FwCommon.Hci.ReceiveBuf[1] = 0;  /*Length*/
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("        Cmd Ready\n" ));
+				}
+
+				/*  report command to FW (interrupt wakes CPU from sleep mode) */
+				SK_IN32( IoC, HCU_CCSR, &TmpVal32);
+				SK_OUT32( IoC, HCU_CCSR, TmpVal32 | HCU_CCSR_SET_IRQ_HCU);
+				break;
+
+			case HCI_EN_CMD_READING:
+
+				SK_IN32( IoC, ASF_HCI_DATAREG, &RecValue );
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ,("        RecValue: 0x%x\n", RecValue ));
+				pAC->FwCommon.Hci.ReceiveBuf[pAC->FwCommon.Hci.ReceiveIndex+3] = (SK_U8) (RecValue >>  0) & 0x000000ff;
+				pAC->FwCommon.Hci.ReceiveBuf[pAC->FwCommon.Hci.ReceiveIndex+2] = (SK_U8) (RecValue >>  8) & 0x000000ff;
+				pAC->FwCommon.Hci.ReceiveBuf[pAC->FwCommon.Hci.ReceiveIndex+1] = (SK_U8) (RecValue >> 16) & 0x000000ff;
+				pAC->FwCommon.Hci.ReceiveBuf[pAC->FwCommon.Hci.ReceiveIndex+0] = (SK_U8) (RecValue >> 24) & 0x000000ff;
+				pAC->FwCommon.Hci.ReceiveIndex   += 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ,("        RecValue: 0x%x RecIndex:%d l:%d\n",
+															  RecValue,pAC->FwCommon.Hci.ReceiveIndex, pAC->FwCommon.Hci.ReceiveBuf[1] ));
+
+				if ( pAC->FwCommon.Hci.ReceiveBuf[1] > pAC->FwCommon.Hci.ReceiveIndex ) { /* check length*/
+					SK_OUT32( IoC, ASF_HCI_CMDREG, ASF_HCI_READ | ASF_HCI_UNSUCCESS | (pAC->FwCommon.Hci.ReceiveIndex/4));
+				}
+				else  {
+					SK_OUT32( IoC, ASF_HCI_CMDREG, ASF_HCI_CMD_RD_READY );
+					pAC->FwCommon.Hci.Status = HCI_EN_CMD_READY_END;
+				}
+
+				/*  report command to FW (interrupt wakes CPU from sleep mode) */
+				SK_IN32( IoC, HCU_CCSR, &TmpVal32);
+				SK_OUT32( IoC, HCU_CCSR, TmpVal32 | HCU_CCSR_SET_IRQ_HCU);
+				break;
+
+			case HCI_EN_CMD_READY_END:
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ, ("FwHciStateMachine -> Read completed\n"));
+				pAC->FwCommon.Hci.Status = HCI_EN_CMD_READY;
+				break;
+
+			case HCI_EN_CMD_READY:
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ, ("FwHciStateMachine -> HCI_EN_CMD_READY (%d)\n",pAC->FwCommon.Hci.Cycles));
+				break;
+
+		}  /*   switch( pAC->FwCommon.Hci.Status ) { */
+
+		pAC->FwCommon.Hci.To = 0;
+
+	}  /*   if ((Cmd & (ASF_HCI_READ | ASF_HCI_WRITE | ASF_HCI_CMD_RD_READY | ASF_HCI_CMD_WR_READY)) == 0) */
+	else  {
+
+		if ( ToEna ) {
+			pAC->FwCommon.Hci.To++;
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_IRQ,("                    CmdReg: 0x%x TO:%d\n", Cmd, pAC->FwCommon.Hci.To ));
+		}
+		/*  Timeout ! */
+		if ( pAC->FwCommon.Hci.To > ASF_HCI_TO ) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("FwHciStateMachine -> ERROR TO:%d\n",pAC->FwCommon.Hci.To));
+			pAC->FwCommon.Hci.Status = HCI_EN_CMD_ERROR;
+		}
+	}
+
+	if ( ToEna ) {
+		if ( pAC->FwCommon.Hci.Status != HCI_EN_CMD_IDLE &&
+			 pAC->FwCommon.Hci.Status != HCI_EN_CMD_READY &&
+			 pAC->FwCommon.Hci.Status != HCI_EN_CMD_ERROR ) {
+			SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+/*             SkTimerStart(pAC, IoC, &pAC->FwCommon.Hci.AsfTimerHci,  *  100ms * */
+/*                          100000, SKGE_ASF, SK_ASF_EVT_TIMER_HCI_EXPIRED, */
+/*                          EventParam); */
+
+			SkTimerStart(pAC, IoC, &pAC->FwCommon.Hci.AsfTimerHci,  /*  10ms */
+						 100000, SKGE_ASF, SK_ASF_EVT_TIMER_HCI_EXPIRED,
+						 EventParam);
+		}
+	}
+
+	return;
+}
+
diff -ruN linux/drivers/net/sk98lin/fwimage.c linux-new/drivers/net/sk98lin/fwimage.c
--- linux/drivers/net/sk98lin/fwimage.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwimage.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,914 @@
+/******************************************************************************
+ *
+ * Name:    fwimage.c
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware image function
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+static void FwLockSpi( SK_AC *pAC, SK_IOC  IoC );
+static void FwUnlockSpi( SK_AC *pAC, SK_IOC  IoC );
+
+/*****************************************************************************
+*
+* FwLockSpi
+*
+* Description:
+*
+* Returns:
+*
+*/
+static void FwLockSpi(
+	SK_AC  *pAC,
+	SK_IOC IoC)
+{
+	SK_U8  TmpVal8;
+	SK_U32 TmpVal32;
+	SK_U32 i;
+
+	SK_IN8( IoC, GPHY_CTRL + 2, &TmpVal8);
+	TmpVal8 |= BIT_0;
+	SK_OUT8( IoC, GPHY_CTRL + 2, TmpVal8);
+
+	if( (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+		(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)    )  {
+		for( i=0; i<10; i++ )  {
+			SK_IN32( IoC, SPI_Y2_CONTROL_REG, &TmpVal32);
+			if( (TmpVal32 & ( BIT_30 )) == 0 )
+				break;
+			FwOsSleep( 1000 );  /* 1ms */
+		}
+	}
+}
+
+/*****************************************************************************
+*
+* FwUnlockSpi
+*
+* Description:
+*
+* Returns:
+*
+*/
+static void FwUnlockSpi(
+	SK_AC  *pAC,
+	SK_IOC IoC)
+{
+	SK_U8 TmpVal8;
+
+	SK_IN8( IoC, GPHY_CTRL + 2, &TmpVal8);
+	TmpVal8 &= ~BIT_0;
+	SK_OUT8( IoC, GPHY_CTRL + 2, TmpVal8);
+}
+
+void FwFreePatchMemory(
+	SK_AC *pAC)  /* Pointer to adapter context */
+{
+	int i;
+
+	for (i = 0; i < pAC->FwCommon.PatchNumber; i++) {
+		FwOsFreeMemory(pAC, pAC->FwCommon.Patch[i].Ptr);
+	}
+}
+
+void FwReadFwVersionFromFile(
+	SK_AC        *pAC,  /* Pointer to adapter context */
+	SK_FW_HANDLE fh)    /* file handler */
+{
+	pAC->FwCommon.VersionLength = 5;
+	pAC->FwCommon.VersionOffset = ASF_FLASH_SU_OFFS_VER;
+	FwOsFileRead(pAC, fh,
+				 (SK_U8 *)pAC->FwCommon.FileVersion,
+				 pAC->FwCommon.VersionOffset,
+				 pAC->FwCommon.VersionLength);
+
+	FW_DBG_MSG_I(("FwReadFwVersionFromFile: %s\n", pAC->FwCommon.FileVersion));
+	SK_DBG_PRINTF("%s: FwReadFwVersionFromFile: %s\n", DRV_NAME,
+		pAC->FwCommon.FileVersion);
+}
+
+void FwAddPatch(
+	SK_AC  *pAC,     /* Pointer to adapter context */
+	SK_U32 Offset,
+	SK_U32 Size,
+	SK_U8  *Ptr)
+{
+	pAC->FwCommon.Patch[pAC->FwCommon.PatchNumber].Offset = Offset;
+	pAC->FwCommon.Patch[pAC->FwCommon.PatchNumber].Size = Size;
+	pAC->FwCommon.Patch[pAC->FwCommon.PatchNumber].Ptr = Ptr;
+
+	pAC->FwCommon.PatchNumber++;
+
+	FW_DBG_MSG_I(("FwAddPatch Offset 0x%x, Size 0x%x, Ptr 0x%x\n", Offset, Size, Ptr));
+}
+
+SK_U32 FwGetImageWord(
+	SK_AC        *pAC,  /* Pointer to adapter context */
+	SK_FW_HANDLE fh,    /* image file handler */
+	SK_U32       Off)   /* offset in image */
+{
+	SK_U32 Val32;
+	int    i;
+
+	for (i = 0; i < pAC->FwCommon.PatchNumber; i++) {
+
+		if( Off >= pAC->FwCommon.Patch[i].Offset &&
+			Off < (pAC->FwCommon.Patch[i].Offset +
+				   pAC->FwCommon.Patch[i].Size)) {
+
+			Val32 = (*((SK_U32*)(pAC->FwCommon.Patch[i].Ptr +
+								(Off - pAC->FwCommon.Patch[i].Offset) )));
+
+			if (Off + 4 > pAC->FwCommon.Patch[i].Offset +
+				pAC->FwCommon.Patch[i].Size) {
+
+				Val32 &= (0x00ffffff >> (3 - pAC->FwCommon.Patch[i].Size%4) * 8);
+			}
+			return LITTLEENDIAN_TO_HOST_32(Val32);
+		}
+	}
+
+	FwOsFileRead(pAC, fh, (SK_U8 *) &Val32, Off, 4);
+
+	return LITTLEENDIAN_TO_HOST_32(Val32);
+}
+
+SK_U32 FwChkSumImage(
+	SK_AC        *pAC,  /* Pointer to adapter context */
+	SK_FW_HANDLE fh)    /* image file handler */
+{
+	SK_U32 ImCs = 0;
+	int i;
+
+	/*   calculate CSum of the image including patches */
+
+	pAC->FwApp.FlashSize = ASF_FLASH_SU_SIZE;
+
+	for( i = 0; i < (pAC->FwApp.FlashSize - 4) ; i += 4 )  {
+		ImCs += FwGetImageWord(pAC, fh, i);
+	}
+	FW_DBG_MSG_I(("FwChkSumImage: 0x%x\n", ImCs));
+
+	return (ImCs);
+}
+
+SK_U32 FwGetFlashWord(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context handle */
+	SK_U32 Off)
+{
+	SK_U32 Val32;
+
+	if (SkPflManage(pAC, IoC, (SK_U8 *) &Val32, Off, 4, SK_PFL_READ) ) {
+
+		FW_DBG_MSG_IE(("FwGetFlashWord ERROR: PFlash read timeout\n"));
+	}
+	return (Val32);
+}
+
+SK_U32 FwChkSumFlash(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_U32 FlCs = 0;
+	int i;
+
+	/*   calculate CSum of the immage including patches */
+	if (!SkPflCheck( pAC, IoC) ) {
+		FW_DBG_MSG_IE(("FwChkSumFlash ERROR: PFlash timeout\n"));
+		return (0);
+	}
+	for( i=0; i < (pAC->FwApp.FlashSize - 4); i += 4 )  {
+
+		FlCs += FwGetFlashWord(pAC, IoC, i);
+	}
+	FW_DBG_MSG_I(("FwChkSumFlash: 0x%x\n", FlCs));
+	return (FlCs);
+}
+
+void FwReadFwVersionFromFlash(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	unsigned char buf[4];
+#ifndef	SK_LITTLE_ENDIAN
+	SK_U32	*val32 = (SK_U32*)buf;
+#endif
+	int i;
+
+	for (i = 0; i < pAC->FwCommon.VersionLength; i++) {
+
+		if (i%4 == 0) { /*  one read for 4 byte */
+			if (SkPflManage(pAC, IoC, buf,
+							pAC->FwCommon.VersionOffset + i, 4, SK_PFL_READ) ) {
+				FW_DBG_MSG_IE(("FwReadFwVersionFromFlash ERROR: version read timeout\n"));
+				return;
+			}
+#ifndef	SK_LITTLE_ENDIAN
+			*val32 = LITTLEENDIAN_TO_HOST_32(*val32);
+#endif
+		}
+		pAC->FwCommon.FlashVersion[i] = buf[i%4];
+	}
+	FW_DBG_MSG_I(("FwReadFwVersionFromFlash: %s\n", pAC->FwCommon.FlashVersion));
+}
+
+SK_BOOL FwIsImageInFlashOk(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context handle */
+	SK_U32 CSum)  /* flash checksum */
+{
+	SK_U32 Val32;
+
+	if (SkPflManage(pAC, IoC, (SK_U8 *) &Val32, pAC->FwApp.FlashSize - 4, 4, SK_PFL_READ) ) {
+
+		FW_DBG_MSG_IE(("FwGetFlashWord ERROR: PFlash CSum read timeout\n"));
+	}
+	if (Val32 + CSum) {
+		FW_DBG_MSG_I(("FwIsImageInFlashOk: CSum is not ok!\n"));
+		return SK_FALSE;
+	}
+	else {
+		FW_DBG_MSG_I(("FwIsImageInFlashOk: CSum is ok\n"));
+		return SK_TRUE;
+	}
+}
+
+SK_BOOL FwIsImageNewer(SK_AC *pAC)  /* Pointer to adapter context */
+{
+	int i;
+
+	for (i = 0; i < pAC->FwCommon.VersionLength; i++) {
+		if (pAC->FwCommon.FileVersion[i] > pAC->FwCommon.FlashVersion[i] ) {
+			FW_DBG_MSG_I(("FwIsImageNewer: yes\n"));
+			return SK_TRUE;
+		}
+	}
+	FW_DBG_MSG_I(("FwIsImageNewer: no\n"));
+	return SK_FALSE;
+}
+
+SK_BOOL FwProgrammSPI(
+	SK_AC        *pAC,      /* Pointer to adapter context */
+	SK_IOC       IoC,       /* IO context handle */
+	SK_FW_HANDLE fh,        /* image file handler */
+	SK_U32       ImageOff,
+	SK_U32       SPIOff,
+	SK_U32       Size)
+{
+	SK_U32 i;
+	SK_U32 Val32, Ver32;
+
+	if( spi_flash_erase( pAC, IoC, SPIOff, Size))  {
+
+			FW_DBG_MSG_IE(("FwProgrammSPI ERROR: SPI erase timeout\n"));
+			return SK_FALSE;
+
+	}
+
+	for( i = 0; i < Size; i += 4 )  {
+
+		FwOsFileRead(pAC, fh, (SK_U8 *) &Val32, ImageOff + i, 4);
+
+		/*  write buffer to flash  */
+		if( spi_flash_manage( pAC, IoC, (SK_U8 *) &Val32, SPIOff + i, 4, SPI_WRITE )) {
+
+			FW_DBG_MSG_IE(("FwProgrammSPI ERROR: SPI write at 0x%x\n",
+						   SPIOff + i ));
+			return SK_FALSE;
+		}
+	}
+
+	for( i = 0; i < Size; i += 4 )  {
+
+		FwOsFileRead(pAC, fh, (SK_U8 *) &Ver32, ImageOff + i, 4);
+
+		if( spi_flash_manage( pAC, IoC, (SK_U8 *) &Val32, SPIOff + i, 4, SPI_READ )) {
+
+			FW_DBG_MSG_IE(("FwProgrammSPI ERROR: SPI read at 0x%x\n",
+							   SPIOff + i ));
+			return SK_FALSE;
+		}
+
+		if (Val32 != Ver32) {
+			FW_DBG_MSG_IE(("FwProgrammSPI ERROR: SPI verify at 0x%x\n",
+						   SPIOff + i ));
+			return SK_FALSE;
+		}
+	}
+
+	FW_DBG_MSG_I(("FwProgrammSPI: ok\n"));
+
+	return (SK_TRUE);
+}
+
+SK_BOOL FwProgrammPFlash(
+	SK_AC        *pAC,      /* Pointer to adapter context */
+	SK_IOC       IoC,       /* IO context handle */
+	SK_FW_HANDLE fh,        /* image file handler */
+	SK_U32       ImageOff,
+	SK_U32       PFlashOff,
+	SK_U32       Size)
+{
+	SK_U32 i, maxcnt;
+	SK_U32 cnt = 0;
+	SK_U32 Val32;
+	SK_U32 buf [16];
+
+	if( SkPflManage( pAC, IoC, NULL, PFlashOff, Size, SK_PFL_ERASE )) {
+
+		FW_DBG_MSG_IE(("FwProgrammPFlash ERROR: erase timeout\n"));
+		return (SK_FALSE);
+	}
+
+	SK_DBG_PRINTF("%s: Flash device ", DRV_NAME);
+	maxcnt = (Size/4)/200;
+
+	for( i = 0; i < Size; i += 4 )  {
+		Val32 = FwGetImageWord(pAC, fh, ImageOff + i);
+		buf[(i%64)/4] = Val32;
+		if (i == 0 || (i+4)%64 ) {
+			continue;
+		}
+
+		if (cnt++ >= maxcnt) {
+			cnt = 0;
+			SK_DBG_PRINTF(".");
+		}
+
+		if (i == (Size - 4)) {
+			buf[(i%64)/4] = ~pAC->FwCommon.ImageChkSum + 1;
+		}
+
+		if (SkPflManage(pAC, IoC, (SK_U8*)buf, PFlashOff + i - 60, 64,
+						 SK_PFL_WRITE)) {
+			FW_DBG_MSG_IE(("FwProgrammPFlash ERROR: write timeout at 0x%x\n",
+						    PFlashOff +i ));
+			return (SK_FALSE);
+		}
+	}
+
+	for( i = 0; i < Size; i += 4 )  {
+			if( SkPflManage(pAC, IoC, (SK_U8 *) &Val32, PFlashOff + i, 4, SK_PFL_READ)) {
+
+			FW_DBG_MSG_IE(("FwProgrammPFlash ERROR: read timeout at 0x%x\n",
+					   PFlashOff + i ));
+			return (SK_FALSE);
+		}
+
+		if (i == (Size - 4)) {
+			if (Val32 + pAC->FwCommon.ImageChkSum) { /* should be 0 */
+				FW_DBG_MSG_IE(("FwProgrammPFlash ERROR: CSum verify at 0x%x\n",
+							   PFlashOff + i ));
+				return (SK_FALSE);
+			}
+			continue;
+		}
+
+		if (Val32 != FwGetImageWord(pAC, fh, ImageOff + i)) {
+			FW_DBG_MSG_IE(("FwProgrammPFlash ERROR: verify at 0x%x\n",
+					   PFlashOff + i ));
+			return (SK_FALSE);
+		}
+	}
+
+	SK_DBG_PRINTF(" finished!\n");
+
+	FW_DBG_MSG_I(("FwProgrammPFlash: ok\n"));
+	return (SK_TRUE);
+}
+
+SK_BOOL FwProgrammImage(
+	SK_AC        *pAC,  /* Pointer to adapter context */
+	SK_IOC       IoC,   /* IO context handle */
+	SK_FW_HANDLE fh)    /* image file handler */
+{
+	FwSmartResetCpu( pAC, IoC, ASF_RESET_COLD );
+
+	if (pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR) {
+		if ( pAC->FwCommon.ImageSize > pAC->FwApp.FlashSize) {
+
+			if ( !FwProgrammSPI(pAC, IoC, fh,
+								pAC->FwApp.FlashSize,
+								0,
+								pAC->FwCommon.ImageSize -
+								pAC->FwApp.FlashSize )) {
+			return SK_FALSE;
+			}
+
+		}
+
+		return ( FwProgrammPFlash(pAC, IoC, fh, 0, 0,
+								  pAC->FwApp.FlashSize ));
+	}
+	else {
+		return ( FwProgrammSPI(pAC, IoC, fh,
+							   0,
+							   0,
+							   pAC->FwApp.FlashSize));
+	}
+}
+
+SK_BOOL FwIsImageOk(
+	SK_AC        *pAC,  /* Pointer to adapter context */
+	SK_FW_HANDLE fh)    /* file handler */
+{
+	SK_U32 ImCs = 0;
+	SK_U32 Val32;
+	int i;
+
+	for( i = 0; i < pAC->FwApp.FlashSize; i += 4 )  {
+		FwOsFileRead(pAC, fh, (SK_U8 *)&Val32, i, 4);
+		ImCs += LITTLEENDIAN_TO_HOST_32(Val32);
+	}
+
+	if (ImCs) { /* should be 0 */
+		FW_DBG_MSG_IE(("FwIsImageOk ERROR: bad CSum\n"));
+		return SK_FALSE;
+	}
+	FwReadFwVersionFromFile(pAC, fh);
+
+	if (!FwAppIsVersionOk(pAC)) {
+		FW_DBG_MSG_IE(("FwIsImageOk ERROR: wrong image version\n"));
+		return SK_FALSE;
+	}
+
+	FW_DBG_MSG_I(("FwIsImageOk: ok\n"));
+	return SK_TRUE;
+}
+
+SK_U32	FwGetSpiCheckSum(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)  /* IO context handle */
+{
+	SK_U32 Val32;
+
+	/* read SPI checksum from PFlash */
+	if (SkPflManage(pAC, IoC, (SK_U8 *) &Val32,
+					pAC->FwApp.FlashSize - 8, 4, SK_PFL_READ) ) {
+
+		FW_DBG_MSG_IE(("FwGetSpiCheckSum ERROR: PFlash read timeout\n"));
+	}
+	FW_DBG_MSG_I(("FwGetSpiCheckSum: 0x%x\n", Val32));
+	return (Val32);
+}
+
+SK_U32	FwGetSpiCodeSize(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)  /* IO context handle */
+{
+	SK_U32 Val32;
+
+	/* read SPI code size from PFlash */
+	if (SkPflManage(pAC, IoC, (SK_U8 *) &Val32,
+					pAC->FwApp.FlashSize - 12, 4, SK_PFL_READ) ) {
+
+		FW_DBG_MSG_IE(("FwGetSpiCodeSize ERROR: PFlash read timeout\n"));
+	}
+	FW_DBG_MSG_I(("FwGetSpiCodeSize: 0x%x\n", Val32));
+	return (Val32);
+}
+
+SK_BOOL FwIsSpiOk(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)  /* IO context handle */
+{
+	SK_U32	i, Val32;
+	SK_U32	SpiCs = FwGetSpiCheckSum(pAC, IoC);
+	SK_U32  SPICodeSize = FwGetSpiCodeSize(pAC, IoC);
+
+	if (SPICodeSize ) { /*  if there code in spi flash */
+
+		FwLockSpi( pAC, IoC );
+
+		for (i = 0; i < SPICodeSize/4; i++ ) {
+
+			if (spi_flash_manage( pAC, IoC, (SK_U8 *) &Val32, i*4, 4, SPI_READ) ) {
+
+				FW_DBG_MSG_IE(("FwIsSpiOk ERROR: SPI read timeout at 0x%0x\n", i*4));
+				FwUnlockSpi( pAC, IoC );
+				return (SK_FALSE);
+			}
+			SpiCs = SpiCs + Val32;
+		}
+
+		if (SPICodeSize%4) {
+			/* read last incomplete word */
+			if (spi_flash_manage( pAC, IoC, (SK_U8 *) &Val32, i*4, 4, SPI_READ) ) {
+
+				FW_DBG_MSG_IE(("FwIsSpiOk ERROR: SPI read timeout at 0x%0x\n", i*4));
+				FwUnlockSpi( pAC, IoC );
+				return (SK_FALSE);
+			}
+			SpiCs = SpiCs + (Val32 & (0x00ffffff >> ((3 - SPICodeSize%4) * 8)));
+		}
+
+		FwUnlockSpi( pAC, IoC );
+
+		if (SpiCs) { /* Should be 0 if ok */
+			FW_DBG_MSG_IE(("FwIsSpiOk ERROR: SPI CSum 0x%x is not ok\n", SpiCs));
+			return (SK_FALSE);
+		}
+
+		FW_DBG_MSG_I(("FwIsSpiOk: SPI CSum ok\n"));
+		return (SK_TRUE);
+	}
+	else {
+		return (SK_FALSE);
+	}
+}
+
+SK_BOOL FwIsFwInFlashOk(
+	SK_AC *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)  /* IO context handle */
+{
+	SK_U32 Val32;
+
+	/* Calculate Checksum in Flash */
+	SK_U32 FlashChkSum = FwChkSumFlash(pAC, IoC);
+
+	/* read CSum from Flash */
+	if (SkPflManage(pAC, IoC, (SK_U8 *) &Val32,
+					pAC->FwApp.FlashSize - 4, 4, SK_PFL_READ) ) {
+
+		FW_DBG_MSG_IE(("FwIsFlashImageOk ERROR: PFlash CSum read timeout\n"));
+	}
+
+	FwReadFwVersionFromFlash(pAC, IoC);
+
+	if ( (Val32 + FlashChkSum) /* CSum is not ok, Fw in Flash damaged or absent*/
+		|| FlashChkSum != pAC->FwCommon.ImageChkSum /* Fw needs new patches*/
+		|| FwIsImageNewer(pAC) ) {	/* image newer than fw in flash */
+
+		FW_DBG_MSG_I(("FwIsFlashImageOk: Flash needs update\n"));
+
+		return (SK_FALSE);
+	}
+
+	if (pAC->FwCommon.ImageSize > pAC->FwApp.FlashSize &&
+		!FwIsSpiOk(pAC, IoC)) {
+
+		FW_DBG_MSG_I(("FwIsFlashImageOk: Image in SPI needs update\n"));
+		return (SK_FALSE);
+	}
+
+	FW_DBG_MSG_I(("FwIsFlashImageOk: Image in Flash is up to date\n"));
+
+	return (SK_TRUE);
+}
+
+#define SPI_ASF_FW_ADDR			0x20000
+#define SPI_ASF_FW_SIZE			0x20000
+#define PXE_MAGIC_NUM_LEN		2
+#define PXE_MAGIC_NUM			0xaa55
+#define SPI_ASF_CONFIG_COPY		0x1FF80
+#define SPI_ASF_CONFIG2			0x1CF80
+
+int FwRemoveFirmware(
+	SK_AC  *pAC,
+	SK_IOC IoC)
+{
+	int i, ret;
+	SK_U32 flash_size = 0;
+	SK_U32 our_reg2;
+	SK_U8	TmpVal8;
+	SK_U32  TmpVal32, TmpVpd;
+	SK_U32 offset = SPI_ASF_FW_ADDR;
+	unsigned char cv;
+	unsigned char cdb[0x90];
+	unsigned char cd12[] = {
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		85,1,104,14,0,0,0,0,
+		85,1,104,14,2,0,0,0,
+		85,12,88,28,0,0,0,2,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,};
+
+	unsigned char cd13[] = {
+		85,12,88,28,0,0,0,1,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		85,1,104,14,0,0,0,0,
+		85,1,104,14,2,0,0,0,
+		85,1,16,15,1,0,0,0,
+		85,15,128,28,20,52,7,0,
+		85,12,88,28,0,0,0,2,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,
+		255,255,255,255,255,255,255,255,};
+
+	if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+		/*  reset CPU Watchdog */
+		SK_OUT32( IoC, CPU_WDOG, 0);
+		/* Stop Asf timer to avoid restart CPU (dr) */
+		SkTimerStop(pAC, IoC, &pAC->FwApp.AsfTimer);
+		FwDisablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ARP );
+		FwDisablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ICMP );
+		FwDisablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_TCP );
+		FwDisablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_UDP );
+	}
+	else  {
+		/* Stop Asf timer to avoid restart CPU (dr) */
+		SkTimerStop(pAC, IoC, &pAC->FwApp.AsfTimer);
+		/* disable all pattern for asf/ipmi */
+		FwDisablePattern(pAC, IoC, 0, ASF_PATTERN_ID_RSP);
+		FwDisablePattern(pAC, IoC, 0, ASF_PATTERN_ID_ARP);
+		FwDisablePattern(pAC, IoC, 0, ASF_PATTERN_ID_RMCP);
+	}
+
+	pAC->FwApp.InitState  = ASF_INIT_UNDEFINED;
+	pAC->FwApp.OpMode     = SK_GEASF_MODE_UNKNOWN;
+
+	/* Stop CPU */
+	FwLockSpi( pAC, IoC );
+
+	FwResetCpu( pAC, IoC );
+
+	SK_OUT32( IoC, SMB_CSR, SMB_CSR_TX_CLR | SMB_CSR_TX_STOP); /*  clear SmBus  */
+
+	SK_OUT8(IoC, SMB_CFG, SMB_CFG_RST_SET); /*  reset SmBus  */
+
+	/* disable ASF logic (dr) */
+	SK_IN32(IoC, B0_CTST, &TmpVal32);
+	TmpVal32 &= ~0x00003000;    /* clear bit13, bit12 */
+	TmpVal32 |= 0x00001000;             /* set bit13 */
+	SK_OUT32(IoC, B0_CTST, TmpVal32);
+
+	pAC->GIni.GIAsfEnabled = SK_FALSE;   /*  update asf flag for common modules  */
+	pAC->GIni.GIAsfRunning = SK_FALSE;   /*  update asf flag for common modules  */
+
+	if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+
+		/*  set ASF FIFO in Reset */
+		SK_IN32( IoC, ASF_CTRL, &TmpVal32 );
+		TmpVal32 &= ~(BIT_0 | BIT_1);
+		TmpVal32 |= BIT_0;
+		SK_OUT32( IoC, ASF_CTRL, TmpVal32 );
+
+		/*   erase pflash */
+		if( SkPflCheck( pAC, IoC) )  {
+			if( SkPflManage( 	pAC, IoC,
+								pAC->FwApp.FlashBuffer,
+								pAC->FwApp.FlashOffs,
+								pAC->FwApp.FlashSize, SK_PFL_ERASE) == 0 )  {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("pflash successfully erased !\n"));
+			}
+			else  {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("Error: pflash erase failed\n"));
+			}
+		}
+
+		/*  erase SPI - flash */
+		if (spi_flash_erase( pAC, IoC, 0, pAC->FwApp.SPIFlashSize) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("Error: flash erase failed (0x%x)\n",pAC->FwApp.SPIFlashSize));
+		}
+		else  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("spi flash successfully erased (0x%x)\n",pAC->FwApp.SPIFlashSize));
+		}
+
+		/*  erase vpd */
+		for( i=0; i<ASF_VPD_MAX_CONFIG_SIZE; i++ )
+			pAC->FwApp.VpdConfigBuf[i] = 0;
+		SK_TST_MODE_ON(IoC);
+		/*  select EEPROM */
+		SK_IN32(IoC, PCI_C(pAC, VPD_CTRL_ADD), &TmpVal32);
+		TmpVpd = TmpVal32;
+		TmpVal32 = 0xff000007;
+		SK_OUT32(IoC, PCI_C(pAC, VPD_CTRL_ADD), TmpVal32);
+
+		/*  read vpd size
+		 * VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &TmpVal32);
+		 * pAC->vpd.rom_size = 256 << ((TmpVal32 & PCI_VPD_ROM_SZ) >> 14);
+		 */
+
+		if (pAC->FwApp.VpdInitOk == 0) {
+			VpdInit( pAC, IoC );
+		}
+		ret = VpdWriteBlock( pAC, IoC, &pAC->FwApp.VpdConfigBuf[0], 0x0, ASF_VPD_MAX_CONFIG_SIZE);
+		if (ret == ASF_VPD_MAX_CONFIG_SIZE) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("VPD 0 - 0x%x successfully erased\n",ASF_VPD_MAX_CONFIG_SIZE));
+		}
+		else  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("Error: VPD 0 - 0x%x erase failed\n",ASF_VPD_MAX_CONFIG_SIZE));
+		}
+
+		/*  restore VPD ctrl */
+		SK_TST_MODE_ON(IoC);  /*  will be switched off in VpdWriteBlock */
+		SK_OUT32(IoC, PCI_C(pAC, VPD_CTRL_ADD), TmpVpd );
+		SK_TST_MODE_OFF(IoC);
+	}
+	else  {  /*  != SK_GEASF_CHIP_SU */
+
+#ifdef CHIP_ID_YUKON_EX
+		if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX ) {
+			SK_IN32( IoC, ASF_CTRL, &TmpVal32 );
+			TmpVal32 &= ~(BIT_0 | BIT_1);
+			TmpVal32 |= BIT_0;  /*  set ASF FIFO in Reset */
+			SK_OUT32( IoC, ASF_CTRL, TmpVal32 );
+		}
+#endif
+		flash_check_spi( pAC, IoC, (unsigned long *) &flash_size);
+
+		if (flash_size <= SPI_ASF_FW_ADDR) {
+			offset = 0;
+		}
+
+		if (pAC->FwApp.FlashSize == ASF_FLASH_NOVPD_SIZE) {
+			flash_size =  ASF_FLASH_NOVPD_SIZE + 8192;
+		}
+		else {
+			flash_size =  ASF_FLASH_SIZE;
+		}
+
+		if (spi_flash_erase( pAC, IoC, offset, flash_size) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("Error: flash erase failed\n"));
+		}
+		else  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, ("spi flash successfully erased\n"));
+		}
+
+		SK_IN8( IoC, B2_CHIP_ID, &cv); /* read Chip ID */
+
+		SK_IN8( IoC, Y2_CFG_SPC + PCI_PM_NITEM, &TmpVal8);
+
+		if (TmpVal8 != PCI_VPD_CAP_ID ) { /* Parameters in SPI */
+			if (spi_flash_manage(pAC, IoC, cdb, SPI_ASF_CONFIG_COPY, 0x80, SPI_READ) == 0) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+						   ("Error: SPI flash not read\n"));
+
+				spi_flash_manage(pAC, IoC, cdb, offset + SPI_ASF_CONFIG2, 0x80, SPI_WRITE);
+			}
+		}
+		else  { /* if Yukon Extreme */
+
+			for (i=0; i < 0x88; i++) {
+				cdb[i] = 0xff;
+			}
+
+			SK_OUT8(IoC, B0_CTST, CS_RST_CLR); /* clear software reset for sure eeprom write */
+
+			VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
+			pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
+
+			/* enable Config write Reg 0x158 */
+			SK_IN8( IoC, B2_TST_REG1, &TmpVal8 );
+			TmpVal8 &= ~0x03;
+			TmpVal8 |= 0x02;
+			SK_OUT8( IoC, B2_TST_REG1, TmpVal8 );
+
+			/* Restore ASF area  */
+			ret = VpdWriteBlock(pAC,IoC, (char *)cdb, cv == CHIP_ID_YUKON_EX ? 0x160 : 0x340, 0x88);
+
+			if (ret != 0x88) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+						("Error: Restory ASF area failed\n"));
+
+			}
+
+			if (cv == CHIP_ID_YUKON_EX) {
+				ret = VpdReadBlock(pAC, IoC, (char *)cdb, 0x300, 0x80);
+
+				if (ret != 0x80) {
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+							("Error: Read Config data failed\n"));
+
+				}
+				if (cdb[0] == 0x55) { /* is this stored data? */
+					ret = VpdWriteBlock(pAC,IoC, (char *)cdb, 0x380, 0x80);
+					if (ret != 0x80) {
+						SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+								("Error: Restory Config data failed\n"));
+
+					}
+				}
+				else {
+					SK_IN8( IoC, 0x1c08, &cv); /* read Config Data Version */
+
+					switch (cv) {
+					case 0x12:
+						ret = VpdWriteBlock(pAC, IoC, (char *)cd12, 0x380, 0x80);
+						if (ret != 0x80) {
+							SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+									("Error: Restory Config data failed\n"));
+						}
+						break;
+					case 0x13:
+						ret = VpdWriteBlock(pAC, IoC, (char *)cd13, 0x380, 0x80);
+						if (ret != 0x80) {
+							SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+									("Error: Restory Config data failed\n"));
+						}
+						break;
+					default:
+						SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+							("Error: Uknown Config Data Version, not restored\n"));
+						break;
+					}
+				}
+				/* disable Config write Reg 0x158 */
+				SK_IN8( IoC, B2_TST_REG1, &TmpVal8 );
+				TmpVal8 &= ~0x03;
+				TmpVal8 |= 0x01;
+				SK_OUT8( IoC, B2_TST_REG1, TmpVal8 );
+			}
+		}
+	}
+
+	FwUnlockSpi( pAC, IoC );
+
+	return(0);
+}
+
+/******************************************************************************
+ *
+ * FwCheckSPI() - Check if SPI is present
+ *
+ * Description:
+ *
+ * Returns:
+ *  0:         SPI not found
+ *  2:         PXE is present
+ *  1:         PXE is not present
+ *  otherwise: error code (take a look at asfinstdll.h)
+ */
+SK_U8  FwCheckSPI(
+	SK_AC  *pAC,
+	SK_IOC IoC)
+{
+	SK_U32 flash_size = 0;
+	SK_U8 buffer[PXE_MAGIC_NUM_LEN];
+	SK_U16 *p_pxe_magic_number;
+	int ret;
+
+	FwLockSpi( pAC, IoC );
+
+	ret = flash_check_spi( pAC, IoC, (unsigned long *) &flash_size);
+	pAC->FwApp.SPIFlashSize = flash_size;
+
+	if (ret == 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+				("Error: SPI flash not found\n"));
+		FwUnlockSpi( pAC, IoC );
+		return(0);/* ASFINST_ERROR_NO_SPI_FLASH); */
+	}
+
+	/*
+	 * Read the necessary number of bytes from the SPI Flash
+	 * to check if PXE is present.
+	 */
+	if (spi_flash_manage(pAC, IoC, buffer, SPI_ASF_FW_ADDR, PXE_MAGIC_NUM_LEN, SPI_READ) != 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT,
+				("Error: SPI flash not read\n"));
+		FwUnlockSpi( pAC, IoC );
+		return(0);/* ASFINST_ERROR_READ_FLASH); */
+	}
+
+	/*
+	 * Check if the read bytes are equal to
+	 * the PXE magic number
+	 */
+	p_pxe_magic_number = (SK_U16*)buffer;
+
+	if ((*p_pxe_magic_number) == PXE_MAGIC_NUM) {
+		FwUnlockSpi( pAC, IoC );
+		return(2);/* ASFINST_PXE_PRESENT); */
+	}
+	FwUnlockSpi( pAC, IoC );
+	return(1);/* ASFINST_PXE_NOT_PRESENT); */
+}
+
diff -ruN linux/drivers/net/sk98lin/fwmain.c linux-new/drivers/net/sk98lin/fwmain.c
--- linux/drivers/net/sk98lin/fwmain.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwmain.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,756 @@
+/******************************************************************************
+ *
+ * Name:    fwmain.c
+ * Project: fwcommon
+ * Version: $Revision: #5 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: common firmware interface for driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+static void FwSetAsfCtrl( SK_AC *pAC, SK_IOC IoC);
+static void FwEnableFlushFifo(  SK_AC *pAC, SK_IOC IoC);
+
+#define NOT_EC_CHIP (pAC->FwCommon.ChipID == CHIP_ID_YUKON_EX) || \
+		(pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR)
+	
+#define FW_CPU_STATE_UNKNOWN       0
+#define FW_CPU_STATE_RESET         1
+#define FW_CPU_STATE_RUNNING       2
+
+
+/*****************************************************************************
+*
+* FwSetOsPresentBit
+*
+* Description: Report to Firmware presence of OS
+*
+* Returns:
+*
+*/
+void FwSetOsPresentBit(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context */
+{
+	SK_U32 TmpVal32;
+	
+	SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+	
+	if ( NOT_EC_CHIP )  {
+
+		TmpVal32 |= HCU_CCSR_OS_PRSNT;
+	}
+	else {
+		TmpVal32 |= Y2_ASF_OS_PRES;
+	}
+	SK_OUT32( IoC, HCU_CCSR, TmpVal32 );	
+	FW_DBG_MSG_I(("FwSetOsPresentBit\n"));
+}
+
+/*****************************************************************************
+*
+* FwInit0 - Init0 function of Firmware
+*
+* Description:
+* 	 Initialises the data structures
+*
+* Returns:
+*   
+*/
+void FwInit0(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	FW_DBG_MSG_I(("FwInit0\n"));
+
+}
+
+/*****************************************************************************
+*
+* FwResetOsPresentBit
+*
+* Description: Report to Firmware absence of OS
+*
+* Returns:
+*
+*/
+void FwResetOsPresentBit(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context */
+{
+	SK_U32 TmpVal32;
+	
+	SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+	
+	if ( NOT_EC_CHIP )  {
+
+		TmpVal32 &= ~HCU_CCSR_OS_PRSNT;
+	}
+	else {
+
+		TmpVal32 &= ~Y2_ASF_OS_PRES;
+	}
+	SK_OUT32( IoC, HCU_CCSR, TmpVal32 );
+
+	FW_DBG_MSG_I(("FwResetOsPresentBit\n"));
+}
+
+/*****************************************************************************
+*
+* FwSetAsfCtrl
+*
+* Description: FIFO ASF FIFO
+*
+* Returns:
+*
+*/
+static void FwSetAsfCtrl(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_U32 TmpVal32;
+
+	if ( NOT_EC_CHIP )  {
+
+		SK_IN32( IoC, ASF_CTRL, &TmpVal32 );
+				TmpVal32 &= ~(BIT_0 | BIT_1);
+		TmpVal32 |= BIT_1;  /*   Release Reset */
+		SK_OUT32( IoC, ASF_CTRL, TmpVal32 );	
+	}
+
+	FW_DBG_MSG_I(("FwSetAsfCtrl\n"));
+}
+
+/*****************************************************************************
+*
+* FwInit1 - Init1 function of Firmware
+*
+* Description:
+* 	 Checks and initializes the firmware specific hardware
+*
+* Returns:
+*/
+void FwInit1(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_IN8( IoC, B2_CHIP_ID, &(pAC->FwCommon.ChipID));
+	pAC->FwOs.FileIndex = 0;
+
+	/* we need to save spi and pxe presence flags at begin
+	 * to avoid read access to flash during programming
+	 */
+	pAC->FwApp.PxeSPI = FwCheckSPI(pAC, IoC);
+
+	/*   check settings in ASF control register */
+	FwSetAsfCtrl( pAC, IoC );
+}
+
+SK_BOOL FwRemoveImage(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	FW_DBG_MSG_I(("FwRemoveImage:...\n"));
+	
+	FwRemoveFirmware( pAC, IoC );
+
+	return SK_TRUE;
+}
+
+/*****************************************************************************
+*
+* FwCpuState
+*
+* Description:	Check state of CPU
+*
+* Returns:
+*
+*/
+SK_U8 FwCpuState(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_U32 TmpVal32;
+
+	SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+
+	if ( NOT_EC_CHIP )  {
+
+		if( (TmpVal32 & HCU_CCSR_UC_STATE_MSK) == 0 ) {
+
+			return( FW_CPU_STATE_RESET );
+		}
+		else if ( (TmpVal32 & HCU_CCSR_UC_STATE_MSK) == 1 ) {
+
+			return( FW_CPU_STATE_RUNNING );
+		}
+		else {
+
+			return( FW_CPU_STATE_UNKNOWN );
+		}
+	}
+	else  { /*  if ( NOT_EC_CHIP ) */
+
+		if( TmpVal32 & Y2_ASF_RESET ) {
+
+			return( FW_CPU_STATE_RESET );
+		}
+
+		if( TmpVal32 & Y2_ASF_RUNNING ) {
+
+			return( FW_CPU_STATE_RUNNING );
+		}
+	} /*  if ( NOT_EC_CHIP ) */
+
+	return( FW_CPU_STATE_UNKNOWN );
+}
+
+#ifndef MV_INCLUDE_SDK_SUPPORT
+/*****************************************************************************
+*
+* FwIsFwRunning
+*
+* Description: 
+*
+* if CPU is running send CHECK ALIVE command to firmware and wait for answer
+* 
+* Returns:
+* 
+* 0 if firmware doesn't answer
+* 1 if firmware answers
+*/
+static SK_U8 FwIsFwRunning(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_U8 Alive;
+
+	/* SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("AsfCheckAliveCpu -> \n")); */
+
+	Alive = 0;  /*   Not alive */
+
+	/*   check, whether cpu is in reset state... */
+	if( FwCpuState(pAC, IoC) == ASF_CPU_STATE_RUNNING )  {
+
+		if( FwHciSendCommand( pAC, IoC,
+			YASF_HOSTCMD_CHECK_ALIVE, 0, 0, 0, ASF_HCI_WAIT, 2 )
+			== HCI_EN_CMD_READY )  {
+
+			Alive = 1;
+			FW_DBG_MSG_I(("FwIsFwRunning: *** Firmware is running ***\n"));
+		}
+		else  {
+			FW_DBG_MSG_I(("FwIsFwRunning: *** No answer from Firmware ***\n"));
+		}
+	}  /*   if( AsfCpuState(pAC ) != ASF_CPU_STATE_RESET )  { */
+	else  {
+		FW_DBG_MSG_I(("FwIsFwRunning: *** CPU is not running ***\n"));
+	}
+
+	return( Alive );
+}
+#endif
+
+/*****************************************************************************
+*
+* FwResetCpu 
+*
+* Description: Reset CPU
+*
+* Returns:
+*
+*/
+void FwResetCpu(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_U32 TmpVal32;
+
+	if ( NOT_EC_CHIP )  {
+
+		if( pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR )
+			SK_OUT32(IoC, CPU_WDOG, 0); /* stop the watch dog */
+		
+		SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+		TmpVal32 &= ~(BIT_0 | BIT_1);
+		SK_OUT32( IoC, HCU_CCSR, TmpVal32 );
+	}
+	else  {
+		SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+		TmpVal32 &= ~(BIT_2 | BIT_3);
+		TmpVal32 |= BIT_3;
+		SK_OUT32( IoC, HCU_CCSR, TmpVal32 );
+	}
+}
+
+/*****************************************************************************
+*
+* FwStartCpu
+*
+* Description:
+*
+* Returns:
+*
+*/
+void FwStartCpu(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context */
+{
+	SK_U32 	TmpVal32;
+	SK_U16	TmpVal16;
+	
+	if( NOT_EC_CHIP)  {
+
+		/* W A R 
+		 * CPU clock divider shouldn't be used because
+		 * - ASF firmware may malfunction
+		 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
+		 */
+		if ( pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR )  {
+			
+			SK_IN16(IoC, HCU_CCSR, &TmpVal16);
+			
+			if ((TmpVal16 & HCU_CCSR_CPU_CLK_DIVIDE_MSK) != 0) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("\n*******************************************\n"));
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(  "*  WARNING: CLOCK DIVIDE WAS SET : 0x%x    \n", TmpVal16));
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(  "*******************************************\n"));
+				TmpVal16 &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_ASF_E010, SKERR_ASF_E010MSG);
+			}
+			SK_OUT16(IoC, HCU_CCSR, TmpVal16);
+		}
+		
+		SK_OUT32( IoC, ASF_CTRL, 0x02 );	/* enable FIFO & RAM access */
+		SK_IN32( IoC, HCU_CCSR, &TmpVal32 );
+		TmpVal32 &= ~HCU_CCSR_UC_STATE_MSK;   /*  reset halt if set */
+		TmpVal32 |= HCU_CCSR_ASF_RUNNING;  /*  Set to running state */
+		SK_OUT32( IoC, HCU_CCSR, TmpVal32 );
+	}
+	else  { /* if( NOT_EC_CHIP) */
+
+		SK_IN32( IoC, B28_Y2_ASF_STAT_CMD, &TmpVal32 );
+		TmpVal32 &= ~Y2_ASF_UC_STATE;
+		TmpVal32 |= Y2_ASF_RESET;  /*  Set to Reset state (Clk running) */
+		SK_OUT32( IoC, B28_Y2_ASF_STAT_CMD, TmpVal32 );
+		TmpVal32 &= ~Y2_ASF_UC_STATE;
+		TmpVal32 |= Y2_ASF_RUNNING;  /*  Set to running state */
+		SK_OUT32( IoC, B28_Y2_ASF_STAT_CMD, TmpVal32 );
+	
+	} /* if( NOT_EC_CHIP) */
+}
+
+/*****************************************************************************
+*
+* FwSmartResetCpu
+*
+* Description:
+*
+* Returns:
+*
+*/
+void FwSmartResetCpu(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context */
+	SK_U8 Cold )
+{
+	SK_U64 StartTime, CurrTime;
+	SK_U8   ResetCommand;
+
+	if ( Cold ) {
+		ResetCommand = YASF_HOSTCMD_RESET_COLD;
+	}
+	else {
+		ResetCommand = YASF_HOSTCMD_RESET;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> \n"));
+
+	/*   check, whether cpu is already in reset state... */
+	if ( FwCpuState(pAC, IoC) == ASF_CPU_STATE_RUNNING )  {
+
+		/*  ...if not, try SmartReset */
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> Send reset command\n"));
+		
+		if ( pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR ) {
+
+			SK_OUT32(IoC, CPU_WDOG, 0); /* stop the watch dog */
+		}
+
+		if ( FwHciSendCommand( pAC, IoC, ResetCommand, 0, 0, 0, ASF_HCI_WAIT, 2 ) != HCI_EN_CMD_READY )  {
+
+			/*   if Smart Reset fails, do hard reset */
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> Do hard reset\n"));
+			FwResetCpu( pAC, IoC );
+		}
+
+		StartTime = SkOsGetTime(pAC);
+
+		while( FwCpuState(pAC, IoC ) != ASF_CPU_STATE_RESET ) {
+
+			CurrTime = SkOsGetTime(pAC);
+
+			if ( (CurrTime - StartTime) > (SK_TICKS_PER_SEC*5) )  {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> Error: CPU is not in reset state - Do hard reset\n"));
+				FwResetCpu( pAC, IoC );
+				break;
+			}
+		}  /*   while( AsfCpuState(pAC ) != ASF_CPU_STATE_RESET ) { */
+
+		if( FwCpuState(pAC, IoC ) == ASF_CPU_STATE_RESET )
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> CPU is in reset state\n"));
+
+	}  /*   if( AsfCpuState(pAC ) != ASF_CPU_STATE_RESET )  { */
+	else  {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("FwSmartResetCpu -> Cpu already in reset state\n"));
+	}
+}
+
+/*****************************************************************************
+*
+* FwEnableFlushFifo
+*
+* Description:
+*
+* Returns:
+*
+*/
+static void FwEnableFlushFifo(
+	SK_AC  *pAC,
+	SK_IOC IoC )
+{
+	SK_U32 TmpVal32;
+
+#ifdef CHIP_ID_YUKON_EX
+	SK_IN32( IoC, RXMF_TCTL, &TmpVal32 );
+	TmpVal32 &= ~(BIT_23 | BIT_22);
+	TmpVal32 |= BIT_23;
+	SK_OUT32( IoC, RXMF_TCTL, TmpVal32 );
+#endif
+
+}
+
+void FwAsfEnable(
+	SK_AC  *pAC,
+	SK_IOC IoC )
+{
+	SK_OUT32(IoC, B0_CTST, Y2_ASF_ENABLE);
+
+	pAC->GIni.GIAsfEnabled = SK_TRUE;   /*  update asf flag for common modules */
+	pAC->GIni.GIAsfRunning = SK_TRUE;   /*  update asf flag for common modules */
+}
+
+void FwAsfDisable(
+	SK_AC  *pAC,
+	SK_IOC IoC )
+{
+	/*  SK_IN32(IoC, B0_CTST, &TmpVal32); */
+	/*  TmpVal32 &= ~0x00003000;    // clear bit13, bit12 */
+	/*  TmpVal32 |= 0x00001000;             // set bit13 */
+	/*  SK_OUT32(IoC, B0_CTST, TmpVal32); */
+
+	/* Don't disable ASF for restart after Standby/Hibernate 
+	 * to avoid full initialization in common modules (driver)
+	 * that conflicts with running Firmware
+	 *
+	 * SK_OUT32(IoC, B0_CTST, Y2_ASF_DISABLE);
+	 *
+	 * pAC->GIni.GIAsfEnabled = SK_FALSE;  // update asf flag for common modules
+	 */
+}
+
+SK_BOOL FwInit2(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC)   /* IO context handle */
+{
+	SK_FW_HANDLE FileHandle = 0;
+	SK_BOOL RetVal = SK_FALSE;
+	pAC->FwCommon.ImageName = FwAppGetImageName(pAC);
+	FileHandle = FwOsOpenFile(pAC, pAC->FwCommon.ImageName);
+
+	if (FileHandle) {
+		/* if image CS ok and version suitable for driver */
+		if (FwIsImageOk(pAC, FileHandle)) {
+			FwAppPatchImage(pAC, IoC); /* prepare patches for image */
+			pAC->FwCommon.ImageSize = FwOsGetFileSize(pAC, FileHandle);
+			pAC->FwCommon.ImageChkSum = FwChkSumImage(pAC, FileHandle);
+
+			/* calculate new ChkSum */
+			if (!FwIsFwInFlashOk(pAC, IoC) ) { /* Is Fw in Flash need update?*/
+				RetVal = FwProgrammImage(pAC, IoC, FileHandle);
+			}
+			else {
+				RetVal = SK_TRUE; /* Firmware is ok */
+			}
+
+			FwFreePatchMemory(pAC);
+		}
+
+		FwOsCloseFile(pAC, FileHandle);
+	}
+	else { /* firmware image was not found */
+#ifndef MV_INCLUDE_SDK_SUPPORT
+		if (FwIsFwRunning(pAC, IoC)) {
+
+			/* remove fw from flash and clear parameters */
+			FwRemoveImage(pAC, IoC); 
+			FwAsfDisable(pAC, IoC); 
+		}
+#endif
+	}
+
+	return (RetVal);
+}
+
+/*****************************************************************************
+*
+* FwInit - Init function of FW common module
+*
+* Description:
+*   SK_INIT_DATA: Initialises the data structures
+*   SK_INIT_IO: Resets the XMAC statistics, determines the device and
+*    connector type.
+*   SK_INIT_RUN: Starts a timer event for port switch per hour
+*    calculation.
+*
+* Returns:
+*   1 on success
+*   0 on error
+*/
+int FwInit(
+	SK_AC  *pAC,   /* Pointer to adapter context */
+	SK_IOC IoC,    /* IO context handle */
+	int    Level)  /* Initialization level */
+{
+	int RetCode;
+
+	RetCode = SK_FALSE;
+
+	FW_DBG_MSG_I(("FwInit: Called, level=%d\n", Level));
+
+	switch(Level) {
+
+	case SK_INIT_DATA:
+
+		FwInit0(pAC, IoC);
+		RetCode = FwAppInit0(pAC, IoC);
+		break;
+
+	case SK_INIT_IO:
+
+		FwInit1(pAC, IoC);
+		RetCode = FwAppInit1(pAC, IoC);
+		break;
+
+	case SK_INIT_RUN:
+
+		if ((RetCode = FwInit2(pAC, IoC)) == SK_TRUE) {
+			/* FW image is ok */
+			FW_DBG_MSG_I(("FwInit: Image OK, call FwAppInit2\n"));
+			RetCode = FwAppInit2(pAC, IoC);
+		}
+		break;
+
+	default:
+		break; /* Nothing todo */
+	}
+
+	return( RetCode );
+}
+
+/*****************************************************************************
+*
+* FwDeInit - DeInit function of FW common module
+*
+* Description:
+*
+* Returns:
+*   Always 0
+*/
+int FwDeInit(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC )  /* IO context handle */
+{
+	/*  Reset OS Present Flag in ASF Status and Command Register */
+	FwResetOsPresentBit( pAC, IoC );
+
+	if( pAC->FwApp.InitState == ASF_INIT_OK )  {
+		switch(pAC->FwApp.OpMode)  {
+			case SK_GEASF_MODE_ASF:
+				/*   Enable ARP pattern, ASF FW is now responsible for ARP handling */
+				FwEnablePattern ( pAC, IoC, 0, ASF_PATTERN_ID_ARP );
+				break;
+			case SK_GEASF_MODE_IPMI:
+				/*   Enable ARP pattern, ASF FW is now responsible for ARP handling */
+				FwEnablePattern ( pAC, IoC, 0, ASF_PATTERN_ID_ARP );
+
+				if (pAC->FwApp.DualMode == SK_GEASF_Y2_DUALPORT) {
+					FwEnablePattern ( pAC, IoC, 1, ASF_PATTERN_ID_ARP );
+				}
+				break;
+			case SK_GEASF_MODE_DASH:
+			case SK_GEASF_MODE_DASH_ASF:
+				/*   Enable ARP pattern, ASF FW is now responsible for ARP handling */
+				FwEnablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ARP );
+				FwEnablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ICMP );		
+				break;
+		} /*   switch(pAC->FwApp.OpMode)  */
+
+		/*   Inform the FW that the driver will be unloaded */
+		FwHciSendCommand( pAC, IoC, YASF_HOSTCMD_DRV_GOODBYE, 0, 0, 0, ASF_HCI_WAIT, 2 );
+
+		/*   will be done in FW now */
+		if( (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+			(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)  )
+			FwEnableFlushFifo( pAC, IoC );
+	}
+
+
+	/* SkPflCheck( pAC, IoC); */   /*   just for debugging */
+
+	if( SK_FW_DBG(pAC) & DEBUGFW_ERASE_FLASH_DURING_UNLOAD )  {
+		FwRemoveFirmware( pAC, IoC );
+	}
+
+	return( 0 );
+}
+
+/*****************************************************************************
+*
+* FwDeInitStandBy - StandBy -DeInit function of FW common module
+*
+* Description:
+*
+* Returns:
+*   Always 0
+*/
+int FwDeInitStandBy(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC )  /* IO context handle */
+{
+	if( pAC->FwApp.InitState == ASF_INIT_OK )  {	
+		
+		/*   will be done in FW now */
+		if( (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+			(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)  )
+		  	FwEnableFlushFifo( pAC, IoC );
+
+		switch(pAC->FwApp.OpMode)  {
+			case SK_GEASF_MODE_ASF:
+			case SK_GEASF_MODE_IPMI:
+				/*   Enable ARP pattern, ASF FW is now responsible for ARP handling */
+				FwEnablePattern ( pAC, IoC, pAC->FwApp.ActivePort, ASF_PATTERN_ID_ARP );
+				break;
+			case SK_GEASF_MODE_DASH:
+			case SK_GEASF_MODE_DASH_ASF:
+				/*   Enable ARP pattern, ASF FW is now responsible for ARP handling */
+				FwEnablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ARP );
+				FwEnablePattern( pAC, IoC, 0, ASF_DASH_PATTERN_NUM_ICMP );		
+				break;
+		} /*   switch(pAC->FwApp.OpMode)  */
+		
+		/*   Inform the FW that the driver will be unloaded */
+		FwHciSendCommand( pAC ,IoC , YASF_HOSTCMD_DRV_STANDBY, 0, 0, 0, ASF_HCI_WAIT, 2 );
+		pAC->FwApp.StandBy = 1;
+	}
+
+	return( 0 );
+}
+
+/*****************************************************************************
+*
+* FwInitStandBy - StandBy - Init function of FW common module
+*
+* Description:
+*
+* Returns:
+*   Always 0
+*/
+int FwInitStandBy(
+	SK_AC  *pAC,  /* Pointer to adapter context */
+	SK_IOC IoC,   /* IO context handle */
+	int    Level) /* Initialization level */
+{
+	SK_EVPARA EventParam; /* Event struct for timer event */
+
+	if( pAC->FwApp.InitState == ASF_INIT_OK )  {
+		switch(Level) {
+			case SK_INIT_DATA:
+				break;
+
+			case SK_INIT_IO:
+				break;
+
+			case SK_INIT_RUN:
+				/*  Set OS Present Flag in ASF Status and Command Register */
+				FwSetOsPresentBit( pAC ,IoC );
+				/*   Disable ARP pattern, host system takes over the ARP handling */
+				FwDisablePattern( pAC, IoC,pAC->FwApp.ActivePort, ASF_PATTERN_ID_ARP);
+				/*   Inform the FW that the driver will be activated again */
+				FwHciSendCommand( pAC ,IoC , YASF_HOSTCMD_DRV_HELLO, 0, 0, 0, ASF_HCI_WAIT, 2 );
+				SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+				SkTimerStart(pAC, IoC, &pAC->FwApp.AsfTimer,
+							5000000, SKGE_ASF, SK_ASF_EVT_TIMER_EXPIRED, EventParam);
+				pAC->FwApp.Mib.NewParam = 1;
+				pAC->FwApp.StandBy = 0;
+				break;
+		}  /*   switch( Level ) */
+	}  /*   if( pAC->FwApp.InitState == ASF_INIT_OK ) */
+
+	return( 0 );
+}
+
+/*****************************************************************************
+*
+* FwEvent - Event handler
+*
+* Description:
+*   Handles the following events:
+*   SK_ASF_EVT_TIMER_EXPIRED When a hardware counter overflows an
+*
+* Returns:
+*   Always 0
+*/
+int FwEvent(
+	SK_AC     *pAC,   /* Pointer to adapter context */
+	SK_IOC    IoC,    /* IO context handle */
+	SK_U32    Event,  /* Event-Id */
+	SK_EVPARA Param)  /* Event dependent parameter */
+{
+	switch(Event) {
+		case SK_ASF_EVT_TIMER_EXPIRED:
+			/*  SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("FW: FwEvent -> Timer expired\n" )); */
+			FwMainStateMachine( pAC, IoC );
+			break;
+
+		case SK_ASF_EVT_TIMER_HCI_EXPIRED:
+			/*   SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("FW: FwEvent -> TimerWrHci expired GlHciState:%d\n", */
+			/*                                                 pAC->FwApp.GlHciState )); */
+			FwHciStateMachine( pAC, IoC, 1 );
+			break;
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("FW: FwEvent -> Unknown Event:0x%x\n", Event ));
+			break;
+	}
+	return(0); /* Success. */
+} /* FwEvent */
+
diff -ruN linux/drivers/net/sk98lin/fwoids.c linux-new/drivers/net/sk98lin/fwoids.c
--- linux/drivers/net/sk98lin/fwoids.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwoids.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1281 @@
+/******************************************************************************
+ *
+ * Name:    fwoids.c
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware sepcific oids handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/******************************************************************************
+*
+*   FwSetOid -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwSetOid(
+	SK_AC *pAC, /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U32 Id,  /* OID  */
+	SK_U32 Inst,
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	SK_U32     RetLocVal;
+	SK_U16     i;
+	SK_U8      *pTmp;
+	SK_U32     TmpLen = 0;
+	SK_U32     RetCode = SK_ASF_PNMI_ERR_OK;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_INIT,("FwSetOid -> OID:0x%x Len:%d ***********************\n", Id, *pLen ));
+	SK_DBG_DMP(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, pBuf, *pLen );
+
+	if( pAC->FwApp.InitState != ASF_INIT_OK )  {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwSetOid -> Set OID denied, ASF not initialized !\n"));
+		return( SK_ASF_PNMI_ERR_GENERAL );
+	}
+
+	/*  Check if the buffer used by OIDs is valid.	 */
+	if(pBuf == NULL){
+		 return( SK_ASF_PNMI_ERR_GENERAL );
+	}
+
+	switch( Id )  {		
+		case OID_SKGE_ASF_STORE_CONFIG:
+			pAC->FwApp.Mib.NewParam = 4;
+			break;
+
+		case OID_SKGE_ASF_DASH_ENA:
+			if( *pLen == 1 )  {
+				if(pAC->FwApp.NewOpMode == SK_GEASF_MODE_DASH)  {
+					if( *pBuf != pAC->FwApp.Mib.Ena )
+						pAC->FwApp.Mib.ConfigChange |= 0x01;
+					pAC->FwApp.Mib.Ena = *pBuf;
+				}
+				else  {
+					if( *pBuf != 0 )  {
+						if( *pBuf != pAC->FwApp.Mib.Ena )
+							pAC->FwApp.Mib.ConfigChange |= 0x01;
+						pAC->FwApp.Mib.Ena = *pBuf;
+					}
+				}
+				
+				*pLen = 1;
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+					if( *pBuf != 0 ) 
+						pAC->FwApp.NewOpMode = SK_GEASF_MODE_DASH;
+				}
+				else  {
+					pAC->FwApp.NewOpMode = SK_GEASF_MODE_ASF;
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_DASH_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_ENA:
+			if( *pLen == 1 )  {
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+					if(pAC->FwApp.NewOpMode == SK_GEASF_MODE_DASH_ASF)  {
+						if( *pBuf != pAC->FwApp.Mib.Ena )
+							pAC->FwApp.Mib.ConfigChange |= 0x01;
+						pAC->FwApp.Mib.Ena = *pBuf;
+					}
+					else  {
+						if( *pBuf != 0 )  {
+							if( *pBuf != pAC->FwApp.Mib.Ena )
+								pAC->FwApp.Mib.ConfigChange |= 0x01;
+							pAC->FwApp.Mib.Ena = *pBuf;
+						}
+					}
+					*pLen = 1;
+					if( *pBuf != 0 )  
+						pAC->FwApp.NewOpMode = SK_GEASF_MODE_DASH_ASF;
+				}
+				else  {
+					if( *pBuf != pAC->FwApp.Mib.Ena )
+						pAC->FwApp.Mib.ConfigChange |= 0x01;
+					pAC->FwApp.Mib.Ena = *pBuf;
+					*pLen = 1;
+					pAC->FwApp.NewOpMode = SK_GEASF_MODE_ASF;
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_ENA: %d\n",  pAC->FwApp.Mib.Ena ));				
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_RETRANS:
+			if( *pLen == 2 )  {
+				pAC->FwApp.Mib.Retrans = *( (SK_U16 *) pBuf );
+				*pLen = 2;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS: %d\n",  pAC->FwApp.Mib.Retrans ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT:
+			if( *pLen == 2 )  {
+				pAC->FwApp.Mib.RetransInt = *( (SK_U16 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 2;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT: %d\n",  pAC->FwApp.Mib.RetransInt ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_HB_ENA:
+			if( *pLen == 1 )  {
+				pAC->FwApp.Mib.HbEna = *pBuf;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_ENA: %d\n",  pAC->FwApp.Mib.HbEna ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_HB_INT:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.HbInt = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT: %d\n",  pAC->FwApp.Mib.HbInt ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_WD_ENA:
+			if( *pLen == 1 )  {
+				pAC->FwApp.Mib.WdEna = *pBuf;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_ENA: %d\n",  pAC->FwApp.Mib.WdEna ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_WD_TIME:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.WdTime = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME: %d\n",  pAC->FwApp.Mib.WdTime ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_IP_DEST:
+			if( AsfAsci2Ip( pBuf, *pLen, pAC->FwApp.Mib.IpDest )  == 1 )   {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_IP_DEST: %d.%d.%d.%d\n",
+										pAC->FwApp.Mib.IpDest[0], pAC->FwApp.Mib.IpDest[1],
+										pAC->FwApp.Mib.IpDest[2], pAC->FwApp.Mib.IpDest[3] ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_GENERAL;
+			break;
+
+		case OID_SKGE_ASF_MAC_DEST:
+			if( AsfAsci2Mac( pBuf, *pLen, pAC->FwApp.Mib.MacDest )  == 1 )   {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_MAC_DEST: %02x:%02x:%02x:%02x:%02x:%02x\n",
+										pAC->FwApp.Mib.MacDest[0], pAC->FwApp.Mib.MacDest[1],
+										pAC->FwApp.Mib.MacDest[2], pAC->FwApp.Mib.MacDest[3],
+										pAC->FwApp.Mib.MacDest[4], pAC->FwApp.Mib.MacDest[5] ));
+#ifdef ASF_FW_ARP_RESOLVE
+			/* just for FW-ARP-Resolve testing purposes */
+			/* for( i=0; i<6; i++ ) */
+			/*     pAC->FwApp.Mib.MacDest[i] = 0; */
+#endif  /* ASF_FW_ARP_RESOLVE */
+
+			}
+			else
+				RetCode = SK_PNMI_ERR_GENERAL;
+			break;
+
+		case OID_SKGE_ASF_COMMUNITY_NAME:
+			for( i=0; (i<*pLen)&&(i<63); i++ )
+				pAC->FwApp.Mib.CommunityName[i] = *(pBuf + i);
+			pAC->FwApp.Mib.CommunityName[i] = 0;
+			break;
+
+		case OID_SKGE_ASF_RSP_ENA:
+			if( *pLen == 1 )  {
+				if( *pBuf != pAC->FwApp.Mib.RspEnable )
+					pAC->FwApp.Mib.ConfigChange |= 0x02;
+
+				pAC->FwApp.Mib.RspEnable = *pBuf;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RSP_ENA: %d\n",  pAC->FwApp.Mib.RspEnable ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+			case OID_SKGE_ASF_RETRANS_COUNT_MIN:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.RetransCountMin = *( (SK_U32 *) pBuf );
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_COUNT_MIN: %d\n",  pAC->FwApp.Mib.RetransCountMin ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_RETRANS_COUNT_MAX:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.RetransCountMax = *( (SK_U32 *) pBuf );
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_COUNT_MAX: %d\n",  pAC->FwApp.Mib.RetransCountMax ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT_MIN:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.RetransIntMin = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT_MIN: %d\n",  pAC->FwApp.Mib.RetransIntMin ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT_MAX:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.RetransIntMax = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT_MAX: %d\n",  pAC->FwApp.Mib.RetransIntMax ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_HB_INT_MIN:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.HbIntMin = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT_MIN: %d\n",  pAC->FwApp.Mib.HbIntMin ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_HB_INT_MAX:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.HbIntMax = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT_MAX: %d\n",  pAC->FwApp.Mib.HbIntMax ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_WD_TIME_MIN:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.WdTimeMin = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME_MIN: %d\n",  pAC->FwApp.Mib.WdTimeMin ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_WD_TIME_MAX:
+			if( *pLen == 4 )  {
+				pAC->FwApp.Mib.WdTimeMax = *( (SK_U32 *) pBuf ) * ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME_MAX: %d\n",  pAC->FwApp.Mib.WdTimeMax ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_KEY_OP:
+			if( *pLen == (RSP_KEYLENGTH*2) )  {
+				AsfHex2Array( pBuf, *pLen, pAC->FwApp.Mib.KeyOperator );
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_OP:\n >"));
+				for( i=0; i<RSP_KEYLENGTH; i++ )
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("%02x",pAC->FwApp.Mib.KeyOperator[i] ));
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("<\n"));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_KEY_ADM:
+			if( *pLen == (RSP_KEYLENGTH*2) )  {
+				AsfHex2Array( pBuf, *pLen, pAC->FwApp.Mib.KeyAdministrator );
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_ADM:\n >"));
+				for( i=0; i<RSP_KEYLENGTH; i++ )
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("%02x",pAC->FwApp.Mib.KeyAdministrator[i] ));
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("<\n"));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_KEY_GEN:
+			if( *pLen == (RSP_KEYLENGTH*2) )  {
+				AsfHex2Array( pBuf, *pLen, pAC->FwApp.Mib.KeyGenerator );
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_GEN:\n >"));
+				for( i=0; i<RSP_KEYLENGTH; i++ )
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("%02x",pAC->FwApp.Mib.KeyGenerator[i] ));
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("<\n"));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_PAR_1:
+			if( *pLen == 1 )  {
+				pAC->FwApp.Mib.Reserved[Id-OID_SKGE_ASF_PAR_1] = *pBuf;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_PAR_X: ---\n" ));
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_FW_REMOVE:
+			if( *pLen == 4 )  {
+				FwRemoveFirmware(pAC, IoC);
+				*pBuf= 0x66;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_FW_REMOVE: ---\n" ));
+				*pLen = 4;
+			}
+			else
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			break;
+
+		case OID_SKGE_ASF_DASH_IP_INFO:
+			if(*pLen >= SK_GEASF_IP_INFO_SIZE){
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_IP_INFO\n"));
+				/*  we must only to read the info which is in the buffer. */
+				SK_MEMCPY(&pAC->FwApp.IpInfoBuff[0], pBuf, SK_GEASF_IP_INFO_SIZE);
+			}
+			else{
+				*pLen = SK_GEASF_IP_INFO_SIZE;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+			
+		case OID_SKGE_ASF_DASH_IP_INFO_EXT:
+			if(*pLen >= sizeof(TAsfDashIpInfoExt)){
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_IP_INFO_EXT\n"));
+				/*  we must only to read the info which is in the buffer. */
+				if( SK_MEMCMP(&pAC->FwApp.Mib.IpInfoExt, pBuf, sizeof(TAsfDashIpInfoExt)) != 0 )  {
+					pAC->FwApp.Mib.ConfigChange |= 0x01;
+					SK_MEMCPY(&pAC->FwApp.Mib.IpInfoExt, pBuf, sizeof(TAsfDashIpInfoExt));
+				}
+			}
+			else{
+				*pLen = sizeof(TAsfDashIpInfoExt);
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_USER_DAT:
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_USER_DAT\n"));
+			pTmp = pBuf;
+			TmpLen = *pLen;
+
+			/*   delete old user list */
+			for( i=0; i<DASH_USER_DATA_MAX_USER; i++ )  {
+				pAC->FwApp.Mib.User[i].Priv = 0;
+				pAC->FwApp.Mib.User[i].NameLength = 0;
+				pAC->FwApp.Mib.User[i].PwdLength = 0;
+			}
+
+			i = 0;
+			while( TmpLen > 0 )  {
+				/*   name  */
+				pAC->FwApp.Mib.User[i].NameLength = *(pTmp++);
+				if( (pAC->FwApp.Mib.User[i].NameLength > DASH_USER_DATA_MAX_NAME_LEN) ||
+					(pAC->FwApp.Mib.User[i].NameLength < 1)  )
+					break;
+				SK_MEMSET(pAC->FwApp.Mib.User[i].Name, 0, DASH_USER_DATA_MAX_NAME_LEN );
+				SK_STRNCPY(pAC->FwApp.Mib.User[i].Name, pTmp, pAC->FwApp.Mib.User[i].NameLength);
+				pTmp += pAC->FwApp.Mib.User[i].NameLength;
+				TmpLen -= (pAC->FwApp.Mib.User[i].NameLength+1);
+				/*   password */
+				pAC->FwApp.Mib.User[i].PwdLength = *(pTmp++);
+				if( (pAC->FwApp.Mib.User[i].PwdLength > DASH_USER_DATA_MAX_NAME_LEN) ||
+					(pAC->FwApp.Mib.User[i].PwdLength < 1)  )
+					break;
+				SK_MEMSET(pAC->FwApp.Mib.User[i].Pwd, 0, DASH_USER_DATA_MAX_PWD_LEN );
+				SK_STRNCPY(pAC->FwApp.Mib.User[i].Pwd, pTmp, pAC->FwApp.Mib.User[i].PwdLength);
+				pTmp += pAC->FwApp.Mib.User[i].PwdLength;
+				TmpLen -= (pAC->FwApp.Mib.User[i].PwdLength+1);
+				/*   privilege */
+				pTmp++; /*   skip length field of prvileges (allways 1) */
+				pAC->FwApp.Mib.User[i].Priv = *(pTmp++);
+				TmpLen -= 2;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    User %d -> %s %s %c (pLen:%d)\n",
+					i,
+					pAC->FwApp.Mib.User[i].Name,
+					pAC->FwApp.Mib.User[i].Pwd,
+					pAC->FwApp.Mib.User[i].Priv,
+					TmpLen));
+				i++;
+				if( i >= DASH_USER_DATA_MAX_USER )
+					break;
+			}
+
+			if( TmpLen > 0 )  {
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_USER_DAT -> ERROR\n"));
+				/*   ERROR  */
+			}
+			break;
+
+		case OID_SKGE_ASF_CHECK_SPI:
+		case OID_SKGE_ASF_IP_SOURCE:
+			*pLen = 0;
+			break;
+
+		case OID_SKGE_ASF_FWVER_OID:
+			/*  fall through            */
+		case OID_SKGE_ASF_ACPI_OID:
+			/*  fall through */
+		case OID_SKGE_ASF_SMBUS_OID:
+			/*  these OIDs are read only - they cannot be set */
+			*pLen = 0;
+			break;
+
+		default:
+			*pLen = 0;
+			RetCode = SK_ASF_PNMI_ERR_NOT_SUPPORTED;
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwSetOid -> OID not supported \n" ));
+			break;
+	}
+
+	if( RetCode != SK_ASF_PNMI_ERR_OK )  { /*   No bytes used */
+		if( RetCode == SK_PNMI_ERR_TOO_SHORT )  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwSetOid ->  Error Length: %d \n", *pLen ));
+		}
+		else  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwSetOid -> Error ???\n"));
+		}
+		*pLen = 0;
+	}
+	else
+		pAC->FwApp.Mib.NewParam = 2;  /*   Trigger SEPROM Update */
+
+	return(RetCode);
+}
+
+/******************************************************************************
+*
+*   FwGetOid -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwGetOid(
+	SK_AC *pAC, /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U32 Id,  /* OID  */
+	SK_U32 Inst,
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	SK_I8   RetLocVal, *pTmp;
+	SK_U32  TmpVal32;
+	SK_U32  RetCode = SK_ASF_PNMI_ERR_OK;
+	SK_U16   i;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_INIT,("FwGetOid -> OID:0x%x Len:%d\n", Id, *pLen ));
+	
+	if( pAC->FwApp.InitState != ASF_INIT_OK )  {
+		SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwGetOid -> Get OID denied, ASF not initialized !\n"));
+		if( Id != OID_SKGE_ASF_CAP && Id != OID_SKGE_ASF_CHECK_SPI)
+			return( SK_ASF_PNMI_ERR_GENERAL );
+	}
+
+	switch( Id )  {
+		case OID_SKGE_ASF_DASH_CAP:
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    (1) OID_SKGE_ASF_DASH_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+			if( *pLen >= 4 )  {
+				TmpVal32 = 0;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    (2) OID_SKGE_ASF_DASH_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )
+					TmpVal32 |= BIT_0;  /*   DASH capable */
+				if( pAC->FwApp.InitState == ASF_INIT_OK )
+					TmpVal32 |= BIT_1;  /*   Init OK */
+				if( pAC->FwApp.Mib.Ena )
+					TmpVal32 |= BIT_2;  /*   enable */
+				*( (SK_U32 *) pBuf ) = TmpVal32;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_CAP:
+			if( *pLen >= 4 )  {
+				TmpVal32 = 0;
+				if( (pAC->FwApp.InitState != ASF_INIT_UNDEFINED) &&
+					(pAC->FwApp.InitState != ASF_INIT_ERROR_CHIP_ID) )
+					TmpVal32 |= BIT_0;  /*   ASF capable */
+				if( pAC->FwApp.InitState == ASF_INIT_OK )
+					TmpVal32 |= BIT_1;  /*   ASF Init OK */
+				if( pAC->FwApp.Mib.Ena )
+					TmpVal32 |= BIT_2;  /*   ASF enable */
+				*( (SK_U32 *) pBuf ) = TmpVal32;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_BUSY:
+			if( *pLen >= 1 )  {
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+					/*   Indication for configuration in progress */
+					if( pAC->FwApp.NewOpMode != pAC->FwApp.OpMode )  {
+						*( (SK_U8 *) pBuf ) = 1;
+					}
+					else  {
+						*( (SK_U8 *) pBuf ) = 0;
+					}
+					*pLen = 1;
+				}
+				else  {
+					*( (SK_U8 *) pBuf ) = 0;
+					*pLen = 1;
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_DASH_BUSY: %d\n",    *( (SK_U8 *) pBuf )));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_ENA:
+			if( *pLen >= 1 )  {
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+					if( (pAC->FwApp.NewOpMode == SK_GEASF_MODE_DASH) &&
+						(pAC->FwApp.OpMode == SK_GEASF_MODE_DASH) )  {
+						*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					}
+					else  {
+						*( (SK_U8 *) pBuf ) = 0;
+					}
+
+#ifdef WORKING_INDICATION_IN_GUI
+					/*   Indication for configuration in progress */
+					if( pAC->FwApp.NewOpMode != pAC->FwApp.OpMode )  {
+						*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					}
+#endif  /* WORKING_INDICATION_IN_GUI */
+					*pLen = 1;
+				}
+				else  {
+					*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					*pLen = 1;
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_ENA: %d\n",    *( (SK_U8 *) pBuf )));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_ENA:
+			if( *pLen >= 1 )  {
+				if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+					if( (pAC->FwApp.NewOpMode == SK_GEASF_MODE_DASH_ASF) &&
+						(pAC->FwApp.OpMode == SK_GEASF_MODE_DASH_ASF ) ) {
+						*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					}
+					else  {
+						*( (SK_U8 *) pBuf ) = 0;
+					}
+					
+#ifdef WORKING_INDICATION_IN_GUI
+					/*   Indication for configuration in progress */
+					if( pAC->FwApp.NewOpMode != pAC->FwApp.OpMode )  {
+						*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					}
+#endif /* WORKING_INDICATION_IN_GUI */
+					*pLen = 1;
+				}
+				else  {
+					*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Ena;
+					*pLen = 1;
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_DASH_ENA: %d\n",  pAC->FwApp.Mib.Ena ));
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_DASH_ENA: %d\n",    *( (SK_U8 *) pBuf )));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS:
+			if( *pLen >= 2 )  {
+				*( (SK_U16 *) pBuf ) = pAC->FwApp.Mib.Retrans;
+				*pLen = 2;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS: %d\n",  pAC->FwApp.Mib.Retrans ));
+			}
+			else  {
+				*pLen = 2;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.RetransInt / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT: %d\n",  pAC->FwApp.Mib.RetransInt ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_HB_ENA:
+			if( *pLen >= 1 )  {
+				*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.HbEna;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_ENA: %d\n",  pAC->FwApp.Mib.HbEna ));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_HB_INT:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.HbInt / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT: %d\n",  pAC->FwApp.Mib.HbInt ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_WD_ENA:
+			if( *pLen >= 1 )  {
+				*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.WdEna;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_ENA: %d\n",  pAC->FwApp.Mib.WdEna ));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_WD_TIME:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.WdTime / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME: %d\n",  pAC->FwApp.Mib.WdTime ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_IP_SOURCE:
+			if( *pLen >= 16 )  {
+				AsfIp2Asci( pBuf+1, pLen, pAC->FwApp.Mib.IpSource );
+				*pBuf = (SK_U8) *pLen;
+				(*pLen)++;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_IP_SOURCE: %d.%d.%d.%d\n",
+										pAC->FwApp.Mib.IpSource[0], pAC->FwApp.Mib.IpSource[1],
+										pAC->FwApp.Mib.IpSource[2], pAC->FwApp.Mib.IpSource[3] ));
+			}
+			else  {
+				*pLen = 16;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_IP_DEST:
+			if( *pLen >= 16 )  {
+				AsfIp2Asci( pBuf+1, pLen, pAC->FwApp.Mib.IpDest );
+				*pBuf = (SK_U8) *pLen;
+				(*pLen)++;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_IP_DEST: %d.%d.%d.%d\n",
+										pAC->FwApp.Mib.IpDest[0], pAC->FwApp.Mib.IpDest[1],
+										pAC->FwApp.Mib.IpDest[2], pAC->FwApp.Mib.IpDest[3] ));
+			}
+			else  {
+				*pLen = 16;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_MAC_DEST:
+			if( *pLen >= 18 )  {
+				AsfMac2Asci( pBuf+1, pLen, pAC->FwApp.Mib.MacDest );
+				*pBuf = (SK_U8) *pLen;
+				(*pLen)++;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_MAC_DEST: %02x:%02x:%02x:%02x:%02x:%02x\n",
+										pAC->FwApp.Mib.MacDest[0], pAC->FwApp.Mib.MacDest[1],
+										pAC->FwApp.Mib.MacDest[2], pAC->FwApp.Mib.MacDest[3],
+										pAC->FwApp.Mib.MacDest[4], pAC->FwApp.Mib.MacDest[5] ));
+			}
+			else  {
+				*pLen = 18;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_MAC_SOURCE:
+			if( *pLen >= 18 )  {
+				AsfMac2Asci( pBuf+1, pLen, pAC->FwApp.Mib.MacSource );
+				*pBuf = (SK_U8) *pLen;
+				(*pLen)++;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_MAC_SOURCE: %02x:%02x:%02x:%02x:%02x:%02x\n",
+										pAC->FwApp.Mib.MacSource[0], pAC->FwApp.Mib.MacSource[1],
+										pAC->FwApp.Mib.MacSource[2], pAC->FwApp.Mib.MacSource[3],
+										pAC->FwApp.Mib.MacSource[4], pAC->FwApp.Mib.MacSource[5] ));
+			}
+			else  {
+				*pLen = 18;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_COMMUNITY_NAME:
+			if( *pLen >= 64 )  {
+				for( *pLen=0; *pLen<63; (*pLen)++  )  {
+					*(pBuf + *pLen + 1 ) = pAC->FwApp.Mib.CommunityName[*pLen];
+
+					if( pAC->FwApp.Mib.CommunityName[*pLen] != 0 )  {
+						*(pBuf + *pLen + 1 ) = pAC->FwApp.Mib.CommunityName[*pLen];
+					}
+					else  {
+						break;
+					}
+				}
+				*pBuf = (SK_U8) *pLen;
+				(*pLen)++;
+			}
+			else  {
+				*pLen = 64;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RSP_ENA:
+			if( *pLen >= 1 )  {
+				*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.RspEnable;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RSP_ENA: %d\n",  pAC->FwApp.Mib.RspEnable ));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS_COUNT_MIN:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.RetransCountMin;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_COUNT_MIN: %d\n",  pAC->FwApp.Mib.RetransCountMin ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS_COUNT_MAX:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.RetransCountMax;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_COUNT_MAX: %d\n",  pAC->FwApp.Mib.RetransCountMax ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT_MIN:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.RetransIntMin / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT_MIN: %d\n",  pAC->FwApp.Mib.RetransIntMin ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_RETRANS_INT_MAX:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.RetransIntMax / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_RETRANS_INT_MAX: %d\n",  pAC->FwApp.Mib.RetransIntMax ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_HB_INT_MIN:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.HbIntMin / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT_MIN: %d\n",  pAC->FwApp.Mib.HbIntMin ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_HB_INT_MAX:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.HbIntMax / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_HB_INT_MAX: %d\n",  pAC->FwApp.Mib.HbIntMax ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_WD_TIME_MIN:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.WdTimeMin / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME_MIN: %d\n",  pAC->FwApp.Mib.WdTimeMin ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_WD_TIME_MAX:
+			if( *pLen >= 4 )  {
+				*( (SK_U32 *) pBuf ) = pAC->FwApp.Mib.WdTimeMax / ASF_GUI_TSF;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_WD_TIME_MAX: %d\n",  pAC->FwApp.Mib.WdTimeMax ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_GUID:
+			if( *pLen >= 33 )  {
+				AsfArray2Hex( pBuf+1, 16, pAC->FwApp.Mib.Guid );
+				*pBuf = 32;
+				*pLen = 33;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_GUID\n" ));
+			}
+			else  {
+				*pLen = 33;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_KEY_OP:
+			if( *pLen >= 41 )  {
+				AsfArray2Hex( pBuf+1, 40, pAC->FwApp.Mib.KeyOperator );
+				*pBuf = (SK_U8) 40;
+				*pLen = 41;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_OP:\n"));
+			}
+			else  {
+				*pLen = 41;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_KEY_ADM:
+			if( *pLen >= 41 )  {
+				AsfArray2Hex( pBuf+1, 40, pAC->FwApp.Mib.KeyAdministrator );
+				*pBuf = (SK_U8) 40;
+				*pLen = 41;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_ADM:\n"));
+			}
+			else  {
+				*pLen = 41;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_KEY_GEN:
+			if( *pLen >= 41 )  {
+				AsfArray2Hex( pBuf+1, 40, pAC->FwApp.Mib.KeyGenerator );
+				*pBuf = (SK_U8) 40;
+				*pLen = 41;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_KEY_GEN:\n"));
+			}
+			else  {
+				*pLen = 41;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_PAR_1:
+			if( *pLen >= 1 )  {
+				*( (SK_U8 *) pBuf ) = pAC->FwApp.Mib.Reserved[Id-OID_SKGE_ASF_PAR_1];
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_PAR_X: --\n"));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_FWVER_OID:
+			/*  returns the firmware revision to GUI */
+			if (*pLen >= ASF_FWVER_MAXBUFFLENGTH) {
+				for (i=0; i < ASF_FWVER_MAXBUFFLENGTH; i++ ) {
+					/*  maybe we should lock the access to FwVersionString against reading/writing at the same time? */
+					*((SK_U8 *)pBuf+i) = pAC->FwApp.FwVersionString[i];
+				}
+				*pLen = ASF_FWVER_MAXBUFFLENGTH;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_FWVER_OID: %d\n", *pLen));
+			}
+			else {
+				/*  set the right length */
+				*pLen   = ASF_FWVER_MAXBUFFLENGTH;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_ACPI_OID:
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    (1)OID_SKGE_ASF_ACPI_OID: %d\n", *pLen));
+
+			/*  returns ACPI/ASF table (ASF_ACPI_MAXBUFFLENGTH bytes) to GUI */
+			if ( (pAC->FwApp.Mib.Acpi.length > 0) && (pAC->FwApp.Mib.Acpi.length <= ASF_ACPI_MAXBUFFLENGTH) ) {
+				if (*pLen >= pAC->FwApp.Mib.Acpi.length) {
+					/*  there is enough space in buffer for reporting ACPI buffer */
+					for (i=0; i < pAC->FwApp.Mib.Acpi.length; i++) {
+						/*  maybe we should lock the access to Acpi.buffer against reading/writing at the same time? */
+						*((SK_U8 *)pBuf+i) = pAC->FwApp.Mib.Acpi.buffer[i];
+					}
+					*pLen = pAC->FwApp.Mib.Acpi.length;
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    (2)OID_SKGE_ASF_ACPI_OID: %d\n", *pLen));
+				}
+				else {
+					/*  there is not enough space in buffer to report ACPI buffer */
+					/*   *pLen   = ASF_ACPI_MAXBUFFLENGTH; */
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+						("    OID_SKGE_ASF_ACPI_OID: ERROR -> buffer too short %d\n",*pLen));
+					*pLen   = pAC->FwApp.Mib.Acpi.length;
+					RetCode = SK_PNMI_ERR_TOO_SHORT;
+				}
+			}
+			else {
+				/*  no buffer to report */
+				*pLen = 0;
+				RetCode = SK_PNMI_ERR_GENERAL;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+					("    OID_SKGE_ASF_ACPI_OID: ERROR -> Length:%d\n",pAC->FwApp.Mib.Acpi.length));
+			}
+			break;
+
+		case OID_SKGE_ASF_SMBUS_OID:
+			/*  set a request flag, that smbus info must be updated */
+			pAC->FwApp.Mib.SMBus.UpdateReq = 1;
+			/*  returns SMBus table GUI */
+			if ( (pAC->FwApp.Mib.SMBus.length > 0) && (pAC->FwApp.Mib.SMBus.length <= ASF_SMBUS_MAXBUFFLENGTH) ) {
+				if (*pLen >= pAC->FwApp.Mib.SMBus.length) {
+					/*  there is enough space in buffer for reporting ACPI buffer */
+					for (i=0; i < pAC->FwApp.Mib.SMBus.length; i++) {
+						/*  maybe we should lock the access to SMBus.buffer against reading/writing at the same time? */
+						*((SK_U8 *)pBuf+i) = pAC->FwApp.Mib.SMBus.buffer[i];
+					}
+					*pLen = pAC->FwApp.Mib.SMBus.length;
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_SMBUS_OID: %d\n", *pLen));
+				}
+				else {
+					/*  there is not enough space in buffer to report SMBus buffer */
+					*pLen   = ASF_SMBUS_MAXBUFFLENGTH;
+					RetCode = SK_PNMI_ERR_TOO_SHORT;
+				}
+			}
+			else {
+				/*  no buffer to report */
+				*pLen = 0;
+			}
+			break;
+		case OID_SKGE_ASF_CHECK_SPI:
+			if( *pLen >= 4 )  {
+				*((SK_U8 *)pBuf) = pAC->FwApp.PxeSPI;
+				*pLen = 4;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
+							("    OID_SKGE_ASF_CHECK_SPI: %d\n",
+							pAC->FwApp.PxeSPI ));
+			}
+			else  {
+				*pLen = 4;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_MAX_USER:
+			if( *pLen >= 1 )  {
+				*( (SK_U8 *) pBuf ) = DASH_USER_DATA_MAX_USER;
+				*pLen = 1;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_MAX_USER: %d\n",    *( (SK_U8 *) pBuf )));
+			}
+			else  {
+				*pLen = 1;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_IP_INFO:
+			if(*pLen >= SK_GEASF_IP_INFO_SIZE){
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_IP_INFO\n"));
+				/*  we must only to read the info which is in the buffer. */
+				SK_MEMCPY(&pAC->FwApp.IpInfoBuff[0], pBuf, SK_GEASF_IP_INFO_SIZE);
+			}
+			else{
+				*pLen = SK_GEASF_IP_INFO_SIZE;
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+
+		case OID_SKGE_ASF_DASH_IP_INFO_EXT:
+			if(*pLen >= sizeof(TAsfDashIpInfoExt)){
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_IP_INFO_EXT\n"));
+				/*  we must only read the info that is in the buffer. */
+				SK_MEMCPY( pBuf, &pAC->FwApp.Mib.IpInfoExt, sizeof(TAsfDashIpInfoExt) );
+			}
+			else{
+				*pLen = sizeof(TAsfDashIpInfoExt);
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_DASH_SPECIAL_ACTION:
+			if( *pLen >= sizeof(TAsfDashSpecialAction) )  {
+				PAsfDashSpecialAction pAction = (PAsfDashSpecialAction) pBuf;
+
+				if( (pAction->Header.Revision 	== ASF_DASH_SPECIAL_ACTION_VERSION) &&
+					(pAction->Header.Type 		== ASF_DASH_SPECIAL_ACTION_OBJECT_TYPE) &&
+					(pAction->Header.Size 		== sizeof(TAsfDashSpecialAction)) )  {
+
+					pAction->Header.Revision 	= ASF_DASH_SPECIAL_ACTION_VERSION;
+					pAction->Header.Type		= ASF_DASH_SPECIAL_ACTION_OBJECT_TYPE;
+					pAction->Header.Size		= sizeof(TAsfDashSpecialAction);
+					pAction->bNeedDriverReload 	= 0;  /*  SSL: don't reload driver  */
+					if( pAC->FwApp.SslPatchedFile > 0 ) {
+						pAC->FwApp.SslPatchedFile--;
+						pAction->bDeleteSslCertificate= 1;  /*  SSL: delete SSL certificates */
+					} else
+						pAction->bDeleteSslCertificate= 0;
+					*pLen = sizeof(TAsfDashSpecialAction);
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_SPECIAL_ACTION: %d\n",    *( (SK_U8 *) pBuf )));
+				}
+			}
+			else  {
+				*pLen = sizeof(TAsfDashSpecialAction);
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+			
+		case OID_SKGE_ASF_DASH_USER_DAT:
+			if (*pLen >= (DASH_USER_DATA_MAX_USER*sizeof(STR_DASH_USER_DAT)) ) {
+				pTmp = (SK_U8 *)pBuf;
+				*pLen = 0;
+				SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    OID_SKGE_ASF_DASH_USER_DAT\n"));
+				for( i=0; i<DASH_USER_DATA_MAX_USER; i++ )  {
+					SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("    User %d: %s %s %c\n",
+						i,
+						pAC->FwApp.Mib.User[i].Name,
+						pAC->FwApp.Mib.User[i].Pwd,
+						pAC->FwApp.Mib.User[i].Priv));
+					/*   name */
+					*(pTmp++) = pAC->FwApp.Mib.User[i].NameLength;
+					SK_STRNCPY(pTmp, pAC->FwApp.Mib.User[i].Name, pAC->FwApp.Mib.User[i].NameLength);
+					pTmp += pAC->FwApp.Mib.User[i].NameLength;
+					/*   password */
+					*(pTmp++) = pAC->FwApp.Mib.User[i].PwdLength;
+					SK_STRNCPY(pTmp, pAC->FwApp.Mib.User[i].Pwd, pAC->FwApp.Mib.User[i].PwdLength);
+					pTmp += pAC->FwApp.Mib.User[i].PwdLength;
+					/*   priv */
+					*(pTmp++) = 1;
+					*(pTmp++) = pAC->FwApp.Mib.User[i].Priv;
+					*pLen = (SK_U32) (pTmp - (SK_U8 *)pBuf);
+				}
+			}
+			else {
+				/*  set the right length */
+				*pLen   = DASH_USER_DATA_MAX_USER*sizeof(STR_DASH_USER_DAT);
+				RetCode = SK_PNMI_ERR_TOO_SHORT;
+			}
+			break;
+
+		case OID_SKGE_ASF_FW_REMOVE:
+		case OID_SKGE_ASF_HB_CAP:
+			/*  oid not used */
+			*pLen = 0;
+			break;
+
+		default:
+			*pLen   = 0;
+			RetCode = SK_ASF_PNMI_ERR_NOT_SUPPORTED;
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("FwGetOid -> OID not supported\n"));
+			break;
+	}
+
+	if( RetCode != SK_ASF_PNMI_ERR_OK )  { /*   No bytes used */
+		if( RetCode == SK_PNMI_ERR_TOO_SHORT )  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("\n*** FwGetOid ->  Error Length: %d \n", *pLen ));
+		}
+		else  {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL | SK_DBGCAT_ERR,("\n*** FwGetOid -> Error ???\n"));
+		}
+	}
+	else  {
+		SK_DBG_DMP(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, pBuf, *pLen );
+	}
+
+	return(RetCode);
+}
+
+/******************************************************************************
+*
+*   FwGet -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwGet(
+	SK_AC *pAC,    /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	SK_U32  RetCode = SK_ASF_PNMI_ERR_OK;
+
+	return(RetCode) ;
+}
+
+/******************************************************************************
+*
+*   FwPreSet -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwPreSet(
+	SK_AC *pAC, /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	/* preset the Return code to error */
+	SK_U32  RetCode = SK_ASF_PNMI_ERR_OK;
+
+	return(RetCode);
+}
+
+/******************************************************************************
+*
+*   FwPreSetOid -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwPreSetOid(
+	SK_AC *pAC, /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U32 Id,  /* OID  */
+	SK_U32 Inst,
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	SK_U32 RetCode = SK_ASF_PNMI_ERR_OK;
+
+	switch( Id )  {
+		case OID_SKGE_ASF_ENA:
+			break;
+
+		default:
+			*pLen = 0;
+			RetCode = SK_ASF_PNMI_ERR_NOT_SUPPORTED;
+			break;
+	}
+
+	return(RetCode);
+}
+
+/******************************************************************************
+*
+*   FwSet -
+*
+* Context:
+*   init, pageable
+*
+* Returns:
+*/
+int FwSet(
+	SK_AC *pAC, /* the adapter context */
+	SK_IOC IoC, /* I/O context */
+	SK_U8 *pBuf,
+	unsigned int *pLen)
+{
+	SK_U32  RetCode = SK_ASF_PNMI_ERR_OK;
+
+	return(RetCode);
+}
diff -ruN linux/drivers/net/sk98lin/fwos.c linux-new/drivers/net/sk98lin/fwos.c
--- linux/drivers/net/sk98lin/fwos.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwos.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,205 @@
+/******************************************************************************
+ *
+ * Name:    fwos.c
+ * Project: Gigabit Ethernet Adapters, Common Modules
+ * Version: $Revision: #5 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: Kernel mode file read functions.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ *****************************************************************************/
+
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+"$Header: //Release/Yukon_1G/Shared/fw_interface/V1/linux/fwos.c#5 $" ;
+#endif
+
+#include "h/sktypes.h"
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/fcntl.h>
+
+/********************************************************
+		Local Variables
+********************************************************/
+
+/********************************************************
+		Global Variables
+********************************************************/
+
+/********************************************************
+		Local Functions
+********************************************************/
+
+/********************************************************
+		Global Functions
+********************************************************/
+
+/**
+ *  @brief This function opens the FW image file and stores
+ *         the data in an allocated buffer.
+ *
+ *  @param pAC           Pointer to adapter context
+ *  @param pFilePathName Pointer to full pathname of FW image file
+ *  @param FileHandle    FileHandle of the FW image file
+ *  @return              FileHandle
+ */
+SK_FW_HANDLE FwOsOpenFile(
+SK_AC *pAC,
+char  *pFilePathName
+)
+{
+	struct file	*filp = NULL;
+	struct inode	*inode = NULL;
+	loff_t		size;
+
+
+	/* Open the file in kernel mode */
+	printk("Open File %s\n", FW_FILE_PATHNAME);
+	filp = filp_open(FW_FILE_PATHNAME, O_RDONLY | O_LARGEFILE, 0);
+
+	/* Check if the file was opened successfully
+	   and return the file pointer of it was.
+	*/
+	if (IS_ERR(filp)) {
+		printk("sk98lin: Firmware image NOT found.\n");
+		filp = NULL;
+		return filp;
+	}
+
+	inode = filp->f_dentry->d_inode;
+	size = i_size_read(inode->i_mapping->host);
+
+	if (size <= 0) {
+		printk("sk98lin: Firmware image found but not readable.\n");
+		filp = NULL;
+		return filp;
+	}
+
+	printk("sk98lin: Using flash image from binary file. Size: %d\n", (int) size);
+	return filp;
+
+} /* FwOsOpenFile */
+
+/**
+ *  @brief This function closes the FW image file.
+ *
+ *  @param pAC        Pointer to adapter context
+ *  @param FileHandle FileHandle of the FW image file
+ *  @return           SK_TRUE or SK_FALSE
+ */
+int FwOsCloseFile(
+SK_AC 			*pAC,
+SK_FW_HANDLE	pFileHandle)
+{
+	filp_close(pFileHandle, current->files);
+	return SK_TRUE;
+} /* FwOsCloseFile */
+
+/**
+ *  @brief This function returns the size of the FW image file.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @return         Size of FW image file
+ */
+SK_U32 FwOsGetFileSize(SK_AC *pAC, SK_FW_HANDLE FileHandle)
+{
+	struct inode	*inode = NULL;
+	loff_t		size;
+
+	inode = FileHandle->f_dentry->d_inode;
+	size = i_size_read(inode->i_mapping->host);
+
+	return size;
+} /* FwOsGetFileSize */
+
+/**
+ *  @brief This function allocates kernel memory.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @return         Pointer to allocated memory
+ */
+SK_U8 *FwOsAllocMemory(SK_AC *pAC, size_t Size)
+{
+	SK_U8 *pMemory;
+
+	pMemory = kmalloc(Size, GFP_KERNEL);
+
+	return pMemory;
+} /* FwOsAllocMemory */
+
+/**
+ *  @brief This function frees previously allocated memory.
+ *
+ *  @param pAC      Pointer to adapter context
+ *  @return         SK_TRUE or SK_FALSE
+ */
+int FwOsFreeMemory(SK_AC *pAC, SK_U8 *pMemory)
+{
+	if (pMemory != NULL) {
+		kfree(pMemory);
+	}
+
+	return SK_TRUE;
+} /* FwOsFreeMemory */
+
+/**
+ *  @brief This function reads data from the FW image file.
+ *
+ *  @param pAC        Pointer to adapter context
+ *  @param FileHandle Pointer to adapter context
+ *  @param pData      Pointer to data buffer
+ *  @param Offset     Start offset in flash eprom for operation
+ *  @param Length     Length in flash eprom
+ *  @return           SK_TRUE or SK_FALSE
+ */
+int FwOsFileRead(
+SK_AC  			*pAC,
+SK_FW_HANDLE 		FileHandle,
+SK_U8			*pData,
+SK_U32			Offset,
+SK_U32			Length)
+{
+	int	readret;
+	loff_t	origpos;
+	mm_segment_t	old_fs;
+	origpos = FileHandle->f_pos;
+	FileHandle->f_pos += Offset;
+
+	old_fs=get_fs();
+	set_fs(get_ds());
+	readret = FileHandle->f_op->read(FileHandle, pData, Length, &FileHandle->f_pos);
+	set_fs(old_fs);
+
+	FileHandle->f_pos = origpos;
+	return SK_TRUE;
+} /* FwOsFileRead */
+
+/**
+ *  @brief This function frees previously allocated memory.
+ *
+ *  @param Delay    Time to sleep
+ *  @return         SK_TRUE or SK_FALSE
+ */
+void FwOsSleep(int Delay)
+{
+	/* Time to sleep in milliseconds */
+	msleep((unsigned int)(Delay/1000));
+} /* FwOsSleep */
+
diff -ruN linux/drivers/net/sk98lin/fwptrn.c linux-new/drivers/net/sk98lin/fwptrn.c
--- linux/drivers/net/sk98lin/fwptrn.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/fwptrn.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1008 @@
+/******************************************************************************
+ *
+ * Name:    fwptrn.c
+ * Project: firmware common modules
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware pattern function
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+static SK_I8 FwWriteIpmiPattern( SK_AC *pAC, SK_IOC IoC, SK_U8 port);
+static SK_I8 FwWritePatternRamEx(SK_AC *pAC,
+SK_IOC IoC, SK_U8 Port,
+SK_U8 PatternId ,
+SK_U8 Length ,
+SK_U8 *pMask ,
+SK_U8 *pPattern );
+static SK_I8 FwWritePatternRam(
+SK_AC   *pAC,
+SK_IOC  IoC,
+SK_U8   Port,
+SK_U8   PatternId1,
+SK_U8   PatternId2,
+SK_U8   Length1,
+SK_U8   Length2,
+SK_U8   *pMask1,
+SK_U8   *pPattern1,
+SK_U8   *pMask2,
+SK_U8   *pPattern2);
+
+/*  ARP pattern 40 byte (5 bytes in mask) */
+/*  this pattern length corresponds with YLCI_MACRXFIFOTHRES */
+/*  Pattern mask for ARP Frames */
+#ifdef ASF_ONLY_ARP_REQUEST
+static SK_U8 ARP_FRAME_PATTERN[] =
+{
+    /* MAC Header - 14 bytes */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Dest MAC Addr */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Src MAC Addr  */
+    0x08, 0x06,                              /*Frame Type    */
+    /* ARP Header - 28 bytes */
+    0x00, 0x01,                              /* hard type    */
+    0x08, 0x00,                              /* prot type    */
+    0x06,                                    /* hard size    */
+    0x04,                                    /* prot size    */
+    0x00, 0x01,                              /* op = request */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /* senders mac  */
+    0x00, 0x00, 0x00, 0x00,                  /* senders ip   */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /* target mac   */
+    0x00, 0x00};
+static SK_U8 ARP_PATTERN_MASK[] = { 0x00, 0xF0, 0x3F, 0x00, 0x00 };
+#else
+static SK_U8 ARP_FRAME_PATTERN[] =
+{
+    /* MAC Header - 14 bytes */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Dest MAC Addr */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Src MAC Addr  */
+    0x08, 0x06,                              /*Frame Type    */
+    /* ARP Header - 28 bytes */
+    0x00, 0x01,                              /* hard type    */
+    0x08, 0x00,                              /* prot type    */
+    0x06,                                    /* hard size    */
+    0x04,                                    /* prot size    */
+    0x00, 0x00,                              /* op = request */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /* senders mac  */
+    0x00, 0x00, 0x00, 0x00,                  /* senders ip   */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /* target mac   */
+    0x00, 0x00};
+static SK_U8 ARP_PATTERN_MASK[] = { 0x00, 0xF0, 0x00, 0x00, 0x00 };
+#endif
+
+/*  RSP pattern - 40 bytes (this makes 5 bytes in RSP_PATTERN_MASK) */
+/*  this pattern length corresponds with YLCI_MACRXFIFOTHRES */
+static SK_U8 RSP_FRAME_PATTERN[] =
+{   /* MAC Header (14 bytes) */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,     /*Dest MAC Addr*/
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,     /*Src MAC Addr */
+    0x08, 0x00,                             /*Frame Type   */
+    /* IP Header (20 bytes) */
+    0x45, 0x00, 0x00, 0x00,                 /* Version & Header Length */
+    0x00, 0x00, 0x00, 0x00,
+    0x00, 0x11, 0x00, 0x00,                 /* Protocol */
+    0x00, 0x00, 0x00, 0x00,                 /*Src IP address*/
+    0x00, 0x00, 0x00, 0x00,                 /*My IP address*/
+    /* part of UDP Header (6 bytes) */
+    0x00, 0x00,                             /* src port   */
+    0x02, 0x98,                             /* dest. port */
+    0x00, 0x00};                            /* length     */
+
+/*  Pattern mask for RSP Frames */
+static SK_U8 RSP_PATTERN_MASK[] = { 0x00, 0x70, 0x80, 0x00, 0x30 };
+
+/*  RMCP pattern (unsecure port) */
+/*  this pattern length corresponds with YLCI_MACRXFIFOTHRES */
+static SK_U8 RMCP_FRAME_PATTERN[] =
+{   /* MAC Header */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Dest MAC Addr*/
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Src MAC Addr */
+    0x08, 0x00,                              /*Frame Type   */
+    /* IP Header */
+    0x45, 0x00, 0x00, 0x00,                  /* Version & Header Length */
+    0x00, 0x00, 0x00, 0x00,
+    0x00, 0x11, 0x00, 0x00,                  /* Protocol */
+    0x00, 0x00, 0x00, 0x00,                  /*Src IP address*/
+    0x00, 0x00, 0x00, 0x00,                  /*My IP address*/
+    /* UDP Header */
+    0x00, 0x00,                             /* src port */
+    0x02, 0x6f,                             /* unsecure dest. port */
+    0x00, 0x00};
+
+/*  Pattern mask for RMCP Frames */
+static SK_U8 RMCP_PATTERN_MASK[] = { 0x00, 0x70, 0x80, 0x00, 0x30 };
+
+/*  ICMP pattern */
+static SK_U8 ICMP_FRAME_PATTERN[] =
+{   /* MAC Header */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Dest MAC Addr*/
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,      /*Src MAC Addr */
+    0x08, 0x00,                              /*Frame Type   */
+    /* IP Header */
+    0x45, 0x00, 0x00, 0x00,                  /* Version & Header Length */
+    0x00, 0x00, 0x00, 0x00,
+    0x00, 0x01, 0x00, 0x00,                  /* Protocol */
+    0x00, 0x00, 0x00, 0x00,                  /*Src IP address*/
+    0x00, 0x00, 0x00, 0x00,                  /*My IP address*/
+    /* ICMP Header */
+    0x00, 0x00,                          
+    0x00, 0x00,                      
+    0x00, 0x00};
+
+/*  Pattern mask for ICMP Frames */
+static SK_U8 ICMP_PATTERN_MASK[] = 
+{ 0x00, 0x70, 0x80, 0x00, 0x00 };
+
+/*****************************************************************************
+*
+* FwWriteIpmiPattern
+*
+* Description:  write all 3 pattern for IPMI to pattern ram
+*
+* Notes:        none
+*
+* Context:      none
+*
+* Returns:      1:  SUCCESS
+*               0:  ERROR
+*
+*/
+
+static SK_I8 FwWriteIpmiPattern(
+	SK_AC   *pAC,
+	SK_IOC  IoC,
+	SK_U8   port)
+{
+	SK_I8   RetVal;
+	SK_U8   i, j;
+	SK_U32  idx;
+	SK_U32  PattRamCluster[ASF_YEC_PATTRAM_CLUSTER_WORDS];
+	SK_U8   PattSrcByte[2];     /*  2 pattern bytes to read/write in one cluster */
+	SK_U32  TmpVal32;
+	SK_U32  mask;
+	SK_U8   pattern_no;
+
+	RetVal = 1;     /*  success */
+
+	if (RetVal == 1) {
+
+		for (i = 0; (i < ASF_YEC_PATTRAM_CLUSTER_SIZE) && (RetVal == 1); i++) {
+			/*  pattern ram is organized into cluster (i is cluster index) */
+			/*  _after_ writing a whole cluster (= 128bit), the pattern will be written into ram! */
+
+			/*  read a cluster */
+			for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+				PattRamCluster[j] = 0;
+			}
+
+			/* ----------------------- */
+			/*  read source pattern 6 */
+			/* ----------------------- */
+			pattern_no = 6;
+			for (j=0; j < 2; j++) {
+				/*  we have 2 pattern bytes to read/write for one cluster */
+				/*  i is cluster index */
+				/*  j is byte index */
+				idx = 2*i+j;
+				if (idx < 40) {
+					/*  we can read from our pattern pointer */
+					PattSrcByte[j] = RMCP_FRAME_PATTERN[idx];
+
+					/*  read from our enable mask pointer */
+					TmpVal32 = RMCP_PATTERN_MASK[idx/8];
+					mask     = 0x01 << (idx % 8);
+
+					if ( (TmpVal32 & mask) != 0 ) {
+						/*  enable byte */
+						PattRamCluster[j*2+1] |= (BIT_24 << pattern_no);
+					}
+					else {
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+					}
+				}
+				else {
+					/*  fill up with zeros */
+					PattSrcByte[j] = 0;
+					/*  disable byte */
+					PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+				}
+			}
+
+			/*  upper words are interesting here */
+			idx = 1;
+
+			/*  first byte */
+			mask = 0x000000ff;
+			j    = pattern_no % 4;
+			PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+			mask = PattSrcByte[0];
+			PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+
+			/*  second byte */
+			mask = 0x000000ff;
+			PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+			mask = PattSrcByte[1];
+			PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+			/* ----------------------- */
+			/*  read source pattern 5 */
+			/* ----------------------- */
+			pattern_no = 5;
+			for (j=0; j < 2; j++) {
+				/*  we have 2 pattern bytes to read/write for one cluster */
+				/*  i is cluster index */
+				/*  j is byte index */
+				idx = 2*i+j;
+				if (idx < 40) {
+					/*  we can read from our pattern pointer */
+					PattSrcByte[j] = ARP_FRAME_PATTERN[idx];
+
+					/*  read from our enable mask pointer */
+					TmpVal32 = ARP_PATTERN_MASK[idx/8];
+					mask     = 0x01 << (idx % 8);
+
+					if ( (TmpVal32 & mask) != 0 ) {
+						/*  enable byte */
+						PattRamCluster[j*2+1] |= (BIT_24 << pattern_no);
+					}
+					else {
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+					}
+				}
+				else {
+					/*  fill up with zeros */
+					PattSrcByte[j] = 0;
+					/*  disable byte */
+					PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+				}
+			}
+
+			/*  upper words are interesting here */
+			idx = 1;
+
+			/*  first byte */
+			mask = 0x000000ff;
+			j    = pattern_no % 4;
+			PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+			mask = PattSrcByte[0];
+			PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+
+			/*  second byte */
+			mask = 0x000000ff;
+			PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+			mask = PattSrcByte[1];
+			PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+			/* ----------------------- */
+			/*  read source pattern 4 */
+			/* ----------------------- */
+			pattern_no = 4;
+			for (j=0; j < 2; j++) {
+				/*  we have 2 pattern bytes to read/write for one cluster */
+				/*  i is cluster index */
+				/*  j is byte index */
+				idx = 2*i+j;
+				if (idx < 40) {
+					/*  we can read from our pattern pointer */
+					PattSrcByte[j] = RSP_FRAME_PATTERN[idx];
+
+					/*  read from our enable mask pointer */
+					TmpVal32 = RSP_PATTERN_MASK[idx/8];
+					mask     = 0x01 << (idx % 8);
+
+					if ( (TmpVal32 & mask) != 0 ) {
+						/*  enable byte */
+						PattRamCluster[j*2+1] |= (BIT_24 << pattern_no);
+					}
+					else {
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+					}
+				}
+				else {
+					/*  fill up with zeros */
+					PattSrcByte[j] = 0;
+					/*  disable byte */
+					PattRamCluster[j*2+1] &= ~(BIT_24 << pattern_no);
+				}
+			}
+
+			/*  upper words are interesting here */
+			idx = 1;
+
+			/*  first byte */
+			mask = 0x000000ff;
+			j    = pattern_no % 4;
+			PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+			mask = PattSrcByte[0];
+			PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+
+			/*  second byte */
+			mask = 0x000000ff;
+			PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+			mask = PattSrcByte[1];
+			PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+			/*  write a cluster */
+			/*  after writing the last cluster word, the hardware will trigger writing all cluster words */
+			for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+				idx = ASF_YEC_PATTRAM_CLUSTER_WORDS*ASF_YEC_PATTRAM_CLUSTER_BYTES*i + ASF_YEC_PATTRAM_CLUSTER_BYTES*j;
+
+				if( port == 0 )  {
+					SK_OUT32( IoC, WOL_PATT_RAM_1+idx, PattRamCluster[j] );
+				}
+				else  {
+					SK_OUT32( IoC, WOL_PATT_RAM_2+idx, PattRamCluster[j] );
+				}
+			}
+		}
+	}
+
+	return (RetVal);
+}
+
+void FwCheckPattern(
+SK_AC   *pAC,
+SK_IOC  IoC,
+SK_U8   port )  {
+
+	SK_U16 val16;
+
+	/*   WAR: sometimes, for some reasons the ARP and ICMP pattern remain */
+	/*        enabled after disable/enable the driver or rebooting the system. */
+	if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU )  {
+		/*  set ASF match enable register (incomming packets will redirect to ASF queue) */
+		SK_IN16(IoC, ASF_YEX_PATTERN_ENA1+(port*0x80), &val16);
+		if( (val16 & (0x01 << ASF_DASH_PATTERN_NUM_ARP)) || 
+			 (val16 & (0x01 << ASF_DASH_PATTERN_NUM_ICMP))  )  {
+			pAC->FwApp.ToPatternCheck++;
+			if( pAC->FwApp.ToPatternCheck >= 15 )  {
+				if(pAC->FwApp.FwState & BIT_1) { /*  Bit 1 set means port disabled */
+					pAC->FwApp.ToPatternCheck = 0; /*  avoid disable pattern in this case */
+				} else {
+					FwDisablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_ARP );		
+					FwDisablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_ICMP );		
+				}
+			}
+		}
+		else
+			pAC->FwApp.ToPatternCheck = 0;
+	}
+
+}
+
+void FwSetUpPattern(
+SK_AC   *pAC,
+SK_IOC  IoC,
+SK_U8   port )  {
+
+	SK_U8   TmpVal8;
+	SK_U16  TmpVal16;
+	SK_U32  TmpVal32;
+
+	if( port > 1 )
+		return;
+
+	switch (pAC->FwApp.OpMode) {
+		case SK_GEASF_MODE_ASF:
+			/*  see "problems.txt" note #344 */
+			/*  set MAC Rx fifo flush threshold register */
+			/*  (please refer also to note #yuk_hw01) */
+			SK_IN32(IoC, ASF_YEC_MAC_FIFO_FLUSHTHRES1+(port*0x80), &TmpVal32);
+			TmpVal32 &= ~0x7f;  /*  delete bit 6:0 */
+			TmpVal32 |= ASF_YLCI_MACRXFIFOTHRES;
+			SK_OUT32(IoC, ASF_YEC_MAC_FIFO_FLUSHTHRES1+(port*0x80), TmpVal32);
+
+			/*  disable Wake Up Frame Unit before write to pattern ram */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  clear bit 0, bit1 */
+			TmpVal16 |=  0x01;   /*  set bit 0 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+
+			/*   Set new pattern for ASF */
+			/*   This will override the driver WOL pattern, but the driver is going to set */
+			/*   the WOL pattern again before it "shut down" or "stand by" */
+
+			if (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX ) {
+					/*  write ARP, RMCP and RSS patterns */
+					FwWritePatternRamEx(pAC, IoC, port, 7, 40, ARP_PATTERN_MASK, ARP_FRAME_PATTERN );
+					FwWritePatternRamEx(pAC, IoC, port, 6, 40, RSP_PATTERN_MASK, RSP_FRAME_PATTERN );
+					FwWritePatternRamEx(pAC, IoC, port, 8, 40, RMCP_PATTERN_MASK, RMCP_FRAME_PATTERN );
+					if (pAC->FwApp.Mib.Ena) {
+
+						FwEnablePattern( pAC, IoC, port, ASF_PATTERN_ID_RMCP );
+						FwEnablePattern( pAC, IoC, port, ASF_PATTERN_ID_RSP );
+					}
+
+/* We need not disable asf pattern, they are already disabled if asf disabled
+ * if shutdown or standby before parameters from FW are read
+ * the patterns are allways disabled #651
+ * 
+ *
+ *					else {
+ *						FwDisablePattern( pAC, IoC, port, ASF_PATTERN_ID_RMCP );		
+ *						FwDisablePattern( pAC, IoC, port, ASF_PATTERN_ID_RSP );       
+ *					}
+ */
+			}
+			else  {
+				if( pAC->FwApp.Mib.RspEnable )  {
+					/*  security is on - write ARP and RSP pattern */
+					FwWritePatternRam(pAC, IoC, port, 5, 6, 40, 40,
+										ARP_PATTERN_MASK, ARP_FRAME_PATTERN,
+										RSP_PATTERN_MASK, RSP_FRAME_PATTERN);
+			}
+
+/* We need not disable asf pattern, they are already disabled if asf disabled
+ * if shutdown or standby before parameters from FW are read
+ * the patterns are allways disabled #651
+ * 
+ *
+ *				
+ *	            else  {
+ *	                // security is off - write ARP and RMCP pattern
+ * 	                AsfWritePatternRam(pAC, IoC, port, 5, 6, 40, 40,
+ *	                                   ARP_PATTERN_MASK, ARP_FRAME_PATTERN,
+ *	                                   RMCP_PATTERN_MASK, RMCP_FRAME_PATTERN);
+ *				}
+ */
+				/*  set pattern length register */
+				SK_IN32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), &TmpVal32);
+				TmpVal32 &= ~(0x0000007f << 8*(5%4));
+				TmpVal32 |= (40-1) << 8*(5%4);     /*  write length-1 to pattern length register */
+				SK_OUT32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), TmpVal32);
+
+				/*  set pattern length register */
+				SK_IN32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), &TmpVal32);
+				TmpVal32 &= ~(0x0000007f << 8*(6%4));
+				TmpVal32 |= (40-1) << 8*(6%4);     /*  write length-1 to pattern length register */
+				SK_OUT32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), TmpVal32);
+
+				/*  set ASF match enable register (incomming packets will redirect to ASF queue) */
+				SK_IN8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), &TmpVal8);
+				TmpVal8 |= 0x40;    /*  pattern 6 enable */
+				SK_OUT8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), TmpVal8);
+
+				/*  enable pattern pattno */
+				SK_IN8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), &TmpVal8);
+				TmpVal8 |= 0x40;    /*  pattern 6 enable */
+				SK_OUT8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), TmpVal8);
+			}
+
+			/*  enable Wake Up Frame Unit */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  delete bit 0 and 1 */
+			TmpVal16 |=  0x02;   /*  set bit 1 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+			break;
+
+		case SK_GEASF_MODE_IPMI:
+			/*   currently not supported with Yukon Extreme */
+			if( pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX )
+				break;
+			
+			/*  disable Wake Up Frame Unit before write to pattern ram */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  clear bit 0, bit1 */
+			TmpVal16 |=  0x01;   /*  set bit 0 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+
+			/*  write all 3 pattern (RMCP, RSP and ARP) */
+			FwWriteIpmiPattern(pAC, IoC, port);
+
+			/*  set pattern length register */
+			SK_IN32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), &TmpVal32);
+			TmpVal32 &= 0xff000000;     /*  delete length for pattern 4, 5 and 6 */
+			TmpVal32 |= 0x00272727;     /*  set new length for pattern 4, 5 and 6 */
+			SK_OUT32(IoC, ASF_YEC_PATTERN_LENGTH_R1_H+(port*0x80), TmpVal32);
+
+			/*  set ASF match enable register (incomming packets will redirect to ASF queue) */
+			SK_IN8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), &TmpVal8);
+			TmpVal8 = 0x50;    /*  enable pattern 4 and 6 (do not enable arp pattern) */
+			SK_OUT8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), TmpVal8);
+
+			/*  enable pattern pattno */
+			SK_IN8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), &TmpVal8);
+			TmpVal8 = 0x50;    /*  enable pattern 4 and 6 (do not enable arp pattern) */
+			SK_OUT8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), TmpVal8);
+
+			/*  enable Wake Up Frame Unit */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  delete bit 0 and 1 */
+			TmpVal16 |=  0x02;   /*  set bit 1 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+			break;
+
+		case SK_GEASF_MODE_DASH:
+		case SK_GEASF_MODE_DASH_ASF:
+			/*   currently only supported on Yukon Extreme */
+			if( pAC->FwApp.ChipMode != SK_GEASF_CHIP_SU )
+				break;
+
+			/*  see "problems.txt" note #344 */
+			/*  set MAC Rx fifo flush threshold register */
+			/*  (please refer also to note #yuk_hw01) */
+			SK_IN32(IoC, ASF_YEC_MAC_FIFO_FLUSHTHRES1+(port*0x80), &TmpVal32);
+			TmpVal32 &= ~0x7f;  /*  delete bit 6:0 */
+			TmpVal32 |= ASF_YLCI_MACRXFIFOTHRES;
+			SK_OUT32(IoC, ASF_YEC_MAC_FIFO_FLUSHTHRES1+(port*0x80), TmpVal32);
+			
+			/*  disable Wake Up Frame Unit before write to pattern ram */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  clear bit 0, bit1 */
+			TmpVal16 |=  0x01;   /*  set bit 0 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+
+			/*  write all 6 pattern  */
+			FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_ARP,  40, ARP_PATTERN_MASK, ARP_FRAME_PATTERN );
+			FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_ICMP, 40, ICMP_PATTERN_MASK, ICMP_FRAME_PATTERN );
+
+			/*  all UDP and TCP protocoll pattern will be setup by firmware */
+			/* FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_RMCP, 40, RMCP_PATTERN_MASK, RMCP_FRAME_PATTERN ); */
+			/* FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_RSP,  40, RSP_PATTERN_MASK, RSP_FRAME_PATTERN ); */
+			/* FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_TCP1, 40, TCP_PATTERN_MASK, TCP_FRAME_PATTERN1 ); */
+			/* FwWritePatternRamEx(pAC, IoC, port, ASF_DASH_PATTERN_NUM_TCP2, 40, TCP_PATTERN_MASK, TCP_FRAME_PATTERN2 ); */
+			
+			/* FwEnablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_TCP1 );		 */
+			/* FwEnablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_TCP2 );		 */
+			/* FwEnablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_RMCP );		 */
+			/* FwEnablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_RSP );		 */
+			
+			FwDisablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_ARP );		
+			FwDisablePattern( pAC, IoC, port, ASF_DASH_PATTERN_NUM_ICMP );		
+
+			/*  enable Wake Up Frame Unit */
+			SK_IN16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), &TmpVal16);
+			TmpVal16 &= ~0x03;   /*  delete bit 0 and 1 */
+			TmpVal16 |=  0x02;   /*  set bit 1 */
+			SK_OUT16(IoC, ASF_YEC_PATTERN_CTRL1+(port*0x80), TmpVal16);
+			break;
+			
+		default:
+			break;
+	}
+
+	return;
+}
+
+/*****************************************************************************
+*
+* FwWritePatternRam
+*
+* Description:  write to pattern ram
+*
+* Notes:        none
+*
+* Context:      none
+*
+* Returns:      1:  SUCCESS
+*               0:  ERROR
+*
+*/
+
+static SK_I8 FwWritePatternRam(
+SK_AC   *pAC,
+SK_IOC  IoC,
+SK_U8   Port,                       /* for future use   */
+SK_U8   PatternId1,                  /* 0..6             */
+SK_U8   PatternId2,                  /* 0..6             */
+SK_U8   Length1,                     /* 1..128 bytes     */
+SK_U8   Length2,                     /* 1..128 bytes     */
+SK_U8   *pMask1,
+SK_U8   *pPattern1,
+SK_U8   *pMask2,
+SK_U8   *pPattern2)
+
+{
+	SK_U8   i, j;
+	SK_I8   RetVal;
+	SK_U32  idx;
+	SK_U32  PattRamCluster[ASF_YEC_PATTRAM_CLUSTER_WORDS];
+	SK_U8   PattSrcByte1[2];     /*  2 pattern bytes to read/write in one cluster */
+	SK_U8   PattSrcByte2[2];     /*  2 pattern bytes to read/write in one cluster */
+	SK_U32  TmpVal32;
+	SK_U32  mask;
+
+	RetVal = 1;  /*   success */
+
+	/*  pattern size up to 128 bytes, pattern id can be 0...6 */
+	if ( (Length1 <= SK_POW_PATTERN_LENGTH) && (PatternId1 < SK_NUM_WOL_PATTERN) ) {
+
+		for (i = 0; (i < ASF_YEC_PATTRAM_CLUSTER_SIZE) && (RetVal == 1); i++) {
+			/*  pattern ram is organized into cluster (i is cluster index) */
+			/*  _after_ writing a whole cluster (= 128bit), the pattern will be written into ram! */
+
+			/*  read a cluster */
+			for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+				PattRamCluster[j] = 0;
+			}
+			/*  read source pattern 1 */
+			for (j=0; j < 2; j++) {
+				/*  we have 2 pattern bytes to read/write for one cluster */
+				/*  i is cluster index */
+				/*  j is byte index */
+				idx = 2*i+j;
+				if ( idx < Length1 ) {
+					/*  we can read from our pattern pointer */
+					PattSrcByte1[j] = pPattern1[idx];
+
+					/*  read from our enable mask pointer */
+					TmpVal32 = pMask1[idx/8];
+					mask     = 0x01 << (idx % 8);
+
+					if ( (TmpVal32 & mask) != 0 ) {
+						/*  enable byte */
+						PattRamCluster[j*2+1] |= (BIT_24 << PatternId1);
+					}
+					else {
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << PatternId1);
+					}
+				}
+				else {
+					/*  fill up with zeros */
+					PattSrcByte1[j] = 0;
+					/*  disable byte */
+					PattRamCluster[j*2+1] &= ~(BIT_24 << PatternId1);
+				}
+			}
+			/*  read source pattern 2 */
+			for (j=0; j < 2; j++) {
+				/*  we have 2 pattern bytes to read/write for one cluster */
+				/*  i is cluster index */
+				/*  j is byte index */
+				idx = 2*i+j;
+				if ( idx < Length2 ) {
+					/*  we can read from our pattern pointer */
+					PattSrcByte2[j] = pPattern2[idx];
+
+					/*  read from our enable mask pointer */
+					TmpVal32 = pMask2[idx/8];
+					mask     = 0x01 << (idx % 8);
+
+					if ( (TmpVal32 & mask) != 0 ) {
+						/*  enable byte */
+						PattRamCluster[j*2+1] |= (BIT_24 << PatternId2);
+					}
+					else {
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << PatternId2);
+					}
+				}
+				else {
+					/*  fill up with zeros */
+					PattSrcByte2[j] = 0;
+					/*  disable byte */
+					PattRamCluster[j*2+1] &= ~(BIT_24 << PatternId2);
+				}
+			}
+			/*  set our pattern into PattRamCluster[] */
+			if (PatternId1 >= 4) {
+				/*  upper words are interesting here */
+				idx = 1;
+			}
+			else {
+				/*  lower words are interesting here */
+				idx = 0;
+			}
+			/*  first byte */
+			mask = 0x000000ff;
+			j    = PatternId1 % 4;
+			PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+			mask = PattSrcByte1[0];
+			PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+			/*  second byte */
+			mask = 0x000000ff;
+			PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+			mask = PattSrcByte1[1];
+			PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+			/*  set our pattern into PattRamCluster[] */
+			if (PatternId2 >= 4) {
+				/*  upper words are interesting here */
+				idx = 1;
+			}
+			else {
+				/*  lower words are interesting here */
+				idx = 0;
+			}
+			/*  first byte */
+			mask = 0x000000ff;
+			j    = PatternId2 % 4;
+			PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+			mask = PattSrcByte2[0];
+			PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+			/*  second byte */
+			mask = 0x000000ff;
+			PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+			mask = PattSrcByte2[1];
+			PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+			/*  write a cluster */
+			/*  after writing the last cluster word, the hardware will trigger writing all cluster words */
+			for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+				idx = ASF_YEC_PATTRAM_CLUSTER_WORDS*ASF_YEC_PATTRAM_CLUSTER_BYTES*i + ASF_YEC_PATTRAM_CLUSTER_BYTES*j;
+				if( Port == 0 )  {
+					SK_OUT32( IoC, WOL_PATT_RAM_1+idx, PattRamCluster[j] );
+				}
+				else  {
+					SK_OUT32( IoC, WOL_PATT_RAM_2+idx, PattRamCluster[j] );
+				}
+			}
+		}
+	}
+	else {
+		RetVal = 0;  /*   error */
+	}
+
+	return(RetVal);
+}
+
+/*****************************************************************************
+*
+* FwWritePatternRamEx
+*
+* Description:  write to pattern ram
+*
+* Notes:        none
+*
+* Context:      none
+*
+* Returns:      1:  SUCCESS
+*               0:  ERROR
+*
+*/
+
+static SK_I8 FwWritePatternRamEx(
+SK_AC   *pAC,
+SK_IOC  IoC,
+SK_U8   Port,                        /* for future use   */
+SK_U8   PatternId ,                  /* 0..9             */
+SK_U8   Length ,                     /* 1..128 bytes     */
+SK_U8   *pMask ,
+SK_U8   *pPattern )
+
+{
+	SK_U8   i, j;
+	SK_I8   RetVal;
+	SK_U32  idx;
+	SK_U32  PattRamCluster[ASF_YEC_PATTRAM_CLUSTER_WORDS];
+	SK_U8   PattSrcByte[2];     /*  2 pattern bytes to read/write in one cluster */
+	SK_U32  TmpVal32;
+	SK_U32  mask;
+	SK_U8   TmpPatternId;
+	SK_U8   bank;
+	SK_U16  AsfYexPatternLengthReg;
+	
+	RetVal = 1;  /*   success */
+
+	/*  pattern size up to 128 bytes, pattern id can be 0...6 */
+	if ( Length <= SK_POW_PATTERN_LENGTH ) {
+		if ( PatternId < SK_NUM_WOL_PATTERN_EX ) {
+			
+			if( PatternId < SK_NUM_WOL_PATTERN )  {
+				TmpPatternId = PatternId;
+				bank = 0;
+			}
+			else  {
+				TmpPatternId = PatternId - SK_NUM_WOL_PATTERN;
+				bank = 1;
+			}
+
+			/*   select pattern bank */
+			SK_IN32( IoC, PAT_CSR, &TmpVal32 );
+			if( bank == 0 )
+				TmpVal32 &= ~(PAT_CSR_BSEL);
+			else
+				TmpVal32 |= PAT_CSR_BSEL;
+			SK_OUT32( IoC, PAT_CSR, TmpVal32 );
+
+			for (i = 0; (i < ASF_YEC_PATTRAM_CLUSTER_SIZE) && (RetVal == 1); i++) {
+				/*  pattern ram is organized into cluster (i is cluster index) */
+				/*  _after_ writing a whole cluster (= 128bit), the pattern will be written into ram! */
+
+				/*  read a cluster */
+				for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+					idx = ASF_YEC_PATTRAM_CLUSTER_WORDS*ASF_YEC_PATTRAM_CLUSTER_BYTES*i + ASF_YEC_PATTRAM_CLUSTER_BYTES*j;
+					if( Port == 0 )  {
+						SK_IN32( IoC, WOL_PATT_RAM_1+idx, &PattRamCluster[j] );
+					}
+					else  {
+						SK_IN32( IoC, WOL_PATT_RAM_2+idx, &PattRamCluster[j] );
+					}
+				}
+				/*  read source pattern  */
+				for (j=0; j < 2; j++) {
+					/*  we have 2 pattern bytes to read/write for one cluster */
+					/*  i is cluster index */
+					/*  j is byte index */
+					idx = 2*i+j;
+					if ( idx < Length ) {
+						/*  we can read from our pattern pointer */
+						PattSrcByte[j] = pPattern[idx];
+
+						/*  read from our enable mask pointer */
+						TmpVal32 = pMask[idx/8];
+						mask     = 0x01 << (idx % 8);
+
+						if ( (TmpVal32 & mask) != 0 ) {
+							/*  enable byte */
+							PattRamCluster[j*2+1] |= (BIT_24 << TmpPatternId);
+						}
+						else {
+							/*  disable byte */
+							PattRamCluster[j*2+1] &= ~(BIT_24 << TmpPatternId);
+						}
+					}
+					else {
+						/*  fill up with zeros */
+						PattSrcByte[j] = 0;
+						/*  disable byte */
+						PattRamCluster[j*2+1] &= ~(BIT_24 << TmpPatternId);
+					}
+				}
+				/*  set our pattern into PattRamCluster[] */
+				if (TmpPatternId >= 4) {
+					/*  upper words are interesting here */
+					idx = 1;
+				}
+				else {
+					/*  lower words are interesting here */
+					idx = 0;
+				}
+				/*  first byte */
+				mask = 0x000000ff;
+				j    = TmpPatternId % 4;
+				PattRamCluster[idx] &= ~(mask << 8 * j);    /*  delete byte in word */
+				mask = PattSrcByte[0];
+				PattRamCluster[idx] |= (mask << 8 * j);     /*  write pattern byte */
+				/*  second byte */
+				mask = 0x000000ff;
+				PattRamCluster[idx+2] &= ~(mask << 8 * j);  /*  delete byte in word */
+				mask = PattSrcByte[1];
+				PattRamCluster[idx+2] |= (mask << 8 * j);   /*  write pattern byte */
+
+				/*  write a cluster */
+				/*  after writing the last cluster word, the hardware will trigger writing all cluster words */
+				for (j=0; j < ASF_YEC_PATTRAM_CLUSTER_WORDS; j++) {
+					idx = ASF_YEC_PATTRAM_CLUSTER_WORDS*ASF_YEC_PATTRAM_CLUSTER_BYTES*i + ASF_YEC_PATTRAM_CLUSTER_BYTES*j;
+					if( Port == 0 )  {
+						SK_OUT32( IoC, WOL_PATT_RAM_1+idx, PattRamCluster[j] );
+					}
+					else  {
+						SK_OUT32( IoC, WOL_PATT_RAM_2+idx, PattRamCluster[j] );
+					}
+				}
+			}  /*   	for (i = 0; (i < ASF_YEC_PATTRAM_CLUSTER_SIZE) && (RetVal == 1); i++) */
+
+			/*   Set pattern length register */
+			AsfYexPatternLengthReg = ASF_YEX_PATTERN_LENGTH_R1_L+(Port*0x80)+( (PatternId/4)*sizeof(SK_U32) );
+			SK_IN32(IoC, AsfYexPatternLengthReg, &TmpVal32);		
+			TmpVal32 &= ~(0x0000007f << 8*(PatternId%4));			
+			TmpVal32 |= (Length-1) << 8*(PatternId%4);     /*  write length-1 to pattern length register */
+			SK_OUT32(IoC, AsfYexPatternLengthReg, TmpVal32);
+			
+		}  /*   if ( PatternId < SK_NUM_WOL_PATTERN_EX )  */
+		else  {
+			RetVal = 0;  /*   error */
+		}
+	}  /*    if ( Length1 <= SK_POW_PATTERN_LENGTH ) */
+	else {
+		RetVal = 0;  /*   error */
+	}
+	return(RetVal);
+}
+
+SK_I8 FwEnablePattern (
+	SK_AC   *pAC,
+	SK_IOC  IoC,
+	SK_U8   port,
+	SK_U8   pattno ) {
+
+	if (port > 1) {
+		return (1);
+	}
+
+	SK_DBG_MSG(	pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT | SK_DBGCAT_CTRL,
+				("*** FwEnablePattern Port:%d Patt#:%d OpMode:%d\n", port, pattno, pAC->FwApp.OpMode));
+
+	if( (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+		(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU))  {
+		SK_U16   val16;
+		
+		if( (pAC->FwApp.OpMode != SK_GEASF_MODE_DASH) &&
+			(pAC->FwApp.OpMode != SK_GEASF_MODE_DASH_ASF) )
+			pattno += 6;
+		
+		/*  set ASF match enable register (incomming packets will redirect to ASF queue) */
+		SK_IN16(IoC, ASF_YEX_PATTERN_MATCHENA1+(port*0x80), &val16);
+		val16 |= (0x01 << pattno);
+		SK_OUT16(IoC, ASF_YEX_PATTERN_MATCHENA1+(port*0x80), val16);
+
+		/*  enable pattern pattno */
+		SK_IN16(IoC, ASF_YEX_PATTERN_ENA1+(port*0x80), &val16);
+		val16 |= (0x01 << pattno);
+		SK_OUT16(IoC, ASF_YEX_PATTERN_ENA1+(port*0x80), val16);
+	}
+	else  {
+		SK_U8   val8;
+		pattno += 4;
+		/*  set ASF match enable register (incomming packets will redirect to ASF queue) */
+		SK_IN8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), &val8);
+		val8 |= (0x01 << pattno);
+		SK_OUT8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), val8);
+
+		/*  enable pattern pattno */
+		SK_IN8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), &val8);
+		val8 |= (0x01 << pattno);
+		SK_OUT8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), val8);
+	}
+	return ( 1 );
+}
+
+SK_I8 FwDisablePattern (
+	SK_AC   *pAC,
+	SK_IOC  IoC,
+	SK_U8   port,
+	SK_U8   pattno ) {
+
+	if (port > 1) {
+		return (1);
+	}
+
+	SK_DBG_MSG(	pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT | SK_DBGCAT_CTRL,
+				("*** FwDisablePattern Port:%d Patt#:%d OpMode:%d\n", port, pattno, pAC->FwApp.OpMode));
+
+	if( (pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+		(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU))  {
+		SK_U16   val16;
+
+		if( (pAC->FwApp.OpMode != SK_GEASF_MODE_DASH) &&
+			(pAC->FwApp.OpMode != SK_GEASF_MODE_DASH_ASF) )
+			pattno += 6;
+
+		/*  set ASF match disable register (incomming packets will redirect to ASF queue) */
+		SK_IN16(IoC, ASF_YEX_PATTERN_MATCHENA1+(port*0x80), &val16);
+		val16 &= ~(0x01 << pattno);
+		SK_OUT16(IoC, ASF_YEX_PATTERN_MATCHENA1+(port*0x80), val16);
+
+		/*  disable pattern pattno */
+		SK_IN16(IoC, ASF_YEX_PATTERN_ENA1+(port*0x80), &val16);
+		val16 &= ~(0x01 << pattno);
+		SK_OUT16(IoC, ASF_YEX_PATTERN_ENA1+(port*0x80), val16);
+	}
+	else  {
+		SK_U8   val8;
+		pattno += 4;
+		/*  set ASF match disable register (incomming packets will redirect to ASF queue) */
+		SK_IN8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), &val8);
+		val8 &= ~(0x01 << pattno);
+		SK_OUT8(IoC, ASF_YEC_PATTERN_MATCHENA1+(port*0x80), val8);
+
+		/*  disable pattern pattno */
+		SK_IN8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), &val8);
+		val8 &= ~(0x01 << pattno);
+		SK_OUT8(IoC, ASF_YEC_PATTERN_ENA1+(port*0x80), val8);
+	}
+	return ( 1 );
+}
+
diff -ruN linux/drivers/net/sk98lin/h/flash.h linux-new/drivers/net/sk98lin/h/flash.h
--- linux/drivers/net/sk98lin/h/flash.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/flash.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,88 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/h/flash.h#5 $
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools
+ * Version:	$Revision: #5 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains Flash-PROM interface function prototypes
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_FLASH_H
+#define __INC_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ******************************************************************/
+
+#define FT_AMD		0
+#define FT_INTEL	1
+#define FT_29		2
+/*
+ * Next flash type defined in skspi.h
+ * #define FT_SPI		3
+ */
+
+/* typedefs ******************************************************************/
+
+/* function prototypes *******************************************************/
+
+int calibrate(
+	SK_AC		*pAC);
+
+void init_flash(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	unsigned	rombase,
+	long		pages,
+	long		faddr);
+
+int flash_man_code(
+	SK_AC		*pAC,
+	SK_IOC		IoC);
+
+int program_flash(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*prom_data);
+
+int flash_verify(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data);
+
+int erase_flash(
+	SK_AC			*pAC,
+	SK_IOC			IoC);
+
+int read_from_flash(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	offs,
+	unsigned long	size);
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_FLASH_H */
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/h/fwapp.h linux-new/drivers/net/sk98lin/h/fwapp.h
--- linux/drivers/net/sk98lin/h/fwapp.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwapp.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,386 @@
+/******************************************************************************
+ *
+ * Name:    fwapp.h
+ * Project: fwapp
+ * Version: $Revision: #6 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware application support
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWAPP_H__
+#define __SK_FWAPP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+extern int     FwAppInit0(SK_AC *, SK_IOC);
+extern int     FwAppInit1(SK_AC *, SK_IOC);
+extern int     FwAppInit2(SK_AC *, SK_IOC);
+extern char    *FwAppGetImageName(SK_AC *);
+extern int     FwAppPatchImage(SK_AC *, SK_IOC);
+extern SK_BOOL FwAppIsVersionOk(SK_AC *);
+extern void    FwMainStateMachine(SK_AC *, SK_IOC);
+extern void    FwDriverHello(SK_AC *, SK_IOC);
+extern void    FwDriverGoodbye(SK_AC *, SK_IOC);
+extern void    FwRecoverFirmware(SK_AC *, SK_IOC);
+extern void    FwCheckLinkMode(SK_AC *, SK_IOC, int);
+extern void    FwCheckLinkState(SK_AC *, SK_IOC, int, SK_U16 *);
+extern int     FwHandleRmt(SK_AC *, SK_U32, char *, SK_U32);
+extern int     FwWriteRmt(SK_AC *);
+
+#define FW_API_VERSION      "V0.04"
+#define FW_API_VERSION_SIZE 5
+
+/*
+ * Recovery Message Table (RMT) definitions
+ */
+#define	RMT_MSG_ID_DEFAULT		0x00000000	/* Do just pass MSG to FW */
+#define	RMT_MSG_ID_RESET		0xffffffff	/* Clear RMT and pass MG to FW */
+
+#define FW_RMT_MESSAGE_SIZE		1024
+#define FW_RMT_ARRAY_SIZE		32
+#define FW_RMT_ARRAY_LAST_INDEX	(FW_RMT_ARRAY_SIZE - 1)
+
+typedef struct s_FW_RMT_MESSAGE FW_RMT_MESSAGE;
+struct s_FW_RMT_MESSAGE {
+	SK_U32	MessageIndex;
+	SK_U32	MessageID;
+	SK_U32	MessageLength;
+	SK_U8	Message[FW_RMT_MESSAGE_SIZE];
+};
+
+typedef struct s_FW_RMT FW_RMT;
+struct s_FW_RMT {
+	SK_BOOL			RmtFilled;
+	SK_BOOL			RecoverMessageTable;
+	FW_RMT_MESSAGE	RmtMessage[FW_RMT_ARRAY_SIZE];
+};
+
+#define FW_MAX_READTRY	10
+
+/* FW Recovery Message Table (RMT) debugging */
+#if 0
+#define FW_RMT_DEBUG
+#endif
+#if 0
+#define FW_RMT_VERBOSE_DEBUG
+#endif
+
+/* Defines for FW debugging */
+#define DEBUGFW								0x0001  /*   Dont't reset Processor (eg. during  check alive) */
+#define DEBUGFW_INIT_STOP					0x0002  /*   BRK in the ASF init function */
+#define DEBUGFW_FORCE_FW_DNLD				0x0004  /*   Force FW download */
+#define DEBUGFW_SMBUS_ANALYZER				0x0008  /*   Load SMBus analyzer firmware */
+#define DEBUGFW_ERASE_CONFIG		    	0x0010  /*   Load SMBus analyzer firmware */
+#define DEBUGFW_INIT_SKIP_ASF				0x0020
+#define DEBUGFW_INIT_STOP_CPU				0x0040  /*   BRK in the ASF init function */
+#define DEBUGFW_INIT_ENA_JTAG				0x0080  /*   Activates JTAG interface by writing 0x01 to 0xe67 register */
+#define DEBUGFW_DASH_MODE					0x0100  /*   As long as we have no GUI for setting the DASH mode we use this bit */
+#define DEBUGFW_SET_TEST_PATTERN			0x0200  /*   enables certain pattern for firmware testing */
+#define DEBUGFW_DISABLE_HW_WD           	0x0400  /*   Disables HW watchdog (needed for debugging) */
+#define DEBUGFW_DISABLE_API_RESET       	0x0800  /*   Disables API HW Reset function (needed for debugging) */
+#define DEBUGFW_ERASE_FLASH_DURING_UNLOAD   0x1000  /*   Removes firmware from flash during driver unload */
+#define DEBUGFW_SSL_CERTIFICATE_PATCH       0x2000  /*   Not used anymore !!! */
+
+/* Firmware commands */
+#define YASF_HOSTCMD_SYS_WILL_SLEEP         ((SK_U8)20)
+#define YASF_HOSTCMD_SYS_SA_UPDATE_COMPLETE ((SK_U8)21)
+
+/* ASF HCI Commands */
+#define YASF_HOSTCMD_ASF_INFO                   1
+#define YASF_HOSTCMD_LEG_CONF                   2
+#define YASF_HOSTCMD_ASF_CONF                   3
+#define YASF_HOSTCMD_RCTRL_CONF                 4
+#define YASF_HOSTCMD_KEEP_ALIVE                 5
+#define YASF_HOSTCMD_NEW_SEPROM_CONFIG          6
+#define YASF_HOSTCMD_ENTER_RAM_IDLE             7
+#define YASF_HOSTCMD_LEAVE_RAM_IDLE             8
+#define YASF_HOSTCMD_RUN_DIAG                   9
+#define YASF_HOSTCMD_RESET_STATE                10
+#define YASF_HOSTCMD_RESET                      11
+#define YASF_HOSTCMD_CHECK_ALIVE                12
+#define YASF_HOSTCMD_DRV_HELLO                  13
+#define YASF_HOSTCMD_DRV_GOODBYE                14
+#define YASF_HOSTCMD_DRV_STANDBY                15
+#define YASF_HOSTCMD_UPDATE_OWN_MACADDR         16
+#define YASF_HOSTCMD_ARP_RESOLVE                17
+#define YASF_HOSTCMD_RESET_COLD                 18
+#define YASF_HOSTCMD_ACPI_RMCP_DATA             19
+#define YASF_HOSTCMD_ACPI_ERROR                 20
+
+#define YASF_HOSTCMD_CFG_SET_ASF_ENABLE         100
+#define YASF_HOSTCMD_CFG_SET_RSP_ENABLE         101
+#define YASF_HOSTCMD_CFG_SET_RETRANS            102
+#define YASF_HOSTCMD_CFG_SET_RETRANS_INT        103
+#define YASF_HOSTCMD_CFG_SET_HB_ENABLE          104
+#define YASF_HOSTCMD_CFG_SET_HB_INT             105
+#define YASF_HOSTCMD_CFG_SET_IP_DESTINATION     106
+#define YASF_HOSTCMD_CFG_SET_IP_SOURCE          107
+#define YASF_HOSTCMD_CFG_SET_MAC_DESTINATION    108
+#define YASF_HOSTCMD_CFG_SET_COMMUNITY_NAME     109
+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_1          110
+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_2          111
+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_3          112
+#define YASF_HOSTCMD_CFG_SET_DRWD_ENABLE        113
+#define YASF_HOSTCMD_CFG_SET_DRWD_INT           114
+#define YASF_HOSTCMD_CFG_SET_WD_ENABLE          115
+#define YASF_HOSTCMD_CFG_SET_WD_INT             116
+#define YASF_HOSTCMD_CFG_SET_ASF_RAMSIZE        117
+#define YASF_HOSTCMD_CFG_SET_ACTIVE_PORT        118
+#define YASF_HOSTCMD_CFG_SET_DASH_ENABLE        119
+#define YASF_HOSTCMD_CFG_SET_DEBUG_INFO         120
+#define YASF_HOSTCMD_CFG_SET_USER_DATA			121
+#define YASF_HOSTCMD_CFG_SET_INIT_SEPROM		122
+#define YASF_HOSTCMD_CFG_SET_IP_INFO			123
+#define YASF_HOSTCMD_CFG_SET_EXT_IP_INFO       	124
+
+#define YASF_HOSTCMD_CFG_STORE_CONFIG           130
+#define YASF_HOSTCMD_CFG_ERASE_CONFIG           131
+
+#define YASF_HOSTCMD_CFG_GET_ASF_ENABLE         150
+#define YASF_HOSTCMD_CFG_GET_RSP_ENABLE         151
+#define YASF_HOSTCMD_CFG_GET_RETRANS            152
+#define YASF_HOSTCMD_CFG_GET_RETRANS_INT        153
+#define YASF_HOSTCMD_CFG_GET_HB_ENABLE          154
+#define YASF_HOSTCMD_CFG_GET_HB_INT             155
+#define YASF_HOSTCMD_CFG_GET_IP_DESTINATION     156
+#define YASF_HOSTCMD_CFG_GET_IP_SOURCE          157
+#define YASF_HOSTCMD_CFG_GET_MAC_DESTINATION    158
+#define YASF_HOSTCMD_CFG_GET_COMMUNITY_NAME     159
+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_1          160
+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_2          161
+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_3          162
+#define YASF_HOSTCMD_CFG_GET_DRWD_ENABLE        163
+#define YASF_HOSTCMD_CFG_GET_DRWD_INT           164
+#define YASF_HOSTCMD_CFG_GET_WD_ENABLE          165
+#define YASF_HOSTCMD_CFG_GET_WD_INT             166
+#define YASF_HOSTCMD_CFG_GET_ASF_RAMSIZE        167
+#define YASF_HOSTCMD_CFG_GET_FW_VERSION_STRING  168
+#define YASF_HOSTCMD_CFG_GET_SMBUS_INFOS        169
+#define YASF_HOSTCMD_CFG_GET_ACTIVE_PORT        170
+#define YASF_HOSTCMD_CFG_GET_FW_STATE 		    171
+#define YASF_HOSTCMD_CFG_GET_FW_MODE 		    172
+#define YASF_HOSTCMD_CFG_GET_USER_DATA			173
+#define YASF_HOSTCMD_CFG_GET_SSL_DATA			174
+#define YASF_HOSTCMD_CFG_READ_CONFIG            180
+#define YASF_HOSTCMD_CFG_GET_IP_INFO			181
+#define YASF_HOSTCMD_CFG_GET_EXT_IP_INFO        182
+
+/* ASF MIB default values */
+#define ASF_DEF_RETRANS_COUNT_MIN   0           /*  x1 */
+#define ASF_DEF_RETRANS_COUNT_MAX   255         /*  x1 */
+#define ASF_DEF_WATCHDOG_ENA        0           /*  */
+#define ASF_DEF_WATCHDOG_TIME       1200        /*  *100ms */
+#define ASF_DEF_WATCHDOG_TIME_MAX   36000       /*  *100ms */
+#define ASF_DEF_WATCHDOG_TIME_MIN   10          /*  *100ms */
+#define ASF_DEF_RETRANS_INT_MIN     0           /*  *100ms */
+#define ASF_DEF_RETRANS_INT_MAX     2550        /*  *100ms */
+#define ASF_DEF_HB_INT_MIN          10          /*  *100ms */
+#define ASF_DEF_HB_INT_MAX          2550        /*  *100ms */
+#define ASF_DEF_ASF_ENA             0
+#define ASF_DEF_RETRANS             2
+#define ASF_DEF_RETRANS_INT         10          /*  *100ms */
+#define ASF_DEF_HB_ENA              0
+#define ASF_DEF_HB_INT              600         /*  *100ms */
+
+/*  we need a buffer for 3 IP addresses and one char for DHCP enabled/disabled. */
+/*  4 = one IP address e.g. 255.255.255.255 */
+/*  THe data is stored as follows: */
+/* 				- bytes 0 - 3 IP address of the network adapter */
+/* 				- bytes 4 - 7 IP mask of the network adapter */
+/*  				- bytes 8 - 11 IP address of the DHCP server. */
+/* 				- byte 12		DHCP enable flag */
+#define SK_GEASF_IP_INFO_SIZE				13
+
+/* Defines */
+#define ASF_FW_ARP_RESOLVE                  /*   FW is resolving the destination IP addr */
+#define ASF_FW_WD                           /*   Driver is watching the FW */
+#define ASF_CHECK_HIDDEN_ID                 /*   ASF init checks hidden id */
+
+/* Operating modes of the asf driver */
+#define SK_GEASF_MODE_UNKNOWN               0       /*  unknown operation mode (initial) */
+#define SK_GEASF_MODE_ASF                   1       /*  asfec.bin binary found -> ASF operation */
+#define SK_GEASF_MODE_IPMI                  2       /*  ipmiy2.bin binary found -> IPMI operation */
+#define SK_GEASF_MODE_DASH                  3       /*  txdashsu.bin binary found -> DASH operation */
+#define SK_GEASF_MODE_DASH_ASF              4       /*  txdashsu.bin binary found -> ASF operation */
+#define SK_GEASF_MODE_DASH_ASF_MIXED        5       /*  txdashsu.bin binary found -> ASF/DASH mixed operation */
+#define SK_GEASF_MODE_EMBEDDED_SDK          6       /*  txbasesu.bin binary found -> PRINTER SDK FW */
+
+/* Chip modes for asf driver */
+#define SK_GEASF_CHIP_UNKNOWN               0       /*  bad chip id / hidden id */
+#define SK_GEASF_CHIP_EC                    1       /*  EC: ASF */
+#define SK_GEASF_CHIP_Y2                    2       /*  Yukon2 */
+#define SK_GEASF_CHIP_EX                    3       /*  Yukon Extreme */
+#define SK_GEASF_CHIP_SU                    4       /*  Yukon Supreme */
+
+/* Dual link mode */
+#define SK_GEASF_Y2_SINGLEPORT              1       /*  Yukon2 sigle link adapter */
+#define SK_GEASF_Y2_DUALPORT                2       /*  Yukon2 dual link adapter */
+
+#define ASF_GUI_TSF                         10      /* Time Scale Factor: 1s(GUI) <-> 10*100ms(FW) */
+
+#define ASF_MAX_STRLEN                      64
+
+/* Lengths used in get oid */
+#define ASF_ACPI_MAXBUFFLENGTH              1024     /*  max bytes for holding ACPI table */
+#define ASF_SMBIOS_MAXBUFFLENGTH            (1024*3) /*  max bytes for holding SMBIOS table */
+#define ASF_SMBUS_MAXBUFFLENGTH             128      /*  max bytes for holding SMBus info */
+#define ASF_FWVER_MAXBUFFLENGTH             84       /*  max stringlen for firmware version */
+
+#define SK_ASF_EVT_TIMER_EXPIRED            1       /* Counter overflow */
+#define SK_ASF_EVT_TIMER_SPI_EXPIRED        2       /* Counter overflow */
+#define SK_ASF_EVT_TIMER_HCI_EXPIRED        3       /* Counter overflow */
+
+/* ACPI module defines */
+#define ASF_ACPI_STATE_OK                       1
+#define ASF_ACPI_STATE_UNDEFINED                0
+#define ASF_ACPI_STATE_ERROR                    -1
+#define ASF_ACPI_STATE_ERROR_NO_RSDPTR          -2
+#define ASF_ACPI_STATE_ERROR_RSDT               -3
+#define ASF_ACPI_STATE_ERROR_XSDT               -4
+#define ASF_ACPI_STATE_ERROR_RSDT_NO_TABLE      -5
+#define ASF_ACPI_STATE_ERROR_RSDT_HEADER        -6
+#define ASF_ACPI_STATE_ERROR_ASF                -7
+#define ASF_ACPI_STATE_ERROR_ASF_HEADER         -8
+#define ASF_ACPI_STATE_ERROR_RSDT_NO_ASF_TABLE  -9
+#define ASF_ACPI_STATE_ERROR_FILE_OPEN          -10
+#define ASF_ACPI_STATE_ERROR_FILE_MAP           -11
+#define ASF_ACPI_STATE_ERROR_FILE_SIZE          -12
+#define ASF_ACPI_STATE_ERROR_FILE_CS            -13
+#define ASF_ACPI_STATE_ERROR_NO_UUID          	-14
+#define ASF_ACPI_STATE_ERROR_NO_SMBIOS_SM 	    -15
+#define ASF_ACPI_STATE_ERROR_NO_SMBIOS_SM_ADDR	-16
+#define ASF_ACPI_STATE_ERROR_NO_SMBIOS_SYS_INFO -17
+#define ASF_ACPI_STATE_ERROR_SMBIOS_TAB_LEN     -18
+
+#define ASF_FW_VERSION_STRING_SIZE	100
+#define RSP_KEYLENGTH           20
+
+/* VPD */
+#define ASF_VPD_MAX_CONFIG_SIZE	0x200  /*   512 byte */
+#define ASF_VPD_CONFIG_BASE     0x340
+#define ASF_VPD_CONFIG_SIZE     0x80
+#define ASF_VPD_DATA_BASE       0x3c0
+#define ASF_VPD_DATA_SIZE       0x40
+
+#define ASF_FLASH_SIZE_128K     (1024*128)
+#define ASF_FLASH_SIZE_256K     (1024*256)
+#define ASF_FLASH_SIZE_384K     (1024*384)
+
+#define ASF_MAX_FLASH_SIZE 		ASF_FLASH_SIZE_384K
+
+/*  Flash (SPI) VPD present */
+#define ASF_FLASH_SIZE          (1024*128)
+/*  Flash (SPI) NO VPD present */
+#define ASF_FLASH_NOVPD_SIZE    (1024*116)  /*   Code + ACPI data */
+
+/* Yukon EC etc. */
+#define ASF_FLASH_EC_OFFS          0x20000
+#define ASF_FLASH_EC_OFFS_VER      0x1fc00
+#define ASF_FLASH_EC_OFFS_REV      0x1fc0b
+#define ASF_FLASH_EC_OFFS_CS       0x1fffc
+#define ASF_FLASH_EC_OFFS_GUID     0x1f000
+#define ASF_FLASH_EC_OFFS_ACPI     0x1f010
+
+/*  Yukon Extreme  */
+#define ASF_FLASH_EX_OFFS          0x20000
+#define ASF_FLASH_EX_OFFS_VER      0x1cc00
+#define ASF_FLASH_EX_OFFS_REV      0x1cc0b
+#define ASF_FLASH_EX_OFFS_CS       0x1cffc
+#define ASF_FLASH_EX_OFFS_GUID     0x1c000
+#define ASF_FLASH_EX_OFFS_ACPI     0x1c010
+
+/*  Yukon Supreme  */
+#define ASF_FLASH_SU_SIZE    	   (1024*384)
+#define ASF_FLASH_SU_OFFS          0x00000
+#define ASF_FLASH_SU_OFFS_SMBIOS   0x5eb00
+#define ASF_FLASH_SU_OFFS_SSL_CERT 0x5e300
+/* #define ASF_FLASH_SU_OFFS_GUID     0x5f300 */
+/* #define ASF_FLASH_SU_OFFS_ACPI     0x5f310 */
+#define ASF_FLASH_SU_OFFS_GUID     0x5f700
+#define ASF_FLASH_SU_OFFS_ACPI     0x5f710
+#define ASF_FLASH_SU_OFFS_VER      0x5ff00
+#define ASF_FLASH_SU_OFFS_REV      0x5ff0b
+#define ASF_FLASH_SU_OFFS_CS       0x5fffc
+
+#define ASF_RESET_HOT           0
+#define ASF_RESET_COLD          1
+
+#define ASF_INIT_UNDEFINED      0
+#define ASF_INIT_OK             1
+#define ASF_INIT_ERROR          2
+#define ASF_INIT_ERROR_CHIP_ID  3
+#define ASF_INIT_ERROR_OPMODE   4
+
+/* Defines for FW state */
+#define ASF_FW_STATE_NEEDS_CONFIG				BIT_0
+#define ASF_FW_STATE_DISABLE_LAN_PORT			BIT_1
+#define ASF_FW_STATE_UPDATE_SSL_CERTIFICATE		BIT_2
+
+#define ASF_SSL_BUFFER_SIZE						1024
+#define	ASF_PFLASH_PART_INFO					0
+#define	ASF_PFLASH_PART_MAIN					1
+
+#define ASF_PORT_TRAFFIC_UNCHANGED		0
+#define ASF_PORT_TRAFFIC_STARTED		1
+#define ASF_PORT_TRAFIC_STOPPED			2
+
+struct _STR_ASF_MIB
+{
+    SK_U8       NewParam;
+    SK_U8       Ena;
+    SK_U8       RspEnable;
+};
+typedef struct _STR_ASF_MIB STR_ASF_MIB;
+
+/*
+ * FW application specific adapter context structure
+ */
+typedef struct s_FwApp {
+    SK_TIMER    AsfTimer;
+    SK_U8       DriverVersion[FW_API_VERSION_SIZE+1];
+    SK_U8       *FlashBuffer;
+    char        VpdConfigBuf[ASF_VPD_MAX_CONFIG_SIZE];
+    STR_ASF_MIB Mib;
+    STR_HCI     Hci;
+    SK_U8       GlHciState;
+    SK_U8       InitState;
+    SK_U8       VpdInitOk;
+    SK_U8       CpuAlive;
+    SK_U8       ActivePort;
+    SK_U8       OpMode;
+    SK_U8       ChipMode;
+    SK_U8       DualMode;
+    SK_U8       StandBy; 
+    SK_U8       PxeSPI;
+    SK_U8       FwState;
+    SK_U8       ToPatternCheck;
+    SK_U32      FlashSize;
+    SK_U32      FlashOffs;
+    SK_U32      SPIFlashSize;
+    FW_RMT      *pRMT;
+} SK_FWAPP;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWAPP_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwcommon.h linux-new/drivers/net/sk98lin/h/fwcommon.h
--- linux/drivers/net/sk98lin/h/fwcommon.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwcommon.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Name:    fwcommon.h
+ * Project: firmware common modules
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware common function
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWCOMMON_H__
+#define __SK_FWCOMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+#include "fwhci.h"
+#include "fwos.h"
+#include "fwapp.h"
+#include "fwimage.h"
+#include "fwptrn.h"
+#include "fwoids.h"
+#include "fwmain.h"
+
+
+
+/*  Return codes to the PNMI module  */
+#define SK_ASF_PNMI_ERR_OK              0
+#define SK_ASF_PNMI_ERR_GENERAL         1
+#define SK_ASF_PNMI_ERR_TOO_SHORT       2
+#define SK_ASF_PNMI_ERR_BAD_VALUE       3
+#define SK_ASF_PNMI_ERR_READ_ONLY       4
+#define SK_ASF_PNMI_ERR_UNKNOWN_OID     5
+#define SK_ASF_PNMI_ERR_UNKNOWN_INST    6
+#define SK_ASF_PNMI_ERR_UNKNOWN_NET     7
+#define SK_ASF_PNMI_ERR_NOT_SUPPORTED   10
+
+
+#define ASF_CPU_STATE_UNKNOWN       0
+#define ASF_CPU_STATE_RESET         1
+#define ASF_CPU_STATE_RUNNING       2
+
+
+
+typedef struct s_FwCommon {
+
+    SK_U8       ChipID;
+    char*       ImageName;
+    SK_U32      ImageSize;
+    char        FileVersion[5+1];
+    char        FlashVersion[5+1];
+    SK_U32      PatchNumber;
+    SK_PATCH    Patch[FW_MAX_PATCH_NUMBER];
+    SK_U32      VersionOffset; 
+    SK_U32      VersionLength;
+    SK_U32      ImageChkSum;
+    STR_HCI     Hci;
+
+} SK_FWCOMMON;
+
+
+/* Functions provided by SkGeAsf */
+
+/* ANSI/C++ compliant function prototypes */
+
+/*                                    
+ * Public Function prototypes
+ */
+extern int FwDeInit(SK_AC *pAC, SK_IOC IoC );
+extern int FwInit (SK_AC *pAC , SK_IOC IoC , int level);
+extern int FwDeInitStandBy( SK_AC *pAC, SK_IOC IoC );
+extern int FwInitStandBy( SK_AC *pAC, SK_IOC IoC, int Level );
+extern int FwGet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, SK_U32 *pLen);
+extern int FwPreSet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, SK_U32 *pLen);
+extern int FwSet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, SK_U32 *pLen);
+extern int FwEvent (SK_AC *pAC , SK_IOC IoC , SK_U32 Event , SK_EVPARA Param);
+extern int FwSetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
+extern int FwPreSetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
+extern int FwGetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWCOMMON_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwhci.h linux-new/drivers/net/sk98lin/h/fwhci.h
--- linux/drivers/net/sk98lin/h/fwhci.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwhci.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,161 @@
+/******************************************************************************
+ *
+ * Name:    fwhci.h
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware host communication interface
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWHCI_H__
+#define __SK_FWHCI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+/* ASF HCI Master */
+#define ASF_HCI_READ            0x08000000
+#define ASF_HCI_WRITE           0x04000000
+#define ASF_HCI_CMD_RD_READY    0x02000000
+#define ASF_HCI_CMD_WR_READY    0x01000000
+#define ASF_HCI_UNSUCCESS       0x00800000
+#define ASF_HCI_OFFSET          0x000000ff
+
+#define ASF_HCI_CMDREG          0x0e70
+#define ASF_HCI_DATAREG         0x0e78
+
+#define ASF_HCI_WAIT            1
+#define ASF_HCI_NOWAIT          0
+
+#ifdef DASH_APP
+#define ASF_HCI_WAIT_TICKS      10000
+#else
+#define ASF_HCI_WAIT_TICKS      1
+#endif
+
+/* #define ASF_HCI_TO              100     * 1s * */
+/* #define ASF_HCI_TO              500     * 5s * */
+#define ASF_HCI_TO              5000     /* WAR for DASH: 50s */
+
+#define HCI_EN_CMD_IDLE             0
+#define HCI_EN_CMD_WRITING          1
+#define HCI_EN_CMD_READING          2
+#define HCI_EN_CMD_WAIT             3
+#define HCI_EN_CMD_READY            4
+#define HCI_EN_CMD_ERROR            5
+#define HCI_EN_CMD_READY_END        6
+
+#define ASF_HCI_REC_BUF_SIZE    128
+#define ASF_HCI_TRA_BUF_SIZE    128
+
+/*  endianess depended macros */
+
+#define REVERSE_16(x)   ((((x)<<8)&0xff00) + (((x)>>8)&0x00ff))
+
+#define REVERSE_32(x)   ( ((((SK_U32)(x))<<24UL)&0xff000000UL) + \
+                          ((((SK_U32)(x))<< 8UL)&0x00ff0000UL) + \
+                          ((((SK_U32)(x))>> 8UL)&0x0000ff00UL) + \
+                          ((((SK_U32)(x))>>24UL)&0x000000ffUL) )
+
+#ifdef SK_LITTLE_ENDIAN
+#define LITTLEENDIAN_TO_HOST_16(x)	(x)
+#define LITTLEENDIAN_TO_HOST_32(x)	(x)
+#else
+#define LITTLEENDIAN_TO_HOST_16(x)	REVERSE_16(x)
+#define LITTLEENDIAN_TO_HOST_32(x)	REVERSE_32(x)
+#endif
+
+#ifdef DASH_APP
+#ifdef SK_LITTLE_ENDIAN
+#define NTOHS(x) REVERSE_16(x)
+#define HTONS(x) REVERSE_16(x)
+#define NTOHL(x) REVERSE_32(x)
+#define HTONL(x) REVERSE_32(x)
+#else
+#define NTOHS(x) (x)
+#define HTONS(x) (x)
+#define NTOHL(x) (x)
+#define HTONL(x) (x)
+#endif
+#endif
+
+typedef struct s_Hci
+{
+    SK_U32      To;
+    SK_U8       Status;
+    SK_U8       OldStatus;
+    SK_U32      OldCmdReg;
+    SK_U8       SendIndex;
+    SK_U8       ReceiveIndex;
+    SK_U8       SendLength;
+    SK_U8       ReceiveLength;
+    SK_U8       ExpectResponse;
+    SK_U8       Cycles;
+    SK_U64      Time;
+    SK_U8       ReceiveBuf  [ASF_HCI_REC_BUF_SIZE];
+    SK_U8       TransmitBuf [ASF_HCI_TRA_BUF_SIZE];
+    SK_TIMER    AsfTimerHci;
+} STR_HCI;
+
+#ifdef DASH_APP
+static SK_U16 FwRaw16ToPlain16(SK_U8 *data);
+static void FwPlain16ToRaw16(SK_U16 val, SK_U8 *data);
+static SK_U32 FwRaw32ToPlain32(SK_U8 *data);
+static void FwPlain32ToRaw32(SK_U32 val, SK_U8 *data);
+static SK_U64 FwRaw64ToPlain64(SK_U8 *data);
+static void FwPlain64ToRaw64(SK_U64 val, SK_U8 *data);
+static void FwPrintIpData(
+	SK_AC   *pAC,
+	SK_U32	Modules,
+	SK_U32	Categories);
+extern SK_U8 FwHciPrepareMessage(
+	SK_AC	*pAC,
+	SK_U8 	Cmd,
+	SK_U8	*pBuf,
+	SK_U8	BufLen );
+extern SK_U8 FwHciProcessData(SK_AC *pAC, SK_U8	Cmd, SK_U8 *pBuf );
+#endif /*DASH_APP */
+extern SK_U8 FwHciSendCommand(
+	SK_AC 	*pAC,
+	SK_IOC	IoC,
+	SK_U8	Command,
+	SK_U8	Par1,
+	SK_U8	Par2,
+	SK_U8	ExpectResponse,
+	SK_U8	Wait,
+	SK_U8	Retry );
+extern SK_U8 FwHciSendData(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U8	*Buffer,
+	SK_U8	ExpectResponse,
+	SK_U8	Wait,
+	SK_U8	Retry );
+extern void FwHciStateMachine(	SK_AC *pAC, SK_IOC IoC,	SK_U8 ToEna );
+extern SK_U8 FwHciGetData(SK_AC *pAC, SK_U8 **pHciRecBuf );
+extern SK_U8 FwHciGetState(SK_AC *pAC);
+extern SK_U8 FwHciFinishCommand(SK_AC *pAC, SK_IOC IoC);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWHCI_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwimage.h linux-new/drivers/net/sk98lin/h/fwimage.h
--- linux/drivers/net/sk98lin/h/fwimage.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwimage.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Name:    fwimage.h
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware image function
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWIMAGE_H__
+#define __SK_FWIMAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+#define FW_MAX_PATCH_NUMBER 10
+
+/*
+ * ASF specific adapter context structure
+ */
+typedef struct s_Patch{
+
+    SK_U8*  Ptr;
+    SK_U32  Offset; 
+    SK_U32  Size;
+
+}SK_PATCH;
+
+extern void  FwFreePatchMemory( SK_AC *pAC);
+extern void FwReadFwVersionFromFile( SK_AC *pAC, SK_FW_HANDLE fh);
+extern void FwAddPatch( SK_AC *pAC, SK_U32 Offset, SK_U32 Size, SK_U8 * Ptr);
+extern SK_U32 FwGetImageWord( SK_AC * pAC, SK_FW_HANDLE fh, SK_U32  Off);
+extern SK_U32 FwChkSumImage( SK_AC * pAC, SK_FW_HANDLE fh);
+extern SK_U32 FwGetFlashWord( SK_AC *pAC, SK_IOC IoC, SK_U32 Off);
+extern SK_U32 FwChkSumFlash( SK_AC *pAC, SK_IOC IoC);
+extern void	FwReadFwVersionFromFlash(  SK_AC *pAC, SK_IOC IoC);
+extern SK_BOOL FwIsImageInFlashOk( SK_AC *pAC, SK_IOC IoC, SK_U32 CSum);
+extern SK_BOOL FwIsImageNewer(SK_AC *pAC);
+extern SK_BOOL FwProgrammSPI(
+	SK_AC			*pAC,	/* Pointer to adapter context */
+	SK_IOC			IoC,	/* IO context handle */
+	SK_FW_HANDLE	fh,	/* image file handler */
+	SK_U32			ImageOff,
+	SK_U32			SPIOff,
+	SK_U32			Size);
+extern SK_BOOL FwProgrammPFlash(
+	SK_AC			*pAC,	/* Pointer to adapter context */
+	SK_IOC			IoC,	/* IO context handle */
+	SK_FW_HANDLE	fh,	/* image file handler */
+	SK_U32			ImageOff,
+	SK_U32			PFlashOff,
+	SK_U32			Size);
+extern SK_BOOL FwProgrammImage( SK_AC *pAC, SK_IOC IoC, SK_FW_HANDLE fh);
+extern SK_BOOL FwIsImageOk( SK_AC *pAC, SK_FW_HANDLE fh);
+extern SK_U32	FwGetSpiCheckSum( SK_AC *pAC, SK_IOC IoC);
+extern SK_U32	FwGetSpiCodeSize( SK_AC *pAC, SK_IOC IoC);
+extern SK_BOOL FwIsSpiOk( SK_AC *pAC, SK_IOC IoC);
+extern SK_BOOL FwIsFwInFlashOk( SK_AC *pAC, SK_IOC IoC);
+extern int FwRemoveFirmware( SK_AC   *pAC, SK_IOC  IoC);
+extern SK_U8 FwCheckSPI( SK_AC *pAC, SK_IOC IoC);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWIMAGE_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwmain.h linux-new/drivers/net/sk98lin/h/fwmain.h
--- linux/drivers/net/sk98lin/h/fwmain.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwmain.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,82 @@
+/******************************************************************************
+ *
+ * Name:    fwmain.h
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: common firmware interface for driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWMAIN_H__
+#define __SK_FWMAIN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+#define SKERR_ASF_E001      (SK_ERRBASE_ASF)
+#define SKERR_ASF_E001MSG   "SkAsfInit() error: wrong HCI version"
+#define SKERR_ASF_E002      (SKERR_ASF_E001+1)
+#define SKERR_ASF_E002MSG   "SkAsfInit() error: flash read"
+#define SKERR_ASF_E003      (SKERR_ASF_E001+2)
+#define SKERR_ASF_E003MSG   "SkAsfInit() error: flash erase"
+#define SKERR_ASF_E004      (SKERR_ASF_E001+3)
+#define SKERR_ASF_E004MSG   "SkAsfInit() error: flash write"
+#define SKERR_ASF_E005      (SKERR_ASF_E001+4)
+#define SKERR_ASF_E005MSG   "SkAsfInit() error: map FW image"
+#define SKERR_ASF_E006      (SKERR_ASF_E001+5)
+#define SKERR_ASF_E006MSG   "SkAsfInit() error: flash reread"
+#define SKERR_ASF_E007      (SKERR_ASF_E001+6)
+#define SKERR_ASF_E007MSG   "SkAsfInit() error: flash compare"
+#define SKERR_ASF_E008      (SKERR_ASF_E001+7)
+#define SKERR_ASF_E008MSG   "SkAsfInit() flash successfully updated"
+#define SKERR_ASF_E009      (SKERR_ASF_E001+8)
+#define SKERR_ASF_E009MSG   "SkAsfInit() updating flash"
+#define SKERR_ASF_E010      (SKERR_ASF_E001+9)
+#define SKERR_ASF_E010MSG   "SkAsfInit() CLOCK DIV"
+
+#define SK_FW_DBG(x)        0
+
+#define FW_DBG_MSG_IE(x)    SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT | SK_DBGCAT_ERR, x)
+#define FW_DBG_MSG_I(x)     SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_INIT, x)
+
+extern void FwInit0( SK_AC *pAC, SK_IOC IoC);
+extern void FwInit1( SK_AC *pAC, SK_IOC IoC);
+extern SK_BOOL FwRemoveImage( SK_AC *pAC, SK_IOC IoC);
+extern SK_BOOL FwInit2( SK_AC *pAC, SK_IOC IoC);
+extern int FwInit( SK_AC *pAC, SK_IOC IoC, int Level);
+extern int FwDeInit( SK_AC *pAC, SK_IOC IoC);
+extern int FwDeInitStandBy(SK_AC *pAC, SK_IOC IoC);
+extern int FwInitStandBy( SK_AC *pAC, SK_IOC IoC, int Level);
+extern int FwEvent( SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
+extern void FwResetCpu(	SK_AC *pAC, SK_IOC IoC);
+extern void FwSmartResetCpu( SK_AC *pAC, SK_IOC IoC, SK_U8 Cold);
+extern void FwStartCpu( SK_AC *pAC, SK_IOC IoC);
+extern void FwAsfEnable( SK_AC *pAC, SK_IOC IoC);
+extern void FwAsfDisable( SK_AC *pAC, SK_IOC IoC);
+extern SK_U8 FwCpuState( SK_AC *pAC, SK_IOC IoC);
+extern void FwSetOsPresentBit( SK_AC *pAC, SK_IOC IoC);
+extern void FwResetOsPresentBit( SK_AC *pAC, SK_IOC IoC);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWMAIN_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwoids.h linux-new/drivers/net/sk98lin/h/fwoids.h
--- linux/drivers/net/sk98lin/h/fwoids.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwoids.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,75 @@
+/******************************************************************************
+ *
+ * Name:    fwoids.h
+ * Project: fwcommon
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware sepcific oids handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWOIDS_H__
+#define __SK_FWOIDS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+int FwSetOid(
+            SK_AC *pAC, /* the adapter context */
+            SK_IOC IoC, /* I/O context */
+            SK_U32 Id,  /* OID  */
+            SK_U32 Inst,
+            SK_U8 *pBuf,
+            unsigned int *pLen);
+int FwGetOid(
+            SK_AC *pAC, /* the adapter context */
+            SK_IOC IoC, /* I/O context */
+            SK_U32 Id,  /* OID  */
+            SK_U32 Inst,
+            SK_U8 *pBuf,
+            unsigned int *pLen);
+int FwGet(
+            SK_AC *pAC,    /* the adapter context */
+            SK_IOC IoC, /* I/O context */
+            SK_U8 *pBuf,
+            unsigned int *pLen);
+int FwPreSet(
+			SK_AC *pAC, /* the adapter context */
+			SK_IOC IoC, /* I/O context */
+			SK_U8 *pBuf,
+			unsigned int *pLen);
+int FwPreSetOid(
+            SK_AC *pAC, /* the adapter context */
+            SK_IOC IoC, /* I/O context */
+            SK_U32 Id,  /* OID  */
+            SK_U32 Inst,
+            SK_U8 *pBuf,
+            unsigned int *pLen);
+int FwSet(
+            SK_AC *pAC, /* the adapter context */
+            SK_IOC IoC, /* I/O context */
+            SK_U8 *pBuf,
+            unsigned int *pLen);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWOIDS_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwos.h linux-new/drivers/net/sk98lin/h/fwos.h
--- linux/drivers/net/sk98lin/h/fwos.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwos.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,96 @@
+/******************************************************************************
+ *
+ * Name:    fwos.h
+ * Project: Gigabit Ethernet Adapters, Common Modules
+ * Version: $Revision: #5 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: Kernel mode file read functions.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWOS_H__
+#define __SK_FWOS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define SK_FW_HANDLE			struct file *
+
+#define FW_RECOVER_DELAY_VALUE		100000	/* ms * 1000 */
+#define FW_READ_DELAY_VALUE			20000	/* ms * 1000 */
+
+extern SK_FW_HANDLE FwOsOpenFile(SK_AC *, char *);
+extern int          FwOsCloseFile(SK_AC *, SK_FW_HANDLE);
+extern SK_U32       FwOsGetFileSize(SK_AC *, SK_FW_HANDLE);
+extern SK_U8        *FwOsAllocMemory(SK_AC *, size_t);
+extern int          FwOsFreeMemory(SK_AC *, SK_U8 *);
+extern int          FwOsFileRead(SK_AC *, SK_FW_HANDLE, SK_U8 *, SK_U32, SK_U32);
+extern void         FwOsSleep(int);
+
+/******************************************************************************
+ *
+ * Linux specific IOCTL defines and typedefs
+ *
+ ******************************************************************************/
+
+/* Embedded SDK driver ioctl */
+#define SK_IOCTL_GETLINKCAP  (SK_IOCTL_BASE + 14)
+#define SK_AUTONEG_SUCCESS 0
+#define SK_AUTONEG_FAIL    1
+#define SK_AUTONEG_OFF     2
+#define SK_AUTONEG_NOLINK  3
+
+/* Firmware ioctl defines and commands */
+#define SK_IOCTL_APPTOFW     (SK_IOCTL_BASE + 5)
+#define SK_IOCTL_APPTODRV    (SK_IOCTL_BASE + 6)
+#define SK_IOCTL_FW_SEND	1
+#define SK_IOCTL_FW_RECEIVE	2
+#define SK_IOCTL_COMMAND	5
+
+typedef struct s_FWIOCTL SK_GE_FWIOCTL;
+struct s_FWIOCTL {
+	unsigned int	Command;
+	unsigned int	Len;
+	char  __user	*pData;
+	SK_U32			ID;
+};
+
+/*******************************************************************************
+ *
+ * OS specific FW structure
+ *
+ ******************************************************************************/
+
+typedef struct s_FwOs {
+	char    *pFilePathName;
+	SK_U32  FileSize;
+	SK_U32  *pFileHandle;
+	SK_U8   *pFileData;
+#ifdef SK_USE_ISR_FW_ISR
+	SK_U8   *pFwData;
+#endif
+	int     FileIndex;
+} SK_FWOS;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __SK_FWOS_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/fwptrn.h linux-new/drivers/net/sk98lin/h/fwptrn.h
--- linux/drivers/net/sk98lin/h/fwptrn.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/fwptrn.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,85 @@
+/******************************************************************************
+ *
+ * Name:    fwptrn.h
+ * Project: firmware common modules
+ * Version: $Revision: #4 $
+ * Date:    $Date: 2010/11/04 $
+ * Purpose: firmware pattern function
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __SK_FWPTRN_H__
+#define __SK_FWPTRN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+/*   Yukon EC, etc... */
+#define ASF_YEC_YTB_BASE_WOL_CTRL1          ((SK_U32)0x0f20)                    /*  YTB WOL CTRL register link 1 */
+#define ASF_YEC_PATTRAM_CLUSTER_BYTES       ((SK_U8)4)    /*  4 bytes is a word */
+#define ASF_YEC_PATTRAM_CLUSTER_WORDS       ((SK_U8)4)    /*  4 words in a cluster */
+#define ASF_YEC_PATTRAM_CLUSTER_SIZE        ((SK_U8)64)   /*  pattern ram has 64 cluster */
+
+#define ASF_YEC_PATTERN_ENA1                (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x02)     /*  enable pattern register, width:8 */
+#define ASF_YEC_PATTERN_LENGTH_R1_L         (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x10)     /*  pattern length register, pattern 0-3, width: 4x8 */
+#define ASF_YEC_PATTERN_LENGTH_R1_H         (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x14)     /*  pattern length register, pattern 4-6, width: 3x8 */
+#define ASF_YEC_PATTERN_MATCHENA1           (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x0b)     /*  ASF/PME match enable register, width: 8 */
+#define ASF_YEC_PATTERN_CTRL1               (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x00)     /*  match result, match control, wol ctrl and status */
+
+#define ASF_YEC_YTB_BASE_MACRXFIFO1         ((SK_U32)0x0c40)                        /*  base of receive MAC fifo registers, port 1 */
+#define ASF_YEC_MAC_FIFO_CTRL1              (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x08)    /*  control/test Rx MAC, link1, 32 bit */
+#define ASF_YEC_MAC_FIFO_FLUSHMASK1         (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x0c)    /*  flush mask register Rx MAC, link1, 32 bit */
+#define ASF_YEC_MAC_FIFO_FLUSHTHRES1        (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x10)    /*  Rx MAC FIFO Flush Threshold, link1, 32 bit */
+
+#define ASF_YLCI_MACRXFIFOTHRES             8                                       /*  mac rx threshold in qwords */
+
+#define ASF_PATTERN_ID_RSP					0
+#define ASF_PATTERN_ID_ARP					1
+#define ASF_PATTERN_ID_RMCP					2
+
+/*   Yukon Extreme */
+#define ASF_YEX_YTB_BASE_WOL_CTRL1          ((SK_U32)0x0f20)                    /*  YTB WOL CTRL register link 1 */
+#define ASF_YEX_PATTRAM_CLUSTER_BYTES       ((SK_U8)4)    /*  4 bytes is a word */
+#define ASF_YEX_PATTRAM_CLUSTER_WORDS       ((SK_U8)4)    /*  4 words in a cluster */
+#define ASF_YEX_PATTRAM_CLUSTER_SIZE        ((SK_U8)64)   /*  pattern ram has 64 cluster */
+
+#define ASF_YEX_PATTERN_ENA1                (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x02)     /*  enable pattern register, width:8 */
+#define ASF_YEX_PATTERN_LENGTH_R1_L         (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x10)     /*  pattern length register, pattern 0-3, width: 4x8 */
+#define ASF_YEX_PATTERN_LENGTH_R1_H         (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x14)     /*  pattern length register, pattern 4-6, width: 3x8 */
+#define ASF_YEX_PATTERN_LENGTH_R1_EH        (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x18)     /*  pattern length register, pattern 7-8, width: 3x8 */
+#define ASF_YEX_PATTERN_MATCHENA1           (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x0c)     /*  ASF/PME match enable register, width: 8 */
+#define ASF_YEX_PATTERN_CTRL1               (ASF_YEX_YTB_BASE_WOL_CTRL1 + 0x00)     /*  match result, match control, wol ctrl and status */
+
+/*   Yukon Supreme */
+#define ASF_DASH_PATTERN_NUM_TCP 	13
+#define ASF_DASH_PATTERN_NUM_UDP	12
+#define ASF_DASH_PATTERN_NUM_ICMP	11
+#define ASF_DASH_PATTERN_NUM_ARP	10
+
+extern void FwCheckPattern(SK_AC *pAC, SK_IOC IoC, SK_U8 port );
+extern void FwSetUpPattern(SK_AC *pAC, SK_IOC IoC, SK_U8 port );
+extern SK_I8 FwEnablePattern (SK_AC *pAC, SK_IOC IoC, SK_U8 port, SK_U8 pattno);
+extern SK_I8 FwDisablePattern (SK_AC *pAC, SK_IOC IoC, SK_U8 port, SK_U8 pattno);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __SK_FWPTRN_H__ */
+
diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h
--- linux/drivers/net/sk98lin/h/lm80.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/lm80.h	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,180 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/lm80.h#6 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #6 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	Contains all defines for the LM80 Chip
+ *		(National Semiconductor).
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_LM80_H
+#define __INC_LM80_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * LM80 register definition
+ *
+ * All registers are 8 bit wide
+ */
+#define LM80_CFG			0x00	/* Configuration Register */
+#define LM80_ISRC_1			0x01	/* Interrupt Status Register 1 */
+#define LM80_ISRC_2			0x02	/* Interrupt Status Register 2 */
+#define LM80_IMSK_1			0x03	/* Interrupt Mask Register 1 */
+#define LM80_IMSK_2			0x04	/* Interrupt Mask Register 2 */
+#define LM80_FAN_CTRL		0x05	/* Fan Devisor/RST#/OS# Register */
+#define LM80_TEMP_CTRL		0x06	/* OS# Config, Temp Res. Reg */
+	/* 0x07 - 0x1f reserved	*/
+	/* current values */
+#define LM80_VT0_IN			0x20	/* current Voltage 0 value */
+#define LM80_VT1_IN			0x21	/* current Voltage 1 value */
+#define LM80_VT2_IN			0x22	/* current Voltage 2 value */
+#define LM80_VT3_IN			0x23	/* current Voltage 3 value */
+#define LM80_VT4_IN			0x24	/* current Voltage 4 value */
+#define LM80_VT5_IN			0x25	/* current Voltage 5 value */
+#define LM80_VT6_IN			0x26	/* current Voltage 6 value */
+#define LM80_TEMP_IN		0x27	/* current Temperature value */
+#define LM80_FAN1_IN		0x28	/* current Fan 1 count */
+#define LM80_FAN2_IN		0x29	/* current Fan 2 count */
+	/* limit values */
+#define LM80_VT0_HIGH_LIM	0x2a	/* high limit val for Voltage 0 */
+#define LM80_VT0_LOW_LIM	0x2b	/* low limit val for Voltage 0 */
+#define LM80_VT1_HIGH_LIM	0x2c	/* high limit val for Voltage 1 */
+#define LM80_VT1_LOW_LIM	0x2d	/* low limit val for Voltage 1 */
+#define LM80_VT2_HIGH_LIM	0x2e	/* high limit val for Voltage 2 */
+#define LM80_VT2_LOW_LIM	0x2f	/* low limit val for Voltage 2 */
+#define LM80_VT3_HIGH_LIM	0x30	/* high limit val for Voltage 3 */
+#define LM80_VT3_LOW_LIM	0x31	/* low limit val for Voltage 3 */
+#define LM80_VT4_HIGH_LIM	0x32	/* high limit val for Voltage 4 */
+#define LM80_VT4_LOW_LIM	0x33	/* low limit val for Voltage 4 */
+#define LM80_VT5_HIGH_LIM	0x34	/* high limit val for Voltage 5 */
+#define LM80_VT5_LOW_LIM	0x35	/* low limit val for Voltage 5 */
+#define LM80_VT6_HIGH_LIM	0x36	/* high limit val for Voltage 6 */
+#define LM80_VT6_LOW_LIM	0x37	/* low limit val for Voltage 6 */
+#define LM80_THOT_LIM_UP	0x38	/* hot temperature limit (high) */
+#define LM80_THOT_LIM_LO	0x39	/* hot temperature limit (low) */
+#define LM80_TOS_LIM_UP		0x3a	/* OS temperature limit (high) */
+#define LM80_TOS_LIM_LO		0x3b	/* OS temperature limit (low) */
+#define LM80_FAN1_COUNT_LIM	0x3c	/* Fan 1 count limit (high) */
+#define LM80_FAN2_COUNT_LIM	0x3d	/* Fan 2 count limit (low) */
+	/* 0x3e - 0x3f reserved	*/
+
+/*
+ * LM80 bit definitions
+ */
+
+/*	LM80_CFG		Configuration Register */
+#define LM80_CFG_START		(1<<0)	/* start monitoring operation */
+#define LM80_CFG_INT_ENA	(1<<1)	/* enables the INT# Interrupt output */
+#define LM80_CFG_INT_POL	(1<<2)	/* INT# pol: 0 act low, 1 act high */
+#define LM80_CFG_INT_CLR	(1<<3)	/* disables INT#/RST_OUT#/OS# outputs */
+#define LM80_CFG_RESET		(1<<4)	/* signals a reset */
+#define LM80_CFG_CHASS_CLR	(1<<5)	/* clears Chassis Intrusion (CI) pin */
+#define LM80_CFG_GPO		(1<<6)	/* drives the GPO# pin */
+#define LM80_CFG_INIT		(1<<7)	/* restore power on defaults */
+
+/*	LM80_ISRC_1		Interrupt Status Register 1 */
+/*	LM80_IMSK_1		Interrupt Mask Register 1 */
+#define LM80_IS_VT0			(1<<0)	/* limit exceeded for Voltage 0 */
+#define LM80_IS_VT1			(1<<1)	/* limit exceeded for Voltage 1 */
+#define LM80_IS_VT2			(1<<2)	/* limit exceeded for Voltage 2 */
+#define LM80_IS_VT3			(1<<3)	/* limit exceeded for Voltage 3 */
+#define LM80_IS_VT4			(1<<4)	/* limit exceeded for Voltage 4 */
+#define LM80_IS_VT5			(1<<5)	/* limit exceeded for Voltage 5 */
+#define LM80_IS_VT6			(1<<6)	/* limit exceeded for Voltage 6 */
+#define LM80_IS_INT_IN		(1<<7)	/* state of INT_IN# */
+
+/*	LM80_ISRC_2		Interrupt Status Register 2 */
+/*	LM80_IMSK_2		Interrupt Mask Register 2 */
+#define LM80_IS_TEMP		(1<<0)	/* HOT temperature limit exceeded */
+#define LM80_IS_BTI			(1<<1)	/* state of BTI# pin */
+#define LM80_IS_FAN1		(1<<2)	/* count limit exceeded for Fan 1 */
+#define LM80_IS_FAN2		(1<<3)	/* count limit exceeded for Fan 2 */
+#define LM80_IS_CI			(1<<4)	/* Chassis Intrusion occured */
+#define LM80_IS_OS			(1<<5)	/* OS temperature limit exceeded */
+	/* bit 6 and 7 are reserved in LM80_ISRC_2 */
+#define LM80_IS_HT_IRQ_MD	(1<<6)	/* Hot temperature interrupt mode */
+#define LM80_IS_OT_IRQ_MD	(1<<7)	/* OS temperature interrupt mode */
+
+/*	LM80_FAN_CTRL		Fan Devisor/RST#/OS# Register */
+#define LM80_FAN1_MD_SEL	(1<<0)	/* Fan 1 mode select */
+#define LM80_FAN2_MD_SEL	(1<<1)	/* Fan 2 mode select */
+#define LM80_FAN1_PRM_CTL	(3<<2)	/* Fan 1 speed control */
+#define LM80_FAN2_PRM_CTL	(3<<4)	/* Fan 2 speed control */
+#define LM80_FAN_OS_ENA		(1<<6)	/* enable OS mode on RST_OUT#/OS# pins*/
+#define LM80_FAN_RST_ENA	(1<<7)	/* sets RST_OUT#/OS# pins in RST mode */
+
+/*	LM80_TEMP_CTRL		OS# Config, Temp Res. Reg */
+#define LM80_TEMP_OS_STAT	(1<<0)	/* mirrors the state of RST_OUT#/OS# */
+#define LM80_TEMP_OS_POL	(1<<1)	/* select OS# polarity */
+#define LM80_TEMP_OS_MODE	(1<<2)	/* selects Interrupt mode */
+#define LM80_TEMP_RES		(1<<3)	/* selects 9 or 11 bit temp resulution*/
+#define LM80_TEMP_LSB		(0xf<<4)/* 4 LSBs of 11 bit temp data */
+#define LM80_TEMP_LSB_9		(1<<7)	/* LSB of 9 bit temperature data */
+
+	/* 0x07 - 0x1f reserved	*/
+/*	LM80_VT0_IN		current Voltage 0 value */
+/*	LM80_VT1_IN		current Voltage 1 value */
+/*	LM80_VT2_IN		current Voltage 2 value */
+/*	LM80_VT3_IN		current Voltage 3 value */
+/*	LM80_VT4_IN		current Voltage 4 value */
+/*	LM80_VT5_IN		current Voltage 5 value */
+/*	LM80_VT6_IN		current Voltage 6 value */
+/*	LM80_TEMP_IN		current temperature value */
+/*	LM80_FAN1_IN		current Fan 1 count */
+/*	LM80_FAN2_IN		current Fan 2 count */
+/*	LM80_VT0_HIGH_LIM	high limit val for Voltage 0 */
+/*	LM80_VT0_LOW_LIM	low limit val for Voltage 0 */
+/*	LM80_VT1_HIGH_LIM	high limit val for Voltage 1 */
+/*	LM80_VT1_LOW_LIM	low limit val for Voltage 1 */
+/*	LM80_VT2_HIGH_LIM	high limit val for Voltage 2 */
+/*	LM80_VT2_LOW_LIM	low limit val for Voltage 2 */
+/*	LM80_VT3_HIGH_LIM	high limit val for Voltage 3 */
+/*	LM80_VT3_LOW_LIM	low limit val for Voltage 3 */
+/*	LM80_VT4_HIGH_LIM	high limit val for Voltage 4 */
+/*	LM80_VT4_LOW_LIM	low limit val for Voltage 4 */
+/*	LM80_VT5_HIGH_LIM	high limit val for Voltage 5 */
+/*	LM80_VT5_LOW_LIM	low limit val for Voltage 5 */
+/*	LM80_VT6_HIGH_LIM	high limit val for Voltage 6 */
+/*	LM80_VT6_LOW_LIM	low limit val for Voltage 6 */
+/*	LM80_THOT_LIM_UP	hot temperature limit (high) */
+/*	LM80_THOT_LIM_LO	hot temperature limit (low) */
+/*	LM80_TOS_LIM_UP		OS temperature limit (high) */
+/*	LM80_TOS_LIM_LO		OS temperature limit (low) */
+/*	LM80_FAN1_COUNT_LIM	Fan 1 count limit (high) */
+/*	LM80_FAN2_COUNT_LIM	Fan 2 count limit (low) */
+	/* 0x3e - 0x3f reserved	*/
+
+#define LM80_ADDR		0x28	/* LM80 default addr */
+
+/* typedefs *******************************************************************/
+
+
+/* function prototypes ********************************************************/
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_LM80_H */
diff -ruN linux/drivers/net/sk98lin/h/mvyexhw.h linux-new/drivers/net/sk98lin/h/mvyexhw.h
--- linux/drivers/net/sk98lin/h/mvyexhw.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/mvyexhw.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,7595 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/mvyexhw.h#9 $
+ * Project:	Ethernet Adapters, Common Modules
+ * Version:	$Revision: #9 $, $Change: 5903 $
+ * Date:	$DateTime: 2011/03/29 15:10:31 $
+ * Purpose:	Defines and Macros for the Ethernet Adapter Product Family
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * This file was automatically generated by reg.pl (Rev. 1.55) using
+ *	Yukon_Extreme_Registers_Config.csv
+ *	Yukon_Extreme_Registers_Control.csv
+ *	Yukon_Extreme_Registers_GMAC.csv
+ *
+ ******************************************************************************/
+
+#ifndef __INC_MVYEXHW_H
+#define __INC_MVYEXHW_H
+
+#define	PCI_VEN_ID						0x0000	/* 16 bit	Vendor ID Register */
+#define	PCI_DEV_ID						0x0002	/* 16 bit	Device ID Register */
+#define	PCI_CMD							0x0004	/* 16 bit	Command Register */
+#define	PCI_STAT						0x0006	/* 16 bit	Status Register */
+#define	PCI_HW_REV_ID					0x0008	/*  8 bit	HW Revision ID */
+#define	PCI_PIF							0x0009	/*  8 bit	Programming	Interface
+												 *			Register, Lower	Byte
+												 */
+#define	PCI_SCC							0x000A	/*  8 bit	Sub-Class Register,
+												 *			Middle Byte
+												 */
+#define	PCI_BCC							0x000B	/*  8 bit	Base-Class Register,
+												 *			Upper Byte
+												 */
+#define	PCI_CLS							0x000C	/*  8 bit	Cache Line Size
+												 *			Register
+												 */
+#define	PCI_LAT_TIMER					0x000D	/*  8 bit	Latency Timer */
+#define	PCI_HDRTYP						0x000E	/*  8 bit	Header Type Register */
+#define	PCI_BI_ST						0x000F	/*  8 bit	Built-in Self Test */
+#define	PCI_BAR1_LO						0x0010	/* 32 bit	Base Address
+												 *			Register (1st),
+												 *			Lower Address
+												 */
+#define	PCI_BAR1_HI						0x0014	/* 32 bit	Base Address
+												 *			Register (1st),
+												 *			Upper Address
+												 */
+#define	PCI_BAR2						0x0018	/* 32 bit	Base Address
+												 *			Register (2nd)
+												 */
+#define	PCI_SSVEN_ID					0x002C	/* 16 bit	Subsystem Vendor ID
+												 *			Register
+												 */
+#define	PCI_SSDEV_ID					0x002E	/* 16 bit	Subsystem ID
+												 *			Register
+												 */
+#define	PCI_ERBAR						0x0030	/* 32 bit	Expansion Rom Base
+												 *			Address Register
+												 */
+#define	PCI_NCAP_PTR					0x0034	/*  8 bit	New Capabilities
+												 *			Pointer (New Cap
+												 *			Ptr) Register
+												 */
+#define	PCI_INT_LINE					0x003C	/*  8 bit	Interrupt Line
+												 *			Register
+												 */
+#define	PCI_INT_PIN						0x003D	/*  8 bit	Interrupt Pin
+												 *			Register
+												 */
+/* #define	PCI_MIN_GNT						0x003E	*  8 bit	Min_Gnt Register * */
+/* #define	PCI_MAX_LAT						0x003F	*  8 bit	Max_Lat Register * */
+#ifdef YUK_USB
+#define	PCI_OUR1						0x0940	/* 32 bit	Our Register 1 */
+#define	PCI_OUR2						0x0944	/* 32 bit	Our Register 2 */
+#else	/* !YUK_USB */
+#define	PCI_OUR1						0x0040	/* 32 bit	Our Register 1 */
+#define	PCI_OUR2						0x0044	/* 32 bit	Our Register 2 */
+#endif	/* !YUK_USB */
+/* #define	PCI_PM_CAP_ID					0x0048	*  8 bit	Power Management */
+/* 												 *			Capability ID */
+/* 												 *			Register (PM Cap ID) */
+/* 												 * */
+#define	PCI_PM_NXT_PTR					0x0049	/*  8 bit	Power Management
+												 *			Next Item Pointer
+												 *			Register
+												 */
+#define	PCI_PM_CAP						0x004A	/* 16 bit	Power Management
+												 *			Capabilities
+												 *			Register
+												 */
+#define	PCI_PM_CSR						0x004C	/* 16 bit	Power Management
+												 *			Control/Status
+												 *			Register
+												 */
+#define	PCI_PM_DATA						0x004F	/*  8 bit	Power Management
+												 *			Data Register
+												 */
+/* #define	PCI_VPD_CAP_ID					0x0050	*  8 bit	VPD Capability ID */
+/* 												 *			Register (VPD Cap */
+/* 												 *			ID) */
+/* 												 * */
+#define	PCI_VPD_NPTR					0x0051	/*  8 bit	VPD Next Item
+												 *			Pointer Register
+												 */
+#ifdef XXX	/* Naming Conflict with Linux */
+#define	PCI_VPD_ADDR					0x0052	/* 16 bit	VPD Address Register */
+#define	PCI_VPD_DATA					0x0054	/* 32 bit	VPD Data Register */
+#endif /* XXX */
+#ifdef YUK_USB
+#define	PCI_LDR_CTRL					0x0958	/* 32 bit	TWSI EEPROM Loader
+												 *			Control Register
+												 */
+#else	/* !YUK_USB */
+#define	PCI_LDR_CTRL					0x0058	/* 32 bit	TWSI EEPROM Loader
+												 *			Control Register
+												 */
+#endif	/* !YUK_USB */
+/* #define	PCI_MSI_CAP_ID					0x005C	*  8 bit	MSI Capability ID */
+/* 												 *			Register (MSI Cap */
+/* 												 *			ID) */
+/* 												 * */
+#define	PCI_MSI_NPTR					0x005D	/*  8 bit	MSI Next Item
+												 *			Pointer Register
+												 */
+/* #define	PCI_MSI_CTRL					0x005E	* 16 bit	MSI Message Control */
+/* 												 *			Register */
+/* 												 * */
+#define	PCI_MSI_ADDR_LO					0x0060	/* 32 bit	MSI Message Address
+												 *			Register, Lower
+												 *			Address
+												 */
+#define	PCI_MSI_ADDR_HI					0x0064	/* 32 bit	MSI Message Address
+												 *			Register, Upper
+												 *			Address
+												 */
+/* #define	PCI_MSI_DATA					0x0068	* 32 bit	MSI Message Data */
+/* 												 *			Register */
+/* 												 * */
+#define	PCIE_STAT						0x0070	/* 32 bit	PCI Express Status
+												 *			Register
+												 */
+#define	PCIE_OUR_STAT					0x007C	/* 32 bit	Our Status Reg. */
+
+#ifdef YUK_USB
+#define	PCIE_OUR3						0x0980	/* 32 bit	Our Register 3 */
+#define	PCIE_OUR4						0x0984	/* 32 bit	Our Register 4 */
+#define	PCIE_OUR5						0x0988	/* 32 bit	Our Register 5 */
+#define	PCIE_ER_MASK					0x008C	/* 32 bit	Error Reporting
+												 *			Mask Register
+												 */
+#define	CONFIG_REG0						0x0990	/* 32 bit	Config Register 0 */
+#define	CONFIG_REG1						0x0994	/* 32 bit	Config Register 1 */
+#define	PSM_CONFIG_REG0					0x0998	/* 32 bit	PSM Config Reg. 0 */
+#define	PSM_CONFIG_REG1					0x099C	/* 32 bit	PSM Config Reg. 1 */
+
+#define	VPD_CTRL_ADD					0x09A0	/* 32 bit	VPD Start End Address
+												 */
+#define	OTP_LDR_CTRL					0x09A4	/* 32 bit	OTP Loader Control
+												 */
+#define	OTP_MEM_CTRL_0					0x09A8	/* 32 bit	OTP Memory Control
+												 */
+#define	OTP_MEM_CTRL_1					0x09AC	/* 32 bit	OTP Memory Control
+												 */
+#define	OTP_MEM_CTRL_2					0x09B0	/* 32 bit	OTP Memory Control
+												 */
+#define	OTP_MEM_ST_0					0x09B4	/* 32 bit	OTP Memory Status
+												 */
+#define	VPD_CTRL						0x09B8	/* 32 bit	EEPROM and OTP
+												 */
+#define	OTP_MEM_CTRL_3					0x09BC	/* 32 bit	LDO Control Register */
+
+#define	FLASH_LDR_CTRL					0x09A4	/* 32 bit	Flash Loader Control
+												 */
+#define	LD_STATUS_0						0x09A8	/* 32 bit	Loader Status
+												 */
+#define	VPD_FLASH_CTRL					0x09B8	/* 32 bit	EEPROM and Flash Control
+												 */
+#else /* !YUK_USB */
+
+#define	PCIE_OUR3						0x0080	/* 32 bit	Our Register 3 */
+#define	PCIE_OUR4						0x0084	/* 32 bit	Our Register 4 */
+#define	PCIE_OUR5						0x0088	/* 32 bit	Our Register 5 */
+#define	PCIE_ER_MASK					0x008C	/* 32 bit	Error Reporting
+												 *			Mask Register
+												 */
+#define	CONFIG_REG0						0x0090	/* 32 bit	Config Register 0 */
+#define	CONFIG_REG1						0x0094	/* 32 bit	Config Register 1 */
+#define	PSM_CONFIG_REG0					0x0098	/* 32 bit	PSM Config Reg. 0 */
+#define	PSM_CONFIG_REG1					0x009C	/* 32 bit	PSM Config Reg. 1 */
+
+/* Yukon-FE+ */
+#define	VPD_CTRL_ADD					0x00A0	/* 32 bit	VPD Start End Address
+												 */
+#define	OTP_LDR_CTRL					0x00A4	/* 32 bit	OTP Loader Control
+												 */
+#define	OTP_MEM_CTRL_0					0x00A8	/* 32 bit	OTP Memory Control 0
+												 */
+#define	OTP_MEM_CTRL_1					0x00AC	/* 32 bit	OTP Memory Control 1
+												 */
+#define	OTP_MEM_CTRL_2					0x00B0	/* 32 bit	OTP Memory Control 2
+												 */
+#define	OTP_MEM_ST_0					0x00B4	/* 32 bit	OTP Memory Status
+												 */
+#define	VPD_CTRL						0x00B8	/* 32 bit	EEPROM and OTP Control
+												 */
+#define	OTP_MEM_CTRL_3					0x00BC	/* 32 bit	LDO Control Register */
+
+/* Yukon-Supreme */
+#define	FLASH_LDR_CTRL					0x00A4	/* 32 bit	Flash Loader Control
+												 */
+#define	LD_STATUS_0						0x00A8	/* 32 bit	Loader Status
+												 */
+#define	VPD_FLASH_CTRL					0x00B8	/* 32 bit	EEPROM and Flash Control
+												 */
+#endif /* !YUK_USB */
+
+#define	PCIE_CAP_ID						0x00C0	/*  8 bit	PE Capability ID
+												 */
+#define	PCIE_NPTR						0x00C1	/*  8 bit	PE Next Item Pointer
+												 */
+#define	PCIE_CAP						0x00C2	/* 16 bit	PE Capabilities
+												 */
+#define	DEVICE_CAPABILITIES_REGISTER	0x00C4	/* 32 bit	Device Capabilities
+												 */
+#define	PCIE_DEVCTRL					0x00C8	/* 16 bit	Device Control
+												 */
+#define	PCIE_DEVSTAT					0x00CA	/* 16 bit	Device Status
+												 */
+#define	PCIE_LNKCAP						0x00CC	/* 32 bit	Link Capabilities
+												 */
+#define	PCIE_LNKCTRL					0x00D0	/* 16 bit	Link Control
+												 */
+#define	PCIE_LNKSTAT					0x00D2	/* 16 bit	Link Status
+												 */
+#define	PCIE_DEV_CAP_2					0x00E4	/* 32 bit	Device Capabilities	2
+												 */
+#define	PCIE_DEV_CTRL_2					0x00E8	/* 32 bit	Device Control 2
+												 */
+#define	PCIE_AE_CAP_HDR					0x0100	/* 32 bit	Advanced Error
+												 *			Reporting
+												 *			Enhanced
+												 *			Capability Header
+												 *			Register
+												 */
+#define	PCIE_UE_STAT					0x0104	/* 32 bit	Uncorrectable Error
+												 *			Status Register
+												 */
+#define	PCIE_UE_MASK					0x0108	/* 32 bit	Uncorrectable Error
+												 *			Mask Register
+												 */
+#define	PCIE_UE_SVRT					0x010C	/* 32 bit	Uncorrectable Error
+												 *			Severity Register
+												 */
+#define	PCIE_CA_STAT					0x0110	/* 32 bit	Correctable Error
+												 *			Status Register
+												 */
+#define	PCIE_CA_MASK					0x0114	/* 32 bit	Correctable Error
+												 *			Mask Register
+												 */
+#define	PCIE_AE_CAPCTRL					0x0118	/* 32 bit	Advanced Error
+												 *			Capabilities and
+												 *			Control Register
+												 */
+#define	PCIE_HDRLOG_RNG_LO				0x011C 	/* Header Log Registers Start */
+#define	PCIE_HDRLOG_RNG_HI				0x0128	/* Header Log Registers End */
+#define	PCIE_DEVSERNUMCAP				0x0130	/* 32 bit	Device Serial
+												 *			Number Enhanced
+												 *			Capability Header
+												 */
+#define	PCIE_SERNUM_LOWDW				0x0134	/* 32 bit	Serial Number
+												 *			Register (Lower
+												 *			DW)
+												 */
+#define	PCIE_SERNUM_UPPDW				0x0138	/* 32 bit	Serial Number
+												 *			Register (Upper
+												 *			DW)
+												 */
+#define	PCIE_PWRBDGT_CAPHDR				0x0140	/* 32 bit	Power Budgeting
+												 *			Enhanced
+												 *			Capability Header
+												 */
+#define	PCIE_PWRBDGT_DATASEL			0x0144	/* 32 bit	Power Budgeting
+												 *			Data Select
+												 */
+#define	PCIE_PWRBDGT_DATA				0x0148	/* 32 bit	Power Budgeting
+												 *			Data Register
+												 */
+#define	PCIE_PWRBDGT_CAP				0x014C	/* 32 bit	Power Budgeting
+												 *			Capability
+												 */
+#ifdef YUK_USB
+#define	PSM_CONFIG_REG2					0x0A60	/* 32 bit	PSM Config Register 2 */
+#define	PSM_CONFIG_REG3					0x0A64	/* 32 bit	PSM Config Register 3 */
+#define	PSM_CONFIG_REG4					0x0A68	/* 32 bit	PSM Config Register 4 */
+#define	IO_CONFIG						0x0A6C	/* 32 bit	I/O Timing Control
+												 *			Register
+												 */
+#define	PCIE_TL_CTRL					0x0B00	/* 32 bit	Transaction Layer
+												 *			Control Register
+												 */
+#else	/* !YUK_USB */
+#define	PSM_CONFIG_REG2					0x0160	/* 32 bit	PSM Config Register 2 */
+#define	PSM_CONFIG_REG3					0x0164	/* 32 bit	PSM Config Register 3 */
+#define	PSM_CONFIG_REG4					0x0168	/* 32 bit	PSM Config Register 4 */
+#define	IO_CONFIG						0x016C	/* 32 bit	I/O Timing Control
+												 *			Register
+												 */
+#define	PCIE_TL_CTRL					0x0200	/* 32 bit	Transaction Layer
+												 *			Control Register
+												 */
+#endif	/* !YUK_USB */
+#define	PCIE_TL_STAT					0x0204	/* 32 bit	Transaction Layer
+												 *			Status Register
+												 */
+#define	PCIE_DL_CTRL					0x0208	/* 32 bit	Data Link Layer
+												 *			Control Register
+												 */
+#define	PCIE_DL_STAT					0x020C	/* 32 bit	Data Link Layer
+												 *			Status Register
+												 */
+#define	PCIE_PL_CTRL					0x0210	/* 32 bit	PE Physical Layer
+												 *			Control Register
+												 */
+#define	PCIE_PL_STAT					0x0214	/* 32 bit	PE Physical Layer
+												 *			Status Register
+												 */
+#define	PCIE_CPLTO						0x0220	/* 32 bit	PE Completion
+												 *			Timeout Register
+												 */
+#define	PCIE_FC							0x0224	/* 32 bit	PE Flow Control
+												 *			Register
+												 */
+#define	PCIE_ACKTIM_X1					0x0228	/* 32 bit	PE Ack Timer for 1x
+												 *			Link Register
+												 */
+
+/*
+ *	THE BIT DEFINES
+ */
+/*	PCI_VEN_ID				0x0000	Vendor ID Register */
+#define	PCI_VEN_ID_MSK		SHIFT0(0xffffU)	/* Vendor ID */
+#define	PCI_VEN_ID_BASE		0
+
+/*	PCI_DEV_ID				0x0002	Device ID Register */
+#define	PCI_DEV_ID_MSK		SHIFT0(0xffffU)	/* Device ID */
+#define	PCI_DEV_ID_BASE		0
+
+/*	PCI_CMD					0x0004	Command Register */
+/*		Bit(s) PCI_CMD_RSRV_15_11 reserved */
+#define	PCI_CMD_INT_DIS				BIT_10S			/* Interrupt Disable */
+/*		Bit(s) PCI_CMD_RSRV_9 reserved */
+#define	PCI_CMD_SERR_ENA			BIT_8S			/* SERR Enable */
+/*		Bit(s) PCI_CMD_RSRV_7 reserved */
+#define	PCI_CMD_PERREN				BIT_6S			/* Parity Error Response */
+/*		Bit(s) PCI_CMD_RSRV_5_3 reserved */
+#define	PCI_CMD_BMEN				BIT_2S			/* Bus Master Enable */
+#define	PCI_CMD_MEMEN				BIT_1S			/* Memory Space Access Enable */
+#define	PCI_CMD_IOEN				BIT_0S			/* I/O Space Access Enable */
+
+/*	PCI_STAT				0x0006	Status Register */
+#define	PCI_STAT_PERR				BIT_15S			/* Parity Error */
+#define	PCI_STAT_SERR				BIT_14S			/* Signaled SERRn */
+#define	PCI_STAT_RMABORT			BIT_13S			/* Received Master Abort */
+#define	PCI_STAT_RTABORT			BIT_12S			/* Received Target Abort */
+/*		Bit(s) PCI_STAT_RSRV_11_9 reserved */
+#define	PCI_STAT_DATAPERR			BIT_8S			/* Data Parity Error Detected */
+/*		Bit(s) PCI_STAT_RSRV_7_5 reserved */
+#define	PCI_STAT_NEWCAP				BIT_4S			/* New Capabilities Bit */
+#define	PCI_STAT_INTSTA				BIT_3S			/* Interrupt Message Pending */
+/*		Bit(s) PCI_STAT_RSRV_2_0 reserved */
+
+/*	PCI_REV_ID				0x0008	Revision ID Register */
+#define	PCI_REV_ID_MSK		SHIFT0(0xffU)	/* Revision ID */
+#define	PCI_REV_ID_BASE		0
+
+/*	PCI_PIF					0x0009	Programming Interface Register, Lower Byte */
+#define	PCI_PIF_MSK			SHIFT0(0xffU)	/* Prog Interface */
+#define	PCI_PIF_BASE		0
+
+/*	PCI_SCC					0x000A	Sub-Class Register, Middle Byte */
+#define	PCI_SCC_MSK			SHIFT0(0xffU)	/* Sub Class */
+#define	PCI_SCC_BASE		0
+
+/*	PCI_BCC					0x000B	Base-Class Register, Upper Byte */
+#define	PCI_BCC_MSK			SHIFT0(0xffU)	/* Base Class */
+#define	PCI_BCC_BASE		0
+
+/*	PCI_CLS					0x000C	Cache Line Size Register */
+/*		Bit(s) PCI_CLS_RSRV_7_0 reserved */
+
+/*	PCI_LAT_TIM				0x000D	Latency Timer Register */
+/*		Bit(s) PCI_LAT_TIM_RSRV_7_0 reserved */
+
+/*	PCI_HDRTYP				0x000E	Header Type Register */
+/*		Bit(s) PCI_HDRTYP_RSRV_7_0 reserved */
+
+/*	PCI_BIST				0x000F	Built-in Self Test (BIST) Register */
+/*		Bit(s) PCI_BIST_RSRV_7_0 reserved */
+
+/*	PCI_BAR1_LO				0x0010	Base Address Register (1st), Lower Address */
+#define	PCI_BAR1_LO_BASE_MSK		SHIFT14(0x3ffffUL)	/* Lower MEMBASE Address */
+#define	PCI_BAR1_LO_BASE_BASE		14
+#define	PCI_BAR1_LO_SIZE_MSK		SHIFT4(0x3ff)		/* Memory Size Requirements */
+#define	PCI_BAR1_LO_SIZE_BASE		4
+#define	PCI_BAR1_LO_PREFEN			BIT_3				/* Prefetch Enable */
+#define	PCI_BAR1_LO_TYPE_MSK		SHIFT1(0x3)			/* Memory Type */
+#define	PCI_BAR1_LO_TYPE_BASE		1
+#define	PCI_BAR1_LO_IO_SPC			BIT_0				/* Memory Space Indicator */
+
+/*	PCI_BAR1_HI				0x0014	Base Address Register (1st), Upper Address */
+#define	PCI_BAR1_HI_BASE_MSK		SHIFT0(0xffffffff)	/* Upper MEMBASE */
+#define	PCI_BAR1_HI_BASE_BASE		0
+
+/*	PCI_BAR2				0x0018	Base Address Register (2nd) */
+#define	PCI_BAR2_BASE_MSK		SHIFT8(0xffffff)	/* I/O Base Address MSb */
+#define	PCI_BAR2_BASE_BASE		8
+#define	PCI_BAR2_SIZE_MSK		SHIFT2(0x3f)		/* I/O Size Requirements */
+#define	PCI_BAR2_SIZE_BASE		2
+/*		Bit(s) PCI_BAR2_RSRV_1 reserved */
+#define	PCI_BAR2_IO_SPC			BIT_0				/* I/O Space Indicator */
+
+/*	PCI_SSVEN_ID			0x002C	Subsystem Vendor ID Register */
+#define	PCI_SSVEN_ID_MSK		SHIFT0(0xffffU)	/* Subsystem Vendor ID */
+#define	PCI_SSVEN_ID_BASE		0
+
+/*	PCI_SSDEV_ID			0x002E	Subsystem ID Register */
+#define	PCI_SSDEV_ID_MSK		SHIFT0(0xffffU)	/* Subsystem ID */
+#define	PCI_SSDEV_ID_BASE		0
+
+/*	PCI_ERBAR				0x0030	Expansion Rom Base Address Register */
+#define	PCI_ERBAR_BASE_MSK				SHIFT17(0x7fffUL)	/* ROM Base Address MSb */
+#define	PCI_ERBAR_BASE_BASE				17
+#define	PCI_ERBAR_BASE_SIZE_MSK			SHIFT14(0x7UL)		/* Rombase/size */
+#define	PCI_ERBAR_BASE_SIZE_BASE		14
+#define	PCI_ERBAR_SIZE_MSK				SHIFT11(0x7)		/* ROM Size Requirements */
+#define	PCI_ERBAR_SIZE_BASE				11
+/*		Bit(s) PCI_ERBAR_RSRV_10_1 reserved */
+#define	PCI_ERBAR_ENA					BIT_0			/* Address Decode Enable */
+
+/*	PCI_NCAP_PTR			0x0034	New Capabilities Pointer (New Cap Ptr)
+ *									Register
+ */
+#define	PCI_NCAP_PTR_MSK		SHIFT0(0xffU)	/* New Capabilities Pointer */
+#define	PCI_NCAP_PTR_BASE		0
+
+/*	PCI_INT_LINE			0x003C	Interrupt Line Register */
+#define	PCI_INT_LINE_MSK		SHIFT0(0xffU)	/* Interrupt Line */
+#define	PCI_INT_LINE_BASE		0
+
+/*	PCI_INT_PIN				0x003D	Interrupt Pin Register */
+#define	PCI_INT_PIN_MSK			SHIFT0(0xffU)	/* Interrupt Pin */
+#define	PCI_INT_PIN_BASE		0
+
+/*	PCI_MIN_GNT				0x003E	Min_Gnt Register */
+/*		Bit(s) PCI_MIN_GNT_RSRV_7_0 reserved */
+
+/*	PCI_MAX_LAT				0x003F	Max_Lat Register */
+/*		Bit(s) PCI_MAX_LAT_RSRV_7_0 reserved */
+
+/*	PCI_OUR1				0x0040	Our Register 1 */
+/*		Bit(s) PCI_OUR1_RSRV_31 reserved */
+#define	PCI_OUR1_SW_POR					BIT_30			/* Software Power-on-reset */
+/* Enable Generation Preset during Software POR */
+#define	PCI_OUR1_EN_GEN_PRSET			BIT_29
+#define	PCI_OUR1_GP_COMA				BIT_28			/* Set PHY to Coma Mode */
+#define	PCI_OUR1_DIS_SPI_LOAD			BIT_27			/* Disable SPI Loader */
+#define	PCI_OUR1_GP_PWD					BIT_26			/* PHY Power Down Mode */
+#define	PCI_OUR1_DIS_VPD_LOAD			BIT_25			/* Disable VPD Loader */
+#define	PCI_OUR1_ENBOOT					BIT_24			/* Enable Boot */
+#define	PCI_OUR1_ENIOMAP				BIT_23			/* Enable I/O Mapping */
+#define	PCI_OUR1_ENEPROM				BIT_22			/* Enable Eprom */
+/* Pagesize[1:0]/SPI Flash Memory */
+#define	PCI_OUR1_PAGE_SIZ_MSK			SHIFT20(0x3UL)
+#define	PCI_OUR1_PAGE_SIZ_BASE			20
+
+/* Yukon-Supreme */
+#define	PCI_OUR1_ROM_SRC_SEL			BIT_19			/* ROM Source Select */
+#define	PCI_OUR1_PAGE_SEL_MSK			SHIFT16(0x7UL)	/* Page Register[2:0] */
+#define	PCI_OUR1_PAGE_SEL_BASE			16
+#define	PCI_OUR1_DBG_PEX_PME			BIT_15			/* Debug PCI Express PME */
+/*		Bit(s) PCI_OUR1_RSRV_14_10 reserved */
+/* Timer for GPHY Link Trigger */
+#define	PCI_OUR1_GP_TRIG_TIM_MSK		SHIFT8(0x3)
+#define	PCI_OUR1_GP_TRIG_TIM_BASE		8
+#define	PCI_OUR1_L1_EVT_ENA				BIT_7			/* L1 Event Enable */
+#define	PCI_OUR1_GP_LNK_ENA				BIT_6			/* Enable GPHY Link */
+#define	PCI_OUR1_FORCE_L1				BIT_5			/* Force to L1 */
+/*		Bit(s) PCI_OUR1_RSRV_4_1 reserved */
+/* PCIe Receiver Overflow Control */
+#define	PCI_OUR1_PEX_RX_OF_CTRL			BIT_0
+
+/*	PCI_OUR2				0x0044	Our Register 2 */
+/*		Bit(s) PCI_OUR2_RSRV_31_24 reserved */
+#define	PCI_OUR2_VPD_DEVSEL_MSK			SHIFT17(0x7fUL)	/* VPD Devsel */
+#define	PCI_OUR2_VPD_DEVSEL_BASE		17
+#define	PCI_OUR2_VPD_ROMSIZE_MSK		SHIFT14(0x7UL)	/* VPD ROM Size */
+#define	PCI_OUR2_VPD_ROMSIZE_BASE		14
+/*		Bit(s) PCI_OUR2_RSRV_13_0 reserved */
+
+/*	PCI_PM_CAP_ID			0x0048	Power Management Capability ID Register
+ *									(PM Cap ID)
+ */
+#define	PCI_PM_CAP_ID_MSK		SHIFT0(0xffU)	/* Power Management Capabilities ID */
+#define	PCI_PM_CAP_ID_BASE		0
+
+/*	PCI_PM_NXT_PTR			0x0049	Power Management Next Item Pointer Register */
+#define	PCI_PM_NXT_PTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
+#define	PCI_PM_NXT_PTR_BASE		0
+
+/*	PCI_PM_CAP				0x004A	Power Management Capabilities Register */
+/* D3 Cold Power Management Event Support */
+#define	PCI_PM_CAP_D3C_ENA				BIT_15S
+/* D3 Hot Power Management Event Support */
+#define	PCI_PM_CAP_D3H_ENA				BIT_14S
+/* D2 Power Management Event Support */
+#define	PCI_PM_CAP_D2_ENA				BIT_13S
+/* D1 Power Management Event Support */
+#define	PCI_PM_CAP_D1_ENA				BIT_12S
+/* D0 Power Management Event Support */
+#define	PCI_PM_CAP_D0_ENA				BIT_11S
+#define	PCI_PM_CAP_D2_SUP				BIT_10S			/* D2 Support */
+#define	PCI_PM_CAP_D1_SUP				BIT_9S			/* D1 Support */
+/*		Bit(s) PCI_PM_CAP_RSRV_8_6 reserved */
+/* Device Specific Initialization */
+#define	PCI_PM_CAP_DSI_ENA				BIT_5S
+/*		Bit(s) PCI_PM_CAP_RSRV_4_3 reserved */
+#define	PCI_PM_CAP_VER_ID_MSK			SHIFT0(0x7U)	/* Version */
+#define	PCI_PM_CAP_VER_ID_BASE			0
+
+/*	PCI_PM_CSR				0x004C	Power Management Control/Status Register */
+#define	PCI_PM_CSR_PME_STAT				BIT_15S			/* PME Status */
+#define	PCI_PM_CSR_D_SCALE_MSK			SHIFT13(0x3U)	/* Data Scale */
+#define	PCI_PM_CSR_D_SCALE_BASE			13
+#define	PCI_PM_CSR_D_SEL_MSK			SHIFT9(0xfU)	/* Data Select */
+#define	PCI_PM_CSR_D_SEL_BASE			9
+#define	PCI_PM_CSR_PME_EN				BIT_8S			/* PME En */
+/*		Bit(s) PCI_PM_CSR_RSRV_7_2 reserved */
+#define	PCI_PM_CSR_PWST_MSK				SHIFT0(0x3U)	/* Power State */
+#define	PCI_PM_CSR_PWST_BASE			0
+
+/*	PCI_PM_DATA				0x004F	Power Management Data Register */
+#define	PCI_PM_DATA_MSK			SHIFT0(0xffU)	/* Data */
+#define	PCI_PM_DATA_BASE		0
+
+/*	PCI_VPD_CAP_ID			0x0050	VPD Capability ID Register (VPD Cap ID) */
+#define	PCI_VPD_CAP_ID_MSK		SHIFT0(0xffU)	/* VPD Capabilities ID */
+#define	PCI_VPD_CAP_ID_BASE		0
+
+/*	PCI_VPD_NPTR			0x0051	VPD Next Item Pointer Register */
+#define	PCI_VPD_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
+#define	PCI_VPD_NPTR_BASE		0
+
+/*	PCI_VPD_ADDR			0x0052	VPD Address Register */
+#define	PCI_VPD_ADDR_FLAG		BIT_15S			/* Flag */
+#define	PCI_VPD_ADDR_MSK		SHIFT0(0x7fffU)	/* VPD Address */
+#define	PCI_VPD_ADDR_BASE		0
+
+/*	PCI_VPD_DATA			0x0054	VPD Data Register */
+#define	PCI_VPD_DATA_MSK		SHIFT0(0xffffffff)	/* VPD Data */
+#define	PCI_VPD_DATA_BASE		0
+
+/*	PCI_LDR_CTRL			0x0058	TWSI EEPROM Loader Control Register */
+#define	PCI_LDR_CTRL_FLAG				BIT_31			/* Flag */
+/* TWSI EEPROM Loader Address */
+#define	PCI_LDR_CTRL_ADDR_TWSI_MSK		SHIFT16(0x7fffUL)
+#define	PCI_LDR_CTRL_ADDR_TWSI_BASE		16
+/* EEPROM Loader Start Address for PCI Loader */
+#define	PCI_LDR_CTRL_ADDR_PCI_MSK		SHIFT8(0xff)
+#define	PCI_LDR_CTRL_ADDR_PCI_BASE		8
+/* EEPROM loader start Address for PiG */
+#define	PCI_LDR_CTRL_ADDR_PIG_MSK		SHIFT0(0xff)
+#define	PCI_LDR_CTRL_ADDR_PIG_BASE		0
+
+/*	PCI_MSI_CAP_ID			0x005C	MSI Capability ID Register (MSI Cap ID) */
+#define	PCI_MSI_CAP_ID_MSK		SHIFT0(0xffU)	/* MSI Capabilities ID */
+#define	PCI_MSI_CAP_ID_BASE		0
+
+/*	PCI_MSI_NPTR			0x005D	MSI Next Item Pointer Register */
+#define	PCI_MSI_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
+#define	PCI_MSI_NPTR_BASE		0
+
+/*	PCI_MSI_CTRL			0x005E	MSI Message Control Register */
+/*		Bit(s) PCI_MSI_CTRL_RSRV_15_8 reserved */
+#define	PCI_MSI_CTRL_64CAP				BIT_7S			/* 64-bit Address Capable */
+#define	PCI_MSI_CTRL_MM_ENA_MSK			SHIFT4(0x7U)	/* Multiple Message Enable */
+#define	PCI_MSI_CTRL_MM_ENA_BASE		4
+#define	PCI_MSI_CTRL_MM_CAP_MSK			SHIFT1(0x7U)	/* Multiple Message Capable */
+#define	PCI_MSI_CTRL_MM_CAP_BASE		1
+#define	PCI_MSI_CTRL_ENA				BIT_0S			/* MSI Enable */
+
+/*	PCI_MSI_ADDR_LO			0x0060	MSI Message Address Register, Lower Address */
+/* MSI Message Address, Lower Address */
+#define	PCI_MSI_ADDR_LO_MSK					SHIFT2(0x3fffffff)
+#define	PCI_MSI_ADDR_LO_BASE				2
+/*		Bit(s) PCI_MSI_ADDR_LO_RSRV_1_0 reserved */
+
+/*	PCI_MSI_ADDR_HI			0x0064	MSI Message Address Register, Upper Address */
+/* MSI Message Address, Upper Address */
+#define	PCI_MSI_ADDR_HI_MSK			SHIFT0(0xffffffff)
+#define	PCI_MSI_ADDR_HI_BASE		0
+
+/*	PCI_MSI_DATA			0x0068	MSI Message Data Register */
+/*		Bit(s) PCI_MSI_DATA_RSRV_31_16 reserved */
+#define	PCI_MSI_DATA_MSK					SHIFT0(0xffff)	/* Message Data */
+#define	PCI_MSI_DATA_BASE					0
+
+/*	PCIE_STAT				0x0070	PCI Express Status Register */
+/*		Bit(s) PCIE_STAT_RSRV_31_30 reserved */
+#define	PCIE_STAT_FIX_MSK				SHIFT16(0x3fffUL)	/* Fixed Value */
+#define	PCIE_STAT_FIX_BASE				16
+#define	PCIE_STAT_BUS_NUM_MSK			SHIFT8(0xff)		/* Request ID (Bus Number) */
+#define	PCIE_STAT_BUS_NUM_BASE			8
+/* Request ID (Device Number) */
+#define	PCIE_STAT_DEV_NUM_MSK			SHIFT3(0x1f)
+#define	PCIE_STAT_DEV_NUM_BASE			3
+/* Request ID (Function Number) */
+#define	PCIE_STAT_FUN_NUM_MSK			SHIFT0(0x7)
+#define	PCIE_STAT_FUN_NUM_BASE			0
+
+/*	PCIE_OUR_STAT			0x007C	Our Status Register */
+/*		Bit(s) PCIE_OUR_STAT_RSRV_31_26 reserved */
+/* DLL Error Status Indication */
+#define	PCIE_OUR_STAT_DLL_ERR_MSK			SHIFT24(0x3UL)
+#define	PCIE_OUR_STAT_DLL_ERR_BASE			24
+/* DLL Row Counters Values */
+#define	PCIE_OUR_STAT_DLL_ROW_MSK			SHIFT20(0xfUL)
+#define	PCIE_OUR_STAT_DLL_ROW_BASE			20
+/* DLL Column Counters Values */
+#define	PCIE_OUR_STAT_DLL_COL_MSK			SHIFT16(0xfUL)
+#define	PCIE_OUR_STAT_DLL_COL_BASE			16
+/*		Bit(s) PCIE_OUR_STAT_RSRV_15_0 reserved */
+
+/*	PCIE_OUR3				0x0080	Our Register 3 */
+/* Mask L0 Condition */
+#define	PCIE_OUR3_MASK_L0_COMMA					BIT_31
+/* Mask L0s Condition */
+#define	PCIE_OUR3_MASK_L0S_COMMA				BIT_30
+/* Select MACSec clock */
+#define	PCIE_OUR3_MACSEC_CLK_SEL				BIT_29
+/*		Bit(s) PCIE_OUR3_RSRV_27_20 reserved */
+/* Select MAC Rx Clock for Tx */
+#define	PCIE_OUR3_CLK_RX_TO_TX					BIT_28
+
+/* Yukon-Supreme */
+/* Disable Free Running Clock for GMAC and WOL */
+#define	PCIE_OUR3_DIS_CLK_WOL_GMAC				BIT_27
+/*		Bit(s) PCIE_OUR3_RSRV_26_21 reserved */
+/* Disable clk_clk for ASF Flash */
+#define	PCIE_OUR3_CLK_FLASH_DIS					BIT_20
+/* Disable clk_clk for USB */
+#define	PCIE_OUR3_CLK_USB_DIS					BIT_19
+/* Disable clk_asf */
+#define	PCIE_OUR3_CLK_ASF_REGS_DIS				BIT_18
+/*		Bit(s) PCIE_OUR3_RSRV_17 reserved */
+/* Disable clk_pci_regs_d0 */
+#define	PCIE_OUR3_CLK_PCI_REGS_DIS				BIT_16
+/* Disable clk_core_ytb_arb */
+#define	PCIE_OUR3_CLK_CORE_YTB_ARB_DIS			BIT_15
+/* Disable clk_mac_lnk1_d3 */
+#define	PCIE_OUR3_CLK_MAC_LNK1_D3_DIS			BIT_14
+/* Disable clk_core_lnk1_d0 */
+#define	PCIE_OUR3_CLK_CORE_LNK1_D0_DIS			BIT_13
+/* Disable clk_mac_lnk1_d0 */
+#define	PCIE_OUR3_CLK_MAC_LNK1_D0_DIS			BIT_12
+/* Disable clk_core_lnk1_d3 */
+#define	PCIE_OUR3_CLK_CORE_LNK1_D3_DIS			BIT_11
+/* Disable clk_pci_master_arb */
+#define	PCIE_OUR3_CLK_PCI_MST_ARB_DIS			BIT_10
+/* Disable clk_core_regs_d3 */
+#define	PCIE_OUR3_CLK_CORE_REGS_D3_DIS			BIT_9
+/* Disable clk_pci_regs_d3 */
+#define	PCIE_OUR3_CLK_PCI_REGS_D3_DIS			BIT_8
+/* Disable clk_ref_lnk1_gmac */
+#define	PCIE_OUR3_CLK_REF_LNK1_GMAC_DIS			BIT_7
+/* Disable clk_core_lnk1_gmac */
+#define	PCIE_OUR3_CLK_CORE_LNK1_GMAC_DIS		BIT_6
+/* Disable clk_pci_common */
+#define	PCIE_OUR3_CLK_PCI_COM_DIS				BIT_5
+/* Disable clk_core_common */
+#define	PCIE_OUR3_CLK_CORE_COM_DIS				BIT_4
+/* Disable clk_pci_lnk1_bmu */
+#define	PCIE_OUR3_CLK_PCI_LNK1_BMU_DIS			BIT_3
+/* Disable clk_core_lnk1_bmu */
+#define	PCIE_OUR3_CLK_CORE_LNK1_BMU_DIS			BIT_2
+/* Disable pci_clk_biu */
+#define	PCIE_OUR3_PCI_CLK_BIU_DIS				BIT_1
+/* Disable clk_core_biu */
+#define	PCIE_OUR3_CLK_CORE_BIU_DIS				BIT_0
+
+#define PCIE_OUR3_WOL_D3_COLD_SETTING		\
+	( PCIE_OUR3_CLK_CORE_LNK1_BMU_DIS	|	\
+	  PCIE_OUR3_CLK_CORE_COM_DIS		|	\
+	  PCIE_OUR3_CLK_PCI_MST_ARB_DIS		|	\
+	  PCIE_OUR3_CLK_MAC_LNK1_D0_DIS		|	\
+	  PCIE_OUR3_CLK_CORE_LNK1_D0_DIS	|	\
+	  PCIE_OUR3_CLK_PCI_REGS_DIS		|	\
+	  PCIE_OUR3_CLK_MACSEC_REGS_DIS 	|	\
+	  PCIE_OUR3_CLK_ASF_REGS_DIS)
+
+/*	PCIE_OUR4				0x0084	Our Register 4 */
+/* PEXUNIT LTSSM State for Gating Core Clock */
+#define	PCIE_OUR4_PEX_LTSSM_STATE_MSK			SHIFT25(0x7fUL)
+#define	PCIE_OUR4_PEX_LTSSM_STATE_BASE			25
+#define	PCIE_OUR4_GPHY_INT_ASPM					BIT_24			/* GPHY Get INT */
+#define	PCIE_OUR4_TIM_VAL_MSK					SHIFT16(0xffUL)	/* Timer Value */
+#define	PCIE_OUR4_TIM_VAL_BASE					16
+/* Force ASPM Request */
+#define	PCIE_OUR4_FORCE_ASPM_REQ				BIT_15
+#define	PCIE_OUR4_GPHY_LNK_DOWN					BIT_14			/* GPHY Link Down */
+/* Internal FIFO Empty */
+#define	PCIE_OUR4_INT_FIFO_EMPTY				BIT_13
+#define	PCIE_OUR4_CLKRUN_REQ					BIT_12			/* Clkrun Request */
+/* Enable EC SMBUS Pin mode */
+#define	PCIE_OUR4_EN_EC_SMBUS_PIN				BIT_11
+/* Enable PCIe RX Overflow Status */
+#define	PCIE_OUR4_EN_PCIE_RX_OVERFLOW			BIT_10
+/* Enable ASPM at No-D0 mode */
+#define	PCIE_OUR4_EN_ASPM_NOND0					BIT_9
+/* Enable Pin #63 as LED_LINK */
+#define	PCIE_OUR4_EN_LED_LINK_PIN63				BIT_8
+/* Force ASPM L1 Enable */
+#define	PCIE_OUR4_FORCE_ASPM_L1_ENA				BIT_7
+/* Force ASPM L0s Enable */
+#define	PCIE_OUR4_FORCE_ASPM_L0S_ENA			BIT_6
+/* Force CLKREQn Pin Low */
+#define	PCIE_OUR4_FORCE_CLKREQN_PIN_LO			BIT_5
+/* Force CLKREQ Scheme Enable */
+#define	PCIE_OUR4_FORCE_CLKREQ_SCHEME_ENA		BIT_4
+/* CLKREQn PAD Control */
+#define	PCIE_OUR4_CLKREQN_PAD_CTRL				BIT_3
+#define	PCIE_OUR4_A1_MODE_SEL					BIT_2			/* A1 Mode Select */
+/* Enable Gate Pexunit Clock */
+#define	PCIE_OUR4_GATE_PEXUNIT_CLK_ENA			BIT_1
+/* Enable Gate Root Core Clock */
+#define	PCIE_OUR4_GATE_ROOT_CORE_CLK_ENA		BIT_0
+
+/*	PCIE_OUR5				0x0088	Our Register 5 */
+/* Divide Core Clock Enable */
+#define	PCIE_OUR5_DIV_CORE_CLK_ENA				BIT_31
+/* Soft Reset for Vmain_avlbl De-Glitch Logic */
+#define	PCIE_OUR5_SOFT_RST_VMAIN_DEGLITCH		BIT_30
+/* Bypass Enable for Vmain_avlbl De-Glitch */
+#define	PCIE_OUR5_BYPASS_VMAIN_DEGLITCH_ENA		BIT_29
+/* Timer of Vmain_avlbl De-Glitch */
+#define	PCIE_OUR5_TIM_VMAIN_DEGLITCH_MSK		SHIFT27(0x3UL)
+#define	PCIE_OUR5_TIM_VMAIN_DEGLITCH_BASE		27
+/* PCIe Reset De-Asserted Release Event */
+#define	PCIE_OUR5_PCIE_RST_DEASS				BIT_26
+/* GPHY Received Packet Release Event */
+#define	PCIE_OUR5_GPHY_RX_PKT					BIT_25
+/* Internal FIFO Not Empty Release Event */
+#define	PCIE_OUR5_INT_FIFO_NOT_EMPTY			BIT_24
+/* Main Power is Available Release Event */
+#define	PCIE_OUR5_MAIN_PWR_AVL					BIT_23
+/* CLKRUN Request Release Event */
+#define	PCIE_OUR5_CLKRUN_REQ					BIT_22
+/* PCIe Reset Asserted Release Event */
+#define	PCIE_OUR5_PCIE_RST_ASS					BIT_21
+/* PME Asserted Release Event */
+#define	PCIE_OUR5_PME_ASS						BIT_20
+/* PCIe Exits L1 State Release Event */
+#define	PCIE_OUR5_PCIE_EX_L1_STATE				BIT_19
+/* EPROM Loader Not Finished Release Event */
+#define	PCIE_OUR5_EPROM_LDR_NOT_FIN				BIT_18
+/* PCIe RX Exits ELEC IDLE Release Event */
+#define	PCIE_OUR5_PCIE_RX_EX_ELEC_IDLE			BIT_17
+/* GPHY Link Up Release Event */
+#define	PCIE_OUR5_GPHY_LNK_UP					BIT_16
+/* CPU Goes to Sleep Release Event */
+#define	PCIE_OUR5_CPU_SLEEP						BIT_15
+/* GPHY get INT Release Event */
+#define	PCIE_OUR5_GPHY_INT						BIT_14
+/* Enable RX_DV to quick release clock */
+#define	PCIE_OUR5_EN_RX_DV						BIT_13
+/* GPHY get INT Gate Event */
+#define	PCIE_OUR5_GPHY_INT_EV					BIT_12
+/* CPU Goes to Sleep and Events Gate Event */
+#define	PCIE_OUR5_CPU_SLEEP_EV					BIT_11
+/* PCIe Reset Asserted and Events Gate Event */
+#define	PCIE_OUR5_PCIE_RST_ASS_EV				BIT_10
+/* GPHY Not Received Packet Gate Event */
+#define	PCIE_OUR5_GPHY_NOT_RX_PKT				BIT_9
+/* Internal FIFO Empty Gate Event */
+#define	PCIE_OUR5_INTERNAL_FIFO_EMPTY			BIT_8
+/* Main Power is Not Available Gate Event */
+#define	PCIE_OUR5_MAIN_PWR_NOT_AVL				BIT_7
+/* CLKRUN Not Requested Gate Event */
+#define	PCIE_OUR5_CLKRUN_NOT_REQ				BIT_6
+/* PCIe Reset De-Asserted and Events Gate Event */
+#define	PCIE_OUR5_PCIE_RST_DEASS_EV				BIT_5
+/* PME De-Asserted Gate Event */
+#define	PCIE_OUR5_PME_DEASS						BIT_4
+/* PCIe Goes to L1 State Gate Event */
+#define	PCIE_OUR5_PCIE_GO_L1_STATE				BIT_3
+/* EPROM Loader Finished Gate Event */
+#define	PCIE_OUR5_EPROM_LDR_FIN					BIT_2
+/* PCIe Rx ELEC IDLE Gate Event */
+#define	PCIE_OUR5_PCIE_RX_ELEC_IDLE				BIT_1
+/* GPHY Link Down Gate Event */
+#define	PCIE_OUR5_GPHY_LNK_DOWN					BIT_0
+
+/*	PCIE_ER_MASK			0x008C	Error Reporting Mask Register */
+/* Enable the Device Feature Set SERR */
+#define	PCIE_ER_MASK_DEV_FEAT_SET_SERR_ENA		BIT_31
+/* Receiver Error Mask */
+#define	PCIE_ER_MASK_RCV_ERR_MASK				BIT_30
+/*		Bit(s) PCIE_ER_MASK_RSRV_29_28 reserved */
+/* Enable Uncorrectable Error (UR Error) */
+#define	PCIE_ER_MASK_UR_ENA						BIT_27
+/* Enable Uncorrectable Error (ECRC Error) */
+#define	PCIE_ER_MASK_ECRCERR_ENA				BIT_26
+/* Enable Uncorrectable Error (Malformed TLP) */
+#define	PCIE_ER_MASK_MTLP_ENA					BIT_25
+/* Enable Uncorrectable Error (RX Overflow) */
+#define	PCIE_ER_MASK_RCVOVFL_ENA				BIT_24
+/* Enable Uncorrectable Error (Unexpected Completion) */
+#define	PCIE_ER_MASK_UNEXPCPL_ENA				BIT_23
+/* Enable Uncorrectable Error (Completer Abort) */
+#define	PCIE_ER_MASK_CPLABRT_ENA				BIT_22
+/* Enable Uncorrectable Error (Completion Timeout) */
+#define	PCIE_ER_MASK_CPLTO_ENA					BIT_21
+/* Enable Uncorrectable Error (Flow Control Protocol Error) */
+#define	PCIE_ER_MASK_FCPROTERR_ENA				BIT_20
+/* Enable Uncorrectable Error (Poisoned TLP) */
+#define	PCIE_ER_MASK_PTLP_ENA					BIT_19
+/* Enable Uncorrectable Error (Data Link Protocol Error) */
+#define	PCIE_ER_MASK_DLPRTERR_ENA				BIT_18
+/* Enable Uncorrectable Error (Training Error) */
+#define	PCIE_ER_MASK_TRAINERR_ENA				BIT_17
+/*		Bit(s) PCIE_ER_MASK_RSRV_16 reserved */
+/* Enable Uncorrectable Error (UR Error) Send Error Message */
+#define	PCIE_ER_MASK_UR_SEND_ENA				BIT_15
+/* Enable Uncorrectable Error (ECRC Error) Send Error Message */
+#define	PCIE_ER_MASK_ECRCERR_SEND_ENA			BIT_14
+/* Enable Uncorrectable Error (Malformed TLP) Send Error Message */
+#define	PCIE_ER_MASK_MTLP_SEND_ENA				BIT_13
+/* Enable Uncorrectable Error (RX Overflow) Send Error Message */
+#define	PCIE_ER_MASK_RCVOVFL_SEND_ENA			BIT_12
+/* Enable Uncorrectable Error (Unexpected Completion) Send Error Message */
+#define	PCIE_ER_MASK_CPLUC_SEND_ENA				BIT_11
+/* Enable Uncorrectable Error (Completer Abort) Send Error Message */
+#define	PCIE_ER_MASK_CPLABRT_SEND_ENA			BIT_10
+/* Enable Uncorrectable Error (Completion Timeout) Send Error Message */
+#define	PCIE_ER_MASK_CPLTO_SEND_ENA				BIT_9
+/* Enable Uncorrectable Error (Flow Control Protocol Error) Send Error Message */
+#define	PCIE_ER_MASK_FCPROTERR_SEND_ENA			BIT_8
+/* Enable Uncorrectable Error (Poisoned TLP) Send Error Message */
+#define	PCIE_ER_MASK_PTLP_SEND_ENA				BIT_7
+/* Enable Uncorrectable Error (Data Link Protocol Error) Send Error Message */
+#define	PCIE_ER_MASK_DLPRTERR_SEND_ENA			BIT_6
+/* Enable Uncorrectable Error (Training Error) Send Error Message */
+#define	PCIE_ER_MASK_TRAINERR_SEND_ENA			BIT_5
+/* Enable Correctable Error (Replay Timer Timeout) Send Error Message */
+#define	PCIE_ER_MASK_RPLYTO_SEND_ENA			BIT_4
+/* Enable Correctable Error (REPLAY_NUM RollOver) Send Error Message */
+#define	PCIE_ER_MASK_RPLYNUMRO_SEND_ENA			BIT_3
+/* Enable Correctable Error (Bad DLLP) Send Error Message */
+#define	PCIE_ER_MASK_BADDLLP_SEND_ENA			BIT_2
+/* Enable Correctable Error (Bad TLP) Send Error Message */
+#define	PCIE_ER_MASK_BADTLP_SEND_ENA			BIT_1
+/* Enable Correctable Error (RX Error) Send Error Message */
+#define	PCIE_ER_MASK_RXERR_SEND_ENA				BIT_0
+
+/*	CONFIG_REG0				0x0090	Config Register 0 */
+#define	CONFIG_REG0_RTC_MSK							SHIFT24(0xffUL)	/* RTC Timing */
+#define	CONFIG_REG0_RTC_BASE						24
+#define	CONFIG_REG0_WTC_MSK							SHIFT16(0xffUL)	/* WTC Timing */
+#define	CONFIG_REG0_WTC_BASE						16
+/* Disable PCIe Reset Extend after Lom_disable */
+#define	CONFIG_REG0_PCIRST_LOM						BIT_15
+/* Enable CPU Fast INT to Clock Gating */
+#define	CONFIG_REG0_CLK_GATE_CPU_INT				BIT_14
+
+/* Yukon-Supreme */
+/* Enable Clock Free Running for ASF Subsystem */
+#define	CONFIG_REG0_CLK_RUN_ASF						BIT_13
+/* Enable Clock Free Running for Flash Subsystem */
+#define	CONFIG_REG0_CLK_RUN_FLASH					BIT_12
+
+/* Random Generator Speed Control */
+#define	CONFIG_REG0_OSC_PU							BIT_12			/* OSC Power Up */
+/* OSC Speed Control */
+#define	CONFIG_REG0_OSC_SPEED_CTRL_MSK				SHIFT9(0x7)
+#define	CONFIG_REG0_OSC_SPEED_CTRL_BASE				BIT_9
+#define	CONFIG_REG0_OSC_OUT							BIT_8			/* OSC output */
+/* Random Generator output */
+#define	CONFIG_REG0_RNDG_OUT						BIT_8
+/*		Bit(s) CONFIG_REG0_RSRV_7 reserved */
+#define	CONFIG_REG0_YTB_ARB_MODE_MSK				SHIFT5(0x3)		/* YTB ARB Mode */
+#define	CONFIG_REG0_YTB_ARB_MODE_BASE				5
+/* Disable GPHY Reset on Lom_disable Mode */
+#define	CONFIG_REG0_GPHY_RST_LOMDISABLE				BIT_4
+/* Disable GPHY DPLL Reset on Lom_disable Mode */
+#define	CONFIG_REG0_GPHY_RST_DPLL_LOMDISABLE		BIT_3
+/* Disable GPHY DPLL Power Down on Lom_disable Mode */
+#define	CONFIG_REG0_GPHY_PD_DPLL_LOMDISABLE			BIT_2
+/* Enable GPHY PD on Lom_disable Mode */
+#define	CONFIG_REG0_GPHY_PD_LOMDISABLE				BIT_1
+/* <mu>C Lock VPD */
+#define	CONFIG_REG0_CPU_LOCK_VPD					BIT_0
+
+/*	CONFIG_REG1				0x0094	Config Register 1 */
+/* Testmode Enable */
+#define	CONFIG_REG1_EN_TESTMODE						BIT_31
+/* Testmode Select */
+#define	CONFIG_REG1_TESTMODE_SEL_MSK				SHIFT28(0x7UL)
+#define	CONFIG_REG1_TESTMODE_SEL_BASE				28
+/*		Bit(s) CONFIG_REG1_RSRV_27 reserved */
+/* USB RESUME Release Clock Event */
+#define	CONFIG_REG1_USB_RESUME_RELEASE_CLK			BIT_26
+/* USB RESUME Gate Clock Event */
+#define	CONFIG_REG1_USB_RESUME_GATE_CLK				BIT_25
+/* Disable Release Event in Our Register 4 during PCIe Reset Asserted */
+#define	CONFIG_REG1_DIS_CFG84_EVENT					BIT_24
+/* EPROM Loader Not Finished Release Event */
+#define	CONFIG_REG1_EPROM_LDR_NOT_FIN_RELEASE		BIT_23
+/* Vmain_avlbl Release Gated Clock Release Event */
+#define	CONFIG_REG1_VMAIN_AVLB_RELEASE				BIT_22
+/* PCIe Reset Release Gated Clock Release Event */
+#define	CONFIG_REG1_PCIE_RST_RELEASE				BIT_21
+/* EPROM Loader Finished Gate Event */
+#define	CONFIG_REG1_EPROM_LDR_FIN					BIT_20
+/* PCI Express Rx Electrical IDLE Gate Event */
+#define	CONFIG_REG1_PCIE_RX_ELEC_IDLE				BIT_19
+/* PCIe Reset Assert Gate Event */
+#define	CONFIG_REG1_PCIE_RST						BIT_18
+/* Enable PCIe Reset and pm2phy_off Generate CLKREQ for Auto-Gated Clock */
+#define	CONFIG_REG1_EN_PERST_PMOFF_CLKREQ			BIT_17
+/* Enable PCIe Reset Generate CLKREQ for Auto-Gated Clock */
+#define	CONFIG_REG1_EN_PERST_CLKREQ					BIT_16
+/*		Bit(s) CONFIG_REG1_RSRV_15_9 reserved */
+/* Enable Core Level Config Loader Done for Gated Clock */
+#define	CONFIG_REG1_EN_CFG_LOAD_DONE				BIT_8
+/* Enable PCIe Header Log Fix */
+#define	CONFIG_REG1_ENA_PCIE_HDRLOG_FIX				BIT_7
+/* Enable PCIe CRS Fix */
+#define	CONFIG_REG1_EN_PCIE_CRS_FIX					BIT_6
+/* FIFO Clock Duty Cycle Control */
+#define	CONFIG_REG1_FIFO_CLK_DUTY_CYC_CTRL			BIT_5
+/* Disable pexunit Synchronization Fix */
+#define	CONFIG_REG1_DIS_PEX_SYNC_FIX				BIT_4
+/* Enable CPU Reset Gated by YTB cmd */
+#define	CONFIG_REG1_EN_CPU_RST_YTB_CMD				BIT_3
+/* Disable PCIe 2.0 Linkup Fix */
+#define	CONFIG_REG1_DIS_PCIE20_LINKUP_FIX			BIT_2
+/* Enable TX BMU Read IDLE for ASPM Request */
+#define	CONFIG_REG1_EN_ASPM_TX_BMU_RD				BIT_1
+/* Enable TX BMU Write IDLE for ASPM Request */
+#define	CONFIG_REG1_EN_ASPM_TX_BMU_WR				BIT_0
+
+/*	PSM_CONFIG_REG0			0x0098	PSM Config Register 0 */
+/* PSM Timer Configuration Value */
+#define	PSM_CONFIG_REG0_PSM_TIM_CONF_MSK		SHIFT0(0xffffffff)
+#define	PSM_CONFIG_REG0_PSM_TIM_CONF_BASE		0
+
+/*	PSM_CONFIG_REG1			0x009C	PSM Config Register 1 */
+
+/* Yukon-Optima */
+#define	PSM_CONFIG_REG1_AC_PRESENT_STATUS			BIT_31	/* AC Present Status */
+/*		Bit(s) PSM_CONFIG_REG1_RSRV_30 reserved */
+#define	PSM_CONFIG_REG1_PTP_CLK_SEL					BIT_29	/* PTP Clock Select */
+#define	PSM_CONFIG_REG1_PTP_MODE					BIT_28	/* PTP Mode */
+/* PHY Energy Detect Event */
+#define	PSM_CONFIG_REG1_MUX_PHY_LINK				BIT_27
+/* Enable LED_DUPLEX for ac_present */
+#define	PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT			BIT_26
+#define	PSM_CONFIG_REG1_EN_PCIE_TIMER				BIT_25	/* Enable PCIe Timer */
+#define	PSM_CONFIG_REG1_EN_SPU_TIMER				BIT_24	/* Enable SPU Timer */
+#define	PSM_CONFIG_REG1_POLARITY_AC_PRESENT			BIT_23	/* AC Present Polarity */
+/*		Bit(s) PSM_CONFIG_REG1_RSRV_22 reserved */
+#define	PSM_CONFIG_REG1_EN_AC_PRESENT				BIT_21	/* Enable AC Present */
+/* Enable GPHY INT for PSM */
+#define	PSM_CONFIG_REG1_EN_GPHY_INT_PSM				BIT_20
+#define	PSM_CONFIG_REG1_DIS_PSM_TIMER				BIT_19	/* Disable PSM Timer */
+
+/* Yukon-Supreme */
+/* GPHY Energy Detect Status */
+#define	PSM_CONFIG_REG1_GPHY_ENERGY_STS				BIT_31
+#define	PSM_CONFIG_REG1_UART_MODE_MSK				SHIFT29(0x3UL)	/* UART_Mode */
+#define	PSM_CONFIG_REG1_UART_MODE_BASE				29
+/* Enable Clock Free Running for ASF Subsystem */
+#define	PSM_CONFIG_REG1_CLK_RUN_ASF					BIT_28
+/* Disable UART clock */
+#define	PSM_CONFIG_REG1_UART_CLK_DISABLE			BIT_27
+/* Tie internal Vaux to 1'b1 */
+#define	PSM_CONFIG_REG1_VAUX_ONE					BIT_26
+/* Default value for UART_RI_n */
+#define	PSM_CONFIG_REG1_UART_FC_RI_VAL				BIT_25
+/* Default value for UART_DCD_n */
+#define	PSM_CONFIG_REG1_UART_FC_DCD_VAL				BIT_24
+/* Default value for UART_DSR_n */
+#define	PSM_CONFIG_REG1_UART_FC_DSR_VAL				BIT_23
+/* Default value for UART_CTS_n */
+#define	PSM_CONFIG_REG1_UART_FC_CTS_VAL				BIT_22
+/* Enable Latch current Vaux_avlbl */
+#define	PSM_CONFIG_REG1_LATCH_VAUX					BIT_21
+/* Force Testmode pin as input PAD */
+#define	PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT		BIT_20
+#define	PSM_CONFIG_REG1_UART_RST					BIT_19			/* UART_RST */
+
+/* PCIE L1 Event Polarity for PSM */
+#define	PSM_CONFIG_REG1_PSM_PCIE_L1_POL				BIT_18
+/* PSM Timer Status */
+#define	PSM_CONFIG_REG1_TIMER_STAT					BIT_17
+/* GPHY INT Status */
+#define	PSM_CONFIG_REG1_GPHY_INT					BIT_16
+/* Force internal Testmode as 1'b0 */
+#define	PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO			BIT_15
+/* ENABLE INT for CLKRUN on ASPM and CLKREQ */
+#define	PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ			BIT_14
+/* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
+#define	PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ		BIT_13
+/* Disable CLK_GATE control snd_task */
+#define	PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK		BIT_12
+/* Disable flip-flop chain for sndmsg_inta */
+#define	PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA		BIT_11
+/*		Bit(s) PSM_CONFIG_REG1_RSRV_10 reserved */
+/* Disable Loader SM after PSM Goes back to IDLE */
+#define	PSM_CONFIG_REG1_DIS_LOADER					BIT_9
+/* Do Power Down, Start PSM Scheme */
+#define	PSM_CONFIG_REG1_DO_PWDN						BIT_8
+/* Disable Plug-in-Go SM after PSM Goes back to IDLE */
+#define	PSM_CONFIG_REG1_DIS_PIG						BIT_7
+/* Disable Internal PCIe Reset after PSM Goes back to IDLE */
+#define	PSM_CONFIG_REG1_DIS_PERST					BIT_6
+/* Enable REG18 Power Down for PSM */
+#define	PSM_CONFIG_REG1_EN_REG18_PD					BIT_5
+/* Disable EEPROM Loader after PSM Goes back to IDLE */
+#define	PSM_CONFIG_REG1_EN_PSM_LOAD					BIT_4
+/* Enable PCIe Hot Reset for PSM */
+#define	PSM_CONFIG_REG1_EN_PSM_HOT_RST				BIT_3
+/* Enable PCIe Reset Event for PSM */
+#define	PSM_CONFIG_REG1_EN_PSM_PERST				BIT_2
+/* Enable PCIe L1 Event for PSM */
+#define	PSM_CONFIG_REG1_EN_PSM_PCIE_L1				BIT_1
+/* Enable PSM Scheme */
+#define	PSM_CONFIG_REG1_EN_PSM						BIT_0
+
+/*	VPD_CTRL_ADD					0x00A0	VPD Start End Address */
+#define	VPD_CTRL_ADD_VPD_END_MSK			SHIFT24(0xffUL)	/* VPD_END */
+#define	VPD_CTRL_ADD_VPD_END_BASE			24
+#define	VPD_CTRL_ADD_VPD_W_START_MSK		SHIFT16(0xffUL)	/* VPD_W_START */
+#define	VPD_CTRL_ADD_VPD_W_START_BASE		16
+#define	VPD_CTRL_ADD_VPD_START_MSK			SHIFT8(0xff)	/* VPD_START */
+#define	VPD_CTRL_ADD_VPD_START_BASE			8
+#define	VPD_CTRL_ADD_OTP_BYTE_EN_MSK		SHIFT4(0xf)		/* OTP_BYTE_EN */
+#define	VPD_CTRL_ADD_OTP_BYTE_EN_BASE		4
+/*		Bit(s) VPD_CTRL_ADD_RSRV_3 reserved */
+#define	VPD_CTRL_ADD_EEPROM_EN				BIT_2			/* EEPROM_EN */
+#define	VPD_CTRL_ADD_OTP_EN					BIT_1			/* OTP_EN */
+#define	VPD_CTRL_ADD_VPD_SEL				BIT_0			/* VPD_SEL */
+
+/* Yukon-Supreme */
+/*	FLASH_LDR_CTRL			0x00A4	Flash Loader Control Register */
+#define	FLASH_LDR_CTRL_OTP_FLAG						BIT_31			/* Flag */
+#define	FLASH_LDR_CTRL_FLASH_REGION					BIT_30			/* Flash Region */
+/* Start Address for Flash Loader */
+#define	FLASH_LDR_CTRL_FLASH_ADDR_MSK				SHIFT16(0x3fffUL)
+#define	FLASH_LDR_CTRL_FLASH_ADDR_BASE				16
+/* Flash Start Address for PCI Loader */
+#define	FLASH_LDR_CTRL_FLASH_LOADER_PCI_MSK			SHIFT8(0xff)
+#define	FLASH_LDR_CTRL_FLASH_LOADER_PCI_BASE		8
+/* Flash Loader Start Address for PiG */
+#define	FLASH_LDR_CTRL_FLASH_LOADER_PIG_MSK			SHIFT0(0xff)
+#define	FLASH_LDR_CTRL_FLASH_LOADER_PIG_BASE		0
+
+/* Yukon-FE+ */
+/*	OTP_LDR_CTRL					0x00A4	OTP Loader Control Register */
+#define	OTP_LDR_CTRL_OTP_FLAG						BIT_31				/* Flag */
+#define	OTP_LDR_CTRL_OTP_ADDR_MSK					SHIFT16(0x7fffUL)	/* OTP Address */
+#define	OTP_LDR_CTRL_OTP_ADDR_BASE					16
+/* EEPROM timeout flag */
+#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_FLAG			BIT_15
+/* EEPROM timeout disable */
+#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_DIS				BIT_14
+/*		Bit(s) OTP_LDR_CTRL_RSRV_13_12 reserved */
+/* EEPROM timeout value */
+#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_MSK			SHIFT9(0x7)
+#define	OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_BASE		9
+/*		Bit(s) OTP_LDR_CTRL_RSRV_8 reserved */
+/* OTP start Address */
+#define	OTP_LDR_CTRL_OTP_ST_ADD_MSK					SHIFT0(0xff)
+#define	OTP_LDR_CTRL_OTP_ST_ADD_BASE				0
+
+/* Yukon-Supreme */
+/*	LD_STATUS_0				0x00A8	LOADER STATUS */
+/* Flash AHB Timeout */
+#define	LD_STATUS_0_FLASH_LOADER_TIMEOUT		BIT_31
+/* EEPROM Serial Interface Timeout */
+#define	LD_STATUS_0_EEPROM_LOADER_TIMEOUT		BIT_30
+/*		Bit(s) LD_STATUS_0_RSRV_29_0 reserved */
+
+/* Yukon-FE+ */
+/*	OTP_MEM_CTRL_0					0x00A8	OTP Memory Control Register 0 */
+#define	OTP_MEM_CTRL_0_CE2RD_SU_TIME_MSK		SHIFT24(0xffUL)	/* CERD setup time */
+#define	OTP_MEM_CTRL_0_CE2RD_SU_TIME_BASE		24
+/* Write data hold time */
+#define	OTP_MEM_CTRL_0_WRDAT_HLD_TIME_MSK		SHIFT20(0xfUL)
+#define	OTP_MEM_CTRL_0_WRDAT_HLD_TIME_BASE		20
+#define	OTP_MEM_CTRL_0_WRDAT_VLD_TIME_MSK		SHIFT16(0xfUL)	/* Write valid time */
+#define	OTP_MEM_CTRL_0_WRDAT_VLD_TIME_BASE		16
+/* Write data setup time */
+#define	OTP_MEM_CTRL_0_WRDAT_SU_TIME_MSK		SHIFT12(0xf)
+#define	OTP_MEM_CTRL_0_WRDAT_SU_TIME_BASE		12
+/* Read data setup time */
+#define	OTP_MEM_CTRL_0_RDDAT_SU_TIME_MSK		SHIFT4(0xff)
+#define	OTP_MEM_CTRL_0_RDDAT_SU_TIME_BASE		4
+#define	OTP_MEM_CTRL_0_RST_PULSE_WIDTH_MSK		SHIFT0(0xf)		/* RSTB pulse width */
+#define	OTP_MEM_CTRL_0_RST_PULSE_WIDTH_BASE		0
+
+/*	OTP_MEM_CTRL_1					0x00AC	OTP Memory Control Register 1 */
+/* CPUMPEN hold time */
+#define	OTP_MEM_CTRL_1_CPUMEM_HLD_TIME_MSK		SHIFT28(0xfUL)
+#define	OTP_MEM_CTRL_1_CPUMEM_HLD_TIME_BASE		28
+/* CPUMPEN setup time */
+#define	OTP_MEM_CTRL_1_CPUMEM_SU_TIME_MSK		SHIFT24(0xfUL)
+#define	OTP_MEM_CTRL_1_CPUMEM_SU_TIME_BASE		24
+#define	OTP_MEM_CTRL_1_PGMEN_HLD_TIME_MSK		SHIFT16(0xffUL)	/* PGMEN hold time */
+#define	OTP_MEM_CTRL_1_PGMEN_HLD_TIME_BASE		16
+#define	OTP_MEM_CTRL_1_PGMEN_VLD_TIME_MSK		SHIFT4(0xfff)	/* Program time */
+#define	OTP_MEM_CTRL_1_PGMEN_VLD_TIME_BASE		4
+#define	OTP_MEM_CTRL_1_PGMEN_SU_TIME_MSK		SHIFT0(0xf)		/* PGMEN setup time */
+#define	OTP_MEM_CTRL_1_PGMEN_SU_TIME_BASE		0
+
+/*	OTP_MEM_CTRL_2					0x00B0	OTP Memory Control Register 2 */
+/* OTP ctrl module status */
+#define	OTP_MEM_CTRL_2_OTP_DBG_BITS_MSK			SHIFT16(0xffffUL)
+#define	OTP_MEM_CTRL_2_OTP_DBG_BITS_BASE		16
+#define	OTP_MEM_CTRL_2_OTP_TST_MODE_MSK			SHIFT8(0xff)	/* OTP test mode */
+#define	OTP_MEM_CTRL_2_OTP_TST_MODE_BASE		8
+/*		Bit(s) OTP_MEM_CTRL_2_RSRV_7 reserved */
+/* Auto read back after programming */
+#define	OTP_MEM_CTRL_2_AUTO_RD_AFTER_WR			BIT_6
+/* OTP test mode enable */
+#define	OTP_MEM_CTRL_2_TSTMODE_ENA				BIT_5
+#define	OTP_MEM_CTRL_2_OTP_RST_WHEN_WR			BIT_4			/* OTP reset mode */
+/* OTP CEB always low */
+#define	OTP_MEM_CTRL_2_CEB_KEEP_LOW				BIT_3
+#define	OTP_MEM_CTRL_2_BYPASS2RSTB				BIT_2			/* OTP RSTB */
+#define	OTP_MEM_CTRL_2_BYPASS2RSTB_ENA			BIT_1			/* OTP RSTB enable */
+/* OTP interface module reset */
+#define	OTP_MEM_CTRL_2_OTP_IF_FREEZE			BIT_0
+
+/*	OTP_MEM_ST_0					0x00B4	OTP Memory Status Register 0 */
+/* OTP memory LOCK pin */
+#define	OTP_MEM_ST_0_OTP_LOCK_PIN			BIT_31
+/*		Bit(s) OTP_MEM_ST_0_RSRV_30_24 reserved */
+/* OTP memory DOUT pin */
+#define	OTP_MEM_ST_0_OTP_DOUT_PIN			BIT_23
+/*		Bit(s) OTP_MEM_ST_0_RSRV_22_0 reserved */
+
+/* Yukon-Supreme */
+/*	VPD_FLASH_CTRL			0x00B8	EEPROM and Flash Control Register */
+/* Disable MDIO to YTB Bus Read/Write */
+#define	VPD_FLASH_CTRL_MDIO2YTB_DIS					BIT_31
+/* Software Reset MDIO to YTB Bus */
+#define	VPD_FLASH_CTRL_MDIO2YTB_SWRST				BIT_30
+/*		Bit(s) VPD_FLASH_CTRL_RSRV_29_28 reserved */
+/* Flash Loader AHB Request Timeout Disable */
+#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_DIS		BIT_27
+/* TWSI Serial Interface Timeout Disable */
+#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_DIS			BIT_26
+/*		Bit(s) VPD_FLASH_CTRL_RSRV_25_24 reserved */
+/* Flash Loader AHB Request Timeout Value */
+#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_MSK		SHIFT21(0x7UL)
+#define	VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_BASE		21
+/*		Bit(s) VPD_FLASH_CTRL_RSRV_20 reserved */
+/* TWSI Serial Interface Timeout Value */
+#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_MSK			SHIFT17(0x7UL)
+#define	VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_BASE			17
+/*		Bit(s) VPD_FLASH_CTRL_RSRV_16 reserved */
+/* EEPROM Loader Timeout Disable */
+#define	VPD_FLASH_CTRL_EEPROM_TMOUT_DIS				BIT_15
+/* Flash Loader Timeout Disable */
+#define	VPD_FLASH_CTRL_FLASH_TMOUT_DIS				BIT_14
+/* EEPROM Loader Timeout Value */
+#define	VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_MSK		SHIFT12(0x3)
+#define	VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_BASE		12
+/* Flash Loader Timeout Value */
+#define	VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_MSK		SHIFT10(0x3)
+#define	VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_BASE		10
+/* EEPROM Speed Select */
+#define	VPD_FLASH_CTRL_SPEED_SELECT_MSK				SHIFT0(0x3ff)
+#define	VPD_FLASH_CTRL_SPEED_SELECT_BASE			0
+
+/* Yukon-FE+ */
+/*	VPD_CTRL						0x00B8	EEPROM and OTP Control Register */
+/* mdio to ytb bus IF disable */
+#define	VPD_CTRL_MDIO2YTB_DIS			BIT_31
+/* mdio to ytb bus IF software reset */
+#define	VPD_CTRL_MDIO2YTB_SWRST			BIT_30
+#define	VPD_CTRL_OTP_TOP_RST			BIT_29			/* otp_top software reset */
+/*		Bit(s) VPD_CTRL_RSRV_28_18 reserved */
+#define	VPD_CTRL_OTP_IF_TMOUT_MSK		SHIFT16(0x3UL)	/* OTP timeout reg */
+#define	VPD_CTRL_OTP_IF_TMOUT_BASE		16
+/* EEPROM loader timeout disable */
+#define	VPD_CTRL_TMOUT_DIS				BIT_15
+/*		Bit(s) VPD_CTRL_RSRV_14 reserved */
+/* EEPROM loader timeout val */
+#define	VPD_CTRL_TMOUT_VALUE_MSK		SHIFT12(0x3)
+#define	VPD_CTRL_TMOUT_VALUE_BASE		12
+/*		Bit(s) VPD_CTRL_RSRV_11_10 reserved */
+#define	VPD_CTRL_SPEED_SELECT_MSK		SHIFT0(0x3ff)	/* EEPROM speed select */
+#define	VPD_CTRL_SPEED_SELECT_BASE		0
+
+/*	OTP_MEM_CTRL_3					0x00BC	LDO Control Register */
+/*		Bit(s) OTP_MEM_CTRL_3_RSRV_31_14 reserved */
+/* CLK generator filter bypass */
+#define	OTP_MEM_CTRL_3_CLK_GEN_BYPASS			BIT_13
+/* CLK generator soft reset */
+#define	OTP_MEM_CTRL_3_CLK_GEN_RST				BIT_12
+/* CLK generator filter control */
+#define	OTP_MEM_CTRL_3_CLK_GEN_CTRL_MSK			SHIFT8(0xf)
+#define	OTP_MEM_CTRL_3_CLK_GEN_CTRL_BASE		8
+/* LDO 2.5 V testmode sel */
+#define	OTP_MEM_CTRL_3_LDO25TSTMODE_MSK			SHIFT4(0x7)
+#define	OTP_MEM_CTRL_3_LDO25TSTMODE_BASE		4
+/* LDO 1.2 V testmode sel */
+#define	OTP_MEM_CTRL_3_LDO12TSTMODE_MSK			SHIFT0(0x7)
+#define	OTP_MEM_CTRL_3_LDO12TSTMODE_BASE		0
+
+/*	PCIE_CAP_ID						0x00C0	PE Capability ID Register (PM Cap
+ *											ID)
+ */
+#define	PCIE_CAP_ID_MSK			SHIFT0(0xffU)	/* Cap ID */
+#define	PCIE_CAP_ID_BASE		0
+
+/*	PCIE_NPTR				0x00C1	PE Next Item Pointer Register */
+#define	PCIE_NPTR_MSK		SHIFT0(0xffU)	/* Next Item Pointer */
+#define	PCIE_NPTR_BASE		0
+
+/*	PCIE_CAP				0x00C2	PE Capabilities Register */
+/*		Bit(s) PCIE_CAP_RSRV_15_14 reserved */
+#define	PCIE_CAP_INTMSG_NUM_MSK			SHIFT9(0x1fU)	/* Interrupt Message Number */
+#define	PCIE_CAP_INTMSG_NUM_BASE		9
+/*		Bit(s) PCIE_CAP_RSRV_8 reserved */
+#define	PCIE_CAP_PORT_TYP_MSK			SHIFT4(0xfU)	/* Device/Port Type */
+#define	PCIE_CAP_PORT_TYP_BASE			4
+#define	PCIE_CAP_CAP_VER_MSK			SHIFT0(0xfU)	/* Capability Version */
+#define	PCIE_CAP_CAP_VER_BASE			0
+
+/*	DEVICE_CAPABILITIES		0x00C4	Device Capabilities Register */
+/*		Bit(s) DEVICE_CAPABILITIES_RSRV_31_28 reserved */
+/* Captured Slot Power Limit Scale */
+#define	DEVICE_CAPABILITIES_SPL_SCALE_MSK			SHIFT26(0x3UL)
+#define	DEVICE_CAPABILITIES_SPL_SCALE_BASE			26
+/* Captured Slot Power Limit Value */
+#define	DEVICE_CAPABILITIES_SPL_VAL_MSK				SHIFT18(0xffUL)
+#define	DEVICE_CAPABILITIES_SPL_VAL_BASE			18
+/*		Bit(s) DEVICE_CAPABILITIES_RSRV_17_16 reserved */
+/* Role-Based Error Reporting */
+#define	DEVICE_CAPABILITIES_ROLE_BASED_ERR_RPT		BIT_15
+/* Power Indicator Present */
+#define	DEVICE_CAPABILITIES_PI_PRS					BIT_14
+/* Attention Indicator Present */
+#define	DEVICE_CAPABILITIES_AI_PRS					BIT_13
+/* Attention Button Present */
+#define	DEVICE_CAPABILITIES_AB_PRS					BIT_12
+/* Endpoint L1 Acceptable Latency */
+#define	DEVICE_CAPABILITIES_L1_AC_LAT_MSK			SHIFT9(0x7)
+#define	DEVICE_CAPABILITIES_L1_AC_LAT_BASE			9
+/* Endpoint L0s Acceptable Latency */
+#define	DEVICE_CAPABILITIES_L0_AC_LAT_MSK			SHIFT6(0x7)
+#define	DEVICE_CAPABILITIES_L0_AC_LAT_BASE			6
+/* Extended Tag Field Supported */
+#define	DEVICE_CAPABILITIES_EXTTAG_SUP				BIT_5
+/* Phantom Functions Supported */
+#define	DEVICE_CAPABILITIES_PHANTOM_SUP_MSK			SHIFT3(0x3)
+#define	DEVICE_CAPABILITIES_PHANTOM_SUP_BASE		3
+/* Max Payload Size Supported */
+#define	DEVICE_CAPABILITIES_MAX_PLS_SUP_MSK			SHIFT0(0x7)
+#define	DEVICE_CAPABILITIES_MAX_PLS_SUP_BASE		0
+
+/*	PCIE_DEVCTRL			0x00C8	Device Control Register */
+/*		Bit(s) PCIE_DEVCTRL_RSRV_15 reserved */
+#define	PCIE_DEVCTRL_MAX_RRS_MSK		SHIFT12(0x7U)	/* Max Read Request Size */
+#define	PCIE_DEVCTRL_MAX_RRS_BASE		12
+#define	PCIE_DEVCTRL_NOSNP_ENA			BIT_11S			/* Enable No Snoop */
+/* Auxiliary (AUX) Power PM Enable */
+#define	PCIE_DEVCTRL_AUXPWR_ENA			BIT_10S
+#define	PCIE_DEVCTRL_PHANTOM__ENA		BIT_9S			/* Phantom Functions Enable */
+/* Extended Tag Field Enable */
+#define	PCIE_DEVCTRL_EXTTAG_ENA			BIT_8S
+#define	PCIE_DEVCTRL_MAX_PLS_MSK		SHIFT5(0x7U)	/* Max_Payload_Size */
+#define	PCIE_DEVCTRL_MAX_PLS_BASE		5
+#define	PCIE_DEVCTRL_REL_ORD_ENA		BIT_4S			/* Enable Relaxed Ordering */
+/* Unsupported Request Reporting Enable */
+#define	PCIE_DEVCTRL_URR_ENA			BIT_3S
+/* Fatal Error Reporting Enable */
+#define	PCIE_DEVCTRL_FERR_ENA			BIT_2S
+/* Non-Fatal Error Reporting Enable */
+#define	PCIE_DEVCTRL_NFERR_ENA			BIT_1S
+/* Correctable Error Reporting Enable */
+#define	PCIE_DEVCTRL_CERR_ENA			BIT_0S
+
+/*	PCIE_DEVSTAT			0x00CA	Device Status Register */
+/*		Bit(s) PCIE_DEVSTAT_RSRV_15_6 reserved */
+#define	PCIE_DEVSTAT_TRANS_PEND			BIT_5S			/* Transactions Pending */
+#define	PCIE_DEVSTAT_AUXPWR_DET			BIT_4S			/* AUX Power Detected */
+/* Unsupported Request Detected */
+#define	PCIE_DEVSTAT_UR_DET				BIT_3S
+#define	PCIE_DEVSTAT_FERR_DET			BIT_2S			/* Fatal Error Detected */
+#define	PCIE_DEVSTAT_NFERR_DET			BIT_1S			/* Non-Fatal Error Detected */
+/* Correctable Error Detected */
+#define	PCIE_DEVSTAT_CERR_DET			BIT_0S
+
+/*	PCIE_LNKCAP				0x00CC	Link Capabilities Register */
+#define	PCIE_LNKCAP_PORT_NUM_MSK			SHIFT24(0xffUL)	/* Port Number */
+#define	PCIE_LNKCAP_PORT_NUM_BASE			24
+/*		Bit(s) PCIE_LNKCAP_RSRV_23_21 reserved */
+/*		Bit(s) PCIE_LNKCAP_RSRV_20_19 reserved */
+/* Clock Power Management */
+#define	PCIE_LNKCAP_CLK_PM					BIT_18
+#define	PCIE_LNKCAP_L1_EXITLAT_MSK			SHIFT15(0x7UL)	/* L1 Exit Latency */
+#define	PCIE_LNKCAP_L1_EXITLAT_BASE			15
+#define	PCIE_LNKCAP_LOS_EXITLAT_MSK			SHIFT12(0x7)	/* L0s Exit Latency */
+#define	PCIE_LNKCAP_LOS_EXITLAT_BASE		12
+/* Active State Link PM Support */
+#define	PCIE_LNKCAP_ASPM_SUP_MSK			SHIFT10(0x3)
+#define	PCIE_LNKCAP_ASPM_SUP_BASE			10
+#define	PCIE_LNKCAP_MAX_LNKWID_MSK			SHIFT4(0x3f)	/* Maximum Link Width */
+#define	PCIE_LNKCAP_MAX_LNKWID_BASE			4
+#define	PCIE_LNKCAP_MAX_LNKSPD_MSK			SHIFT0(0xf)		/* Maximum Link Speed */
+#define	PCIE_LNKCAP_MAX_LNKSPD_BASE			0
+
+/*	PCIE_LNKCTRL			0x00D0	Link Control Register */
+/*		Bit(s) PCIE_LNKCTRL_RSRV_15_9 reserved */
+/* Enable Clock Power Management */
+#define	PCIE_LNKCTRL_CLK_PM_ENA			BIT_8S
+#define	PCIE_LNKCTRL_EXTSYNC			BIT_7S			/* Extended Sync */
+/*		Bit(s) PCIE_LNKCTRL_RSRV_6 reserved */
+/*		Bit(s) PCIE_LNKCTRL_RSRV_5_4 reserved */
+/* Read Completion Boundary (RCB) */
+#define	PCIE_LNKCTRL_RCB_128B			BIT_3S
+/*		Bit(s) PCIE_LNKCTRL_RSRV_2 reserved */
+/* Active State Link PM Control */
+#define	PCIE_LNKCTRL_ASPM_CTRL_MSK		SHIFT0(0x3U)
+#define	PCIE_LNKCTRL_ASPM_CTRL_BASE		0
+
+/*	PCIE_LNKSTAT			0x00D2	Link Status Register */
+/*		Bit(s) PCIE_LNKSTAT_RSRV_15_14 reserved */
+/*		Bit(s) PCIE_LNKSTAT_RSRV_13 reserved */
+/* Slot Clock Configuration */
+#define	PCIE_LNKSTAT_SCLKCFG				BIT_12S
+#define	PCIE_LNKSTAT_LNKTRAIN				BIT_11S			/* Link Training */
+#define	PCIE_LNKSTAT_UNDEF					BIT_10S			/* Undefined */
+/* Negotiated Link Width */
+#define	PCIE_LNKSTAT_NEGLNKWID_MSK			SHIFT4(0x3fU)
+#define	PCIE_LNKSTAT_NEGLNKWID_BASE			4
+#define	PCIE_LNKSTAT_LNKSPD_MSK				SHIFT0(0xfU)	/* Link Speed */
+#define	PCIE_LNKSTAT_LNKSPD_BASE			0
+
+/*	PCIE_DEV_CAP_2			0x00E4	Device Capabilities 2 Register */
+/*		Bit(s) PCIE_DEV_CAP_2_RSRV_31_5 reserved */
+/* Completion Timeout Disable Supported */
+#define	PCIE_DEV_CAP_2_CPL_TO_DIS_SUPP				BIT_4
+/* Completion Timeout Ranges Supported */
+#define	PCIE_DEV_CAP_2_CPL_TO_RANGE_SUPP_MSK		SHIFT0(0xf)
+#define	PCIE_DEV_CAP_2_CPL_TO_RANGE_SUPP_BASE		0
+
+/*	PCIE_DEV_CTRL_2			0x00E8	Device Control 2 Register */
+/*		Bit(s) PCIE_DEV_CTRL_2_RSRV_31_5 reserved */
+/* Completion Timeout Disable */
+#define	PCIE_DEV_CTRL_2_CPL_TO_DIS			BIT_4
+/* Completion Timeout Value */
+#define	PCIE_DEV_CTRL_2_CPL_TO_VAL_MSK		SHIFT0(0xf)
+#define	PCIE_DEV_CTRL_2_CPL_TO_VAL_BASE		0
+
+/*	UART_CONFIG_REG1		0x00F0	UART Config Register 1 */
+/*		Bit(s) UART_CONFIG_REG1_RSRV_31_8 reserved */
+/*		Bit(s) UART_CONFIG_REG1_RSRV_7_0 reserved */
+
+/*	PCIE_AE_CAP_HDR			0x0100	Advanced Error Reporting Enhanced
+ *									Capability Header Register
+ */
+#define	PCIE_AE_CAP_HDR_NPTR_MSK		SHIFT20(0xfffUL)	/* Next Capability Offset */
+#define	PCIE_AE_CAP_HDR_NPTR_BASE		20
+#define	PCIE_AE_CAP_HDR_VER_ID_MSK		SHIFT16(0xfUL)	/* Capability Version */
+#define	PCIE_AE_CAP_HDR_VER_ID_BASE		16
+/* PCI Express Extended Capability ID */
+#define	PCIE_AE_CAP_HDR_CAP_ID_MSK		SHIFT0(0xffff)
+#define	PCIE_AE_CAP_HDR_CAP_ID_BASE		0
+
+/*	PCIE_UE_STAT			0x0104	Uncorrectable Error Status Register */
+/*		Bit(s) PCIE_UE_STAT_RSRV_31_21 reserved */
+/* Unsupported Request Error */
+#define	PCIE_UE_STAT_UR						BIT_20
+#define	PCIE_UE_STAT_ECRCERR				BIT_19			/* ECRC Error */
+#define	PCIE_UE_STAT_MTLP					BIT_18			/* Malformed TLP */
+#define	PCIE_UE_STAT_RCVOVFL				BIT_17			/* Receiver Overflow */
+/* Unexpected Completion */
+#define	PCIE_UE_STAT_UNEXPCPL				BIT_16
+#define	PCIE_UE_STAT_CPLABORT				BIT_15			/* Completer Abort */
+#define	PCIE_UE_STAT_CPLTO					BIT_14			/* Completion Timeout */
+/* Flow Control Protocol Error */
+#define	PCIE_UE_STAT_FCPROTERR				BIT_13
+#define	PCIE_UE_STAT_PTLP					BIT_12			/* Poisoned TLP */
+/*		Bit(s) PCIE_UE_STAT_RSRV_11_5 reserved */
+/* Data Link Protocol Error */
+#define	PCIE_UE_STAT_DLPROTERR				BIT_4
+/*		Bit(s) PCIE_UE_STAT_RSRV_3_1 reserved */
+#define	PCIE_UE_STAT_UNDEF					BIT_0			/* Undefined */
+
+/*	PCIE_UE_MASK			0x0108	Uncorrectable Error Mask Register */
+/*		Bit(s) PCIE_UE_MASK_RSRV_31_21 reserved */
+/* Unsupported Request Error */
+#define	PCIE_UE_MASK_UR						BIT_20
+#define	PCIE_UE_MASK_ECRCERR				BIT_19			/* ECRC Error */
+#define	PCIE_UE_MASK_MTLP					BIT_18			/* Malformed TLP */
+#define	PCIE_UE_MASK_RCVOVFL				BIT_17			/* Receiver Overflow */
+/* Unexpected Completion */
+#define	PCIE_UE_MASK_UNEXPCPL				BIT_16
+#define	PCIE_UE_MASK_CPLABRT				BIT_15			/* Completer Abort */
+#define	PCIE_UE_MASK_CPLTO					BIT_14			/* Completion Timeout */
+/* Flow Control Protocol Error */
+#define	PCIE_UE_MASK_FCPROTERR				BIT_13
+#define	PCIE_UE_MASK_PTLP					BIT_12			/* Poisoned TLP */
+/*		Bit(s) PCIE_UE_MASK_RSRV_11_5 reserved */
+/* Data Link Protocol Error */
+#define	PCIE_UE_MASK_DLPROTERR				BIT_4
+/*		Bit(s) PCIE_UE_MASK_RSRV_3_1 reserved */
+#define	PCIE_UE_MASK_UNDEF					BIT_0			/* Undefined */
+
+/*	PCIE_UE_SVRT			0x010C	Uncorrectable Error Severity Register */
+/*		Bit(s) PCIE_UE_SVRT_RSRV_31_21 reserved */
+/* Unsupported Request Error */
+#define	PCIE_UE_SVRT_UR						BIT_20
+#define	PCIE_UE_SVRT_ECRCERR				BIT_19			/* ECRC Error Severity */
+#define	PCIE_UE_SVRT_MTLP					BIT_18			/* Malformed TLP */
+#define	PCIE_UE_SVRT_RCVOVFL				BIT_17			/* Receiver Overflow */
+/* Unexpected Completion */
+#define	PCIE_UE_SVRT_UNEXPCPL				BIT_16
+#define	PCIE_UE_SVRT_CPLABRT				BIT_15			/* Completer Abort */
+#define	PCIE_UE_SVRT_CPLTO					BIT_14			/* Completion Timeout */
+/* Flow Control Protocol Error */
+#define	PCIE_UE_SVRT_FCPROTERR				BIT_13
+#define	PCIE_UE_SVRT_PTLP					BIT_12			/* Poisoned TLP */
+/*		Bit(s) PCIE_UE_SVRT_RSRV_11_5 reserved */
+/* Data Link Protocol Error */
+#define	PCIE_UE_SVRT_DLPROTERR				BIT_4
+/*		Bit(s) PCIE_UE_SVRT_RSRV_3_1 reserved */
+#define	PCIE_UE_SVRT_UNDEF					BIT_0			/* Undefined */
+
+/*	PCIE_CA_STAT			0x0110	Correctable Error Status Register */
+/*		Bit(s) PCIE_CA_STAT_RSRV_31_14 reserved */
+/* Advisory Non-Fatal Error Status */
+#define	PCIE_CA_STAT_ADV_NONFAT_ERRSTAT		BIT_13
+/* Replay Timer Timeout */
+#define	PCIE_CA_STAT_RPLYTO					BIT_12
+/*		Bit(s) PCIE_CA_STAT_RSRV_11_9 reserved */
+/* REPLAY_NUM Rollover */
+#define	PCIE_CA_STAT_RPLYNUMRO				BIT_8
+#define	PCIE_CA_STAT_BADDLLP				BIT_7				/* Bad DLLP */
+#define	PCIE_CA_STAT_BADTLP					BIT_6				/* Bad TLP */
+/*		Bit(s) PCIE_CA_STAT_RSRV_5_1 reserved */
+#define	PCIE_CA_STAT_RCVERR					BIT_0				/* Receiver Error */
+
+/*	PCIE_CA_MASK			0x0114	Correctable Error Mask Register */
+/*		Bit(s) PCIE_CA_MASK_RSRV_31_14 reserved */
+/* Advisory Non-Fatal Error Mask */
+#define	PCIE_CA_MASK_ADV_NONFAT_ERRSTAT		BIT_13
+/* Replay Timer Timeout */
+#define	PCIE_CA_MASK_RPLYTO					BIT_12
+/*		Bit(s) PCIE_CA_MASK_RSRV_11_9 reserved */
+/* REPLAY_NUM Rollover */
+#define	PCIE_CA_MASK_RPLYNUMRO				BIT_8
+#define	PCIE_CA_MASK_BADDLLP				BIT_7				/* Bad DLLP */
+#define	PCIE_CA_MASK_BADTLP					BIT_6				/* Bad TLP */
+/*		Bit(s) PCIE_CA_MASK_RSRV_5_1 reserved */
+#define	PCIE_CA_MASK_RCVERR					BIT_0				/* Receiver Error */
+
+/*	PCIE_AE_CAPCTRL			0x0118	Advanced Error Capabilities and Control
+ *									Register
+ */
+/*		Bit(s) PCIE_AE_CAPCTRL_RSRV_31_9 reserved */
+/* ECRC Check Enable */
+#define	PCIE_AE_CAPCTRL_ECRCCHK_ENA			BIT_8
+/* ECRC Check Capable */
+#define	PCIE_AE_CAPCTRL_ECRCCHK_CAP			BIT_7
+/* ECRC Generation Enable */
+#define	PCIE_AE_CAPCTRL_ECRCGEN_ENA			BIT_6
+/* ECRC Generation Capable */
+#define	PCIE_AE_CAPCTRL_ECRCGEN_CAP			BIT_5
+/* First Error Pointer */
+#define	PCIE_AE_CAPCTRL_1ERR_PTR_MSK		SHIFT0(0x1f)
+#define	PCIE_AE_CAPCTRL_1ERR_PTR_BASE		0
+
+/*	PCIE_HDRLOG						0x011C	Header Log Registers */
+#define	PCIE_HDRLOG_MSK			SHIFT0(0xffffffffU)	/* Header Log */
+#define	PCIE_HDRLOG_BASE		0
+
+/*	PCIE_DEVSERNUMCAP		0x0130	Device Serial Number Enhanced Capability
+ *									Header
+ */
+/* Next Capability Offset */
+#define	PCIE_DEVSERNUMCAP_NPTR_MSK			SHIFT20(0xfffUL)
+#define	PCIE_DEVSERNUMCAP_NPTR_BASE			20
+#define	PCIE_DEVSERNUMCAP_VER_ID_MSK		SHIFT16(0xfUL)	/* Capability Version */
+#define	PCIE_DEVSERNUMCAP_VER_ID_BASE		16
+/* PCI Express Extended Capability ID */
+#define	PCIE_DEVSERNUMCAP_CAP_ID_MSK		SHIFT0(0xffff)
+#define	PCIE_DEVSERNUMCAP_CAP_ID_BASE		0
+
+/*	PCIE_SERNUM_LOWDW		0x0134	Serial Number Register (Lower DW) */
+/* Serial Number Register (Lower DW) */
+#define	PCIE_SERNUM_LOWDW_SERNUM_LOWDW_MSK		SHIFT0(0xffffffff)
+#define	PCIE_SERNUM_LOWDW_SERNUM_LOWDW_BASE		0
+
+/*	PCIE_SERNUM_UPPDW		0x0138	Serial Number Register (Upper DW) */
+/* Serial Number Register (Upper DW) */
+#define	PCIE_SERNUM_UPPDW_SERNUM_UPPDW_MSK		SHIFT0(0xffffffff)
+#define	PCIE_SERNUM_UPPDW_SERNUM_UPPDW_BASE		0
+
+/*	PCIE_PWRBDGT_CAPHDR		0x0140	Power Budgeting Enhanced Capability Header */
+/* Next Capability Offset */
+#define	PCIE_PWRBDGT_CAPHDR_NPTR_MSK		SHIFT20(0xfffUL)
+#define	PCIE_PWRBDGT_CAPHDR_NPTR_BASE		20
+#define	PCIE_PWRBDGT_CAPHDR_VER_ID_MSK		SHIFT16(0xfUL)	/* Capability Version */
+#define	PCIE_PWRBDGT_CAPHDR_VER_ID_BASE		16
+/* PCI Express Extended Capability ID */
+#define	PCIE_PWRBDGT_CAPHDR_CAP_ID_MSK		SHIFT0(0xffff)
+#define	PCIE_PWRBDGT_CAPHDR_CAP_ID_BASE		0
+
+/*	PCIE_PWRBDGT_DATASEL	0x0144	Power Budgeting Data Select Register */
+/*		Bit(s) PCIE_PWRBDGT_DATASEL_RSRV_31_8 reserved */
+#define	PCIE_PWRBDGT_DATASEL_DATASEL_MSK		SHIFT0(0xff)		/* Data Select */
+#define	PCIE_PWRBDGT_DATASEL_DATASEL_BASE		0
+
+/*	PCIE_PWRBDGT_DATA		0x0148	Power Budgeting Data Register */
+/*		Bit(s) PCIE_PWRBDGT_DATA_RSRV_31_21 reserved */
+#define	PCIE_PWRBDGT_DATA_PWRRAIL_MSK			SHIFT18(0x7UL)	/* Power Rail */
+#define	PCIE_PWRBDGT_DATA_PWRRAIL_BASE			18
+#define	PCIE_PWRBDGT_DATA_TYPE_MSK				SHIFT15(0x7UL)	/* Type */
+#define	PCIE_PWRBDGT_DATA_TYPE_BASE				15
+#define	PCIE_PWRBDGT_DATA_PMSTATE_MSK			SHIFT13(0x3)	/* PM State */
+#define	PCIE_PWRBDGT_DATA_PMSTATE_BASE			13
+#define	PCIE_PWRBDGT_DATA_PMSUBSTATE_MSK		SHIFT10(0x7)	/* PM Sub State */
+#define	PCIE_PWRBDGT_DATA_PMSUBSTATE_BASE		10
+#define	PCIE_PWRBDGT_DATA_DATASCALE_MSK			SHIFT8(0x3)		/* Data Scale */
+#define	PCIE_PWRBDGT_DATA_DATASCALE_BASE		8
+#define	PCIE_PWRBDGT_DATA_BASEPWR_MSK			SHIFT0(0xff)	/* Base Power */
+#define	PCIE_PWRBDGT_DATA_BASEPWR_BASE			0
+
+/*	PCIE_PWRBDGT_CAP		0x014C	Power Budgeting Capability Register */
+/*		Bit(s) PCIE_PWRBDGT_CAP_RSRV_31_1 reserved */
+#define	PCIE_PWRBDGT_CAP_SYSALLOC			BIT_0				/* System Allocated */
+
+/*	PSM_CONFIG_REG2				0x0160	PSM Config Register 2 */
+/* PSM Timer Configuration Value */
+#define	PSM_CONFIG_REG2_PSM_TIM_CONF_MSK		SHIFT0(0xffffffff)
+#define	PSM_CONFIG_REG2_PSM_TIM_CONF_BASE		0
+
+/*	PSM_CONFIG_REG3				0x0164	PSM Config Register 3 */
+/*		Bit(s) PSM_CONFIG_REG3_RSRV_31_4 reserved */
+/* PSM wait power down timer */
+#define	PSM_CONFIG_REG3_PSM_WAIT_PD_TIMER_MSK		SHIFT0(0xf)
+#define	PSM_CONFIG_REG3_PSM_WAIT_PD_TIMER_BASE		0
+
+/*	PSM_CONFIG_REG4				0x0168	PSM Config Register 4 */
+/*		Bit(s) PSM_CONFIG_REG4_RSRV_31_8 reserved */
+/* PHY Link Detect Timer */
+#define	PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK		SHIFT4(0xf)
+#define	PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE		4
+/*		Bit(s) PSM_CONFIG_REG4_RSRV_3_2 reserved */
+/* Debug Timer */
+#define	PSM_CONFIG_REG4_DEBUG_TIMER						BIT_1
+/* Reset GPHY Link Detect */
+#define	PSM_CONFIG_REG4_RST_PHY_LINK_DETECT				BIT_0
+
+/*	IO_CONFIG					0x016C	I/O Timing Control Register */
+#define	IO_CONFIG_PD_PAD				BIT_31				/* Power Down Pad */
+/*		Bit(s) IO_CONFIG_RSRV_30_12 reserved */
+/* Pad LED Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_LED_SR_MSK		SHIFT10(0x3)
+#define	IO_CONFIG_PAD_LED_SR_BASE		10
+/* Pad SPI Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_SPI_SR_MSK		SHIFT8(0x3)
+#define	IO_CONFIG_PAD_SPI_SR_BASE		8
+/* Pad VPD Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_VPD_SR_MSK		SHIFT6(0x3)
+#define	IO_CONFIG_PAD_VPD_SR_BASE		6
+/* Pad Vmain Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_VMAIN_SR_MSK		SHIFT4(0x3)
+#define	IO_CONFIG_PAD_VMAIN_SR_BASE		4
+/* Pad PME/CLKREQn Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_PME_SR_MSK		SHIFT2(0x3)
+#define	IO_CONFIG_PAD_PME_SR_BASE		2
+/* Pad RST/LOM_DISABLEn Slew Rate and Impedance */
+#define	IO_CONFIG_PAD_RST_SR_MSK		SHIFT0(0x3)
+#define	IO_CONFIG_PAD_RST_SR_BASE		0
+
+/*	PCIE_TL_CTRL			0x0200	Transaction Layer Control Register */
+/*		Bit(s) PCIE_TL_CTRL_RSRV_31_2 reserved */
+#define	PCIE_TL_CTRL_MAXOUTSTAND_MSK		SHIFT0(0x3)			/* Max_outstand */
+#define	PCIE_TL_CTRL_MAXOUTSTAND_BASE		0
+
+/*	PCIE_TL_STAT			0x0204	Transaction Layer Status Register */
+/*		Bit(s) PCIE_TL_STAT_RSRV_31_0 reserved */
+
+/*	PCIE_DL_CTRL			0x0208	Data Link Layer Control Register */
+/*		Bit(s) PCIE_DL_CTRL_RSRV_31_0 reserved */
+
+/*	PCIE_DL_STAT			0x020C	Data Link Layer Status Register */
+/*		Bit(s) PCIE_DL_STAT_RSRV_31_0 reserved */
+
+/*	PCIE_PL_CTRL			0x0210	PE Physical Layer Control Register */
+/*		Bit(s) PCIE_PL_CTRL_RSRV_31_16 reserved */
+#define	PCIE_PL_CTRL_N_FTS_MSK				SHIFT8(0xff)	/* Number FTS */
+#define	PCIE_PL_CTRL_N_FTS_BASE				8
+/*		Bit(s) PCIE_PL_CTRL_RSRV_7_0 reserved */
+
+/*	PCIE_PL_STAT			0x0214	PE Physical Layer Status Register */
+/*		Bit(s) PCIE_PL_STAT_RSRV_31_0 reserved */
+
+/*	PCIE_CPLTO				0x0220	PE Completion Timeout Register */
+/*		Bit(s) PCIE_CPLTO_RSRV_31_16 reserved */
+/* Completion Timeout Threshold */
+#define	PCIE_CPLTO_MSK					SHIFT0(0xffff)
+#define	PCIE_CPLTO_BASE					0
+
+/*	PCIE_FC					0x0224	PE Flow Control Register */
+/* Posted Headers Flow Control Credit Initial Value */
+#define	PCIE_FC_PH_INIT_MSK			SHIFT24(0xffUL)
+#define	PCIE_FC_PH_INIT_BASE		24
+/* Non-Posted Headers Flow Control Credit Initial Value */
+#define	PCIE_FC_NPH_INIT_MSK		SHIFT16(0xffUL)
+#define	PCIE_FC_NPH_INIT_BASE		16
+/* Completion Headers Flow Control Credit Initial Value */
+#define	PCIE_FC_CH_INIT_MSK			SHIFT8(0xff)
+#define	PCIE_FC_CH_INIT_BASE		8
+#define	PCIE_FC_UPDATETO_MSK		SHIFT0(0xff)	/* Flow Control Update Timeout */
+#define	PCIE_FC_UPDATETO_BASE		0
+
+/*	PCIE_ACKTIM_X1			0x0228	PE Ack Timer for 1x Link Register */
+/* Ack Replay Timer Timeout Value for x1 */
+#define	PCIE_ACKTIM_X1_RPLYTO_MSK		SHIFT16(0xffffUL)
+#define	PCIE_ACKTIM_X1_RPLYTO_BASE		16
+/* Ack Latency Timer Timeout Value for x1 Link */
+#define	PCIE_ACKTIM_X1_LATTO_MSK		SHIFT0(0xffff)
+#define	PCIE_ACKTIM_X1_LATTO_BASE		0
+
+/* -------------------- */
+
+#define	GLB_RAP				0x0000	/* 32 bit	Register Address Port (RAP)
+									 *			Register
+									 */
+#define	GLB_CSR				0x0004	/* 24 bit	Control/Status Register */
+#define	GLB_PCTRL			0x0007	/*  8 bit	Power Control Register */
+#define	GLB_ISRC			0x0008	/* 32 bit	Interrupt Source Register */
+#define	GLB_IMSK			0x000C	/* 32 bit	Interrupt Mask Register */
+#define	GLB_ISRC_HW			0x0010	/* 32 bit	Interrupt Hardware Error Source
+									 *			Register
+									 */
+#define	GLB_IMSK_HW			0x0014	/* 32 bit	Interrupt Hardware Error Mask
+									 *			Register
+									 */
+#define	GLB_ISRC_SP1		0x0018	/* 32 bit	Special Interrupt Source
+									 *			Register 1
+									 */
+#define	GLB_ISRC_SP2		0x001C	/* 32 bit	Special Interrupt Source
+									 *			Register 2
+									 */
+#define	GLB_ISRC_SP3		0x0020	/* 32 bit	Special Interrupt Source
+									 *			Register 3
+									 */
+#define	GLB_EISR			0x0024	/* 32 bit	Enter Interrupt Service Routine
+									 *			Register
+									 */
+#define	GLB_LISR			0x0028	/* 32 bit	Leave Interrupt Service Routine
+									 *			Register
+									 */
+#define	GLB_ICTRL			0x002C	/* 32 bit	Interrupt Control Register */
+#define	SPI_CTRL			0x0060	/* 32 bit	SPI Flash Memory Control
+									 *			Register
+									 */
+#define	SPI_ADDR			0x0064	/* 32 bit	SPI Flash Memory Address
+									 *			Register
+									 */
+#define	SPI_DATA			0x0068	/* 32 bit	SPI Flash Memory Data Register */
+#define	SPI_ID				0x006C	/* 32 bit	SPI Flash Memory Vendor/Device
+									 *			ID Register
+									 */
+#define	SPI_LCFG			0x0070	/* 32 bit	SPI Flash Memory Loader
+									 *			Configuration Register
+									 */
+#define	SPI_CFG				0x0074	/* 32 bit	SPI Flash Memory Configuration
+									 *			Register
+									 */
+#define	SPI_OPC1			0x0078	/* 32 bit	SPI Flash Memory Opcode 1
+									 *			Register
+									 */
+#define	SPI_OPC2			0x007C	/* 32 bit	SPI Flash Memory Opcode 2
+									 *			Register
+									 */
+#define	GLB_BWIN_RLO		0x0080 	/* Block Window Register Start */
+#define	GLB_BWIN_RHI		0x00FC	/* Block Window Register End */
+#define	L1_CFG_MADDR_HI		0x0100	/* 32 bit	Link1 MAC Address Register High */
+#define	M_CFG_MADDR_HI		0x0110	/* 32 bit	maintenance MAC Address
+									 *			Register High
+									 */
+#define	L1_CFG_MADDR_LO		0x0104	/* 32 bit	Link1 MAC Address Register Low */
+#define	M_CFG_MADDR_LO		0x0114	/* 32 bit	maintenance MAC Address
+									 *			Register Low
+									 */
+#define	CFG_IF				0x0118	/* 16 bit	Interface Type Register (PMD
+									 *			Type and Connector Type)
+									 */
+#define	CFG_CREV			0x011A	/*  8 bit	Chip Revision Register */
+#define	CFG_CID				0x011B	/*  8 bit	Chip ID Register */
+#define	CFG_CGATE			0x011C	/* 16 bit	Clock Gating Register */
+#define	CFG_AIR2			0x011E	/*  8 bit	Application Information
+									 *			Register 2
+									 */
+#define	CFG_AIR1			0x011F	/*  8 bit	Application Information
+									 *			Register 1
+									 */
+#define	CFG_CDIV			0x0120	/* 32 bit	Clock Divider Register */
+#define	IRQ_TIM_INIT		0x0130	/* 32 bit	Timer Init Value Register */
+#define	IRQ_TIM_CNT			0x0134	/* 32 bit	Timer Register */
+#define	IRQ_TIM_TCTRL		0x0138	/* 32 bit	Timer Control/Test Register */
+#define	MOD_TIM_INIT		0x0140	/* 32 bit	IRQ Moderation Timer Init Value
+									 *			Register
+									 */
+#define	MOD_TIM_CNT			0x0144	/* 32 bit	IRQ Moderation Timer Register */
+#define	MOD_TIM_TCTRL		0x0148	/* 32 bit	IRQ Moderation Timer
+									 *			Control/Test Register
+									 */
+#define	MOD_TIM_MSK			0x014C	/* 32 bit	Interrupt Moderation Mask
+									 *			Register
+									 */
+#define	MOD_TIM_MSK_HW		0x0150	/* 32 bit	Interrupt Hardware Error
+									 *			Moderation Mask Register
+									 */
+#define	GLB_TCTRL			0x0158	/* 32 bit	Test Control Register 1 */
+#define	GLB_GPIO			0x015C	/* 32 bit	General Purpose I/O Register */
+#define	SRAM_TC				0x0160	/* 32 bit	SRAM Timing Control */
+#define	SRAM_PD				0x0168	/* 32 bit	SRAM Power-Down Control */
+#define	PCIE_PHY			0x0170	/* 32 bit	PCI Express PHY Address Register */
+#define	RAM_ADDR			0x0180	/* 32 bit	RAM Address Register */
+#define	RAM_DATA_LO			0x0184	/* 32 bit	Data Port/Lower Dword Register */
+#define	RAM_DATA_HI			0x0188	/* 32 bit	Data Port/Upper Dword Register */
+#define	ASF_TO_0_3			0x0190	/* 32 bit	Timeout Register */
+#define	ASF_TO_4			0x0194	/* 32 bit	Timeout Register */
+#define	ASF_SRAMTC			0x0198	/* 32 bit	Timeout Register */
+#define	ASF_CTRL			0x01A0	/* 32 bit	FIFO Interface Control */
+#define	RSS_KEY0			0x0220	/* 32 bit	RSS Key 0 Register */
+#define	RSS_KEY1			0x0224	/* 32 bit	RSS Key 1 Register */
+#define	RSS_KEY2			0x0228	/* 32 bit	RSS Key 2 Register */
+#define	RSS_KEY3			0x022C	/* 32 bit	RSS Key 3 Register */
+#define	RSS_KEY4			0x0230	/* 32 bit	RSS Key 4 Register */
+#define	RSS_KEY5			0x0234	/* 32 bit	RSS Key 5 Register */
+#define	RSS_KEY6			0x0238	/* 32 bit	RSS Key 6 Register */
+#define	RSS_KEY7			0x023C	/* 32 bit	RSS Key 7 Register */
+#define	RSS_KEY8			0x0240	/* 32 bit	RSS Key 8 Register */
+#define	RSS_KEY9			0x0244	/* 32 bit	RSS Key 9 Register */
+#define	RSS_CFG				0x0248	/* 32 bit	RSS Configuration Register */
+#define	FCU_MEM_BASE_ADDR	0x0300	/* 32 bit	FCU Memory Base Address */
+#define	FCU_REG_BASE_ADDR	0x0304	/* 32 bit	FCU Register Base Address */
+#define	FCU_MEM_CTRL		0x0308	/* 32 bit	FCU Memory/Register Control */
+#define	FCU_RD_DATA			0x030C	/* 32 bit	FCU Memory/Register Read Data */
+#define	FCU_WR_DATA			0x0310	/* 32 bit	FCU Memory/Register Write Data */
+#define	FCU_IMEM_BASE_ADDR	0x0314	/* 32 bit	FCU Information Memory Address */
+#define	FCU_ROM_BASE_ADDR	0x0318	/* 32 bit	FCU ROM Base Address */
+#define	FLASH_MEM_CMD		0x0000	/* 32 bit	Flash Memory Instruction and
+									 *			Command Register (indirect
+									 *			access)
+									 */
+#define	FLASH_MEM_THRESH	0x0004	/* 32 bit	Read Buffer Threshold Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_CTRL_CFG	0x0008	/* 32 bit	Flash Memory Controller
+									 *			Configuration Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_STATUS	0x0014	/* 32 bit	Flash Memory Status Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_WORD0		0x0018	/* 32 bit	Flash Memory ID Word 0 Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_WORD1		0x001C	/* 32 bit	Flash Memory ID Word 1 Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_INT_MSK	0x0020	/* 32 bit	Flash Memory Controller
+									 *			Interrupt Enable and Status
+									 *			Register (indirect access)
+									 */
+#define	FLASH_MEM_INPT_CTRL	0x0024	/* 32 bit	Flash Memory Controller Pad
+									 *			Input Delay Selection
+									 *			Register (indirect access)
+									 */
+#define	FLASH_MEM_OUTP_CTRL	0x0028	/* 32 bit	Flash Memory Controller Pad
+									 *			Output Delay Selection
+									 *			Register (indirect access)
+									 */
+#define	FLASH_MEM_PWR_PARA	0x002C	/* 32 bit	Flash Memory Power up Parameter
+									 *			Register (indirect access)
+									 */
+#define	FLASH_MEM_INT_SYNC	0x0030	/* 32 bit	Flash Memory Internal
+									 *			Synchronous Register
+									 *			(indirect access)
+									 */
+#define	FLASH_MEM_INT_DBG1	0x0034	/* 32 bit	Flash Memory Internal Debug
+									 *			Register 1 (indirect access)
+									 */
+#define	FLASH_MEM_INT_DBG2	0x0038	/* 32 bit	Flash Memory Internal Debug
+									 *			Register 2 (indirect access)
+									 */
+#define	FLASH_MEM_WD		0x003C	/* 32 bit	Flash Memory Soft Reset and
+									 *			Watchdog Timeout Reset
+									 *			Parameter Register (indirect
+									 *			access)
+									 */
+#define	RBMU_DESCR			0x0400	/* 32 bit	Current Receive Descriptor
+									 */
+#define	RBMU_HASH			0x0404	/* 32 bit	RSS Hash Checksum
+									 */
+#define	RBMU_ADDR_HI		0x0408	/* 32 bit	Receive Buffer Address Low
+									 */
+#define	RBMU_ADDR_LO		0x040C	/* 32 bit	Receive Buffer Address High
+									 */
+#define	RBMU_RFSW			0x0410	/* 32 bit	Receive Buffer Status Word
+									 */
+#define	RBMU_TSP			0x0414	/* 32 bit	Receive Timestamp
+									 */
+#define	RBMU_VLAN			0x0420	/* 32 bit	VLAN Tag Register/
+									 */
+#define	RBMU_DONE_IDX		0x0424	/* 32 bit	Receive Done Index
+									 */
+#define	RBMU_REQ_ADDR_LOW	0x0428	/* 32 bit	Receive Request Address, Lower
+									 */
+#define	RBMU_REQ_ADDR_HIGH	0x042C	/* 32 bit	Receive Request Address, Upper
+									 */
+#define	RBMU_REQ_CNT		0x0430	/* 32 bit	Receive Request Byte Count
+									 */
+#define	RBMU_CSR			0x0434	/* 32 bit	Receive BMU Control/Status
+									 */
+#define	RBMU_TEST			0x0438	/* 32 bit	Receive BMU Test
+									 */
+#define	RBMU_SM				0x043C	/* 32 bit	Receive BMU State Machine
+									 */
+#define	RBMU_FIFO_WM		0x0440	/* 16 bit	Receive FIFO Watermark
+									 */
+#define	RBMU_FIFO_AL		0x0442	/* 16 bit	Receive FIFO Alignment
+									 */
+#define	RPFU_CTRL			0x0450	/* 32 bit	Receive Prefetch Control
+									 */
+#define	RPFU_LAST_IDX		0x0454	/* 32 bit	Receive PFU List Last Index
+									 */
+#define	RPFU_LADR_LO		0x0458	/* 32 bit	Receive PFU List Start Address Low
+									 */
+#define	RPFU_LADR_HI		0x045C	/* 32 bit	Receive PFU List Start Address High
+									 */
+#define	RPFU_GET_IDX		0x0460	/* 32 bit	Receive PFU Get Index
+									 */
+#define	RPFU_PUT_IDX		0x0464	/* 32 bit	Receive PFU Put Index
+									 */
+#define	RPFU_FIFO_WR		0x0470	/* 32 bit	Receive PFU FIFO RAM Write and
+									 *			Write Shadow Pointer Register
+									 */
+#define	RPFU_FIFO_RD		0x0474	/* 32 bit	Receive PFU FIFO RAM Read Pointer
+									 */
+#define	RPFU_FIFO_REQ_NB	0x0478	/* 32 bit	Receive PFU Master Request nbytes
+									 */
+#define	RPFU_FIFO_LEV		0x047C	/* 32 bit	Receive PFU FIFO Shadow Level
+									 */
+
+#define	TPFU_CTRL5			0x0510	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX5		0x0514	/* 32 bit	Transmit PFU List Last Index
+									 */
+#define	TPFU_LADR_LO5		0x0518	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI5		0x051C	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX5		0x0520	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX5		0x0524	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR5		0x0530	/* 32 bit	Transmit PFU FIFO RAM Write
+									 *			and Write Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD5		0x0534	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB5	0x0538	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV5		0x053C	/* 32 bit	Transmit PFU FIFO
+									 *			Shadow Level Register
+									 */
+#define	TPFU_CTRL6			0x0550	/* 32 bit	Transmit Prefetch
+									 *			Control Register
+									 */
+#define	TPFU_LAST_IDX6		0x0554	/* 32 bit	Transmit PFU List Last
+									 *			Index Register
+									 */
+#define	TPFU_LADR_LO6		0x0558	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI6		0x055C	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX6		0x0560	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX6		0x0564	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR6		0x0570	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Write and Write
+									 *			Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD6		0x0574	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB6	0x0578	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV6		0x057C	/* 32 bit	Transmit PFU FIFO
+									 *			Shadow Level Register
+									 */
+#define	TPFU_CTRL7			0x0590	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX7		0x0594	/* 32 bit	Transmit PFU List Last
+									 *			Index Register
+									 */
+#define	TPFU_LADR_LO7		0x0598	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI7		0x059C	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX7		0x05A0	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX7		0x05A4	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR7		0x05B0	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Write and Write
+									 *			Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD7		0x05B4	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB7	0x05B8	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV7		0x05BC	/* 32 bit	Transmit PFU FIFO
+									 *			Shadow Level Register
+									 */
+#define	TPFU_CTRL8			0x05D0	/* 32 bit	Transmit Prefetch
+									 *			Control Register
+									 */
+#define	TPFU_LAST_IDX8		0x05D4	/* 32 bit	Transmit PFU List Last
+									 *			Index Register
+									 */
+#define	TPFU_LADR_LO8		0x05D8	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI8		0x05DC	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX8		0x05E0	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX8		0x05E4	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR8		0x05F0	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Write and Write
+									 *			Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD8		0x05F4	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB8	0x05F8	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV8		0x05FC	/* 32 bit	Transmit PFU FIFO
+									 *			Shadow Level Register
+									 */
+
+#define	TPFU_CTRL2			0x0650	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX2		0x0654	/* 32 bit	Transmit PFU List Last Index
+									 */
+#define	TPFU_LADR_LO2		0x0658	/* 32 bit	Transmit PFU List Start Address Low
+									 */
+#define	TPFU_LADR_HI2		0x065C	/* 32 bit	Transmit PFU List Start Address High
+									 */
+#define	TPFU_GET_IDX2		0x0660	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX2		0x0664	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR2		0x0670	/* 32 bit	Transmit PFU FIFO RAM Write and
+									 *			Write Shadow Pointer Register
+									 */
+#define	TPFU_FIFO_RD2		0x0674	/* 32 bit	Transmit PFU FIFO RAM Read Pointer
+									 */
+#define	TPFU_FIFO_REQ_NB2	0x0678	/* 32 bit	Transmit PFU Master Request nbytes
+									 */
+#define	TPFU_FIFO_LEV2		0x067C	/* 32 bit	Transmit PFU FIFO Shadow Level
+									 */
+#define	TBMU_DESC1			0x0680	/* 32 bit	Current Transmit Descriptor 1
+									 */
+#define	TBMU_DESC2			0x0684	/* 16 bit	Current Transmit Descriptor 2
+									 */
+#define	TBMU_ADDR_LO		0x0688	/* 32 bit	Transmit Buffer Address Lower
+									 */
+#define	TBMU_ADDR_HI		0x068C	/* 32 bit	Transmit Buffer Address Upper
+									 */
+#define	TBMU_TFSW			0x0690	/* 32 bit	Transmit Buffer Status Word
+									 */
+#define	TBMU_VLAN			0x06A0	/* 32 bit	Transmit VLAN Tag
+									 */
+#define	TBMU_DONE_IDX		0x06A4	/* 32 bit	Transmit Done Index
+									 */
+#define	TBMU_REQ_ADDR_LO	0x06A8	/* 32 bit	Transmit Request Address Lower
+									 */
+#define	TBMU_REQ_ADDR_HI	0x06AC	/* 32 bit	Transmit Request Address Upper
+									 */
+#define	TBMU_REQ_CNT		0x06B0	/* 32 bit	Transmit Request Byte Count
+									 */
+#define	TBMU_CSR			0x06B4	/* 32 bit	Transmit BMU Control/Status
+									 */
+#define	TBMU_TEST			0x06B8	/* 32 bit	Transmit BMU Test Register
+									 */
+#define	TBMU_SM				0x06BC	/* 32 bit	Transmit BMU State Machine
+									 */
+#define	TBMU_FIFO_WM		0x06C0	/* 16 bit	Transmit FIFO Watermark/
+									 */
+#define	TBMU_FIFO_AL		0x06C2	/* 16 bit	Transmit FIFO Alignment
+									 */
+#define	TBMU_FIFO_WSPTR		0x06C4	/* 16 bit	Transmit FIFO Write Shadow Pointer
+									 */
+#define	TBMU_FIFO_WSLEV		0x06C6	/* 16 bit	Transmit FIFO Write Shadow Level
+									 */
+#define	TBMU_FIFO_WPTR		0x06C8	/* 16 bit	Transmit FIFO Write Pointer
+									 */
+#define	TBMU_FIFO_WLEV		0x06CA	/* 16 bit	Transmit FIFO Write Level
+									 */
+#define	TBMU_FIFO_RPTR		0x06CC	/* 16 bit	Transmit FIFO Read Pointer
+									 */
+#define	TBMU_RLEV			0x06CE	/* 16 bit	Transmit FIFO Read Level
+									 */
+#define	TPFU_CTRL			0x06D0	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX		0x06D4	/* 32 bit	Transmit PFU List Last Index
+									 */
+#define	TPFU_LADR_LO		0x06D8	/* 32 bit	Transmit PFU List Start Address Low
+									 */
+#define	TPFU_LADR_HI		0x06DC	/* 32 bit	Transmit PFU List Start Address High
+									 */
+#define	TPFU_GET_IDX		0x06E0	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX		0x06E4	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR		0x06F0	/* 32 bit	Transmit PFU FIFO RAM Write and
+									 *			Write Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD		0x06F4	/* 32 bit	Transmit PFU FIFO RAM Read Pointer
+									 */
+#define	TPFU_FIFO_REQ_NB	0x06F8	/* 32 bit	Transmit PFU Master Request nbytes
+									 */
+#define	TPFU_FIFO_LEV		0x06FC	/* 32 bit	Transmit PFU FIFO Shadow Level
+									 */
+#define TPLE1_REQ_CTRL		0x0700	/* 32 bit	LE1 Request Control
+									 */
+#define	TPLE_REQ_CTRL_CLR_LEPKT_COUNT		BIT_8			/* Clear Packet Counter */
+#define	TPLE_REQ_CTRL_LE_REQ_PRI_MSK		SHIFT0(0x3)		/* LE Request Priority */
+#define	TPLE_REQ_CTRL_LE_REQ_PRI_BASE		0
+
+#define TPLE1_REQ_TH		0x0704	/* 32 bit	LE1 Request Threshold
+									 */
+
+#define	TPLE_REQ_TH_H_MAP_MSK				SHIFT29(0x7)
+#define	TPLE6_REQ_TH_H_MAP_BASE				29
+#define	TPLE_REQ_TH_CREDIT_OVERFLOW			BIT_31
+#define	TPLE_REQ_TH_CREDIT_REQ_TH_MSK		SHIFT16(0x1fff)	/* Request Threshold */
+#define	TPLE_REQ_TH_CREDIT_REQ_TH_BASE		16
+#define	TPLE_REQ_TH_CREDIT_MSK				SHIFT0(0x1fff)	/* LE1 AVB Queue Credit */
+#define	TPLE_REQ_TH_CREDIT_BASE				0
+
+#define TPLE1_LEPKT_COUNTER 0x0708	/* 32 bit	LE1 Packet Counter
+									 */
+#define TPLE2_REQ_CTRL		0x0710	/* 32 bit	LE2 Request Control
+									 */
+#define TPLE2_REQ_TH		0x0714	/* 32 bit	LE2 Request Threshold
+									 */
+#define TPLE2_LEPKT_COUNTER 0x0718	/* 32 bit	LE2 Packet Counter
+									 */
+#define TPLE3_REQ_CTRL		0x0720	/* 32 bit	LE3 Request Control
+									 */
+#define TPLE3_REQ_TH		0x0724	/* 32 bit	LE3 Request Threshold
+									 */
+#define TPLE3_LEPKT_COUNTER 0x0728	/* 32 bit	LE3 Packet Counter
+									 */
+#define TPLE4_REQ_CTRL		0x0730	/* 32 bit	LE4 Request Control
+									 */
+#define TPLE4_REQ_TH		0x0734	/* 32 bit	LE4 Request Threshold
+									 */
+#define TPLE4_LEPKT_COUNTER 0x0738	/* 32 bit	LE4 Packet Counter
+									 */
+#define	TPFU_CTRL4			0x0750	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX4		0x0754	/* 32 bit	Transmit PFU List Last Index
+									 */
+#define	TPFU_LADR_LO4		0x0758	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI4		0x075C	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX4		0x0760	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX4		0x0764	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR4		0x0770	/* 32 bit	Transmit PFU FIFO RAM Write and
+									 *			Write Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD4		0x0774	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB4	0x0778	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV4		0x077C	/* 32 bit	Transmit PFU FIFO Shadow Level
+									 */
+#define TPLE5_REQ_CTRL		0x0780	/* 32 bit	LE5 Request Control
+									 */
+#define TPLE5_REQ_TH		0x0784	/* 32 bit	LE5 Request Threshold
+									 */
+#define TPLE5_LEPKT_COUNTER 0x0788	/* 32 bit	LE5 Packet Counter
+									 */
+#define TPLE6_REQ_CTRL		0x0790	/* 32 bit	LE6 Request Control
+									 */
+#define TPLE6_REQ_TH		0x0794	/* 32 bit	LE6 Request Threshold
+									 */
+#define TPLE6_LEPKT_COUNTER	0x0798	/* 32 bit	LE6 Packet Counter
+									 */
+#define TPLE7_REQ_CTRL		0x07A0	/* 32 bit	LE7 Request Control
+									 */
+#define TPLE7_REQ_TH		0x07A4	/* 32 bit	LE7 Request Threshold
+									 */
+#define TPLE7_LEPKT_COUNTER 0x07A8	/* 32 bit	LE7 Packet Counter
+									 */
+#define TPLE8_REQ_CTRL		0x07B0	/* 32 bit	LE8 Request Control
+									 */
+#define TPLE8_REQ_TH		0x07B4	/* 32 bit	LE8 Request Threshold
+									 */
+#define TPLE8_LEPKT_COUNTER	0x07B8	/* 32 bit	LE8 Packet Counter
+									 */
+#define LE_ARB_CTL			0x07C0	/* 32 bit	LE Arbiter Control
+									 */
+#define	TPFU_CTRL3			0x07D0	/* 32 bit	Transmit Prefetch Control
+									 */
+#define	TPFU_LAST_IDX3		0x07D4	/* 32 bit	Transmit PFU List Last Index
+									 */
+#define	TPFU_LADR_LO3		0x07D8	/* 32 bit	Transmit PFU List Start
+									 *			Address Low Register
+									 */
+#define	TPFU_LADR_HI3		0x07DC	/* 32 bit	Transmit PFU List Start
+									 *			Address High Register
+									 */
+#define	TPFU_GET_IDX3		0x07E0	/* 32 bit	Transmit PFU Get Index
+									 */
+#define	TPFU_PUT_IDX3		0x07E4	/* 32 bit	Transmit PFU Put Index
+									 */
+#define	TPFU_FIFO_WR3		0x07F0	/* 32 bit	Transmit PFU FIFO RAM Write and
+									 *			Write Shadow Pointer
+									 */
+#define	TPFU_FIFO_RD3		0x07F4	/* 32 bit	Transmit PFU FIFO RAM
+									 *			Read Pointer Register
+									 */
+#define	TPFU_FIFO_REQ_NB3	0x07F8	/* 32 bit	Transmit PFU Master
+									 *			Request nbytes
+									 */
+#define	TPFU_FIFO_LEV3		0x07FC	/* 32 bit	Transmit PFU FIFO Shadow Level
+									 */
+
+#define	PKT_GEN_CTL			0x0800	/* 32 bit	Packet Generator Control
+									 */
+#define	PKT_GEN_LEN_CTRL	0x0804	/* 32 bit	Packet Generator Length
+									 */
+#define	PKT_GEN_PKT_COUNTER	0x0808	/* 32 bit	Packet Generator Packet Counter
+									 */
+#define	PKT_GEN_DELTA		0x080C	/* 32 bit	Packet Generator Data or Packet
+									 *			Size Increment Delta Register
+									 */
+#define	PKT_GEN_PAT1_LO		0x0810	/* 32 bit	Packet Generator Pattern 1 Lo
+									 */
+#define	PKT_GEN_PAT1_HI		0x0814	/* 32 bit	Packet Generator Pattern 1 Hi
+									 */
+#define	PKT_GEN_PAT2_LO		0x0818	/* 32 bit	Packet Generator Pattern 2 Lo
+									 */
+#define	PKT_GEN_PAT2_HI		0x081C	/* 32 bit	Packet Generator Pattern 2 Hi
+									 */
+#define	PKT_GEN_SIZE_LIMIT	0x0820	/* 32 bit	Packet Generator Packet Size Limit
+									 */
+#define	PKT_GEN_PKT_CNT_ST	0x0824	/* 32 bit	Packet Generator Packet Counter
+									 *			Count Down Status Register
+									 */
+#define	PKT_GEN_PKT_GAP		0x0828	/* 32 bit	Packet Generator Packet Gap
+									 */
+#define	PKT_CHK_PFU_START	0x0830	/* 32 bit	Packet Checker RX PFU Start Address
+									 */
+#define	PKT_CHK_BUF_INC		0x0834	/* 32 bit	Packet Checker RX PFU Buffer Increment
+									 */
+#define	PKT_CHK_BUF_SIZE	0x0838	/* 32 bit	Packet Checker RX PFU Buffer Size
+									 */
+#define	PKT_CHK_STATUS		0x083C	/* 32 bit	Packet Checker Status
+									 */
+
+#define	RA_SADDR			0x0900	/* 32 bit	ASF Receive FIFO Start Address
+									 */
+#define	RA_EADDR			0x0904	/* 32 bit	ASF Receive FIFO End Address
+									 */
+#define	RA_WPTR				0x0908	/* 32 bit	ASF Receive FIFO Write Pointer
+									 */
+#define	RA_RPTR				0x090C	/* 32 bit	ASF Receive FIFO Read Pointer
+									 */
+#define	RA_BRST				0x0910	/* 32 bit	ASF Receive FIFO Burst Control
+									 */
+#define	RA_PCNT				0x0920	/* 32 bit	ASF Receive FIFO Packet Counter
+									 */
+#define	RA_LEV				0x0924	/* 32 bit	ASF Receive FIFO Level
+									 */
+#define	RA_CTRL				0x0928	/* 32 bit	ASF Receive FIFO Control/Test
+									 */
+#define	RA_FLSH_CTRL		0x092C	/* 32 bit	ASF Receive FIFO Flush Control
+									 */
+#define	TA_SADDR			0x0940	/* 32 bit	ASF Transmit FIFO Start Address
+									 */
+#define	TA_EADDR			0x0944	/* 32 bit	ASF Transmit FIFO End Address
+									 */
+#define	TA_WPTR				0x0948	/* 32 bit	ASF Transmit FIFO Write Pointer
+									 */
+#define	TA_RPTR				0x094C	/* 32 bit	ASF Transmit FIFO Read Pointer
+									 */
+#define	TA_PCNT				0x0960	/* 32 bit	ASF Transmit FIFO Packet Counter
+									 */
+#define	TA_LEV				0x0964	/* 32 bit	ASF Transmit FIFO Level
+									 */
+#define	TA_CTRL				0x0968	/* 32 bit	ASF Transmit FIFO Control/Test
+									 */
+#define	TA_SEND_CTRL		0x096C	/* 32 bit	ASF Transmit FIFO Send Control
+									 */
+#define	RXMF_EADDR			0x0C40	/* 32 bit	Receive MAC FIFO End Address
+									 */
+#define	RXMF_AFTH			0x0C44	/* 32 bit	Receive MAC FIFO Almost Full
+									 *			Threshold Register
+									 */
+#define	RXMF_TCTL			0x0C48	/* 32 bit	Receive MAC FIFO Control/Test
+									 */
+#define	RXMF_FLMSK			0x0C4C	/* 32 bit	Receive MAC FIFO Flush Mask
+									 */
+#define	RXMF_FLTH			0x0C50	/* 32 bit	Receive MAC FIFO Flush
+									 *			Threshold Register
+									 */
+#define	RXMF_TRTH			0x0C54	/* 32 bit	Receive Truncation Threshold
+									 */
+#define	RXMF_ULTH			0x0C58	/* 32 bit	Upper/Lower Threshold/Pause
+									 *			Packets Register
+									 */
+#define	RXMF_VLTYP			0x0C5C	/* 32 bit	Receive VLAN Type Register
+									 */
+#define	RXMF_WPTR			0x0C60	/* 32 bit	Receive MAC FIFO Write Pointer
+									 */
+#define	RXMF_WLEV			0x0C68	/* 32 bit	Receive MAC FIFO Write Level
+									 */
+#define	RXMF_RPTR			0x0C70	/* 32 bit	Receive MAC FIFO Read Pointer
+									 */
+#define	RXMF_RLEV			0x0C78	/* 32 bit	Receive MAC FIFO Read Level
+									 */
+#define	RXMF_FCNT			0x0C7C	/* 32 bit	Receive MAC FIFO Flush Counter
+									 */
+#define	TXMF_TCTL2			0x0D08	/* 32 bit	Transmit MAC FIFO Control/Test
+									 */
+#define	TX2_RATE_LIMIT		0x0D0C	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Limiter Register
+									 */
+#define	TX2_RATE_INT		0x0D10	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Rate Shaper Register
+									 */
+#define	TX2_RATE_FRAC		0x0D14	/* 32 bit	Tx 2 Rate Fraction
+									 */
+#define	TX2_RATE_MISC		0x0D18	/* 32 bit	Tx 2 Misc Rate Register
+									 */
+#define	TX2_RATE_GAP		0x0D1C	/* 32 bit	Tx 2 Rate Gap Register
+									 */
+#define	TXMF_WPTR2			0x0D20	/* 32 bit	Transmit MAC FIFO Write
+									 *			Pointer Register
+									 */
+#define	TXMF_WSPTR2			0x0D24	/* 32 bit	Transmit MAC FIFO Write
+									 *			Shadow Pointer
+									 */
+#define	TXMF_WLEV2			0x0D28	/* 32 bit	Transmit MAC FIFO Write
+									 *			Level Register
+									 */
+#define	TXMF_RPTR2			0x0D30	/* 32 bit	Transmit MAC FIFO Read
+									 *			Pointer Register
+									 */
+#define	TXMF_RES_PTR2		0x0D34	/* 32 bit	Transmit MAC FIFO
+									 *			Restart Pointer
+									 */
+#define	TXMF_RLEV2			0x0D38	/* 32 bit	Transmit MAC FIFO Read
+									 *			Level Register
+									 */
+#define	TX2_AVB_ST			0x0D3C	/* 32 bit	Transmit Queue 2 AVB
+									 *			Status Register
+									 */
+#define	TXMF_EADDR			0x0D40	/* 32 bit	Transmit MAC FIFO End Address
+									 */
+#define	TXMF_AETH			0x0D44	/* 32 bit	Transmit MAC FIFO Almost Empty
+									 *			Threshold Register
+									 */
+#define	TXMF_TCTL			0x0D48	/* 32 bit	Transmit MAC FIFO Control/Test
+									 */
+#define	TX1_RATE_LIMIT		0x0D4C	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Limiter
+									 */
+#define	TX1_RATE_INT		0x0D50	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Rate Shaper
+									 */
+#define	TX1_RATE_FRAC		0x0D54	/* 32 bit	Tx 1 Rate Fraction
+									 */
+#define	TX1_RATE_MISC		0x0D58	/* 32 bit	Tx 1 Misc Rate Register
+									 */
+#define	TXMF_VLTYP			0x0D5C	/* 32 bit	Transmit VLAN Type Register
+									 */
+#define	TXMF_WPTR			0x0D60	/* 32 bit	Transmit MAC FIFO Write Pointer
+									 */
+#define	TXMF_WSPTR			0x0D64	/* 32 bit	Transmit MAC FIFO Write Shadow
+									 *			Pointer Register
+									 */
+#define	TXMF_WLEV			0x0D68	/* 32 bit	Transmit MAC FIFO Write Level
+									 */
+#define	TXMF_RPTR			0x0D70	/* 32 bit	Transmit MAC FIFO Read Pointer
+									 */
+#define	TXMF_RES_PTR		0x0D74	/* 32 bit	Transmit MAC FIFO Restart Pointer
+									 */
+#define	TXMF_RLEV			0x0D78	/* 32 bit	Transmit MAC FIFO Read Level
+									 */
+#define	TX1_AVB_ST			0x0D7C	/* 32 bit	Transmit Queue 1 AVB
+									 *			Status Register
+									 */
+#define	TXMF_TCTL3			0x0D88	/* 32 bit	Transmit MAC FIFO
+									 *			Control/Test Register
+									 */
+#define	TX3_RATE_LIMIT		0x0D8C	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Limiter Register
+									 */
+#define	TX3_RATE_INT		0x0D90	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Rate Shaper Register
+									 */
+#define	TX3_RATE_FRAC		0x0D94	/* 32 bit	Tx 3 Rate Fraction
+									 */
+#define	TX3_RATE_MISC		0x0D98	/* 32 bit	Tx 3 Misc Rate Register
+									 */
+#define	TX3_RATE_GAP		0x0D9C	/* 32 bit	Tx 3 Rate Gap Register
+									 */
+#define	TXMF_WPTR3			0x0DA0	/* 32 bit	Transmit MAC FIFO Write
+									 *			Pointer Register
+									 */
+#define	TXMF_WSPTR3			0x0DA4	/* 32 bit	Transmit MAC FIFO Write
+									 *			Shadow Pointer
+									 */
+#define	TXMF_WLEV3			0x0DA8	/* 32 bit	Transmit MAC FIFO Write
+									 *			Level Register
+									 */
+#define	TXMF_RPTR3			0x0DB0	/* 32 bit	Transmit MAC FIFO Read
+									 *			Pointer Register
+									 */
+#define	TXMF_RES_PTR3		0x0DB4	/* 32 bit	Transmit MAC FIFO
+									 *			Restart Pointer
+									 */
+#define	TXMF_RLEV3			0x0DB8	/* 32 bit	Transmit MAC FIFO Read
+									 *			Level Register
+									 */
+#define	TX3_AVB_ST			0x0DBC	/* 32 bit	Transmit Queue 3 AVB Status
+									 */
+#define	TXMF_TCTL4			0x0DC8	/* 32 bit	Transmit MAC FIFO Control/Test
+									 */
+#define	TX4_RATE_LIMIT		0x0DCC	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Limiter Register
+									 */
+#define	TX4_RATE_INT		0x0DD0	/* 32 bit	Transmit MAC FIFO AVB
+									 *			Rate Shaper Register
+									 */
+#define	TX4_RATE_FRAC		0x0DD4	/* 32 bit	Tx 4 Rate Fraction
+									 */
+#define	TX4_RATE_MISC		0x0DD8	/* 32 bit	Tx 4 Misc Rate Register
+									 */
+#define	TX4_RATE_GAP		0x0DDC	/* 32 bit	Tx 4 Rate Gap Register
+									 */
+#define	TXMF_WPTR4			0x0DE0	/* 32 bit	Transmit MAC FIFO Write
+									 *			Pointer Register
+									 */
+#define	TXMF_WSPTR4			0x0DE4	/* 32 bit	Transmit MAC FIFO Write
+									 *			Shadow Pointer
+									 */
+#define	TXMF_WLEV4			0x0DE8	/* 32 bit	Transmit MAC FIFO Write
+									 *			Level Register
+									 */
+#define	TXMF_RPTR4			0x0DF0	/* 32 bit	Transmit MAC FIFO Read
+									 *			Pointer Register
+									 */
+#define	TXMF_RES_PTR4		0x0DF4	/* 32 bit	Transmit MAC FIFO
+									 *			Restart Pointer
+									 */
+#define	TXMF_RLEV4			0x0DF8	/* 32 bit	Transmit MAC FIFO Read Level
+									 */
+#define	TX4_AVB_ST			0x0DFC	/* 32 bit	Transmit Queue4 AVB Status
+									 */
+#define	DPOL_TIM_INIT		0x0E00	/* 32 bit	Descriptor Poll Timer Init Value
+									 */
+#define	DPOL_TIM_CNT		0x0E04	/* 32 bit	Descriptor Poll Timer Register
+									 */
+#define	DPOL_TCTL			0x0E08	/* 32 bit	Descriptor Poll Timer
+									 *			Control/Test Register
+									 */
+#define	TSP_TIM_CNT			0x0E14	/* 32 bit	Timestamp Timer Registers
+									 */
+#define	TSP_TIM_TCTL		0x0E18	/* 32 bit	Timestamp Timer Control/Test
+									 */
+/* #define	POLL_CTRL			0x0E20	* 32 bit	Poll Control Register * */
+/* #define	POLL_LAST_IDX		0x0E24	* 32 bit	List Last Index Register * */
+#define	POLL_LADR_LO		0x0E28	/* 32 bit	List Start Address Low Register */
+#define	POLL_LADR_HI		0x0E2C	/* 32 bit	List Start Address High Register */
+#define	CPU_ISRC			0x0E30	/* 32 bit	Interrupt Source Register */
+#define	CPU_IMSK			0x0E34	/* 32 bit	Interrupt Mask Register */
+#define	SMB_CFG				0x0E40	/* 32 bit	SMBus Config Register */
+#define	SMB_CSR				0x0E44	/* 32 bit	SMBus Control/Status Register */
+#define	CPU_WDOG			0x0E48	/* 32 bit	Watchdog Register */
+#define	CPU_CNTR			0x0E4C	/* 32 bit	Counter Register */
+#define	CPU_TIM				0x0E50	/* 32 bit	Timer Compare Register */
+#define	CPU_TIM_2			0x0E54	/* 32 bit	Timer Compare Register (Y-Supreme)*/
+#define	CPU_AHB_WDATA		0x0E58	/* 32 bit	CPU AHB Debug Register */
+#define	CPU_AHB_RDATA		0x0E5C	/* 32 bit	CPU AHB Debug Register */
+#define	HCU_MAP_BASE		0x0E60	/* 32 bit	Reset Mapping Base */
+#define	CPU_AHB_CTRL		0x0E64	/* 32 bit	CPU AHB Debug Register */
+#define	HCU_CCSR			0x0E68	/* 32 bit	CPU Control and Status Register */
+#define	HCU_HCSR			0x0E6C	/* 32 bit	Host Control and Status Register */
+#define	HCU_DATA1			0x0E70	/* 32 bit	Data Register 1 */
+#define	HCU_DATA2			0x0E74	/* 32 bit	Data Register 2 */
+#define	HCU_DATA3			0x0E78	/* 32 bit	Data Register 3 */
+#define	HCU_DATA4			0x0E7C	/* 32 bit	Data Register 4 */
+#define	TXMF_TCTL5			0x0348	/* 32 bit	Transmit MAC FIFO
+									 *			Control/Test Register
+									 */
+#define	TXMF_PRI5			0x0358	/* 32 bit	Transmit MAC FIFO
+									 *			Priority Register
+									 */
+#define	TXMF_WPTR5			0x0360	/* 32 bit	Transmit MAC FIFO Write
+									 *			Pointer Register
+									 */
+#define	TXMF_WSPTR5			0x0364	/* 32 bit	Transmit MAC FIFO Write
+									 *			Shadow Pointer
+									 *			Register
+									 */
+#define	TXMF_WLEV5			0x0368	/* 32 bit	Transmit MAC FIFO Write
+									 *			Level Register
+									 */
+#define	TXMF_RPTR5			0x0370	/* 32 bit	Transmit MAC FIFO Read
+									 *			Pointer Register
+									 */
+#define	TXMF_RES_PTR5		0x0374	/* 32 bit	Transmit MAC FIFO
+									 *			Restart Pointer
+									 *			Register
+									 */
+#define	TXMF_RLEV5			0x0378	/* 32 bit	Transmit MAC FIFO Read
+									 *			Level Register
+									 */
+/* #define	STAT_CTRL			0x0E80	* 32 bit	Status BMU Control Register */
+/* #define	STAT_LAST_IDX		0x0E84	* 32 bit	Last Index Register */
+#define	STAT_LADR_LO		0x0E88	/* 32 bit	List Start Address Lower
+									 */
+#define	STAT_LADR_HI		0x0E8C	/* 32 bit	List Start Address Upper
+									 */
+#define	STAT_TXA_REP		0x0E90	/* 16 bit	TXA Report Index Register */
+#define	STAT_TXTH			0x0E98	/* 16 bit	TX Index Threshold Register */
+#define	STAT_PUT			0x0E9C	/* 32 bit	Put Index Register */
+#define	STAT_FIFO_WPTR		0x0EA0	/* 32 bit	FIFO Write Pointer Register */
+#define	STAT_FIFO_RPTR		0x0EA4	/* 32 bit	FIFO Read Pointer Register */
+#define	STAT_FIFO_LEV		0x0EA8	/* 32 bit	FIFO Level Register */
+/* #define	STAT_FIFO_WM		0x0EAC	*  8 bit	FIFO Watermark Register * */
+#define	STAT_FIFO_WM_ISR	0x0EAD	/*  8 bit	FIFO ISR Watermark Register */
+#define	LEV_TIM_INIT		0x0EB0	/* 32 bit	Level Timer Init Value Register */
+#define	LEV_TIM_CNT			0x0EB4	/* 32 bit	Level Timer Counter Register */
+#define	LEV_TIM_TCTL		0x0EB8	/* 32 bit	Level Timer Control/Test
+									 */
+#define	TX_TIM_INIT			0x0EC0	/* 32 bit	TX TImer Init Value Register */
+#define	TX_TIM_CNT			0x0EC4	/* 32 bit	TX Timer Counter Register */
+#define	TX_TIM_TCTL			0x0EC8	/* 32 bit	TX Timer Control/Test Register */
+#define	ISR_TIM_INIT		0x0ED0	/* 32 bit	ISR Timer Init Value Register */
+#define	ISR_TIM_CNT			0x0ED4	/* 32 bit	ISR Timer Counter Register */
+#define	ISR_TIM_TCTL		0x0ED8	/* 32 bit	ISR Timer Control/Test Register */
+#define	MAC_CTRL			0x0F00	/* 16 bit	MAC Control Registers */
+#define	PHY_CFG				0x0F04	/* 32 bit	PHY Config Register, loaded
+									 *			from external memory
+									 */
+#define	MAC_ISRC			0x0F08	/* 32 bit	MAC Interrupt Source Register */
+#define	MAC_IMSK			0x0F0C	/* 32 bit	MAC Interrupt Mask Register */
+#define	LINK_CTRL			0x0F10	/* 16 bit	Link Control Register */
+#define	WOL_CSR				0x0F20	/* 16 bit	WOL Control/Status Register */
+#define	WOL_MCTRL			0x0F22	/* 16 bit	Match Control Register */
+#define	WOL_MADDR_LO		0x0F24	/* 32 bit	MAC Address Register Low
+									 */
+#define	WOL_MADDR_HI		0x0F28	/* 16 bit	MAC Address Register High
+									 *			Register
+									 */
+#define	WOL_PME_MEN			0x0F2A	/* 16 bit	PME Match Enable Register */
+#define	WOL_ASF_MEN			0x0F2C	/* 16 bit	ASF Match Enable Register */
+#define	WOL_MRSL			0x0F2E	/* 16 bit	Match Result Register */
+#define	WOL_PLEN0			0x0F30	/* 32 bit	Pattern Length Register 0 (0-3) */
+#define	WOL_PLEN1			0x0F34	/* 32 bit	Pattern Length Register 1 (4-7) */
+#define	WOL_PLEN2			0x0F38	/* 32 bit	Pattern Length Register 2 (8-11) */
+#define	WOL_PLEN3			0x0F3C	/* 32 bit	Pattern Length Register 3
+									 *			(12-13)
+									 */
+#define	WOL_PCNT0			0x0F40	/* 32 bit	Pattern Counter Register 0 (0-3) */
+#define	WOL_PCNT1			0x0F44	/* 32 bit	Pattern Counter Register 1 (4-7) */
+#define	WOL_PCNT2			0x0F48	/* 32 bit	Pattern Counter Register 2
+									 *			(8-11)
+									 */
+#define	WOL_PCNT3			0x0F4C	/* 32 bit	Pattern Counter Register 2
+									 *			(12-13)
+									 */
+#define	PAT_CSR				0x0F50	/* 32 bit	Pattern RAM Control/Status
+									 *			Register
+									 */
+#define	PAT_P12PPMC			0x0F5C	/* 32 bit	Pattern 12 Port Pattern Match
+									 *			Control Register
+									 */
+#define	PAT_P12PPMDR0		0x0F60	/* 32 bit	Pattern 12 Port Pattern Match
+									 *			Data 0 Register
+									 */
+#define	PAT_P12PPMDR1		0x0F64	/* 32 bit	Pattern 12 Port Pattern Match
+									 *			Data 1 Register
+									 */
+#define	PAT_P12PPMDR2		0x0F68	/* 32 bit	Pattern 12 Port Pattern Match
+									 *			Data 2 Register
+									 */
+#define	PAT_P12PPMDR3		0x0F6C	/* 32 bit	Pattern 12 Port Pattern Match
+									 *			Data 3 Register
+									 */
+#define	PAT_P13PPMC			0x0F7C	/* 32 bit	Pattern 13 Port Pattern Match
+									 *			Control Register
+									 */
+#define	PAT_P13PPMDR0		0x0F80	/* 32 bit	Pattern 13 Port Pattern Match
+									 *			Data 0 Register
+									 */
+#define	PAT_P13PPMDR1		0x0F84	/* 32 bit	Pattern 13 Port Pattern Match
+									 *			Data 1 Register
+									 */
+#define	PAT_P13PPMDR2		0x0F88	/* 32 bit	Pattern 13 Port Pattern Match
+									 *			Data 2 Register
+									 */
+#define	PAT_P13PPMDR3		0x0F8C	/* 32 bit	Pattern 13 Port Pattern Match
+									 *			Data 3 Register
+									 */
+#define	CLASS_A_RATE_INT	0x0FA0	/* 32 bit	Class A Rate Integer
+									 */
+#define	CLASS_A_RATE_FRAC	0x0FA4	/* 32 bit	Class A Rate Fraction
+									 */
+#define	CLASSA_RATE_LIMIT	0x0FA8	/* 32 bit	Class A Rate Limiter
+									 */
+#define	CLASS_A_ST			0x0FB0	/* 32 bit	Class A Status
+									 */
+#define	CLASS_B_RATE_INT	0x0FC0	/* 32 bit	Class B Rate Integer
+									 */
+#define	CLASS_B_RATE_FRAC	0x0FC4	/* 32 bit	Class B Rate Fraction
+									 */
+#define	CLASSB_RATE_LIMIT	0x0FC8	/* 32 bit	Class B Rate Limiter
+									 */
+#define	CLASS_B_ST			0x0FD0	/* 32 bit	Class B Status
+									 */
+#define	PTP_ADJ_CTRL1		0x0FE0	/* 32 bit	PTP Rate Clock Adjust
+									 *			Control 1 Register
+									 */
+#define	PTP_ADJ_CTRL2		0x0FE4	/* 32 bit	PTP Rate Clock Adjust
+									 *			Control 2 Register
+									 */
+#define	PTP_ADJ_CTRL3		0x0FE8	/* 32 bit	PTP Rate Clock Adjust
+									 *			Control 3 Register
+									 */
+#define	PAT_RAM_RLO			0x1000 	/* Pattern RAM Register Start */
+#define	PAT_RAM_RHI			0x13FC	/* Pattern RAM Register End */
+#define	THDR0_LO			0x1900	/* 32 bit	TCP Segmentation Header
+									 *			Register 0 Lo
+									 */
+#define	THDR0_HI			0x1904	/* 32 bit	TCP Segmentation Header
+									 *			Register 0 Hi
+									 */
+#define	THDR1_LO			0x1908	/* 32 bit	TCP Segmentation Header
+									 *			Register 1 Lo
+									 */
+#define	THDR1_HI			0x190C	/* 32 bit	TCP Segmentation Header
+									 *			Register 1 Hi
+									 */
+#define	THDR2_LO			0x1910	/* 32 bit	TCP Segmentation Header
+									 *			Register 2 Lo
+									 */
+#define	THDR2_HI			0x1914	/* 32 bit	TCP Segmentation Header
+									 *			Register 2 Hi
+									 */
+#define	THDR3_LO			0x1918	/* 32 bit	TCP Segmentation Header
+									 *			Register 3 Lo
+									 */
+#define	THDR3_HI			0x191C	/* 32 bit	TCP Segmentation Header
+									 *			Register 3 Hi
+									 */
+#define	THDR4_LO			0x1920	/* 32 bit	TCP Segmentation Header
+									 *			Register 4 Lo
+									 */
+#define	THDR4_HI			0x1924	/* 32 bit	TCP Segmentation Header
+									 *			Register 4 Hi
+									 */
+#define	THDR5_LO			0x1928	/* 32 bit	TCP Segmentation Header
+									 *			Register 5 Lo
+									 */
+#define	THDR5_HI			0x192C	/* 32 bit	TCP Segmentation Header
+									 *			Register 5 Hi
+									 */
+#define	THDR6_LO			0x1930	/* 32 bit	TCP Segmentation Header
+									 *			Register 6 Lo
+									 */
+#define	THDR6_HI			0x1934	/* 32 bit	TCP Segmentation Header
+									 *			Register 6 Hi
+									 */
+#define	THDR7_LO			0x1938	/* 32 bit	TCP Segmentation Header
+									 *			Register 7 Lo
+									 */
+#define	THDR7_HI			0x193C	/* 32 bit	TCP Segmentation Header
+									 *			Register 7 Hi
+									 */
+#define	THDR8_LO			0x1940	/* 32 bit	TCP Segmentation Header
+									 *			Register 8 Lo
+									 */
+#define	THDR8_HI			0x1944	/* 32 bit	TCP Segmentation Header
+									 *			Register 8 Hi
+									 */
+#define	THDR9_LO			0x1948	/* 32 bit	TCP Segmentation Header
+									 *			Register 9 Lo
+									 */
+#define	THDR9_HI			0x194C	/* 32 bit	TCP Segmentation Header
+									 *			Register 9 Hi
+									 */
+#define	THDR10_LO			0x1950	/* 32 bit	TCP Segmentation Header
+									 *			Register 10 Lo
+									 */
+#define	THDR10_HI			0x1954	/* 32 bit	TCP Segmentation Header
+									 *			Register 10 Hi
+									 */
+#define	THDR11_LO			0x1958	/* 32 bit	TCP Segmentation Header
+									 *			Register 11 Lo
+									 */
+#define	THDR11_HI			0x195C	/* 32 bit	TCP Segmentation Header
+									 *			Register 11 Hi
+									 */
+#define	THDR12_LO			0x1960	/* 32 bit	TCP Segmentation Header
+									 *			Register 12 Lo
+									 */
+#define	THDR12_HI			0x1964	/* 32 bit	TCP Segmentation Header
+									 *			Register 12 Hi
+									 */
+#define	THDR13_LO			0x1968	/* 32 bit	TCP Segmentation Header
+									 *			Register 13 Lo
+									 */
+#define	THDR13_HI			0x196C	/* 32 bit	TCP Segmentation Header
+									 *			Register 13 Hi
+									 */
+#define	THDR14_LO			0x1970	/* 32 bit	TCP Segmentation Header
+									 *			Register 14 Lo
+									 */
+#define	THDR14_HI			0x1974	/* 32 bit	TCP Segmentation Header
+									 *			Register 14 Hi
+									 */
+#define	THDR15_LO			0x1978	/* 32 bit	TCP Segmentation Header
+									 *			Register 15 Lo
+									 */
+#define	THDR15_HI			0x197C	/* 32 bit	TCP Segmentation Header
+									 *			Register 15 Hi
+									 */
+#define	THDR16_LO			0x1980	/* 32 bit	TCP Segmentation Header
+									 *			Register 16 Lo
+									 */
+#define	THDR16_HI			0x1984	/* 32 bit	TCP Segmentation Header
+									 *			Register 16 Hi
+									 */
+#define	THDR17_LO			0x1988	/* 32 bit	TCP Segmentation Header
+									 *			Register 17 Lo
+									 */
+#define	THDR17_HI			0x198C	/* 32 bit	TCP Segmentation Header
+									 *			Register 17 Hi
+									 */
+#define	THDR18_LO			0x1990	/* 32 bit	TCP Segmentation Header
+									 *			Register 18 Lo
+									 */
+#define	THDR18_HI			0x1994	/* 32 bit	TCP Segmentation Header
+									 *			Register 18 Hi
+									 */
+#define	THDR19_LO			0x1998	/* 32 bit	TCP Segmentation Header
+									 *			Register 19 Lo
+									 */
+#define	THDR19_HI			0x199C	/* 32 bit	TCP Segmentation Header
+									 *			Register 19 Hi
+									 */
+#define	THDR20_LO			0x19A0	/* 32 bit	TCP Segmentation Header
+									 *			Register 20 Lo
+									 */
+#define	THDR20_HI			0x19A4	/* 32 bit	TCP Segmentation Header
+									 *			Register 20 Hi
+									 */
+#define	THDR21_LO			0x19A8	/* 32 bit	TCP Segmentation Header
+									 *			Register 21 Lo
+									 */
+#define	THDR21_HI			0x19AC	/* 32 bit	TCP Segmentation Header
+									 *			Register 21 Hi
+									 */
+#define	THDR22_LO			0x19B0	/* 32 bit	TCP Segmentation Header
+									 *			Register 22 Lo
+									 */
+#define	THDR22_HI			0x19B4	/* 32 bit	TCP Segmentation Header
+									 *			Register 22 Hi
+									 */
+#define	THDR23_LO			0x19B8	/* 32 bit	TCP Segmentation Header
+									 *			Register 23 Lo
+									 */
+#define	THDR23_HI			0x19BC	/* 32 bit	TCP Segmentation Header
+									 *			Register 23 Hi
+									 */
+#define	THDR24_LO			0x19C0	/* 32 bit	TCP Segmentation Header
+									 *			Register 24 Lo
+									 */
+#define	THDR24_HI			0x19C4	/* 32 bit	TCP Segmentation Header
+									 *			Register 24 Hi
+									 */
+#define	THDR25_LO			0x19C8	/* 32 bit	TCP Segmentation Header
+									 *			Register 25 Lo
+									 */
+#define	THDR25_HI			0x19CC	/* 32 bit	TCP Segmentation Header
+									 *			Register 25 Hi
+									 */
+#define	THDR26_LO			0x19D0	/* 32 bit	TCP Segmentation Header
+									 *			Register 26 Lo
+									 */
+#define	THDR26_HI			0x19D4	/* 32 bit	TCP Segmentation Header
+									 *			Register 26 Hi
+									 */
+#define	THDR27_LO			0x19D8	/* 32 bit	TCP Segmentation Header
+									 *			Register 27 Lo
+									 */
+#define	THDR27_HI			0x19DC	/* 32 bit	TCP Segmentation Header
+									 *			Register 27 Hi
+									 */
+#define	THDR28_LO			0x19E0	/* 32 bit	TCP Segmentation Header
+									 *			Register 28 Lo
+									 */
+#define	THDR28_HI			0x19E4	/* 32 bit	TCP Segmentation Header
+									 *			Register 28 Hi
+									 */
+#define	THDR29_LO			0x19E8	/* 32 bit	TCP Segmentation Header
+									 *			Register 29 Lo
+									 */
+#define	THDR29_HI			0x19EC	/* 32 bit	TCP Segmentation Header
+									 *			Register 29 Hi
+									 */
+#define	THDR30_LO			0x19F0	/* 32 bit	TCP Segmentation Header
+									 *			Register 30 Lo
+									 */
+#define	CFG_VLAN_ET1		0x2000	/* 32 bit	VLAN Ethernet Type
+									 *			Configuration Register 1
+									 */
+#define	CFG_VLAN_ET0		0x2004	/* 32 bit	VLAN Ethernet Type
+									 *			Configuration Register 0
+									 */
+#define	CFG_MACSEC_ET1		0x2008	/* 32 bit	802.1AE Ethernet Type
+									 *			Configuration Register 1
+									 */
+#define	CFG_MACSEC_ET0		0x200C	/* 32 bit	802.1AE Ethernet Type
+									 *			Configuration Register 0
+									 */
+#define	CFG_TRAIL_SZ		0x2010	/* 32 bit	Trail Size Configuration
+									 *			Register
+									 */
+#define	CFG_DEFAULT_VLAN0	0x2014	/* 32 bit	Default VLAN Register 0 */
+#define	CFG_DEFAULT_VLAN1	0x2018	/* 32 bit	Default VLAN Register 1 */
+#define	CFG_MACSEC_SL_SZ	0x201C	/* 32 bit	MACsec Size Configuration
+									 *			Register
+									 */
+#define	CFG_MIN_PKT_LEN		0x2020	/* 32 bit	Minimum Packet Length
+									 *			Configuration Register
+									 */
+#define	SEC_CLK_RST			0x2024	/* 32 bit	MACsec Clock Reset Register */
+#define	EGR_KS_SELECT		0x2028	/* 32 bit	Egress Key Store Select Register */
+#define	EGR_KS_WRDATA		0x202C	/* 32 bit	Egress Key Store Write Data
+									 *			Register
+									 */
+#define	IGR_KS_SELECT		0x2030	/* 32 bit	Ingress Key Store Select
+									 *			Register
+									 */
+#define	IGR_KS_WRDATA		0x2034	/* 32 bit	Ingress Key Store Write Data
+									 *			Register
+									 */
+#define	CFG_ELU_MC_HIGH0	0x2038	/* 32 bit	Multicast Match Register 0 */
+#define	CFG_ELU_MC_HIGH1	0x203C	/* 32 bit	Multicast Match Register 1 */
+#define	CFG_ELU_MC_HIGH2	0x2040	/* 32 bit	Multicast Match Register 2 */
+#define	CFG_ELU_MC_HIGH3	0x2044	/* 32 bit	Multicast Match Register 3 */
+#define	CFG_ELU_MC_HIGH4	0x2048	/* 32 bit	Multicast Match Register 4 */
+#define	CFG_ELU_MC_HIGH5	0x204C	/* 32 bit	Multicast Match Register 5 */
+#define	CFG_ELU_MC_LOW_MSK0	0x2050	/* 32 bit	Multicast Match Mask Register 0 */
+#define	CFG_ELU_MC_LOW_MSK1	0x2054	/* 32 bit	Multicast Match Mask Register 1 */
+#define	CFG_DEFAULT_PORT0	0x2058	/* 32 bit	Default Port Configuration
+									 *			Register 0
+									 */
+#define	CFG_DEFAULT_PORT1	0x205C	/* 32 bit	Default Port Configuration
+									 *			Register 1
+									 */
+#define	CFG_SCB_PORT0		0x2060	/* 32 bit	SCB Port Configuration Register
+									 *			0
+									 */
+#define	CFG_SCB_PORT1		0x2064	/* 32 bit	SCB Port Configuration Register
+									 *			1
+									 */
+#define	CFG_AUTH_ADJUST		0x2068	/* 32 bit	Authentication Adjustment
+									 *			Register
+									 */
+#define	CFG_ELU_GEN			0x206C	/* 32 bit	ELU Default Configuration
+									 *			Register
+									 */
+#define	CFG_ELUC_ADDR		0x2070	/* 32 bit	ELU Address Configuration
+									 *			Register
+									 */
+#define	CFG_ELUC_DATA		0x2074	/* 32 bit	ELU Context Data Configuration
+									 *			Register
+									 */
+#define	CFG_ELUE_ADDR		0x2078	/* 32 bit	ELU Entry Configuration Register */
+#define	CFG_ELUE_DATA		0x207C	/* 32 bit	ELU Lookup Entry Access
+									 *			Configuration Register
+									 */
+#define	CFG_EPR_GEN			0x2080	/* 32 bit	General Egress Parser
+									 *			Configuration Register
+									 */
+#define	EGR_HR_SELECT		0x2084	/* 32 bit	Egress Write Select for H-Store
+									 *			Register
+									 */
+#define	EGR_HR_WRDATA		0x2088	/* 32 bit	Egress Header Write Data
+									 *			Register
+									 */
+#define	IGR_HR_SELECT		0x208C	/* 32 bit	Ingress Write Select for
+									 *			H-Store Register
+									 */
+#define	IGR_HR_WRDATA		0x2090	/* 32 bit	Ingress Header Write Data
+									 *			Register
+									 */
+#define	CFG_ILU_GEN			0x2094	/*  8 bit	cfg_ilu_gen */
+#define	CFG_IMPLICIT_SCI0	0x2098	/* 32 bit	Implicit SCI Register 0 */
+#define	CFG_IMPLICIT_SCI1	0x209C	/* 32 bit	Implicit SCI Register 1 */
+#define	CFG_IMPLICIT_SCI2	0x20A0	/* 32 bit	Implicit SCI Register 2 */
+#define	CFG_IMPLICIT_SCI3	0x20A4	/* 32 bit	Implicit SCI Register 3 */
+#define	CFG_IMPLICIT_SCI4	0x20A8	/* 32 bit	Implicit SCI Register 4 */
+#define	CFG_IMPLICIT_SCI5	0x20AC	/* 32 bit	Implicit SCI Register 5 */
+#define	CFG_IMPLICIT_SCI6	0x20B0	/* 32 bit	Implicit SCI Register 6 */
+#define	CFG_IMPLICIT_SCI7	0x20B4	/* 32 bit	Implicit SCI Register 7 */
+#define	CFG_REPLAY_WINDOW0	0x20B8	/* 32 bit	Replay Window Register 0 */
+#define	CFG_REPLAY_WINDOW1	0x20BC	/* 32 bit	Replay Window Register 1 */
+#define	CFG_REPLAY_WINDOW2	0x20C0	/* 32 bit	Replay Window Register 2 */
+#define	CFG_REPLAY_WINDOW3	0x20C4	/* 32 bit	Replay Window Register 3 */
+#define	CFG_IPR_GEN			0x20C8	/* 32 bit	Ingress Primary Parser Register */
+#define	CFG_ISC_GEN			0x20CC	/* 32 bit	Ingress Security Check Block
+									 *			Register
+									 */
+#define	CFG_RPY_ADDR		0x20D0	/* 32 bit	Replay Protect Table Access
+									 *			Register
+									 */
+#define	CFG_RPY_DATA		0x20D4	/* 32 bit	ELU Context Data Register */
+#define	CFG_ILUT_ADDR		0x20E0	/* 32 bit	Ingress Lookup Table Access
+									 *			Address Configuration Register
+									 */
+#define	CFG_ILUT_DATA		0x20E4	/* 32 bit	ILU Table Data Register */
+#define	STAT_ADDR			0x20E8	/* 32 bit	Statistic Register Address */
+#define	STAT_DATA0			0x20EC	/* 32 bit	Statistic Data Register 0 */
+#define	STAT_DATA1			0x20F0	/* 32 bit	Statistic Data Register 1 */
+#define	STAT_DATA2			0x20F4	/* 32 bit	Statistic Data Register 2 */
+#define	CFG_OVER_LEN1		0x20F8	/* 32 bit	Over-Length Configuration
+									 *			Register 1
+									 */
+#define	CNT_TX_ERR			0x2100	/* 32 bit	MACsec TX Processing Error Count */
+#define	CFG_IPAR_HYST		0x2104	/* 32 bit	Ingress Parse FIFO Hystersis */
+#define	CFG_EPAR_HYST		0x2108	/* 32 bit	Egress Parse FIFO Hystersis */
+#define	RE_TRF_TCTL			0x2200	/* 32 bit	MACsec Retransmit FIFO Control */
+#define	RE_TRF_PCNT			0x2204	/* 32 bit	Retransmit FIFO Packet Counter */
+#define	RE_TRF_TTH			0x2208	/* 32 bit	Retransmit FIFO Transmit Start
+									 *			Threshold
+									 */
+#define	RE_TRF_WPTR			0x2210	/* 32 bit	Retransmit FIFO Write Pointer
+									 *			Register
+									 */
+#define	RE_TRF_WLEV			0x2218	/* 32 bit	Retransmit FIFO Write Level
+									 *			Register
+									 */
+#define	RE_TRF_RPTR			0x2220	/* 32 bit	Retransmit FIFO Read Pointer
+									 *			Register
+									 */
+#define	RE_TRF_RES_PTR		0x2224	/* 32 bit	Transmit FIFO Restart Pointer
+									 *			Register
+									 */
+#define	RE_TRF_RLEV			0x2228	/* 32 bit	Retransmit FIFO Read Level
+									 *			Register
+									 */
+#define	RE_TRF_RSPTR		0x222C	/* 32 bit	Retransmit FIFO Read Shadow
+									 *			Level Register
+									 */
+#define	USB_CTRL1			0x2280	/* 32 bit	USB Control Register 1 */
+#define	USB_CTRL2			0x2284	/* 32 bit	USB Control Register 2 */
+#define	USB_STAT1			0x2288	/* 32 bit	USB Statistics Register */
+#define	USB_IP_REV			0x22C0	/* 32 bit	USB PHY Revision Register */
+#define	USB_PHY_CTRL		0x22C4	/* 32 bit	USB Control Register */
+#define	USB_PHY_PLL			0x22C8	/* 32 bit	PLL Register */
+#define	USB_PHY_TX			0x22CC	/* 32 bit	Tx Register */
+#define	USB_PHY_RX			0x22D0	/* 32 bit	Rx Register */
+#define	USB_PHY_IVREF		0x22D4	/* 32 bit	IVREF Register */
+#define	USB_PHY_TEST_GRP_0	0x22D8	/* 32 bit	Test Group 0 Register */
+#define	USB_PHY_TEST_GRP_1	0x22DC	/* 32 bit	Test Group 1 Register */
+#define	USB_PHY_TEST_GRP_2	0x22E0	/* 32 bit	Test Group 2 Register */
+#define	USB_PHY_ID_GRP		0x22E4	/* 26 bit	ID Group Register */
+#define	USB_INT1			0x22E8	/* 32 bit	USB Internal Register 1 */
+#define	USB_INT2			0x22EC	/* 32 bit	USB Internal Register 2 */
+#define	USB_ID				0x2300	/* 32 bit	Identification Register */
+#define	USB_HWGENERAL		0x2304	/* 32 bit	General Hardware Parameters
+									 *			Register
+									 */
+#define	USB_HWHOST			0x2308	/* 32 bit	Host Hardware Parameters
+									 *			Register
+									 */
+#define	USB_HWDEVICE		0x230C	/* 32 bit	Device Hardware Parameters
+									 *			Register
+									 */
+#define	USB_HWTXBUF			0x2310	/* 32 bit	TX Buffer Hardware Parameters
+									 *			Register
+									 */
+#define	USB_HWRXBUF			0x2314	/* 32 bit	RX Buffer Hardware Parameters
+									 *			Register
+									 */
+#define	USB_CAPLENGTH		0x2400	/* 16 bit	Capability Register Length -
+									 *			EHCI Compliant Register
+									 */
+#define	USB_DCIVERSION		0x2420	/* 32 bit	Dev. Interface Version Number
+									 *			Register
+									 */
+#define	USB_DCCPARAMS		0x2424	/* 32 bit	Device Ctrl. Capability
+									 *			Parameters Register
+									 */
+#define	USB_CMD				0x2440	/* 32 bit	USB Command Register */
+#define	USB_STS				0x2444	/* 32 bit	USB Status Register */
+#define	USB_INTR			0x2448	/* 32 bit	USB Interrupt Enable Register */
+#define	USB_FRINDEX			0x244C	/* 32 bit	USB Frame Index Register */
+#define	USB_DEVICEADDR		0x2454	/* 32 bit	Device Controller USB Device
+									 *			Address Register (Device Mode)
+									 */
+#define	USB_EP_LISTADDR		0x2458	/* 32 bit	Address at Endpoint List in
+									 *			Memory Register
+									 */
+#define	USB_BURSTSIZE		0x2460	/* 32 bit	Programmable Burst Size
+									 *			Register - Host Controller
+									 */
+#define	USB_ENDPTNAK		0x2478	/* 32 bit	Endpoint NAK Register */
+#define	USB_PORTSC			0x2484	/* 32 bit	Port Status/Control Register */
+#define	USB_MODE			0x24A8	/* 32 bit	USB Device Mode Register */
+#define	USB_ENDPTSETUPSTAT	0x24AC	/* 32 bit	Endpoint Setup Status Register */
+#define	USB_ENDPTPRIME		0x24B0	/* 32 bit	Endpoint Initialization Register */
+#define	USB_ENDPTFLUSH		0x24B4	/* 32 bit	Endpoint De-Initialize Register */
+#define	USB_ENDPTSTAT		0x24B8	/* 32 bit	Endpoint STAT Register */
+#define	USB_EP_COMPL		0x24BC	/* 32 bit	Endpoint Complete Register */
+#define	USB_ENDPTCTRL0		0x24C0	/* 32 bit	Endpoint Control 0 Register */
+#define	USB_EPCTRL1_5_RLO	0x24C4 	/* Endpoint Control 1 to Endpoint Control 5
+									 *			Registers Start
+									 */
+#define	USB_EPCTRL1_5_RHI	0x24D4	/* Endpoint Control 1 to Endpoint Control 5
+									 *			Registers End
+									 */
+#define	SIU_RBR				0x2500	/* 32 bit	Receive Buffer Register */
+#define	SIU_THR				0x2500	/* 32 bit	Transmit Holding Register */
+#define	SIU_DLL				0x2500	/* 32 bit	Divisor Latch Low Register */
+#define	SIU_DLH				0x2504	/* 32 bit	Divisor Latch High Register */
+#define	SIU_IER				0x2504	/* 32 bit	Interrupt Enable Register */
+#define	SIU_IIR				0x2508	/* 32 bit	Interrupt Identity Register */
+#define	SIU_FCR				0x2508	/* 32 bit	FIFO Control Register */
+#define	SIU_LCR				0x250C	/* 32 bit	Line Control Register */
+#define	SIU_MCR				0x2510	/* 32 bit	Modem Control Register */
+#define	SIU_LSR				0x2514	/* 32 bit	Line Status Register */
+#define	SIU_MSR				0x2518	/* 32 bit	Modem Status Register */
+#define	SIU_SCR				0x251C	/* 32 bit	Scratchpad Register */
+#define	SIU_SRBR_RLO		0x2530 	/* Shadow Receive Buffer Register Start */
+#define	SIU_SRBR_RHI		0x256C	/* Shadow Receive Buffer Register End */
+#define	SIU_STHR_RLO		0x2530 	/* Shadow Transmit Holding Register Start */
+#define	SIU_STHR_RHI		0x256C	/* Shadow Transmit Holding Register End */
+#define	SIU_FAR				0x2570	/* 32 bit	FIFO Access Register */
+#define	SIU_TFR				0x2574	/* 32 bit	Transmit FIFO Read */
+#define	SIU_RFW				0x2578	/* 32 bit	Receive FIFO Write */
+#define	SIU_USR				0x257C	/* 32 bit	UART Status Register */
+#define	SIU_TFL				0x2580	/* 32 bit	Transmit FIFO Level */
+#define	SIU_RFL				0x2584	/* 32 bit	Receive FIFO Level */
+#define	SIU_SRR				0x2588	/* 32 bit	Software Reset Register */
+#define	SIU_SRTS			0x258C	/* 32 bit	Shadow Request to Send */
+#define	SIU_SBCR			0x2590	/* 32 bit	Shadow Break Control Register */
+#define	SIU_SDMAM			0x2594	/* 32 bit	Shadow DMA Mode */
+#define	SIU_SFE				0x2598	/* 32 bit	Shadow FIFO Enable */
+#define	SIU_SRT				0x259C	/* 32 bit	Shadow RCVR Trigger */
+#define	SIU_STET			0x25A0	/* 32 bit	Shadow TX Empty Trigger */
+#define	SIU_HTX				0x25A4	/* 32 bit	Halt TX */
+#define	SIU_DMASA			0x25A8	/* 32 bit	DMA Software Acknowledge */
+#define	SIU_CPR				0x25F4	/* 32 bit	Component Parameter Register */
+#define	SIU_UCV				0x25F8	/* 32 bit	UART Component Version */
+#define	SIU_CTR				0x25FC	/* 32 bit	Component Type Register */
+
+#define	PTP_CTRL_REG		0x2500	/* 32 bit	PTP Control Register */
+#define	PTP_DEBUG_REG		0x2504	/* 32 bit	PTP Debug Register */
+#define	PTP_AVB_COMMAND		0x2510	/* 32 bit	PTP AVB Command */
+#define	PTP_AVB_DATA		0x2514	/* 32 bit	PTP AVB Data */
+
+/*
+ *
+ *	THE BIT DEFINES
+ *
+ */
+/*	GLB_RAP				0x0000	Register Address Port (RAP) Register */
+/*		Bit(s) GLB_RAP_RSRV_31_7 reserved */
+#define	GLB_RAP_MSK					SHIFT0(0x7f)		/* RAP */
+#define	GLB_RAP_BASE				0
+
+/*	GLB_CSR				0x0004	Control/Status Register */
+/*		Bit(s) GLB_CSR_RSRV_23_18 reserved */
+#define	GLB_CSR_VMAIN_AVL			BIT_17			/* Vmain Available */
+#define	GLB_CSR_VAUX_AVL			BIT_16			/* Vaux Available */
+#define	GLB_CSR_RUN_PIG_ENA			BIT_15S			/* Run PiG Enable */
+#define	GLB_CSR_RUN_PIG_DIS			BIT_14S			/* Run PiG Disable */
+#define	GLB_CSR_ASF_ENA_SET			BIT_13S			/* ASF Enable Set */
+#define	GLB_CSR_ASF_ENA_CLR			BIT_12S			/* ASF Enable Clear */
+/*		Bit(s) GLB_CSR_RSRV_11 reserved */
+/*		Bit(s) GLB_CSR_RSRV_10 reserved */
+#define	GLB_CSR_LED0_ON				BIT_9S			/* LED<0>On */
+#define	GLB_CSR_LED0_OFF			BIT_8S			/* LED<0>Off */
+#define	GLB_CSR_IRQ_SW_SET			BIT_7S			/* Set IRQ Software */
+#define	GLB_CSR_IRQ_SW_CLR			BIT_6S			/* Clear IRQ Software */
+#define	GLB_CSR_STOP_MST_DONE		BIT_5S			/* Stop Master Done */
+#define	GLB_CSR_STOP_MST			BIT_4S			/* Stop Master */
+#define	GLB_CSR_MST_RST_CLR			BIT_3S			/* Master Reset Clear */
+#define	GLB_CSR_MST_RST_SET			BIT_2S			/* Master Reset Set */
+#define	GLB_CSR_SW_RST_CLR			BIT_1S			/* Software Reset Clear */
+#define	GLB_CSR_SW_RST_SET			BIT_0S			/* Software Reset Set */
+
+/*	GLB_PCTRL			0x0007	Power Control Register */
+#define	GLB_PCTRL_SW_VAUX_ENA		BIT_7S	/* Switch Vaux Enable */
+#define	GLB_PCTRL_SW_VAUX_DIS		BIT_6S	/* Switch Vaux Disable */
+#define	GLB_PCTRL_SW_VCC_ENA		BIT_5S	/* Switch VCC Enable */
+#define	GLB_PCTRL_SW_VCC_DIS		BIT_4S	/* Switch VCC Disable */
+#define	GLB_PCTRL_SW_VAUX_ON		BIT_3S	/* Switch Vaux On */
+#define	GLB_PCTRL_SW_VAUX_OFF		BIT_2S	/* Switch Vaux Off */
+#define	GLB_PCTRL_SW_VCC_ON			BIT_1S	/* Switch VCC On */
+#define	GLB_PCTRL_SW_VCC_OFF		BIT_0S	/* Switch VCC Off */
+
+/*	GLB_ISRC			0x0008	Interrupt Source Register */
+#define	GLB_ISRC_HW_IRQ					BIT_31			/* Hardware Interrupt */
+#define	GLB_ISRC_STAT_BMU				BIT_30			/* Status BMU */
+#define	GLB_ISRC_CPU_HOST				BIT_29			/* CPU to Host */
+#define	GLB_ISRC_CPU_TO					BIT_28			/* CPU Timeout */
+#define	GLB_ISRC_POLL_CHK				BIT_27			/* IRQ Polling CHK */
+#define	GLB_ISRC_TWSI_RDY				BIT_26			/* IRQ TWSI Ready */
+#define	GLB_ISRC_SW						BIT_25			/* IRQ Software */
+#define	GLB_ISRC_TIM					BIT_24			/* IRQ Timer */
+/*		Bit(s) GLB_ISRC_RSRV_23_13 reserved */
+#define	GLB_ISRC_UART					BIT_12			/* UART IRQ */
+/*		Bit(s) GLB_ISRC_RSRV_11_5 reserved */
+#define	GLB_ISRC_PHY					BIT_4			/* IRQ PHY */
+#define	GLB_ISRC_MAC					BIT_3			/* IRQ MAC */
+#define	GLB_ISRC_CHK_RX					BIT_2			/* IRQ CHCK Rx */
+/*		Bit(s) GLB_ISRC_RSRV_1 reserved */
+#define	GLB_ISRC_CHK_TXA				BIT_0			/* IRQ CHCK TxA */
+
+/*	GLB_IMSK			0x000C	Interrupt Mask Register */
+/* En IRQ Hardware Interrupt */
+#define	GLB_IMSK_HW_IRQ					BIT_31
+#define	GLB_IMSK_STAT_BMU				BIT_30			/* En IRQ Status BMU */
+#define	GLB_IMSK_CPU_HOST				BIT_29			/* En CPU to Host */
+#define	GLB_IMSK_CPU_TO					BIT_28			/* En CPU Timeout */
+#define	GLB_IMSK_POLL_CHK				BIT_27			/* En IRQ Polling CHK */
+#define	GLB_IMSK_TWSI_RDY				BIT_26			/* En IRQ TWSI Ready */
+#define	GLB_IMSK_SW						BIT_25			/* En IRQ Software */
+#define	GLB_IMSK_TIM					BIT_24			/* En IRQ Timer */
+/*		Bit(s) GLB_IMSK_RSRV_23_13 reserved */
+#define	GLB_IMSK_UART					BIT_12			/* Enable UART IRQ */
+/*		Bit(s) GLB_IMSK_RSRV_11_5 reserved */
+#define	GLB_IMSK_PHY					BIT_4			/* En IRQ PHY */
+#define	GLB_IMSK_MAC					BIT_3			/* En IRQ MAC */
+#define	GLB_IMSK_CHK_RX					BIT_2			/* En IRQ CHCK Rx */
+/*		Bit(s) GLB_IMSK_RSRV_1 reserved */
+#define	GLB_IMSK_CHK_TXA				BIT_0			/* En IRQ CHCK TxA */
+
+/*	GLB_ISRC_HW			0x0010	Interrupt Hardware Error Source Register */
+/*		Bit(s) GLB_ISRC_HW_RSRV_31_30 reserved */
+/* IRQ Timestamp Timer Overflow */
+#define	GLB_ISRC_HW_TSP_TIM				BIT_29
+#define	GLB_ISRC_HW_SEN					BIT_28			/* IRQ Sensor */
+#define	GLB_ISRC_HW_MST_ERR				BIT_27			/* IRQ Master Error */
+#define	GLB_ISRC_HW_PCI_STAT			BIT_26			/* IRQ Status */
+#define	GLB_ISRC_HW_PCIE_SPE			BIT_25			/* IRQ PE */
+#define	GLB_ISRC_HW_PCIE_NO_PE			BIT_24			/* IRQ NO PE */
+/*		Bit(s) GLB_ISRC_HW_RSRV_23_11 reserved */
+#define	GLB_ISRC_HW_FCU_ERR				BIT_10			/* IRQ FCU */
+/*		Bit(s) GLB_ISRC_HW_RSRV_9_8 reserved */
+#define	GLB_ISRC_HW_PAR_MAC				BIT_3			/* IRQ Par MAC */
+#define	GLB_ISRC_HW_PAR_RX				BIT_2			/* IRQ PAR Rx */
+/*		Bit(s) GLB_ISRC_HW_RSRV_1 reserved */
+#define	GLB_ISRC_HW_TCP_TXA				BIT_0			/* IRQ TCP Length TxA1 */
+
+/*	GLB_IMSK_HW			0x0014	Interrupt Hardware Error Mask Register */
+/*		Bit(s) GLB_IMSK_HW_RSRV_31_30 reserved */
+/* En IRQ Timestamp Timer Overflow */
+#define	GLB_IMSK_HW_TSP_TIM				BIT_29
+#define	GLB_IMSK_HW_SEN					BIT_28			/* En IRQ Sensor */
+#define	GLB_IMSK_HW_MST_ERR				BIT_27			/* En IRQ Master Error */
+#define	GLB_IMSK_HW_PCI_STAT			BIT_26			/* En IRQ Status */
+#define	GLB_IMSK_HW_PCIE_SPE			BIT_25			/* En IRQ PE */
+#define	GLB_IMSK_HW_PCIE_NO_PE			BIT_24			/* En IRQ NO PE */
+/*		Bit(s) GLB_IMSK_HW_RSRV_23_8 reserved */
+/*		Bit(s) GLB_IMSK_HW_RSRV_7_4 reserved */
+#define	GLB_IMSK_HW_PAR_MAC				BIT_3			/* En IRQ Par MAC */
+#define	GLB_IMSK_HW_PAR_RX				BIT_2			/* En IRQ PAR Rx */
+/*		Bit(s) GLB_IMSK_HW_RSRV_1 reserved */
+#define	GLB_IMSK_HW_TCP_TXA				BIT_0			/* En IRQ TCP Length TxA1 */
+
+/*	GLB_ISRC_SP1		0x0018	Special Interrupt Source Register 1 */
+#define	GLB_ISRC_SP1_IRQ_XXX_MSK		SHIFT0(0xffffffff)	/* IRQ xxx */
+#define	GLB_ISRC_SP1_IRQ_XXX_BASE		0
+
+/*	GLB_ISRC_SP2		0x001C	Special Interrupt Source Register 2 */
+#define	GLB_ISRC_SP2_IRQ_XXX_MSK		SHIFT0(0xffffffff)	/* IRQ xxx */
+#define	GLB_ISRC_SP2_IRQ_XXX_BASE		0
+
+/*	GLB_ISRC_SP3		0x0020	Special Interrupt Source Register 3 */
+#define	GLB_ISRC_SP3_IRQ_XXX_MSK		SHIFT0(0xffffffff)	/* IRQ xxx */
+#define	GLB_ISRC_SP3_IRQ_XXX_BASE		0
+
+/*	GLB_EISR			0x0024	Enter Interrupt Service Routine Register */
+#define	GLB_EISR_IRQ_XXX_MSK		SHIFT0(0xffffffff)	/* Enter ISR Reg */
+#define	GLB_EISR_IRQ_XXX_BASE		0
+
+/*	GLB_LISR			0x0028	Leave Interrupt Service Routine Register */
+#define	GLB_LISR_IRQ_XXX_MSK		SHIFT0(0xffffffff)	/* Leave ISR Reg */
+#define	GLB_LISR_IRQ_XXX_BASE		0
+
+/*	GLB_ICTRL			0x002C	Interrupt Control Register */
+/*		Bit(s) GLB_ICTRL_RSRV_31_4 reserved */
+#define	GLB_ICTRL_ISR_MSK				BIT_3				/* ISR Mask Flag Value */
+/* isr_status Flag Value */
+#define	GLB_ICTRL_ISR_STAT				BIT_2
+#define	GLB_ICTRL_LEAVE_ISR				BIT_1				/* Leave ISR */
+#define	GLB_ICTRL_ENTER_ISR				BIT_0				/* Enter ISR */
+
+/*	SPI_CTRL			0x0060	SPI Flash Memory Control Register */
+#define	SPI_CTRL_STRT_LDR				BIT_31			/* Loader Start */
+#define	SPI_CTRL_BSY					BIT_30			/* SPI Busy */
+#define	SPI_CTRL_RESV					BIT_29			/* RESV */
+#define	SPI_CTRL_RD_ID_PROT				BIT_28			/* RD ID Protocol */
+#define	SPI_CTRL_SPI_CLK_RATE_MSK		SHIFT26(0x3UL)	/* SPI CLK rate selection */
+#define	SPI_CTRL_SPI_CLK_RATE_BASE		26
+/*		Bit(s) SPI_CTRL_RSRV_25_20 reserved */
+#define	SPI_CTRL_STRT_SPI				BIT_19			/* Start SPI */
+#define	SPI_CTRL_INST_MSK				SHIFT16(0x7UL)	/* Instruction */
+#define	SPI_CTRL_INST_BASE				16
+/*		Bit(s) SPI_CTRL_RSRV_15_8 reserved */
+#define	SPI_CTRL_STAT_MSK				SHIFT0(0xff)	/* SPI Device Status */
+#define	SPI_CTRL_STAT_BASE				0
+
+/*	SPI_ADDR			0x0064	SPI Flash Memory Address Register */
+/*		Bit(s) SPI_ADDR_RSRV_31_20 reserved */
+#define	SPI_ADDR_MSK					SHIFT0(0xfffff)	/* SPI Flash Memory Address */
+#define	SPI_ADDR_BASE					0
+
+/*	SPI_DATA			0x0068	SPI Flash Memory Data Register */
+#define	SPI_DATA_MSK		SHIFT0(0xffffffff)	/* SPI Flash Memory Data */
+#define	SPI_DATA_BASE		0
+
+/*	SPI_ID				0x006C	SPI Flash Memory Vendor/Device ID Register */
+/*		Bit(s) SPI_ID_RSRV_31_16 reserved */
+#define	SPI_ID_VEN_ID_MSK			SHIFT8(0xff)	/* Vendor-ID */
+#define	SPI_ID_VEN_ID_BASE			8
+#define	SPI_ID_DEV_ID_MSK			SHIFT0(0xff)	/* Device-ID */
+#define	SPI_ID_DEV_ID_BASE			0
+
+/*	SPI_LCFG			0x0070	SPI Flash Memory Loader Configuration Register */
+/*		Bit(s) SPI_LCFG_RSRV_31_28 reserved */
+/* Normal Loader start address */
+#define	SPI_LCFG_NRML_ADDR_MSK			SHIFT16(0xfffUL)
+#define	SPI_LCFG_NRML_ADDR_BASE			16
+/*		Bit(s) SPI_LCFG_RSRV_15_12 reserved */
+#define	SPI_LCFG_INIT_ADDR_MSK			SHIFT0(0xfff)	/* PIG Loader start address */
+#define	SPI_LCFG_INIT_ADDR_BASE			0
+
+/*	SPI_CFG				0x0074	SPI Flash Memory Configuration Register */
+/*		Bit(s) SPI_VCFG_RSRV_31_28 reserved */
+#define	SPI_VCFG_VPD_END_MSK			SHIFT16(0xfffUL)	/* VPD end address */
+#define	SPI_VCFG_VPD_END_BASE			16
+/*		Bit(s) SPI_VCFG_RSRV_15_12 reserved */
+
+/* Yukon-Supreme */
+#define	SPI_VCFG_VPD_START_MSK			SHIFT0(0xfff)	/* VPD start address */
+#define	SPI_VCFG_VPD_START_BASE			0
+/* !Yukon-Supreme */
+#define	SPI_CFG_A17_GATE			BIT_0				/* A17 Gate */
+
+/*	SPI_OPC1			0x0078	SPI Flash Memory Opcode 1 Register */
+#define	SPI_OPC1_RDSR_MSK		SHIFT24(0xffUL)	/* Opcode Read Status */
+#define	SPI_OPC1_RDSR_BASE		24
+#define	SPI_OPC1_RDID_MSK		SHIFT16(0xffUL)	/* Opcode Read ID */
+#define	SPI_OPC1_RDID_BASE		16
+#define	SPI_OPC1_RD_MSK			SHIFT8(0xff)	/* Opcode Read */
+#define	SPI_OPC1_RD_BASE		8
+#define	SPI_OPC1_NOP_MSK		SHIFT0(0xff)	/* Opcode for No Operation */
+#define	SPI_OPC1_NOP_BASE		0
+
+/*	SPI_OPC2			0x007C	SPI Flash Memory Opcode 2 Register */
+#define	SPI_OPC2_CE_MSK			SHIFT24(0xffUL)	/* Opcode Chip Erase */
+#define	SPI_OPC2_CE_BASE		24
+#define	SPI_OPC2_SE_MSK			SHIFT16(0xffUL)	/* Opcode Sector Erase */
+#define	SPI_OPC2_SE_BASE		16
+#define	SPI_OPC2_WR_MSK			SHIFT8(0xff)	/* Opcode Write */
+#define	SPI_OPC2_WR_BASE		8
+#define	SPI_OPC2_WREN_MSK		SHIFT0(0xff)	/* Opcode Write Enable */
+#define	SPI_OPC2_WREN_BASE		0
+
+/*	GLB_BWIN			0x0080	Block Window Register */
+#define	GLB_BWIN_MSK		SHIFT0(0xffffffff)	/* Mapped register XY */
+#define	GLB_BWIN_BASE		0
+
+/*	L1_CFG_MADDR_Hi		0x0100	Link1 MAC Address Register High */
+#define	CFG_MADDR_HI_VAL_3_MSK		SHIFT24(0xffUL)	/* Mac-Address_x, Byte 3 */
+#define	CFG_MADDR_HI_VAL_3_BASE		24
+#define	CFG_MADDR_HI_VAL_2_MSK		SHIFT16(0xffUL)	/* Mac-Address_x, Byte 2 */
+#define	CFG_MADDR_HI_VAL_2_BASE		16
+#define	CFG_MADDR_HI_VAL_1_MSK		SHIFT8(0xff)	/* Mac-Address_x, Byte 1 */
+#define	CFG_MADDR_HI_VAL_1_BASE		8
+#define	CFG_MADDR_HI_VAL_0_MSK		SHIFT0(0xff)	/* Mac-Address_x, Byte 0 */
+#define	CFG_MADDR_HI_VAL_0_BASE		0
+
+/*	L1_CFG_MADDR_LO		0x0104	Link1 MAC Address Register Low */
+/*		Bit(s) CFG_MADDR_LO_RSRV_31_16 reserved */
+#define	CFG_MADDR_LO_VAL_5_MSK				SHIFT8(0xff)	/* MAC Addr_x, Byte 5 */
+#define	CFG_MADDR_LO_VAL_5_BASE				8
+#define	CFG_MADDR_LO_VAL_4_MSK				SHIFT0(0xff)	/* MAC Addr_x, Byte 4 */
+#define	CFG_MADDR_LO_VAL_4_BASE				0
+
+/*	CFG_IF				0x0118	Interface Type Register (PMD Type and
+ *								Connector Type)
+ */
+#define	CFG_IF_PMD_MSK			SHIFT8(0xffU)	/* PMD Type */
+#define	CFG_IF_PMD_BASE			8
+#define	CFG_IF_CONN_MSK			SHIFT0(0xffU)	/* Connector Type */
+#define	CFG_IF_CONN_BASE		0
+
+/*	CFG_CREV			0x011A	Chip Revision Register */
+#define	CFG_CREV_MSK				SHIFT4(0xfU)	/* Chip Revision */
+#define	CFG_CREV_BASE				4
+#define	CFG_CREV_HID_ID_MSK			SHIFT0(0xfU)	/* Hidden ID */
+#define	CFG_CREV_HID_ID_BASE		0
+
+/*	CFG_CID				0x011B	Chip ID Register */
+#define	CFG_CID_MSK			SHIFT0(0xffU)	/* Chip ID */
+#define	CFG_CID_BASE		0
+
+/*	CFG_CGATE			0x011C	Clock Gating Register */
+/*		Bit(s) CFG_CGATE_RSRV_15 reserved */
+/*		Bit(s) CFG_CGATE_RSRV_14_12 reserved */
+/*		Bit(s) CFG_CGATE_RSRV_11 reserved */
+#define	CFG_CGATE_DIS_MAC				BIT_10S			/* Disable PHY/MAC Link */
+#define	CFG_CGATE_CIS_CORE				BIT_9S			/* Disable core_clk Link */
+#define	CFG_CGATE_DIS_PCI				BIT_8S			/* Disable pci_clk Link */
+/*		Bit(s) CFG_CGATE_RSRV_7_0 reserved */
+
+/*	CFG_AIR2			0x011E	Application Information Register 2 */
+/*		Bit(s) CFG_AIR2_RSRV_7_0 reserved */
+
+/*	CFG_AIR1			0x011F	Application Information Register 1 */
+/*		Bit(s) CFG_AIR1_RSRV_7_0 reserved */
+
+/*	CFG_CDIV			0x0120	Clock Divider Register */
+/*		Bit(s) CFG_CDIV_RSRV_31_24 reserved */
+#define	CFG_CDIV_MSK					SHIFT16(0xffUL)	/* Clock Div Value */
+#define	CFG_CDIV_BASE					16
+/*		Bit(s) CFG_CDIV_RSRV_15_2 reserved */
+#define	CFG_CDIV_ENA					BIT_1			/* Clock Div Enable */
+#define	CFG_CDIV_DIS					BIT_0			/* Clock Div Disable */
+
+/*	IRQ_TIM_INIT		0x0130	Timer Init Value Register */
+#define	IRQ_TIM_INIT_MSK		SHIFT0(0xffffffff)	/* Timer Init Value */
+#define	IRQ_TIM_INIT_BASE		0
+
+/*	IRQ_TIM_CNT			0x0134	Timer Register */
+#define	IRQ_TIM_CNT_MSK			SHIFT0(0xffffffff)	/* Timer */
+#define	IRQ_TIM_CNT_BASE		0
+
+/*	IRQ_TIM_TCTRL		0x0138	Timer Control/Test Register */
+/*		Bit(s) IRQ_TIM_TCTRL_RSRV_31_16 reserved */
+/*		Bit(s) IRQ_TIM_TCTRL_RSRV_15_11 reserved */
+#define	IRQ_TIM_TCTRL_ON					BIT_10			/* Timer Test On */
+#define	IRQ_TIM_TCTRL_OFF					BIT_9			/* Timer Test Off */
+#define	IRQ_TIM_TCTRL_STEP					BIT_8			/* Timer Step */
+/*		Bit(s) IRQ_TIM_TCTRL_RSRV_7_3 reserved */
+#define	IRQ_TIM_TCTRL_STRT					BIT_2			/* Timer Start */
+#define	IRQ_TIM_TCTRL_STOP					BIT_1			/* Timer Stop */
+#define	IRQ_TIM_TCTRL_CLR_IRQ				BIT_0			/* Timer Clear IRQ */
+
+/*	MOD_TIM_INIT		0x0140	IRQ Moderation Timer Init Value Register */
+/* IRQ Moderation Timer Init Value */
+#define	MOD_TIM_INIT_MSK		SHIFT0(0xffffffff)
+#define	MOD_TIM_INIT_BASE		0
+
+/*	MOD_TIM_CNT			0x0144	IRQ Moderation Timer Register */
+#define	MOD_TIM_CNT_MSK			SHIFT0(0xffffffff)	/* IRQ Moderation Timer */
+#define	MOD_TIM_CNT_BASE		0
+
+/*	MOD_TIM_TCTRL		0x0148	IRQ Moderation Timer Control/Test Register */
+/*		Bit(s) MOD_TIM_TCTRL_RSRV_31_16 reserved */
+/*		Bit(s) MOD_TIM_TCTRL_RSRV_15_11 reserved */
+#define	MOD_TIM_TCTRL_ON					BIT_10			/* IM Timer Test On */
+#define	MOD_TIM_TCTRL_OFF					BIT_9			/* IM Timer Test Off */
+#define	MOD_TIM_TCTRL_STEP					BIT_8			/* IM Timer Step */
+/*		Bit(s) MOD_TIM_TCTRL_RSRV_7_3 reserved */
+#define	MOD_TIM_TCTRL_STRT					BIT_2			/* IM Timer Start */
+#define	MOD_TIM_TCTRL_STOP					BIT_1			/* IM Timer Stop */
+/*		Bit(s) MOD_TIM_TCTRL_RSRV_0 reserved */
+
+/*	MOD_TIM_MSK			0x014C	Interrupt Moderation Mask Register */
+/* En Moderation IRQ xxx */
+#define	MOD_TIM_MSK_EN_MOD_IRQ_XXX_MSK			SHIFT0(0xffffffff)
+#define	MOD_TIM_BASE_EN_MOD_IRQ_XXX_BASE		0
+
+/*	MOD_TIM_MSK_HW		0x0150	Interrupt Hardware Error Moderation Mask
+ *								Register
+ */
+/* En Moderation IRQ xxx */
+#define	MOD_TIM_MSK_HW_EN_MOD_IRQ_XXX_MSK		SHIFT0(0xffffffff)
+#define	MOD_TIM_BASE_HW_EN_MOD_IRQ_XXX_BASE		0
+
+/*	GLB_TCTRL			0x0158	Test Control Register 1 */
+#define	GLB_TCTRL_BMU_TX_FIFO_RTC			BIT_31	/* BMU TX FIFO RTC */
+#define	GLB_TCTRL_BMU_TX_FIFO_WTC			BIT_30	/* BMU TX FIFO WTC */
+#define	GLB_TCTRL_ASF_FIFO_RTC				BIT_29	/* ASF FIFO RTC */
+#define	GLB_TCTRL_ASF_FIFO_WTC				BIT_28	/* ASF FIFO WTC */
+/* Yukon Fe+ */
+#define	GLB_TCTRL_PWR_BDGT_FIFO_RTC			BIT_29	/* PWR_BDGT FIFO RTC */
+#define	GLB_TCTRL_PWR_BDGT_FIFO_WTC			BIT_28	/* PWR_BDGT FIFO WTC */
+/* Yukon Fe+ end */
+#define	GLB_TCTRL_PCIE_MAC_TX_FIFO_RTC		BIT_27	/* PCIE MAC Tx FIFO RTC */
+#define	GLB_TCTRL_PCIE_MAC_TX_FIFO_WTC		BIT_26	/* PCIE MAC Tx FIFO WTC */
+#define	GLB_TCTRL_PCIE_MAC_RX_FIFO_RTC		BIT_25	/* PCIE MAC Rx FIFO RTC */
+#define	GLB_TCTRL_PCIE_MAC_RX_FIFO_WTC		BIT_24	/* PCIE MAC Rx FIFO WTC */
+#define	GLB_TCTRL_PEX_TL_RX_FIFO_RTC		BIT_23	/* Pex Tl Rx FIFO RTC */
+#define	GLB_TCTRL_PEX_TL_RX_FIFO_WTC		BIT_22	/* Pex Tl Rx FIFO WTC */
+#define	GLB_TCTRL_PEX_TL_TX_FIFO_RTC		BIT_21	/* Pex Tl Tx FIFO RTC */
+#define	GLB_TCTRL_PEX_TL_TX_FIFO_WTC		BIT_20	/* Pex Tl Tx FIFO WTC */
+#define	GLB_TCTRL_WOL_RAM_RTC				BIT_19	/* WOL RAM RTC */
+#define	GLB_TCTRL_WOL_RAM_WTC				BIT_18	/* WOL RAM WTC */
+#define	GLB_TCTRL_RMON_RAM_RTC				BIT_17	/* RMON RAM RTC */
+#define	GLB_TCTRL_RMON_RAM_WTC				BIT_16	/* RMON RAM WTC */
+#define	GLB_TCTRL_PFU_STAT_RTC				BIT_15	/* PFU Status RTC */
+#define	GLB_TCTRL_PFU_STAT_WTC				BIT_14	/* PFU Status WTC */
+#define	GLB_TCTRL_PFU_AQ_FIFO_RTC			BIT_13	/* PFU Aq FIFO RTC */
+#define	GLB_TCTRL_PFU_AQ_FIFO_WTC			BIT_12	/* PFU Aq FIFO WTC */
+#define	GLB_TCTRL_PFU_RQ_FIFO_RTC			BIT_11	/* PFU Rq FIFO RTC */
+#define	GLB_TCTRL_PFU_RQ_FIFO_WTC			BIT_10	/* PFU Rq FIFO WTC */
+#define	GLB_TCTRL_MAC_RX_FIFO_RTC			BIT_9	/* MAC Rx FIFO RTC */
+/*		Bit(s) GLB_TCTRL_RSRV_8 reserved */
+/*		Bit(s) GLB_TCTRL_RSRV_7 reserved */
+#define	GLB_TCTRL_MAC_RX_FIFO_WTC			BIT_6	/* MAC Rx FIFO WTC */
+/*		Bit(s) GLB_TCTRL_RSRV_5 reserved */
+#define	GLB_TCTRL_MAC_TX_FIFO_RTC			BIT_4	/* MAC Tx FIFO RTC */
+/*		Bit(s) GLB_TCTRL_RSRV_3 reserved */
+#define	GLB_TCTRL_MAC_TX_FIFO_WTC			BIT_2	/* MAC Tx FIFO WTC */
+#define	GLB_TCTRL_EN_CFG_WR_ON				BIT_1	/* En Config Write On */
+#define	GLB_TCTRL_EN_CFG_WR_OFF				BIT_0	/* En Config Write Off */
+
+/*	GLB_GPIO			0x015C	General Purpose I/O Register */
+#define	GLB_GPIO_CLK_DEB_ENA			BIT_31			/* Clock Debug Enable */
+/*		Bit(s) GLB_GPIO_RSRV_30 reserved */
+#define	GLB_GPIO_CLK_DBG_MSK			SHIFT26(0xfUL)	/* Clock Debug */
+#define	GLB_GPIO_CLK_DBG_BASE			26
+/*		Bit(s) GLB_GPIO_RSRV_25_16 reserved */
+/* Disable Internal Reset after D3 to D0 */
+#define	GLB_GPIO_INT_RST_D3_DIS			BIT_15
+#define	GLB_GPIO_LED_PAD_SPEED_UP		BIT_14			/* LED PAD Speed Up */
+#define	GLB_GPIO_STAT_RACE_DIS			BIT_13			/* Status Race Disable */
+#define	GLB_GPIO_TEST_SEL_MSK			SHIFT11(0x3)	/* Testmode Select */
+#define	GLB_GPIO_TEST_SEL_BASE			11
+#define	GLB_GPIO_RAND_ENA				BIT_10			/* Random Enable */
+#define	GLB_GPIO_RAND_BIT_1				BIT_9			/* Random Bit 1 */
+/*		Bit(s) GLB_GPIO_RSRV_8_0 reserved */
+
+/*	SRAM_TC				0x0160	SRAM Timing Control */
+/*		Bit(s) SRAM_TC_RSRV_31_24 reserved */
+#define	SRAM_TC_BMU_TX_FIFO_RTC_MSK			SHIFT22(0x3UL)	/* BMU TX FIFO RTC */
+#define	SRAM_TC_BMU_TX_FIFO_RTC_BASE		22
+#define	SRAM_TC_BMU_TX_FIFO_WTC_MSK			SHIFT20(0x3UL)	/* BMU TX FIFO WTC */
+#define	SRAM_TC_BMU_TX_FIFO_WTC_BASE		20
+/* Power Budgeting FIFO RAM RTC */
+#define	SRAM_TC_PWR_BDGT_FIFO_RTC_MSK		SHIFT18(0x3UL)
+#define	SRAM_TC_PWR_BDGT_FIFO_RTC_BASE		18
+/* Power Budgeting FIFO RAM WTC */
+#define	SRAM_TC_PWR_BDGT_FIFO_WTC_MSK		SHIFT16(0x3UL)
+#define	SRAM_TC_PWR_BDGT_FIFO_WTC_BASE		16
+/* PCIe MAC Tx FIFO RTC */
+#define	SRAM_TC_PCIE_MAC_TX_FIFO_RTC_MSK	SHIFT14(0x3)
+#define	SRAM_TC_PCIE_MAC_TX_FIFO_RTC_BASE	14
+/* PCIe MAC Tx FIFO WTC */
+#define	SRAM_TC_PCIE_MAC_TX_FIFO_WTC_MSK	SHIFT12(0x3)
+#define	SRAM_TC_PCIE_MAC_TX_FIFO_WTC_BASE	12
+/* PCIe MAC Rx FIFO RTC */
+#define	SRAM_TC_PCIE_MAC_RX_FIFO_RTC_MSK	SHIFT10(0x3)
+#define	SRAM_TC_PCIE_MAC_RX_FIFO_RTC_BASE	10
+/* PCIe MAC Rx FIFO WTC */
+#define	SRAM_TC_PCIE_MAC_RX_FIFO_WTC_MSK	SHIFT8(0x3)
+#define	SRAM_TC_PCIE_MAC_RX_FIFO_WTC_BASE	8
+/* PCIe Tl Rx FIFO RTC */
+#define	SRAM_TC_PCIE_TL_RX_FIFO_RTC_MSK		SHIFT6(0x3)
+#define	SRAM_TC_PCIE_TL_RX_FIFO_RTC_BASE	6
+/* PCIe Tl Rx FIFO WTC */
+#define	SRAM_TC_PCIE_TL_RX_FIFO_WTC_MSK		SHIFT4(0x3)
+#define	SRAM_TC_PCIE_TL_RX_FIFO_WTC_BASE	4
+/* PCIe Tl Tx FIFO RTC */
+#define	SRAM_TC_PCIE_TL_TX_FIFO_RTC_MSK		SHIFT2(0x3)
+#define	SRAM_TC_PCIE_TL_TX_FIFO_RTC_BASE	2
+/* PCIe Tl Tx FIFO WTC */
+#define	SRAM_TC_PCIE_TL_TX_FIFO_WTC_MSK		SHIFT0(0x3)
+#define	SRAM_TC_PCIE_TL_TX_FIFO_WTC_BASE	0
+
+/*	SRAM_PD				0x0168	SRAM Power-Down Control */
+/*		Bit(s) SRAM_PD_RSRV_31_20 reserved */
+#define	SRAM_PD_RMON_RAM_PD				BIT_19		/* RMON RAM PD */
+/* Power Budgeting FIFO RAM PD */
+#define	SRAM_PD_PWR_BDGT_FIFO_PD		BIT_18
+#define	SRAM_PD_PCIE_TL_RX_FIFO_PD		BIT_17		/* PCIe Tl Rx FIFO PD */
+#define	SRAM_PD_PCIE_TL_TX_FIFO_PD		BIT_16		/* PCIe Tl Tx FIFO PD */
+#define	SRAM_PD_PFU_STAT_PD				BIT_15		/* PFU Status PD */
+#define	SRAM_PD_PFU_KQ_FIFO_PD			BIT_14		/* PFU Kq FIFO PD */
+#define	SRAM_PD_PFU_JQ_FIFO_PD			BIT_13		/* PFU Jq FIFO PD */
+#define	SRAM_PD_PFU_HQ_FIFO_PD			BIT_12		/* PFU Hq FIFO PD */
+#define	SRAM_PD_PFU_GQ_FIFO_PD			BIT_11		/* PFU Gq FIFO PD */
+#define	SRAM_PD_PFU_FQ_FIFO_PD			BIT_10		/* PFU Fq FIFO PD */
+#define	SRAM_PD_PFU_DQ_FIFO_PD			BIT_9		/* PFU Dq FIFO PD */
+#define	SRAM_PD_PFU_SQ_FIFO_PD			BIT_8		/* PFU Sq FIFO PD */
+#define	SRAM_PD_PFU_AQ_FIFO_PD			BIT_7		/* PFU Aq FIFO PD */
+#define	SRAM_PD_PFU_RQ_FIFO_PD			BIT_6		/* PFU Rq FIFO PD */
+#define	SRAM_PD_PCIE_MAC_RX_FIFO_PD		BIT_5		/* PCIe MAC Rx FIFO PD */
+#define	SRAM_PD_PCIE_MAC_TX_FIFO_PD		BIT_4		/* PCIe MAC Tx FIFO PD */
+#define	SRAM_PD_WOL_RAM_PD				BIT_3		/* WOL RAM PD */
+#define	SRAM_PD_BMU_TX_FIFO_PD			BIT_2		/* BMU TX FIFO PD */
+#define	SRAM_PD_MAC_TX_FIFO_PD			BIT_1		/* MAC Tx FIFO PD */
+#define	SRAM_PD_MAC_RX_FIFO_PD			BIT_0		/* MAC Rx FIFO PD */
+
+/*	PCIE_PHY			0x0170	PCI Express PHY Address Register */
+#define	PCIE_PHY_RW				BIT_31				/* PEX PHY Access Mode */
+#define	PCIE_PHY_REGFILE		BIT_30				/* PEX PHY Regfile */
+#define	PCIE_PHY_ADDR_MSK		SHIFT16(0x3fffUL)	/* PEX PHY Address */
+#define	PCIE_PHY_ADDR_BASE		16
+#define	PCIE_PHY_DATA_MSK		SHIFT0(0xffff)		/* PEX PHY Data */
+#define	PCIE_PHY_DATA_BASE		0
+
+/*	RAM_ADDR			0x0180	RAM Address Register */
+#define	RAM_ADDR_SEL_MSK				SHIFT30(0x3UL)	/* RAM Select */
+#define	RAM_ADDR_SEL_BASE				30
+#define	RAM_ADDR_ADDR_MUX				BIT_29			/* RAM Address Mux */
+/*		Bit(s) RAM_ADDR_RSRV_28_15 reserved */
+#define	RAM_ADDR_MSK					SHIFT0(0x7fff)	/* RAM Address */
+#define	RAM_ADDR_BASE					0
+
+/*	RAM_DATA_LO			0x0184	Data Port/Lower Dword Register */
+#define	RAM_DATA_LO_MSK			SHIFT0(0xffffffff)	/* Data Port/Lower dword */
+#define	RAM_DATA_LO_BASE		0
+
+/*	RAM_DATA_HI			0x0188	Data Port/Upper Dword Register */
+#define	RAM_DATA_HI_MSK			SHIFT0(0xffffffff)	/* Data Port/Upper dword */
+#define	RAM_DATA_HI_BASE		0
+
+/*	ASF_TO_0_3			0x0190	Timeout Register */
+#define	ASF_TO_0_3_ASF_TO3_MSK		SHIFT24(0xffUL)	/* Timeout Value 3 */
+#define	ASF_TO_0_3_ASF_TO3_BASE		24
+#define	ASF_TO_0_3_ASF_TO2_MSK		SHIFT16(0xffUL)	/* Timeout Value 2 */
+#define	ASF_TO_0_3_ASF_TO2_BASE		16
+#define	ASF_TO_0_3_ASF_TO1_MSK		SHIFT8(0xff)	/* Timeout Value 1 */
+#define	ASF_TO_0_3_ASF_TO1_BASE		8
+#define	ASF_TO_0_3_ASF_TO0_MSK		SHIFT0(0xff)	/* Timeout Value 0 */
+#define	ASF_TO_0_3_ASF_TO0_BASE		0
+
+/*	ASF_TO_4			0x0194	Timeout Register */
+/*		Bit(s) ASF_TO_4_RSRV_31_8 reserved */
+#define	ASF_TO_4_ASF_TO4_MSK		SHIFT0(0xff)		/* Timeout Value 4 */
+#define	ASF_TO_4_ASF_TO4_BASE		0
+
+/*	ASF_SRAMTC			0x0198	Timeout Register */
+/*		Bit(s) ASF_SRAMTC_RSRV_31_16 reserved */
+#define	ASF_SRAMTC_ASF_RTC3_MSK			SHIFT14(0x3)	/* ASF RAM RTC 3 */
+#define	ASF_SRAMTC_ASF_RTC3_BASE		14
+#define	ASF_SRAMTC_ASF_WTC3_MSK			SHIFT12(0x3)	/* ASF RAM WTC 3 */
+#define	ASF_SRAMTC_ASF_WTC3_BASE		12
+#define	ASF_SRAMTC_ASF_RTC2_MSK			SHIFT10(0x3)	/* ASF RAM RTC 2 */
+#define	ASF_SRAMTC_ASF_RTC2_BASE		10
+#define	ASF_SRAMTC_ASF_WTC2_MSK			SHIFT8(0x3)		/* ASF RAM WTC 2 */
+#define	ASF_SRAMTC_ASF_WTC2_BASE		8
+#define	ASF_SRAMTC_ASF_RTC1_MSK			SHIFT6(0x3)		/* ASF RAM RTC 1 */
+#define	ASF_SRAMTC_ASF_RTC1_BASE		6
+#define	ASF_SRAMTC_ASF_WTC1_MSK			SHIFT4(0x3)		/* ASF RAM WTC 1 */
+#define	ASF_SRAMTC_ASF_WTC1_BASE		4
+#define	ASF_SRAMTC_ASF_RTC0_MSK			SHIFT2(0x3)		/* ASF RAM RTC 0 */
+#define	ASF_SRAMTC_ASF_RTC0_BASE		2
+#define	ASF_SRAMTC_ASF_WTC0_MSK			SHIFT0(0x3)		/* ASF RAM WTC 0 */
+#define	ASF_SRAMTC_ASF_WTC0_BASE		0
+
+/*	ASF_CTRL			0x01A0	FIFO Interface Control */
+/*		Bit(s) ASF_CTRL_RSRV_31_2 reserved */
+#define	ASF_CTRL_ASF_ENA			BIT_1				/* Reset Clear */
+#define	ASF_CTRL_ASF_RST			BIT_0				/* Reset Set */
+
+/*	RSS_KEY0			0x0220	RSS Key 0 Register */
+#define	RSS_KEY0_MSK		SHIFT0(0xffffffff)	/* RSS Key 0 */
+#define	RSS_KEY0_BASE		0
+
+/*	RSS_KEY1			0x0224	RSS Key 1 Register */
+#define	RSS_KEY1_MSK		SHIFT0(0xffffffff)	/* RSS Key 1 */
+#define	RSS_KEY1_BASE		0
+
+/*	RSS_KEY2			0x0228	RSS Key 2 Register */
+#define	RSS_KEY2_MSK		SHIFT0(0xffffffff)	/* RSS Key 2 */
+#define	RSS_KEY2_BASE		0
+
+/*	RSS_KEY3			0x022C	RSS Key 3 Register */
+#define	RSS_KEY3_MSK		SHIFT0(0xffffffff)	/* RSS Key 3 */
+#define	RSS_KEY3_BASE		0
+
+/*	RSS_KEY4			0x0230	RSS Key 4 Register */
+#define	RSS_KEY4_MSK		SHIFT0(0xffffffff)	/* RSS Key 4 */
+#define	RSS_KEY4_BASE		0
+
+/*	RSS_KEY5			0x0234	RSS Key 5 Register */
+#define	RSS_KEY5_MSK		SHIFT0(0xffffffff)	/* RSS Key5 */
+#define	RSS_KEY5_BASE		0
+
+/*	RSS_KEY6			0x0238	RSS Key 6 Register */
+#define	RSS_KEY6_MSK		SHIFT0(0xffffffff)	/* RSS Key 6 */
+#define	RSS_KEY6_BASE		0
+
+/*	RSS_KEY7			0x023C	RSS Key 7 Register */
+#define	RSS_KEY7_MSK		SHIFT0(0xffffffff)	/* RSS Key 7 */
+#define	RSS_KEY7_BASE		0
+
+/*	RSS_KEY8			0x0240	RSS Key 8 Register */
+#define	RSS_KEY8_MSK		SHIFT0(0xffffffff)	/* RSS Key 8 */
+#define	RSS_KEY8_BASE		0
+
+/*	RSS_KEY9			0x0244	RSS Key 9 Register */
+#define	RSS_KEY9_MSK		SHIFT0(0xffffffff)	/* RSS Key 9 */
+#define	RSS_KEY9_BASE		0
+
+/*	RSS_CFG				0x0248	RSS Configuration Register */
+/*		Bit(s) RSS_CFG_RSRV_31_6 reserved */
+/* Microsoft Hashing Type for TCP IPv6 with Extension */
+#define	RSS_CFG_NDIS_HASH_TCP_IPV6_EX_CTRL		BIT_5
+/* Microsoft Hashing Type for IPv6 with Extension */
+#define	RSS_CFG_NDIS_HASH_IPV6_EX_CTRL			BIT_4
+/* Microsoft Hashing Type for TCP IPv6 */
+#define	RSS_CFG_NDIS_HASH_TCP_IPV6_CTRL			BIT_3
+/* Microsoft Hashing Type for IPv6 */
+#define	RSS_CFG_NDIS_HASH_IPV6_CTRL				BIT_2
+/* Microsoft Hashing Type for TCP IPv4 */
+#define	RSS_CFG_NDIS_HASH_TCP_IPV4_CTRL			BIT_1
+/* Microsoft Hashing Type for IPv4 */
+#define	RSS_CFG_NDIS_HASH_IPV4_CTRL				BIT_0
+
+/*	FCU_MEM_BASE_ADDR	0x0300	FCU Memory Base Address */
+/* Flash Main Memory Base Address */
+#define	FCU_MEM_BASE_ADDR_MSK		SHIFT0(0xffffffff)
+#define	FCU_MEM_BASE_ADDR_BASE		0
+
+/*	FCU_REG_BASE_ADDR	0x0304	FCU Register Base Address */
+/* FCU Register Base Address */
+#define	FCU_REG_BASE_ADDR_MSK		SHIFT0(0xffffffff)
+#define	FCU_REG_BASE_ADDR_BASE		0
+
+/*	FCU_MEM_CTRL		0x0308	FCU Memory/Register Control */
+/* FCU Read/Write Action */
+#define	FCU_MEM_CTRL_FCU_RDWR_ACTION			BIT_31
+/* Information/Main Memory Access */
+#define	FCU_MEM_CTRL_INFO_MAIN_MEM_ACCESS		BIT_30
+/* Mem/Register Access */
+#define	FCU_MEM_CTRL_MEMREG_ACCESS				BIT_29
+/*		Bit(s) FCU_MEM_CTRL_RSRV_28_27 reserved */
+#define	FCU_MEM_CTRL_OP_SIZE_MSK				SHIFT24(0x7UL)	/* Operation Size */
+#define	FCU_MEM_CTRL_OP_SIZE_BASE				24
+/*		Bit(s) FCU_MEM_CTRL_RSRV_23_20 reserved */
+/* Byte Address for Memory/Register Operation */
+#define	FCU_MEM_CTRL_OP_ADDR_MSK				SHIFT0(0xfffff)
+#define	FCU_MEM_CTRL_OP_ADDR_BASE				0
+
+/*	FCU_RD_DATA			0x030C	FCU Memory/Register Read Data */
+/* Flash Memory/Register Read Data */
+#define	FCU_RD_DATA_MSK			SHIFT0(0xffffffff)
+#define	FCU_RD_DATA_BASE		0
+
+/*	FCU_WR_DATA			0x0310	FCU Memory/Register Write Data */
+/* Flash Memory/Register Write Data */
+#define	FCU_WR_DATA_MSK			SHIFT0(0xffffffff)
+#define	FCU_WR_DATA_BASE		0
+
+/*	FCU_IMEM_BASE_ADDR	0x0314	FCU Information Memory Address */
+/* Flash Information Memory Base Address */
+#define	FCU_IMEM_BASE_ADDR_MSK		SHIFT0(0xffffffff)
+#define	FCU_IMEM_BASE_ADDR_BASE		0
+
+/*	FCU_ROM_BASE_ADDR	0x0318	FCU ROM Base Address */
+/* Flash ROM Memory Base Address */
+#define	FCU_ROM_BASE_ADDR_MSK		SHIFT0(0xffffffff)
+#define	FCU_ROM_BASE_ADDR_BASE		0
+
+/*	FLASH_MEM_CMD		0x0000	Flash Memory Instruction and Command Register
+ *								(indirect access)
+ */
+#define	FLASH_MEM_CMD_CMD_STATUS			BIT_31			/* Command Status */
+#define	FLASH_MEM_CMD_BAD_CMD				BIT_30			/* Bad Command */
+#define	FLASH_MEM_CMD_FLASH_BUSY			BIT_29			/* Flash Busy */
+#define	FLASH_MEM_CMD_FLASH_SHUT_DOWN		BIT_28			/* Flash Shut Down */
+/*		Bit(s) FLASH_MEM_CMD_RSRV_27_24 reserved */
+/* Instruction/Command Code */
+#define	FLASH_MEM_CMD_CMD_CODE_MSK			SHIFT16(0xffUL)
+#define	FLASH_MEM_CMD_CMD_CODE_BASE			16
+#define	FLASH_MEM_CMD_CMD_DATA_MSK			SHIFT0(0xffff)	/* Command Related Data */
+#define	FLASH_MEM_CMD_CMD_DATA_BASE			0
+
+/*	FLASH_MEM_THRESH	0x0004	Read Buffer Threshold Register (indirect
+ *								access)
+ */
+/*		Bit(s) FLASH_MEM_THRESH_RSRV_31_3 reserved */
+/* Buffer Threshold */
+#define	FLASH_MEM_THRESH_BUFF_THRESHOLD_MSK			SHIFT0(0x7)
+#define	FLASH_MEM_THRESH_BUFF_THRESHOLD_BASE		0
+
+/*	FLASH_MEM_CTRL_CFG	0x0008	Flash Memory Controller Configuration Register
+ *								(indirect access)
+ */
+/*		Bit(s) FLASH_MEM_CTRL_CFG_RSRV_31_6 reserved */
+/* Software Reset FCU */
+#define	FLASH_MEM_CTRL_CFG_SOFT_RST				BIT_4
+/* Flash Gated Clock Enable */
+#define	FLASH_MEM_CTRL_CFG_GATED_CLK_EN			BIT_3
+/* Clear Read Buffer */
+#define	FLASH_MEM_CTRL_CFG_CLEAR_BUFF			BIT_2
+#define	FLASH_MEM_CTRL_CFG_BYPS_READ			BIT_1				/* Bypass Read */
+/* AHB Bus Endian */
+#define	FLASH_MEM_CTRL_CFG_AHB_ENDIAN			BIT_0
+
+/*	FLASH_MEM_STATUS	0x0014	Flash Memory Status Register (indirect access) */
+/*		Bit(s) FLASH_MEM_STATUS_RSRV_31_24 reserved */
+#define	FLASH_MEM_STATUS_CONFIG_VAL_MSK			SHIFT16(0xffUL)	/* Config Data */
+#define	FLASH_MEM_STATUS_CONFIG_VAL_BASE		16
+/*		Bit(s) FLASH_MEM_STATUS_RSRV_15_8 reserved */
+#define	FLASH_MEM_STATUS_WP						BIT_7			/* Write Protection */
+#define	FLASH_MEM_STATUS_COMPARE_ERR			BIT_6			/* Compare Error */
+/* Read Data ECC Error */
+#define	FLASH_MEM_STATUS_ECC_ERR_MSK			SHIFT4(0x3)
+#define	FLASH_MEM_STATUS_ECC_ERR_BASE			4
+/*		Bit(s) FLASH_MEM_STATUS_RSRV_3_1 reserved */
+/* Write in Progress */
+#define	FLASH_MEM_STATUS_WIP					BIT_0
+
+/*	FLASH_MEM_WORD0		0x0018	Flash Memory ID Word 0 Register (indirect
+ *								access)
+ */
+/* Flash Memory Manufacturer and Device Code */
+#define	FLASH_MEM_WORD0_FLASH_ID0_MSK		SHIFT0(0xffffffff)
+#define	FLASH_MEM_WORD0_FLASH_ID0_BASE		0
+
+/*	FLASH_MEM_WORD1		0x001C	Flash Memory ID Word 1 Register (indirect
+ *								access)
+ */
+/*		Bit(s) FLASH_MEM_WORD1_RSRV_31_16 reserved */
+/* Flash Memory Manufacturer and Device Code */
+#define	FLASH_MEM_WORD1_FLASH_ID1_MSK		SHIFT0(0xffff)
+#define	FLASH_MEM_WORD1_FLASH_ID1_BASE		0
+
+/*	FLASH_MEM_INT_MSK	0x0020	Flash Memory Controller Interrupt Enable and
+ *								Status Register (indirect access)
+ */
+/*		Bit(s) FLASH_MEM_INT_MSK_RSRV_31_19 reserved */
+/* Enable Prog/cmp Error Interrupt */
+#define	FLASH_MEM_INT_MSK_CMP_ERR_INT_EN		BIT_18
+/* Enable Address Error Interrupt */
+#define	FLASH_MEM_INT_MSK_ADDR_ERR_INT_EN		BIT_17
+/* Enable Read Data ECC Interrupt */
+#define	FLASH_MEM_INT_MSK_ECC_ERR_INT_EN		BIT_16
+/*		Bit(s) FLASH_MEM_INT_MSK_RSRV_15_3 reserved */
+/* Prog/cmp Error Interrupt */
+#define	FLASH_MEM_INT_MSK_CMP_ERR_INT			BIT_2
+/* Address Error Interrupt */
+#define	FLASH_MEM_INT_MSK_ADDR_ERR_INT			BIT_1
+/* Read Data ECC Error Interrupt */
+#define	FLASH_MEM_INT_MSK_ECC_ERR_INT			BIT_0
+
+/*	FLASH_MEM_INPT_CTRL	0x0024	Flash Memory Controller Pad Input Delay
+ *								Selection Register (indirect access)
+ */
+/*		Bit(s) FLASH_MEM_INPT_CTRL_RSRV_31_21 reserved */
+/* Pad Input Delay Selection Parameter */
+#define	FLASH_MEM_INPT_CTRL_DELAY_SEL_MSK		SHIFT0(0x1fffff)
+#define	FLASH_MEM_INPT_CTRL_DELAY_SEL_BASE		0
+
+/*	FLASH_MEM_OUTP_CTRL	0x0028	Flash Memory Controller Pad Output Delay
+ *								Selection Register (indirect access)
+ */
+/*		Bit(s) FLASH_MEM_OUTP_CTRL_RSRV_31_23 reserved */
+/* Pad Output Delay Selection Parameter */
+#define	FLASH_MEM_OUTP_CTRL_DELAY_SEL_MSK		SHIFT0(0x7fffff)
+#define	FLASH_MEM_OUTP_CTRL_DELAY_SEL_BASE		0
+
+/*	FLASH_MEM_PWR_PARA	0x002C	Flash Memory Power up Parameter Register
+ *								(indirect access)
+ */
+#define	FLASH_MEM_PWR_PARA_RST_WIDTH_MSK			SHIFT16(0xffffUL)	/* Reset Width */
+#define	FLASH_MEM_PWR_PARA_RST_WIDTH_BASE			16
+/* First Access Delay */
+#define	FLASH_MEM_PWR_PARA_FIRST_ACC_DELAY_MSK		SHIFT0(0xffff)
+#define	FLASH_MEM_PWR_PARA_FIRST_ACC_DELAY_BASE		0
+
+/*	FLASH_MEM_INT_SYNC	0x0030	Flash Memory Internal Synchronous Register
+ *								(indirect access)
+ */
+/*		Bit(s) FLASH_MEM_INT_SYNC_RSRV_31_4 reserved */
+/* AHB Sync Cycles */
+#define	FLASH_MEM_INT_SYNC_SYNC_CYC_MSK			SHIFT0(0xf)
+#define	FLASH_MEM_INT_SYNC_SYNC_CYC_BASE		0
+
+/*	FLASH_MEM_INT_DBG1	0x0034	Flash Memory Internal Debug Register 1
+ *								(indirect access)
+ */
+/* Internal Signals */
+#define	FLASH_MEM_INT_DBG1_INTERNAL_SIGNALS0_MSK		SHIFT0(0xffffffff)
+#define	FLASH_MEM_INT_DBG1_INTERNAL_SIGNALS0_BASE		0
+
+/*	FLASH_MEM_INT_DBG2	0x0038	Flash Memory Internal Debug Register 2
+ *								(indirect access)
+ */
+/* Internal Signals */
+#define	FLASH_MEM_INT_DBG2_INTERNAL_SIGNALS1_MSK		SHIFT0(0xffffffff)
+#define	FLASH_MEM_INT_DBG2_INTERNAL_SIGNALS1_BASE		0
+
+/*	FLASH_MEM_WD		0x003C	Flash Memory Soft Reset and Watchdog Timeout
+ *								Reset Parameter Register (indirect access)
+ */
+#define	FLASH_MEM_WD_SOFT_RST_WIDTH_MSK			SHIFT16(0xffffUL)	/* Soft Reset Width */
+#define	FLASH_MEM_WD_SOFT_RST_WIDTH_BASE		16
+/* Flash Recovery Time */
+#define	FLASH_MEM_WD_RECOVER_TIME_MSK			SHIFT0(0xffff)
+#define	FLASH_MEM_WD_RECOVER_TIME_BASE			0
+
+/*	RBMU_DESCR			0x0400	Current Receive Descriptor Register */
+#define	RBMU_DESCR_CTRL_MSK				SHIFT16(0xffffUL)	/* Receive Buffer Control */
+#define	RBMU_DESCR_CTRL_BASE			16
+/* Receive Buffer Byte Count */
+#define	RBMU_DESCR_BYTE_CNT_MSK			SHIFT0(0xffff)
+#define	RBMU_DESCR_BYTE_CNT_BASE		0
+
+/*	RBMU_HASH			0x0404	RSS Hash Checksum Register */
+#define	RBMU_HASH_MSK		SHIFT0(0xffffffff)	/* RSS Hash Checksum */
+#define	RBMU_HASH_BASE		0
+
+/*	RBMU_ADDR_HI		0x0408	Receive Buffer Address Low Register */
+#define	RBMU_ADDR_HI_MSK		SHIFT0(0xffffffff)	/* Receive Buffer Address Low */
+#define	RBMU_ADDR_HI_BASE		0
+
+/*	RBMU_ADDR_LO		0x040C	Receive Buffer Address High Register */
+#define	RBMU_ADDR_LO_MSK		SHIFT0(0xffffffff)	/* Receive Buffer Address High */
+#define	RBMU_ADDR_LO_BASE		0
+
+/*	RBMU_RFSW			0x0410	Receive Buffer Status Word Register */
+#define	RBMU_RFSW_MSK		SHIFT0(0xffffffff)	/* Receive Frame Status Word */
+#define	RBMU_RFSW_BASE		0
+
+/*	RBMU_TSP			0x0414	Receive Timestamp Register */
+#define	RBMU_TSP_MSK		SHIFT0(0xffffffff)	/* Timestamp */
+#define	RBMU_TSP_BASE		0
+
+/*	RBMU_VLAN			0x0420	VLAN Tag Register */
+/*		Bit(s) RBMU_VLAN_RSRV_31_16 reserved */
+#define	RBMU_VLAN_MSK					SHIFT0(0xffff)	/* VLAN Tag */
+#define	RBMU_VLAN_BASE					0
+
+/*	RBMU_DONE_IDX		0x0424	Receive Done Index Register */
+/*		Bit(s) RBMU_DONE_IDX_RSRV_31_12 reserved */
+#define	RBMU_DONE_IDX_MSK					SHIFT0(0xfff)		/* Done Index */
+#define	RBMU_DONE_IDX_BASE					0
+
+/*	RBMU_REQ_ADDR_LOW	0x0428	Receive Request Address, Lower Register */
+#define	RBMU_REQ_ADDR_LOW_MSK		SHIFT0(0xffffffff)	/* Request Address Low */
+#define	RBMU_REQ_ADDR_LOW_BASE		0
+
+/*	RBMU_REQ_ADDR_HIGH	0x042C	Receive Request Address, Upper Register */
+#define	RBMU_REQ_ADDR_HIGH_MSK		SHIFT0(0xffffffff)	/* Request Address High */
+#define	RBMU_REQ_ADDR_HIGH_BASE		0
+
+/*	RBMU_REQ_CNT		0x0430	Receive Request Byte Count Register */
+/*		Bit(s) RBMU_REQ_CNT_RSRV_31_11 reserved */
+/* Request Byte Count */
+#define	RBMU_REQ_CNT_MSK					SHIFT0(0x7ff)
+#define	RBMU_REQ_CNT_BASE					0
+
+/*	RBMU_CSR			0x0434	Receive BMU Control/Status Register */
+#define	RBMU_CSR_IDLE					BIT_31			/* BMU Idle */
+#define	RBMU_CSR_TCPUDP_CSUMOK			BIT_30			/* TCP/UDP Checksum OK Flag */
+#define	RBMU_CSR_UDP_PKT				BIT_29			/* UDP Packet Flag */
+#define	RBMU_CSR_FRAG_PKT				BIT_28			/* Fragment Packet Flag */
+#define	RBMU_CSR_IPV4_CSUMOK			BIT_27			/* IPv4 Checksum OK Flag */
+#define	RBMU_CSR_IPV6_PKT				BIT_26			/* IPv6 Packet Flag */
+#define	RBMU_CSR_TCP_PKT				BIT_25			/* TCP Packet Flag */
+#define	RBMU_CSR_IPV4_PKT				BIT_24			/* IPv4 Packet Flag */
+/*		Bit(s) RBMU_CSR_RSRV_23_20 reserved */
+/* RX Core Clock Gating Enable */
+#define	RBMU_CSR_GCORECLK_ENA			BIT_19
+/* RX Core Clock Gating Disable */
+#define	RBMU_CSR_GCORECLK_DIS			BIT_18
+#define	RBMU_CSR_MACSEC_LE_ENA			BIT_17			/* MACSec LE Enable */
+#define	RBMU_CSR_MACSEC_LE_DIS			BIT_16			/* MACSec LE Disable */
+#define	RBMU_CSR_RSS_ENA				BIT_15			/* RSS Hash Enable */
+#define	RBMU_CSR_RSS_DIS				BIT_14			/* RSS Hash Disable */
+#define	RBMU_CSR_CSUM_ENA				BIT_13			/* RX Checksum Enable */
+#define	RBMU_CSR_CSUM_DIS				BIT_12			/* RX Checksum Disable */
+#define	RBMU_CSR_CLR_IRQ_PAR			BIT_11			/* Clear IRQ Parity Errors */
+#define	RBMU_CSR_CLR_IRQ_CHK			BIT_10			/* Clear IRQ Check */
+#define	RBMU_CSR_STOP_RBMU				BIT_9			/* Stop Rx BMU */
+#define	RBMU_CSR_STRT_RBMU				BIT_8			/* Start Rx BMU */
+#define	RBMU_CSR_FIFO_OP_ON				BIT_7			/* FIFO Operational On */
+#define	RBMU_CSR_FIFO_OP_OFF			BIT_6			/* FIFO Operational Off */
+#define	RBMU_CSR_FIFO_ENA				BIT_5			/* FIFO Enable */
+#define	RBMU_CSR_FIFO_RST				BIT_4			/* FIFO Reset */
+#define	RBMU_CSR_RBMU_OP_ON				BIT_3			/* BMU Operational On */
+#define	RBMU_CSR_RBMU_OP_OFF			BIT_2			/* BMU Operational Off */
+#define	RBMU_CSR_RBMU_ENA				BIT_1			/* BMU Enable */
+#define	RBMU_CSR_RBMU_RST				BIT_0			/* BMU Reset */
+
+/*	RBMU_TEST			0x0438	Receive BMU Test Register */
+/*		Bit(s) RBMU_TEST_RSRV_31_30 reserved */
+#define	RBMU_TEST_EOP_BUSY_DLY_MSK			SHIFT28(0x3UL)	/* EOP Busy Delay */
+#define	RBMU_TEST_EOP_BUSY_DLY_BASE			28
+#define	RBMU_TEST_ENA_A2MREQ_FIX2			BIT_27			/* Enable a2m_req Fix2 */
+#define	RBMU_TEST_DIS_A2MREQ_FIX1			BIT_26			/* Disable a2m_req Fix1 */
+#define	RBMU_TEST_DIS_A2MREQ_FIX0			BIT_25			/* Disable a2m_req Fix0 */
+/* MAC Rx RAM Read Control */
+#define	RBMU_TEST_MAC_RX_RAM_RD_CTRL		BIT_24
+/* Timer RSS Fix Disable */
+#define	RBMU_TEST_TIM_RSS_FIX_DIS			BIT_23
+/*		Bit(s) RBMU_TEST_RSRV_22_8 reserved */
+/*		Bit(s) RBMU_TEST_RSRV_7 reserved */
+/* Testmode Req Nbytes/Addr On */
+#define	RBMU_TEST_TEST_REQ_NB_ON			BIT_6
+/* Testmode Req Nbytes/Addr Off */
+#define	RBMU_TEST_TEST_REQ_NB_OFF			BIT_5
+/* Teststep Request Nbytes/Addresses */
+#define	RBMU_TEST_TESTSTEP_REQ_NB			BIT_4
+/*		Bit(s) RBMU_TEST_RSRV_3 reserved */
+/* Testmode Done Index On */
+#define	RBMU_TEST_TEST_DONE_IDX_ON			BIT_2
+/* Testmode Done Index Off */
+#define	RBMU_TEST_TEST_DONE_IDX_OFF			BIT_1
+#define	RBMU_TEST_TESTSTEP_DONE_IDX			BIT_0			/* Teststep Done Index */
+
+/*	RBMU_SM				0x043C	Receive BMU State Machine Register */
+#define	RBMU_SM_MSK			SHIFT0(0xffffffff)	/* BMU State Machine */
+#define	RBMU_SM_BASE		0
+
+/*	RBMU_FIFO_WM		0x0440	Receive FIFO Watermark Register */
+/*		Bit(s) RBMU_FIFO_WM_RSRV_15_11 reserved */
+#define	RBMU_FIFO_WM_MSK					SHIFT0(0x7ffU)	/* FIFO Watermark */
+#define	RBMU_FIFO_WM_BASE					0
+
+/*	RBMU_FIFO_AL		0x0442	Receive FIFO Alignment Register */
+/*		Bit(s) RBMU_FIFO_AL_RSRV_15_7 reserved */
+#define	RBMU_FIFO_AL_MUX_MSK			SHIFT4(0x7U)	/* Multiplexer Setting */
+#define	RBMU_FIFO_AL_MUX_BASE			4
+/*		Bit(s) RBMU_FIFO_AL_RSRV_3 reserved */
+#define	RBMU_FIFO_AL_VRAM_MSK			SHIFT0(0x7U)	/* VRAM Position */
+#define	RBMU_FIFO_AL_VRAM_BASE			0
+
+/*	RPFU_CTRL			0x0450	Receive Prefetch Control Register */
+/*		Bit(s) RPFU_CTRL_RSRV_31_15 reserved */
+/* Master Request Loopback Test On */
+#define	RPFU_CTRL_MST_REQ_LPBK_ON			BIT_14
+/* Master Request Loopback Test Off */
+#define	RPFU_CTRL_MST_REQ_LPBK_OFF			BIT_13
+/* Master Request Loopback Step */
+#define	RPFU_CTRL_MST_REQ_LPBK_STEP			BIT_12
+/*		Bit(s) RPFU_CTRL_RSRV_11 reserved */
+/* FIFO Read Pointer Test On */
+#define	RPFU_CTRL_FIFO_RPTR_TEST_ON			BIT_10
+/* FIFO Read Pointer Test Off */
+#define	RPFU_CTRL_FIFO_RPTR_TEST_OFF		BIT_9
+/* FIFO Read Pointer Step */
+#define	RPFU_CTRL_FIFO_RPTR_TEST_STEP		BIT_8
+/*		Bit(s) RPFU_CTRL_RSRV_7 reserved */
+/* FIFO Write Pointer Test On */
+#define	RPFU_CTRL_FIFO_WPTR_TEST_ON			BIT_6
+/* FIFO Write Pointer Test Off */
+#define	RPFU_CTRL_FIFO_WPTR_TEST_OFF		BIT_5
+/* FIFO Write Pointer Step */
+#define	RPFU_CTRL_FIFO_WPTR_TEST_STEP		BIT_4
+/* Operational Mode On */
+#define	RPFU_CTRL_OP_ON						BIT_3
+/* Operational Mode Off */
+#define	RPFU_CTRL_OP_OFF					BIT_2
+#define	RPFU_CTRL_PFU_RST_CLR				BIT_1				/* PFU Reset Clear */
+#define	RPFU_CTRL_PFU_RST_SET				BIT_0				/* PFU Reset Set */
+
+/*	RPFU_LAST_IDX		0x0454	Receive PFU List Last Index Register */
+/*		Bit(s) RPFU_LAST_IDX_RSRV_31_12 reserved */
+#define	RPFU_LAST_IDX_MSK					SHIFT2(0x3ff)		/* List Last Index */
+#define	RPFU_LAST_IDX_BASE					2
+/* List Last Index Fix */
+#define	RPFU_LAST_IDX_VAL_FIX_MSK			SHIFT0(0x3)
+#define	RPFU_LAST_IDX_VAL_FIX_BASE			0
+
+/*	RPFU_LADR_LO		0x0458	Receive PFU List Start Address Low Register */
+/* List Start Address Low */
+#define	RPFU_LADR_LO_MSK				SHIFT5(0x7ffffff)
+#define	RPFU_LADR_LO_BASE				5
+/* List Start Address Low Fix */
+#define	RPFU_LADR_LO_VAL_FIX_MSK		SHIFT0(0x1f)
+#define	RPFU_LADR_LO_VAL_FIX_BASE		0
+
+/*	RPFU_LADR_HI		0x045C	Receive PFU List Start Address High Register */
+#define	RPFU_LADR_HI_MSK		SHIFT0(0xffffffff)	/* List Start Address High */
+#define	RPFU_LADR_HI_BASE		0
+
+/*	RPFU_GET_IDX		0x0460	Receive PFU Get Index Register */
+/*		Bit(s) RPFU_GET_IDX_RSRV_31_12 reserved */
+#define	RPFU_GET_IDX_MSK					SHIFT0(0xfff)		/* Get Index */
+#define	RPFU_GET_IDX_BASE					0
+
+/*	RPFU_PUT_IDX		0x0464	Receive PFU Put Index Register */
+/*		Bit(s) RPFU_PUT_IDX_RSRV_31_12 reserved */
+#define	RPFU_PUT_IDX_MSK					SHIFT0(0xfff)		/* Put Index */
+#define	RPFU_PUT_IDX_BASE					0
+
+/*	RPFU_FIFO_WR		0x0470	Receive PFU FIFO RAM Write and Write Shadow
+ *								Pointer Register
+ */
+/*		Bit(s) RPFU_FIFO_WR_RSRV_31_24 reserved */
+/* FIFO Write Shadow Pointer */
+#define	RPFU_FIFO_WR_WSPTR_MSK				SHIFT16(0xffUL)
+#define	RPFU_FIFO_WR_WSPTR_BASE				16
+/*		Bit(s) RPFU_FIFO_WR_RSRV_15_5 reserved */
+#define	RPFU_FIFO_WR_WPTR_MSK				SHIFT0(0x1f)	/* FIFO Write Pointer */
+#define	RPFU_FIFO_WR_WPTR_BASE				0
+
+/*	RPFU_FIFO_RD		0x0474	Receive PFU FIFO RAM Read Pointer Register */
+/*		Bit(s) RPFU_FIFO_RD_RSRV_31_5 reserved */
+#define	RPFU_FIFO_RD_RPTR_MSK			SHIFT0(0x1f)		/* FIFO Read Pointer */
+#define	RPFU_FIFO_RD_RPTR_BASE			0
+
+/*	RPFU_FIFO_REQ_NB	0x0478	Receive PFU Master Request nbytes Register */
+/*		Bit(s) RPFU_FIFO_REQ_NB_RSRV_31_27 reserved */
+/* Master Request nbytes */
+#define	RPFU_FIFO_REQ_NB_MR_MSK					SHIFT16(0x7ffUL)
+#define	RPFU_FIFO_REQ_NB_MR_BASE				16
+/*		Bit(s) RPFU_FIFO_REQ_NB_RSRV_15_8 reserved */
+#define	RPFU_FIFO_REQ_NB_WM_MSK					SHIFT0(0xff)	/* FIFO Watermark */
+#define	RPFU_FIFO_REQ_NB_WM_BASE				0
+
+/*	RPFU_FIFO_LEV		0x047C	Receive PFU FIFO Shadow Level Register */
+/*		Bit(s) RPFU_FIFO_LEV_RSRV_31_24 reserved */
+#define	RPFU_FIFO_LEV_SLEV_MSK				SHIFT16(0xffUL)	/* FIFO Shadow Level */
+#define	RPFU_FIFO_LEV_SLEV_BASE				16
+/*		Bit(s) RPFU_FIFO_LEV_RSRV_15_5 reserved */
+#define	RPFU_FIFO_LEV_MSK					SHIFT0(0x1f)	/* FIFO Level */
+#define	RPFU_FIFO_LEV_BASE					0
+
+/*	TBMU_DESC1			0x0680	Current Transmit Descriptor Register 1 */
+#define	TBMU_DESC1_MSK					SHIFT16(0xffffUL)	/* Transmit Buffer Control */
+#define	TBMU_DESC1_BASE					16
+/*		Bit(s) TBMU_DESC1_RSRV_15_0 reserved */
+
+/*	TBMU_DESC2			0x0684	Current Transmit Descriptor Register 2 */
+#define	TBMU_DESC2_MSK		SHIFT0(0xffffU)	/* Transmit Buffer Byte Count */
+#define	TBMU_DESC2_BASE		0
+
+/*	TBMU_ADDR_LO		0x0688	Transmit Buffer Address Lower Register */
+#define	TBMU_ADDR_LO_MSK		SHIFT0(0xffffffff)	/* Transmit Buffer Address Lo */
+#define	TBMU_ADDR_LO_BASE		0
+
+/*	TBMU_ADDR_HI		0x068C	Transmit Buffer Address Upper Register */
+#define	TBMU_ADDR_HI_MSK		SHIFT0(0xffffffff)	/* Transmit Buffer Address Hi */
+#define	TBMU_ADDR_HI_BASE		0
+
+/*	TBMU_TFSW			0x0690	Transmit Buffer Status Word Register */
+#define	TBMU_TFSW_MSK		SHIFT0(0xffffffff)	/* Transmit Frame Status Word */
+#define	TBMU_TFSW_BASE		0
+
+/*	TBMU_VLAN			0x06A0	Transmit VLAN Tag Register */
+/*		Bit(s) TBMU_VLAN_RSRV_31_16 reserved */
+#define TBMU_LE_SEL_MSK                 SHIFT16(0x7UL)	/* LE ADD HI selection */
+#define TBMU_LE_SEL_BASE                16
+#define	TBMU_VLAN_MSK					SHIFT0(0xffff)	/* VLAN Tag */
+#define	TBMU_VLAN_BASE					0
+
+/*	TBMU_DONE_IDX		0x06A4	Transmit Done Index Register */
+/*		Bit(s) TBMU_DONE_IDX_RSRV_31_12 reserved */
+#define TBMU_DONE_IDX_SEL_MSK               SHIFT0(0x3)     /* Done Index Select LEs */
+#define TBMU_DONE_IDX_SEL_BASE              30
+#define TBMU_DONE_IDX_EVN_MSK               SHIFT0(0xfff)   /* Done Index LEs 2,4,6,8 */
+#define TBMU_DONE_IDX_EVN_BASE              16
+#define TBMU_DONE_IDX_ODD_MSK               SHIFT0(0xfff)   /* Done Index LEs 1,3,5,7 */
+#define TBMU_DONE_IDX_ODD_BASE              0
+#define	TBMU_DONE_IDX_MSK					SHIFT0(0xfff)		/* Done Index */
+#define	TBMU_DONE_IDX_BASE					0
+
+/*	TBMU_REQ_ADDR_LO	0x06A8	Transmit Request Address Lower Register */
+#define	TBMU_REQ_ADDR_LO_MSK		SHIFT0(0xffffffff)	/* Request Address Low */
+#define	TBMU_REQ_ADDR_LO_BASE		0
+
+/*	TBMU_REQ_ADDR_HI	0x06AC	Transmit Request Address Upper Register */
+#define	TBMU_REQ_ADDR_HI_MSK		SHIFT0(0xffffffff)	/* Request Address High */
+#define	TBMU_REQ_ADDR_HI_BASE		0
+
+/*	TBMU_REQ_CNT		0x06B0	Transmit Request Byte Count Register */
+/*		Bit(s) TBMU_REQ_CNT_RSRV_31_11 reserved */
+/* Request Byte Count */
+#define	TBMU_REQ_CNT_MSK					SHIFT0(0x7ff)
+#define	TBMU_REQ_CNT_BASE					0
+
+/*	TBMU_CSR			0x06B4	Transmit BMU Control/Status Register */
+#define	TBMU_CSR_IDLE						BIT_31			/* BMU Idle */
+/*		Bit(s) TBMU_CSR_RSRV_30_24 reserved */
+/* Tx Path Automatic Clock Gating Enable */
+#define	TBMU_CSR_TX_GATE_ON					BIT_23
+/* TX Path Automatic Clock Gating Disable */
+#define	TBMU_CSR_TX_GATE_OFF				BIT_22
+/* TX Path Automatic Clock Gating Timeout */
+#define	TBMU_CSR_TX_GATE_TIMEOUT_MSK		SHIFT16(0x3fUL)
+#define	TBMU_CSR_TX_GATE_TIMEOUT_BASE		16
+/*		Bit(s) TBMU_CSR_RSRV_15_14 reserved */
+/* IP ID Increment Enable */
+#define	TBMU_CSR_IP_ID_INCR_ENA				BIT_13
+/* IP ID Increment Disable */
+#define	TBMU_CSR_IP_ID_INCR_DIS				BIT_12
+#define	TBMU_CSR_CLR_IRQ_TCP				BIT_11			/* Clear IRQ TCP */
+#define	TBMU_CSR_CLR_IRQ_CHK				BIT_10			/* Clear IRQ Check */
+#define	TBMU_CSR_STOP_TBMU					BIT_9			/* Stop Tx BMU */
+#define	TBMU_CSR_STRT_TBMU					BIT_8			/* Start Tx BMU */
+#define	TBMU_CSR_FIFO_OP_ON					BIT_7			/* FIFO Operational On */
+#define	TBMU_CSR_FIFO_OP_OFF				BIT_6			/* FIFO Operational Off */
+#define	TBMU_CSR_FIFO_ENA					BIT_5			/* FIFO Enable */
+#define	TBMU_CSR_FIFO_RST					BIT_4			/* FIFO Reset */
+#define	TBMU_CSR_TBMU_OP_ON					BIT_3			/* BMU Operational On */
+#define	TBMU_CSR_TBMU_OP_OFF				BIT_2			/* BMU Operational Off */
+#define	TBMU_CSR_TBMU_ENA					BIT_1			/* BMU Enable */
+#define	TBMU_CSR_TBMU_RST					BIT_0			/* BMU Reset */
+
+/*	TBMU_TEST			0x06B8	Transmit BMU Test Register */
+/* BMU Tx Checksum Auto Calculation Disable */
+#define	TBMU_TEST_BMU_TX_CHK_AUTO_OFF		BIT_31
+/* BMU Tx Checksum Auto Calculation Enable */
+#define	TBMU_TEST_BMU_TX_CHK_AUTO_ON		BIT_30
+/* Home Address Padding FIX1 Enable */
+#define	TBMU_TEST_HOME_ADD_PAD_FIX1_EN		BIT_29
+/* Home Address Padding FIX1 Disable */
+#define	TBMU_TEST_HOME_ADD_PAD_FIX1_DIS		BIT_28
+/* Routing Address Fix Enable */
+#define	TBMU_TEST_ROUTING_ADD_FIX_EN		BIT_27
+/* Routing Address Fix Disable */
+#define	TBMU_TEST_ROUTING_ADD_FIX_DIS		BIT_26
+/* Home address checksum fix enable */
+#define	TBMU_TEST_HOME_ADD_FIX_EN			BIT_25
+/* Home address checksum fix disable */
+#define	TBMU_TEST_HOME_ADD_FIX_DIS			BIT_24
+/*		Bit(s) TBMU_TEST_RSRV_23 reserved */
+/* Testmode Shadow Read Ptr On */
+#define	TBMU_TEST_TEST_RSPTR_ON				BIT_22
+/* Testmode Shadow Read Ptr Off */
+#define	TBMU_TEST_TEST_RSPTR_OFF			BIT_21
+/* Teststep Shadow Read Ptr */
+#define	TBMU_TEST_TESTSTEP_RSPTR			BIT_20
+/*		Bit(s) TBMU_TEST_RSRV_19 reserved */
+#define	TBMU_TEST_TEST_RPTR_ON				BIT_18			/* Testmode Read Ptr On */
+/* Testmode Read Ptr Off */
+#define	TBMU_TEST_TEST_RPTR_OFF				BIT_17
+#define	TBMU_TEST_TESTSTEP_RPTR				BIT_16			/* Teststep Read Ptr */
+/*		Bit(s) TBMU_TEST_RSRV_15 reserved */
+/* Testmode Shadow Write Ptr On */
+#define	TBMU_TEST_TEST_WSPTR_ON				BIT_14
+/* Testmode Shadow Write Ptr Off */
+#define	TBMU_TEST_TEST_WSPTR_OFF			BIT_13
+/* Teststep Shadow Write Ptr */
+#define	TBMU_TEST_TESTSTEP_WSPTR			BIT_12
+/*		Bit(s) TBMU_TEST_RSRV_11 reserved */
+/* Testmode Write Ptr On */
+#define	TBMU_TEST_TEST_WPTR_ON				BIT_10
+/* Testmode Write Ptr Off */
+#define	TBMU_TEST_TEST_WPTR_OFF				BIT_9
+#define	TBMU_TEST_TESTSTEP_WPTR				BIT_8			/* Teststep Write Ptr */
+/*		Bit(s) TBMU_TEST_RSRV_7 reserved */
+/* Testmode Req Nbytes/Addr On */
+#define	TBMU_TEST_TEST_REQ_NB_ON			BIT_6
+/* Testmode Req Nbytes/Addr Off */
+#define	TBMU_TEST_TEST_REQ_NB_OFF			BIT_5
+/* Teststep Req Nbytes/Addr */
+#define	TBMU_TEST_TESTSTEP_REQ_NB			BIT_4
+/*		Bit(s) TBMU_TEST_RSRV_3 reserved */
+/* Testmode Done Index On */
+#define	TBMU_TEST_TEST_DONE_IDX_ON			BIT_2
+/* Testmode Done Index Off */
+#define	TBMU_TEST_TEST_DONE_IDX_OFF			BIT_1
+#define	TBMU_TEST_TESTSTEP_DONE_IDX			BIT_0			/* Teststep Done Index */
+
+/*	TBMU_SM				0x06BC	Transmit BMU State Machine Register */
+#define	TBMU_SM_MSK			SHIFT0(0xffffffff)	/* BMU State Machine */
+#define	TBMU_SM_BASE		0
+
+/*	TBMU_FIFO_WM		0x06C0	Transmit FIFO Watermark Register */
+/*		Bit(s) TBMU_FIFO_WM_RSRV_15_11 reserved */
+#define	TBMU_FIFO_WM_MSK					SHIFT3(0xffU)	/* FIFO Watermark */
+#define	TBMU_FIFO_WM_BASE					3
+/*		Bit(s) TBMU_FIFO_WM_RSRV_2_0 reserved */
+
+/*	TBMU_FIFO_AL		0x06C2	Transmit FIFO Alignment Register */
+/*		Bit(s) TBMU_FIFO_AL_RSRV_15_7 reserved */
+#define	TBMU_FIFO_AL_MUX_MSK			SHIFT4(0x7U)	/* Multiplexer Setting */
+#define	TBMU_FIFO_AL_MUX_BASE			4
+/*		Bit(s) TBMU_FIFO_AL_RSRV_3 reserved */
+#define	TBMU_FIFO_AL_VRAM_MSK			SHIFT0(0x7U)	/* VRAM Position */
+#define	TBMU_FIFO_AL_VRAM_BASE			0
+
+/*	TBMU_FIFO_WSPTR		0x06C4	Transmit FIFO Write Shadow Pointer Register */
+/*		Bit(s) TBMU_FIFO_WSPTR_RSRV_15_11 reserved */
+/* FIFO Write Shadow Pointer */
+#define	TBMU_FIFO_WSPTR_MSK					SHIFT0(0x7ffU)
+#define	TBMU_FIFO_WSPTR_BASE				0
+
+/*	TBMU_FIFO_WSLEV		0x06C6	Transmit FIFO Write Shadow Level Register */
+/*		Bit(s) TBMU_FIFO_WSLEV_RSRV_15_8 reserved */
+#define	TBMU_FIFO_WSLEV_MSK					SHIFT0(0xffU)	/* FIFO Write Level */
+#define	TBMU_FIFO_WSLEV_BASE				0
+
+/*	TBMU_FIFO_WPTR		0x06C8	Transmit FIFO Write Pointer Register */
+/*		Bit(s) TBMU_FIFO_WPTR_RSRV_15_8 reserved */
+#define	TBMU_FIFO_WPTR_MSK					SHIFT0(0xffU)	/* FIFO Write Pointer */
+#define	TBMU_FIFO_WPTR_BASE					0
+
+/*	TBMU_FIFO_WLEV		0x06CA	Transmit FIFO Write Level Register */
+/*		Bit(s) TBMU_FIFO_WLEV_RSRV_15_8 reserved */
+#define	TBMU_FIFO_WLEV_MSK					SHIFT0(0xffU)	/* FIFO Write Level */
+#define	TBMU_FIFO_WLEV_BASE					0
+
+/*	TBMU_FIFO_RPTR		0x06CC	Transmit FIFO Read Pointer Register */
+/*		Bit(s) TBMU_FIFO_RPTR_RSRV_15_8 reserved */
+#define	TBMU_FIFO_RPTR_MSK					SHIFT0(0xffU)	/* FIFO Read Pointer */
+#define	TBMU_FIFO_RPTR_BASE					0
+
+/*	TBMU_RLEV			0x06CE	Transmit FIFO Read Level Register */
+/*		Bit(s) TBMU_RLEV_RSRV_15_8 reserved */
+#define	TBMU_RLEV_MSK					SHIFT0(0xffU)	/* FIFO Read Level */
+#define	TBMU_RLEV_BASE					0
+
+/*	TPFU_CTRL			0x06D0	Transmit Prefetch Control Register */
+/*		Bit(s) TPFU_CTRL_RSRV_31_15 reserved */
+/* Master Request Loopback Test On */
+#define	TPFU_CTRL_MST_REQ_LPBK_ON			BIT_14
+/* Master Request Loopback Test Off */
+#define	TPFU_CTRL_MST_REQ_LPBK_OFF			BIT_13
+/* Master Request Loopback Step */
+#define	TPFU_CTRL_MST_REQ_LPBK_STEP			BIT_12
+/*		Bit(s) TPFU_CTRL_RSRV_11 reserved */
+/* FIFO Read Pointer Test On */
+#define	TPFU_CTRL_FIFO_RPTR_TEST_ON			BIT_10
+/* FIFO Read Pointer Test Off */
+#define	TPFU_CTRL_FIFO_RPTR_TEST_OFF		BIT_9
+/* FIFO Read Pointer Step */
+#define	TPFU_CTRL_FIFO_RPTR_TEST_STEP		BIT_8
+/*		Bit(s) TPFU_CTRL_RSRV_7 reserved */
+/* FIFO Write Pointer Test On */
+#define	TPFU_CTRL_FIFO_WPTR_TEST_ON			BIT_6
+/* FIFO Write Pointer Test Off */
+#define	TPFU_CTRL_FIFO_WPTR_TEST_OFF		BIT_5
+/* FIFO Write Pointer Step */
+#define	TPFU_CTRL_FIFO_WPTR_TEST_STEP		BIT_4
+/* Operational Mode On */
+#define	TPFU_CTRL_OP_ON						BIT_3
+/* Operational Mode Off */
+#define	TPFU_CTRL_OP_OFF					BIT_2
+#define	TPFU_CTRL_PFU_RST_CLR				BIT_1				/* PFU Reset Clear */
+#define	TPFU_CTRL_PFU_RST_SET				BIT_0				/* PFU Reset Set */
+
+/*	TPFU_LAST_IDX		0x06D4	Transmit PFU List Last Index Register */
+/*		Bit(s) TPFU_LAST_IDX_RSRV_31_12 reserved */
+#define	TPFU_LAST_IDX_MSK					SHIFT2(0x3ff)		/* List Last Index */
+#define	TPFU_LAST_IDX_BASE					2
+/* List Last Index Fix */
+#define	TPFU_LAST_IDX_VAL_FIX_MSK			SHIFT0(0x3)
+#define	TPFU_LAST_IDX_VAL_FIX_BASE			0
+
+/*	TPFU_LADR_LO		0x06D8	Transmit PFU List Start Address Low Register */
+/* List Start Address Low */
+#define	TPFU_LADR_LO_MSK				SHIFT5(0x7ffffff)
+#define	TPFU_LADR_LO_BASE				5
+/* List Start Address Low Fix */
+#define	TPFU_LADR_LO_VAL_FIX_MSK		SHIFT0(0x1f)
+#define	TPFU_LADR_LO_VAL_FIX_BASE		0
+
+/*	TPFU_LADR_HI		0x06DC	Transmit PFU List Start Address High Register */
+#define	TPFU_LADR_HI_MSK		SHIFT0(0xffffffff)	/* List Start Address High */
+#define	TPFU_LADR_HI_BASE		0
+
+/*	TPFU_GET_IDX		0x06E0	Transmit PFU Get Index Register */
+/*		Bit(s) TPFU_GET_IDX_RSRV_31_12 reserved */
+#define	TPFU_GET_IDX_MSK					SHIFT0(0xfff)		/* Get Index */
+#define	TPFU_GET_IDX_BASE					0
+
+/*	TPFU_PUT_IDX		0x06E4	Transmit PFU Put Index Register */
+/*		Bit(s) TPFU_PUT_IDX_RSRV_31_12 reserved */
+#define	TPFU_PUT_IDX_MSK					SHIFT0(0xfff)		/* Put Index */
+#define	TPFU_PUT_IDX_BASE					0
+
+/*	TPFU_FIFO_WR		0x06F0	Transmit PFU FIFO RAM Write and Write Shadow
+ *								Pointer Register
+ */
+/*		Bit(s) TPFU_FIFO_WR_RSRV_31_24 reserved */
+/* FIFO Write Shadow Pointer */
+#define	TPFU_FIFO_WR_WSPTR_MSK				SHIFT16(0xffUL)
+#define	TPFU_FIFO_WR_WSPTR_BASE				16
+/*		Bit(s) TPFU_FIFO_WR_RSRV_15_5 reserved */
+#define	TPFU_FIFO_WR_WPTR_MSK				SHIFT0(0x1f)	/* FIFO Write Pointer */
+#define	TPFU_FIFO_WR_WPTR_BASE				0
+
+/*	TPFU_FIFO_RD		0x06F4	Transmit PFU FIFO RAM Read Pointer Register */
+/*		Bit(s) TPFU_FIFO_RD_RSRV_31_5 reserved */
+#define	TPFU_FIFO_RD_RPTR_MSK			SHIFT0(0x1f)		/* FIFO Read Pointer */
+#define	TPFU_FIFO_RD_RPTR_BASE			0
+
+/*	TPFU_FIFO_REQ_NB	0x06F8	Transmit PFU Master Request nbytes Register */
+/*		Bit(s) TPFU_FIFO_REQ_NB_RSRV_31_27 reserved */
+/* Master Request nbytes */
+#define	TPFU_FIFO_REQ_NB_MR_MSK					SHIFT16(0x7ffUL)
+#define	TPFU_FIFO_REQ_NB_MR_BASE				16
+/*		Bit(s) TPFU_FIFO_REQ_NB_RSRV_15_8 reserved */
+#define	TPFU_FIFO_REQ_NB_WM_MSK					SHIFT0(0xff)	/* FIFO Watermark */
+#define	TPFU_FIFO_REQ_NB_WM_BASE				0
+
+/*	TPFU_FIFO_LEV		0x06FC	Transmit PFU FIFO Shadow Level Register */
+/*		Bit(s) TPFU_FIFO_LEV_RSRV_31_24 reserved */
+#define	TPFU_FIFO_LEV_SLEV_MSK				SHIFT16(0xffUL)	/* FIFO Shadow level */
+#define	TPFU_FIFO_LEV_SLEV_BASE				16
+/*		Bit(s) TPFU_FIFO_LEV_RSRV_15_5 reserved */
+#define	TPFU_FIFO_LEV_MSK					SHIFT0(0x1f)	/* FIFO level */
+#define	TPFU_FIFO_LEV_BASE					0
+
+/*	PKT_GEN_CTL			0x0800	Packet Generator Control Register */
+/*		Bit(s) PKT_GEN_CTL_RSRV_31_9 reserved */
+/* Packet Gen Mode Selection */
+#define	PKT_GEN_CTL_PKT_GEN_MODE_MSK		SHIFT4(0x1f)
+#define	PKT_GEN_CTL_PKT_GEN_MODE_BASE		4
+/* Packet Gen Operate On */
+#define	PKT_GEN_CTL_PKT_GEN_OP_EN			BIT_3
+/* Packet Gen Operate Off */
+#define	PKT_GEN_CTL_PKT_GEN_OP_DIS			BIT_2
+/* Packet Gen Enable */
+#define	PKT_GEN_CTL_PKT_GEN_EN				BIT_1
+/* Packet Gen Reset */
+#define	PKT_GEN_CTL_PKT_GEN_DIS				BIT_0
+
+/*	PKT_GEN_LEN_CTRL	0x0804	Packet Generator Length Register */
+/*		Bit(s) PKT_GEN_LEN_CTRL_RSRV_31_11 reserved */
+/* Packet Gen Length Register */
+#define	PKT_GEN_LEN_CTRL_PKT_GEN_LEN_MSK		SHIFT0(0x7ff)
+#define	PKT_GEN_LEN_CTRL_PKT_GEN_LEN_BASE		0
+
+/*	PKT_GEN_PKT_COUNTER	0x0808	Packet Generator Packet Counter Register */
+/* Packet Gen Packet Counter Register Reload */
+#define	PKT_GEN_PKT_COUNTER_PKT_GEN_CNT_LD			BIT_31
+/*		Bit(s) PKT_GEN_PKT_COUNTER_RSRV_30_24 reserved */
+/* Packet Gen Packet Counter Register */
+#define	PKT_GEN_PKT_COUNTER_PKT_GEN_CNT_MSK			SHIFT0(0xffffff)
+#define	PKT_GEN_PKT_COUNTER_PKT_GEN_CNT_BASE		0
+
+/*	PKT_GEN_DELTA		0x080C	Packet Generator Data or Packet Size Increment
+ *								Delta Register
+ */
+/*		Bit(s) PKT_GEN_DELTA_RSRV_31_27 reserved */
+/* Packet Gen Packet Length Delta */
+#define	PKT_GEN_DELTA_LEN_MSK				SHIFT16(0x7ffUL)
+#define	PKT_GEN_DELTA_LEN_BASE				16
+/*		Bit(s) PKT_GEN_DELTA_RSRV_15_8 reserved */
+/* Packet Gen Data Pattern Increase Delta */
+#define	PKT_GEN_DELTA_PAT_MSK				SHIFT0(0xff)
+#define	PKT_GEN_DELTA_PAT_BASE				0
+
+/*	PKT_GEN_PAT1_LO		0x0810	Packet Generator Pattern 1 Lo Register */
+/* Packet Gen Pattern 1 Register Low qword */
+#define	PKT_GEN_PAT1_LO_MSK			SHIFT0(0xffffffff)
+#define	PKT_GEN_PAT1_LO_BASE		0
+
+/*	PKT_GEN_PAT1_HI		0x0814	Packet Generator Pattern 1 Hi Register */
+/* Packet Gen Pattern 1 Register High qword */
+#define	PKT_GEN_PAT1_HI_MSK			SHIFT0(0xffffffff)
+#define	PKT_GEN_PAT1_HI_BASE		0
+
+/*	PKT_GEN_PAT2_LO		0x0818	Packet Generator Pattern 2 Lo Register */
+/* Packet Gen Pattern 2 Register Low qword */
+#define	PKT_GEN_PAT2_LO_MSK			SHIFT0(0xffffffff)
+#define	PKT_GEN_PAT2_LO_BASE		0
+
+/*	PKT_GEN_PAT2_HI		0x081C	Packet Generator Pattern 2 Hi Register */
+/* Packet Gen Pattern 2 Register High qword */
+#define	PKT_GEN_PAT2_HI_MSK			SHIFT0(0xffffffff)
+#define	PKT_GEN_PAT2_HI_BASE		0
+
+/*	PKT_GEN_SIZE_LIMIT	0x0820	Packet Generator Packet Size Limit Register */
+/*		Bit(s) PKT_GEN_SIZE_LIMIT_RSRV_31_27 reserved */
+/* Packet Length Min Size */
+#define	PKT_GEN_SIZE_LIMIT_PKT_GEN_LEN_MIN_MSK		SHIFT16(0x7ffUL)
+#define	PKT_GEN_SIZE_LIMIT_PKT_GEN_LEN_MIN_BASE		16
+/*		Bit(s) PKT_GEN_SIZE_LIMIT_RSRV_15_11 reserved */
+/* Packet Length Max Size */
+#define	PKT_GEN_SIZE_LIMIT_PKT_GEN_LEN_MAX_MSK		SHIFT0(0x7ff)
+#define	PKT_GEN_SIZE_LIMIT_PKT_GEN_LEN_MAX_BASE		0
+
+/*	PKT_GEN_PKT_CNT_ST	0x0824	Packet Generator Packet Counter Count Down
+ *								Status Register
+ */
+/*		Bit(s) PKT_GEN_PKT_CNT_ST_RSRV_31_24 reserved */
+/* Packet Gen Packet Counter Register */
+#define	PKT_GEN_PKT_CNT_ST_PKT_GEN_CNT_STATUS_MSK		SHIFT0(0xffffff)
+#define	PKT_GEN_PKT_CNT_ST_PKT_GEN_CNT_STATUS_BASE		0
+
+/*	PKT_GEN_PKT_GAP		0x0828	Packet Generator Packet Gap Register */
+/*		Bit(s) PKT_GEN_PKT_GAP_RSRV_31_24 reserved */
+/* Packet Gen Packet Gap Register */
+#define	PKT_GEN_PKT_GAP_MSK					SHIFT0(0xffffff)
+#define	PKT_GEN_PKT_GAP_BASE				0
+
+/*	PKT_CHK_PFU_START	0x0830	Packet Checker RX PFU Start Address Register */
+/* Packet Checker RX LE Address Start Value */
+#define	PKT_CHK_PFU_START_ADDR_MSK		SHIFT0(0xffffffff)
+#define	PKT_CHK_PFU_START_ADDR_BASE		0
+
+/*	PKT_CHK_BUF_INC		0x0834	Packet Checker RX PFU Buffer Increment Register */
+/* Packet Checker RX PFU Put Index Increment */
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_PUTIDX_INC_MSK		SHIFT25(0x7fUL)
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_PUTIDX_INC_BASE		25
+/* Packet Checker RX LE Buffer Length Increment */
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_BUFLEN_INC_MSK		SHIFT14(0x7ffUL)
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_BUFLEN_INC_BASE		14
+/* Packet Checker RX LE Buffer Start Address Increment */
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_ADDR_INC_MSK		SHIFT0(0x3fff)
+#define	PKT_CHK_BUF_INC_PKT_CHK_PFU_ADDR_INC_BASE		0
+
+/*	PKT_CHK_BUF_SIZE	0x0838	Packet Checker RX PFU Buffer Size Register */
+/*		Bit(s) PKT_CHK_BUF_SIZE_RSRV_31_30 reserved */
+/* Packet Checker RX LE Buffer Length Max Value */
+#define	PKT_CHK_BUF_SIZE_PKT_CHK_PFU_BUFLEN_MAX_MSK			SHIFT16(0x3fffUL)
+#define	PKT_CHK_BUF_SIZE_PKT_CHK_PFU_BUFLEN_MAX_BASE		16
+/*		Bit(s) PKT_CHK_BUF_SIZE_RSRV_15_14 reserved */
+/* Packet Checker RX LE Buffer Length Start Value */
+#define	PKT_CHK_BUF_SIZE_PKT_CHK_PFU_BUFLEN_START_MSK		SHIFT0(0x3fff)
+#define	PKT_CHK_BUF_SIZE_PKT_CHK_PFU_BUFLEN_START_BASE		0
+
+/*	PKT_CHK_STATUS			0x083C	Packet Checker Status Register */
+/* Packet Checker Packet Number */
+#define	PKT_CHK_ST_PKT_CHK_PKTNUM_MSK		SHIFT16(0xffffUL)
+#define	PKT_CHK_ST_PKT_CHK_PKTNUM_BASE		16
+/* Packet Checker Packet Fail */
+#define	PKT_CHK_ST_PKT_CHK_PKTFAIL			BIT_15
+/*		Bit(s) PKT_CHK_ST_RSRV_14 reserved */
+/* Packet Checker Packet Length */
+#define	PKT_CHK_ST_PKT_CHK_PKTLEN_MSK		SHIFT0(0x3fff)
+#define	PKT_CHK_ST_PKT_CHK_PKTLEN_BASE		0
+
+/*	RA_SADDR			0x0900	ASF Receive FIFO Start Address */
+/*		Bit(s) RA_SADDR_RSRV_31_15 reserved */
+#define	RA_SADDR_RA_SADDR_MSK			SHIFT0(0x7fff)		/* Start Address */
+#define	RA_SADDR_RA_SADDR_BASE			0
+
+/*	RA_EADDR			0x0904	ASF Receive FIFO End Address */
+/*		Bit(s) RA_EADDR_RSRV_31_15 reserved */
+#define	RA_EADDR_RA_EADDR_MSK			SHIFT0(0x7fff)		/* End Address */
+#define	RA_EADDR_RA_EADDR_BASE			0
+
+/*	RA_WPTR				0x0908	ASF Receive FIFO Write Pointer */
+/*		Bit(s) RA_WPTR_RSRV_31_15 reserved */
+#define	RA_WPTR_RA_WPTR_MSK			SHIFT0(0x7fff)		/* Write Pointer */
+#define	RA_WPTR_RA_WPTR_BASE		0
+
+/*	RA_RPTR				0x090C	ASF Receive FIFO Read Pointer */
+/*		Bit(s) RA_RPTR_RSRV_31_15 reserved */
+#define	RA_RPTR_RA_RPTR_MSK			SHIFT0(0x7fff)		/* Read Pointer */
+#define	RA_RPTR_RA_RPTR_BASE		0
+
+/*	RA_BRST				0x0910	ASF Receive FIFO Burst Control */
+/*		Bit(s) RA_BRST_RSRV_31_18 reserved */
+#define	RA_BRST_RA_BRST_EN				BIT_17			/* Burst Enable */
+#define	RA_BRST_RA_BRST_RST				BIT_16			/* Burst Disable */
+/*		Bit(s) RA_BRST_RSRV_15 reserved */
+#define	RA_BRST_RA_BRST_THRS_MSK		SHIFT0(0x7fff)	/* Burst Threshold */
+#define	RA_BRST_RA_BRST_THRS_BASE		0
+
+/*	RA_PCNT				0x0920	ASF Receive FIFO Packet Counter */
+/*		Bit(s) RA_PCNT_RSRV_31_15 reserved */
+#define	RA_PCNT_RA_PCNT_MSK			SHIFT0(0x7fff)		/* Packet Counter */
+#define	RA_PCNT_RA_PCNT_BASE		0
+
+/*	RA_LEV				0x0924	ASF Receive FIFO Level */
+/*		Bit(s) RA_LEV_RSRV_31_15 reserved */
+#define	RA_LEV_RA_LEV_MSK			SHIFT0(0x7fff)		/* Level */
+#define	RA_LEV_RA_LEV_BASE			0
+
+/*	RA_CTRL				0x0928	ASF Receive FIFO Control/Test */
+/*		Bit(s) RA_CTRL_RSRV_31_20 reserved */
+#define	RA_CTRL_RA_PCNT_DN			BIT_19			/* Packet Counter Step Down */
+#define	RA_CTRL_RA_PCNT_ENA			BIT_18			/* Packet Counter Test On */
+#define	RA_CTRL_RA_PCNT_RST			BIT_17			/* Packet Counter Test Off */
+#define	RA_CTRL_RA_PCNT_UP			BIT_16			/* Packet Counter Step Up */
+/*		Bit(s) RA_CTRL_RSRV_15 reserved */
+#define	RA_CTRL_RA_WPTR_ENA			BIT_14			/* Write Pointer Test On */
+#define	RA_CTRL_RA_WPTR_RST			BIT_13			/* Write Pointer Test Off */
+#define	RA_CTRL_RA_WPTR_UP			BIT_12			/* Write Pointer Step Up */
+/*		Bit(s) RA_CTRL_RSRV_11_7 reserved */
+#define	RA_CTRL_RA_IRQ_CLR			BIT_6			/* Clear IRQ ASF Receive FIFO */
+/*		Bit(s) RA_CTRL_RSRV_5_4 reserved */
+#define	RA_CTRL_RA_OP_ON			BIT_3			/* Operational Mode On */
+#define	RA_CTRL_RA_OP_OFF			BIT_2			/* Operational Mode Off */
+#define	RA_CTRL_RA_RST_CLR			BIT_1			/* Reset Clear */
+#define	RA_CTRL_RA_RST_SET			BIT_0			/* Reset Set */
+
+/*	RA_FLSH_CTRL		0x092C	ASF Receive FIFO Flush Control */
+#define	RA_FLSH_CTRL_RA_FLSH				BIT_31			/* Flush */
+/*		Bit(s) RA_FLSH_CTRL_RSRV_30_15 reserved */
+#define	RA_FLSH_CTRL_RA_FLSH_QWORD_MSK		SHIFT0(0x7fff)	/* Flush Qword */
+#define	RA_FLSH_CTRL_RA_FLSH_QWORD_BASE		0
+
+/*	TA_SADDR			0x0940	ASF Transmit FIFO Start Address */
+/*		Bit(s) TA_SADDR_RSRV_31_15 reserved */
+#define	TA_SADDR_TA_SADDR_MSK			SHIFT0(0x7fff)		/* Start Address */
+#define	TA_SADDR_TA_SADDR_BASE			0
+
+/*	TA_EADDR			0x0944	ASF Transmit FIFO End Address */
+/*		Bit(s) TA_EADDR_RSRV_31_15 reserved */
+#define	TA_EADDR_TA_EADDR_MSK			SHIFT0(0x7fff)		/* End Address */
+#define	TA_EADDR_TA_EADDR_BASE			0
+
+/*	TA_WPTR				0x0948	ASF Transmit FIFO Write Pointer */
+/*		Bit(s) TA_WPTR_RSRV_31_15 reserved */
+#define	TA_WPTR_TA_WPTR_MSK			SHIFT0(0x7fff)		/* Write Pointer */
+#define	TA_WPTR_TA_WPTR_BASE		0
+
+/*	TA_RPTR				0x094C	ASF Transmit FIFO Read Pointer */
+/*		Bit(s) TA_RPTR_RSRV_31_15 reserved */
+#define	TA_RPTR_TA_RPTR_MSK			SHIFT0(0x7fff)		/* Read Pointer */
+#define	TA_RPTR_TA_RPTR_BASE		0
+
+/*	TA_PCNT				0x0960	ASF Transmit FIFO Packet Counter */
+/*		Bit(s) TA_PCNT_RSRV_31_15 reserved */
+#define	TA_PCNT_TA_PCNT_MSK			SHIFT0(0x7fff)		/* Packet Counter */
+#define	TA_PCNT_TA_PCNT_BASE		0
+
+/*	TA_LEV				0x0964	ASF Transmit FIFO Level */
+/*		Bit(s) TA_LEV_RSRV_31_15 reserved */
+#define	TA_LEV_TA_LEV_MSK			SHIFT0(0x7fff)		/* Level */
+#define	TA_LEV_TA_LEV_BASE			0
+
+/*	TA_CTRL				0x0968	ASF Transmit FIFO Control/Test */
+/*		Bit(s) TA_CTRL_RSRV_31_20 reserved */
+#define	TA_CTRL_TA_PCNT_DN			BIT_19			/* Packet Counter Step Down */
+#define	TA_CTRL_TA_PCNT_ENA			BIT_18			/* Packet Counter Test On */
+#define	TA_CTRL_TA_PCNT_RST			BIT_17			/* Packet Counter Test Off */
+#define	TA_CTRL_TA_PCNT_UP			BIT_16			/* Packet Counter Step Up */
+/*		Bit(s) TA_CTRL_RSRV_15 reserved */
+#define	TA_CTRL_TA_WRPTR_ENA		BIT_14			/* Write Pointer Test On */
+#define	TA_CTRL_TA_WPTRR_RST		BIT_13			/* Write Pointer Test OFF */
+#define	TA_CTRL_TA_WPTR_UP			BIT_12			/* Write Pointer Step up */
+/*		Bit(s) TA_CTRL_RSRV_11 reserved */
+#define	TA_CTRL_TA_RPTR_ENA			BIT_10			/* Read Pointer Test On */
+#define	TA_CTRL_TA_RPTR_RST			BIT_9			/* Read Pointer Test Off */
+#define	TA_CTRL_TA_RPTR_UP			BIT_8			/* Read Pointer Step Up */
+/*		Bit(s) TA_CTRL_RSRV_7 reserved */
+#define	TA_CTRL_TA_IRQ_CLR			BIT_6			/* Clear IRQ ASF Transmit FIFO */
+/*		Bit(s) TA_CTRL_RSRV_5_4 reserved */
+#define	TA_CTRL_TA_OP_ON			BIT_3			/* Operational Mode On */
+#define	TA_CTRL_TA_OP_OFF			BIT_2			/* Operational Mode Off */
+#define	TA_CTRL_TA_RST_CLR			BIT_1			/* Reset Clear */
+#define	TA_CTRL_TA_RST_SET			BIT_0			/* Reset Set */
+
+/*	TA_SEND_CTRL		0x096C	ASF Transmit FIFO Send Control */
+#define	TA_SEND_CTRL_TA_SEND				BIT_31			/* Send */
+/*		Bit(s) TA_SEND_CTRL_RSRV_30_15 reserved */
+#define	TA_SEND_CTRL_TA_SEND_QWORD_MSK		SHIFT0(0x7fff)	/* Send Qword */
+#define	TA_SEND_CTRL_TA_SEND_QWORD_BASE		0
+
+/*	RXMF_EADDR			0x0C40	Receive MAC FIFO End Address Register */
+/*		Bit(s) RXMF_EADDR_RSRV_31_11 reserved */
+#define	RXMF_EADDR_MSK					SHIFT0(0x7ff)		/* End Address */
+#define	RXMF_EADDR_BASE					0
+
+/*	RXMF_AFTH			0x0C44	Receive MAC FIFO Almost Full Threshold Register */
+/*		Bit(s) RXMF_AFTH_RSRV_31_11 reserved */
+/* Almost Full Threshold */
+#define	RXMF_AFTH_MSK					SHIFT0(0x7ff)
+#define	RXMF_AFTH_BASE					0
+
+/*	RXMF_TCTL			0x0C48	Receive MAC FIFO Control/Test Register */
+#define	RXMF_TCTL_GCLKMAC_ENA				BIT_31	/* RX MAC Clock Gating Enable */
+#define	RXMF_TCTL_GCLKMAC_DIS				BIT_30	/* RX MAC Clock Gating Disable */
+#define	RXMF_TCTL_STFWD_ENA					BIT_29	/* RX Store and Forward Enable */
+#define	RXMF_TCTL_STFWD_DIS					BIT_28	/* RX Store and Forward Disable */
+#define	RXMF_TCTL_TRUNC_ENA					BIT_27	/* Truncation Enable */
+#define	RXMF_TCTL_TRUNC_DIS					BIT_26	/* Truncation Disable */
+#define	RXMF_TCTL_VLAN_ENA					BIT_25	/* VLAN Enable */
+#define	RXMF_TCTL_VLAN_DIS					BIT_24	/* VLAN Disable */
+#define	RXMF_TCTL_MACSEC_FLSH_ENA			BIT_23	/* RX MACsec Flush Enable */
+#define	RXMF_TCTL_MACSEC_FLSH_DIS			BIT_22	/* RX MACsec Flush Disable */
+#define	RXMF_TCTL_RA_MACSEC_FLSH_ENA		BIT_21	/* ASF RX MACsec Flush Enable */
+#define	RXMF_TCTL_RA_MACSEC_FLSH_DIS		BIT_20	/* ASF RX MACsec Flush Disable */
+#define	RXMF_TCTL_OVRRN_FLSH_ENA			BIT_19	/* RX Overrun Flush Enable */
+#define	RXMF_TCTL_OVRRN_FLSH_DIS			BIT_18	/* RX Overrun Flush Disable */
+#define	RXMF_TCTL_RA_FLSH_ENA				BIT_17	/* ASF RX Overrun Flush Enable */
+#define	RXMF_TCTL_RA_FLSH_DIS				BIT_16	/* ASF RX Overrun Flush Disable */
+/*		Bit(s) RXMF_TCTL_RSRV_15 reserved */
+#define	RXMF_TCTL_WPTR_TEST_ON				BIT_14	/* Write Pointer Test On */
+#define	RXMF_TCTL_WPTR_TEST_OFF				BIT_13	/* Write Pointer Test Off */
+#define	RXMF_TCTL_WPTR_TEST_STEP			BIT_12	/* Write Pointer Step */
+/*		Bit(s) RXMF_TCTL_RSRV_11 reserved */
+#define	RXMF_TCTL_RPTR_TEST_ON				BIT_10	/* Read Pointer Test On */
+#define	RXMF_TCTL_RPTR_TEST_OFF				BIT_9	/* Read Pointer Test Off */
+#define	RXMF_TCTL_RPTR_TEST_STEP			BIT_8	/* Read Pointer Step */
+#define	RXMF_TCTL_FLUSH_ON					BIT_7	/* FIFO Flush Mode On */
+#define	RXMF_TCTL_FLUSH_OFF					BIT_6	/* FIFO Flush Mode Off */
+/* Clear IRQ Receive FIFO Overrun */
+#define	RXMF_TCTL_CLR_IRQ_RX_OF				BIT_5
+/* Clear IRQ Frame Reception Complete */
+#define	RXMF_TCTL_CLR_IRQ_RX_OK				BIT_4
+#define	RXMF_TCTL_OP_ON						BIT_3	/* Operational Mode On */
+#define	RXMF_TCTL_OP_OFF					BIT_2	/* Operational Mode Off */
+#define	RXMF_TCTL_RST_CLR					BIT_1	/* MAC FIFO Reset Clear */
+#define	RXMF_TCTL_RST_SET					BIT_0	/* MAC FIFO Reset Set */
+
+/*	RXMF_FLMSK			0x0C4C	Receive MAC FIFO Flush Mask Register */
+/*		Bit(s) RXMF_FLMSK_RSRV_31_14 reserved */
+#define	RXMF_FLMSK_VLAN					BIT_13				/* VLAN Packet */
+#define	RXMF_FLMSK_JBR					BIT_12				/* Jabber */
+#define	RXMF_FLMSK_USIZE				BIT_11				/* Undersize Packet */
+#define	RXMF_FLMSK_MCST					BIT_10				/* Multicast Packet */
+#define	RXMF_FLMSK_BCST					BIT_9				/* Broadcast Packet */
+#define	RXMF_FLMSK_RX_OK				BIT_8				/* Receive OK */
+/* Good Flow Control Packet */
+#define	RXMF_FLMSK_GD_FC				BIT_7
+/* Bad Flow Control Packet */
+#define	RXMF_FLMSK_BD_FC				BIT_6
+#define	RXMF_FLMSK_MII_ERR				BIT_5				/* MII Error */
+#define	RXMF_FLMSK_TLNG					BIT_4				/* Too Long Packet */
+#define	RXMF_FLMSK_FRAG					BIT_3				/* Fragment */
+/*		Bit(s) RXMF_FLMSK_RSRV_2 reserved */
+#define	RXMF_FLMSK_CRC_ERR				BIT_1				/* CRC Error */
+/* Receive FIFO Overflow */
+#define	RXMF_FLMSK_RX_OF				BIT_0
+
+/*	RXMF_FLTH			0x0C50	Receive MAC FIFO Flush Threshold Register */
+/*		Bit(s) RXMF_FLTH_RSRV_31_26 reserved */
+/* IPv6 Source Address Mobility Support Enable */
+#define	RXMF_FLTH_IPV6_SA_MOBILITY_ENA		BIT_25
+/* IPv6 Source Address Mobility Support Disable */
+#define	RXMF_FLTH_IPV6_SA_MOBILITY_DIS		BIT_24
+/* IPv6 Destination Address Mobility Support Enable */
+#define	RXMF_FLTH_IPV6_DA_MOBILITY_ENA		BIT_23
+/* IPv6 Destination Address Mobility Support Disable */
+#define	RXMF_FLTH_IPV6_DA_MOBILITY_DIS		BIT_22
+/* Pointers Delay Synchronization Enable */
+#define	RXMF_FLTH_PTR_SYNCDLY_ENA			BIT_21
+/* Pointers Delay Synchronization Disable */
+#define	RXMF_FLTH_PTR_SYNCDLY_DIS			BIT_20
+/* RX ASF Flag New Logic Enable */
+#define	RXMF_FLTH_ASF_NEWFLAG_ENA			BIT_19
+/* RX ASF Flag New Logic Disable */
+#define	RXMF_FLTH_ASF_NEWFLAG_DIS			BIT_18
+/* RX Flush Miss-Packet Enable */
+#define	RXMF_FLTH_FLSH_MISSPKT_ENA			BIT_17
+/* RX Flush Miss-Packet Disable */
+#define	RXMF_FLTH_FLSH_MISSPKT_DIS			BIT_16
+/*		Bit(s) RXMF_FLTH_RSRV_15_11 reserved */
+#define	RXMF_FLTH_MSK						SHIFT0(0x7ff)	/* Flush Threshold */
+#define	RXMF_FLTH_BASE						0
+
+/*	RXMF_TRTH			0x0C54	Receive Truncation Threshold Register */
+/*		Bit(s) RXMF_TRTH_RSRV_31_9 reserved */
+/* Truncation Threshold */
+#define	RXMF_TRTH_TRUNCATION_THRESHOLD_MSK		SHIFT0(0x1ff)
+#define	RXMF_TRTH_TRUNCATION_THRESHOLD_BASE		0
+
+/*	RXMF_ULTH			0x0C58	Upper/Lower Threshold/Pause Packets Register */
+/*		Bit(s) RXMF_ULTH_RSRV_31_27 reserved */
+/* Pause Packet Watermark Low Threshold */
+#define	RXMF_ULTH_LO_TH_MSK				SHIFT16(0x7ffUL)
+#define	RXMF_ULTH_LO_TH_BASE			16
+/*		Bit(s) RXMF_ULTH_RSRV_15_11 reserved */
+/* Pause Packet Watermark High Threshold */
+#define	RXMF_ULTH_HI_TH_MSK				SHIFT0(0x7ff)
+#define	RXMF_ULTH_HI_TH_BASE			0
+
+/*	RXMF_VLTYP			0x0C5C	Receive VLAN Type Register */
+/*		Bit(s) RXMF_VLTYP_RSRV_31_16 reserved */
+#define	RXMF_VLTYP_MSK					SHIFT0(0xffff)	/* Receive VLAN Type */
+#define	RXMF_VLTYP_BASE					0
+
+/*	RXMF_WPTR			0x0C60	Receive MAC FIFO Write Pointer Register */
+/*		Bit(s) RXMF_WPTR_RSRV_31_11 reserved */
+#define	RXMF_WPTR_MSK					SHIFT0(0x7ff)		/* Write Pointer */
+#define	RXMF_WPTR_BASE					0
+
+/*	RXMF_WLEV			0x0C68	Receive MAC FIFO Write Level Register */
+/*		Bit(s) RXMF_WLEV_RSRV_31_11 reserved */
+#define	RXMF_WLEV_MSK					SHIFT0(0x7ff)		/* Write Level */
+#define	RXMF_WLEV_BASE					0
+
+/*	RXMF_RPTR			0x0C70	Receive MAC FIFO Read Pointer Register */
+/*		Bit(s) RXMF_RPTR_RSRV_31_11 reserved */
+#define	RXMF_RPTR_MSK					SHIFT0(0x7ff)		/* Read Pointer */
+#define	RXMF_RPTR_BASE					0
+
+/*	RXMF_RLEV			0x0C78	Receive MAC FIFO Read Level Register */
+/*		Bit(s) RXMF_RLEV_RSRV_31_11 reserved */
+#define	RXMF_RLEV_MSK					SHIFT0(0x7ff)		/* Read Level */
+#define	RXMF_RLEV_BASE					0
+
+/*	RXMF_FCNT			0x0C7C	Receive MAC FIFO Flush Counter Register */
+#define	RXMF_FCNT_BLANK_31_16_MSK		SHIFT16(0xffffUL)	/* ASF Flush Counter */
+#define	RXMF_FCNT_BLANK_31_16_BASE		16
+#define	RXMF_FCNT_MSK					SHIFT0(0xffff)	/* BMU Flush Counter */
+#define	RXMF_FCNT_BASE					0
+
+/*  TX_RATE_LIMIT              0x0D0C  Transmit MAC FIFO AVB Limiter Register */
+/* AVB Tx Queue Low Limit Threshold */
+#define TX_RATE_LIMIT_FLOW_LO_LIMIT_MSK        SHIFT16(0xffffUL)
+#define TX_RATE_LIMIT_FLOW_LO_LIMIT_BASE       16
+/* AVB Tx Queue High Limit Threshold */
+#define TX_RATE_LIMIT_FLOW_HI_LIMIT_MSK        SHIFT0(0xffff)
+#define TX_RATE_LIMIT_FLOW_HI_LIMIT_BASE       0
+
+/*  TX_RATE_INT                0x0D10  Transmit MAC FIFO AVB Rate Shaper
+ *                                      Register
+ */
+/* K Factor Enable */
+#define TX_RATE_INT_K_FACTOR_EN                BIT_31
+/*      Bit(s) TX_RATE_INT_RSRV_30_22 reserved */
+/* K Factor/Tx Rate Integer for 1/K Scheme */
+#define TX_RATE_INT_K_FACTOR_RATE_INT_MSK      SHIFT0(0x3fffff)
+#define TX_RATE_INT_K_FACTOR_RATE_INT_BASE     0
+
+/*  TX_RATE_FRAC               0x0D14  Tx Rate Fraction Register */
+/* Tx Rate Denominator for 1/K Factor Scheme */
+#define TX_RATE_FRAC_RATE_DEN_MSK      SHIFT16(0xffffUL)
+#define TX_RATE_FRAC_RATE_DEN_BASE     16
+/* Tx Rate Numerator for 1/K Factor Scheme */
+#define TX_RATE_FRAC_RATE_NUM_MSK      SHIFT0(0xffff)
+#define TX_RATE_FRAC_RATE_NUM_BASE     0
+
+/*  TX_RATE_MISC               0x0D18  Tx Misc Rate Register */
+/* Disable Tx Queue Rate Shaper */
+#define TX_RATE_MISC_RATE_SHAPE_DIS                BIT_31
+/* Disable Tx Queue Flow Rate Shaper */
+#define TX_RATE_MISC_FLOW_SHAPE_DIS                BIT_30
+/*      Bit(s) TX_RATE_MISC_RSRV_29_16 reserved */
+/* Tx Queue Rate Controller Overhead Bytes */
+#define TX_RATE_MISC_RATE_OVERHEAD_MSK         SHIFT8(0xff)
+#define TX_RATE_MISC_RATE_OVERHEAD_BASE        8
+/*      Bit(s) TX_RATE_MISC_RSRV_7 reserved */
+/* Start IdleSlope */
+#define TX_RATE_MISC_SEND_START                    BIT_6
+/* Tx Count Layer 3 */
+#define TX_RATE_MISC_COUNT_LAYER3              BIT_5
+/* Tx Count Layer 1 or 3 */
+#define TX_RATE_MISC_COUNT_LAYER1OR3           BIT_4
+/* Tx Priority */
+#define TX_RATE_MISC_PRI_MSK                   SHIFT2(0x3)
+#define TX_RATE_MISC_PRI_BASE                  2
+#define AVB_PRIO_HIGHEST					   SHIFT2(3)
+#define AVB_PRIO_HIGH						   SHIFT2(2)
+#define AVB_PRIO_LOW						   SHIFT2(1)
+#define AVB_PRIO_LOWEST						   SHIFT2(0)
+
+#define TX_RATE_MISC_CLASS_MSK                 SHIFT0(0x3)     /* Tx Class */
+#define TX_RATE_MISC_CLASS_BASE                0
+#define AVB_CLASS_A							   SHIFT0(1)
+#define AVB_CLASS_B							   SHIFT0(2)
+#define AVB_CLASS_NONE						   SHIFT2(0)
+
+/*  TX_RATE_GAP                0x0D1C  Tx Rate Gap Register */
+/*      Bit(s) TX_RATE_GAP_RSRV_31_24 reserved */
+/* Tx Shaper Gap Adjust */
+#define TX_RATE_GAP_GAP_ADJ_MSK        SHIFT16(0xffUL)
+#define TX_RATE_GAP_GAP_ADJ_BASE       16
+/*      Bit(s) TX_RATE_GAP_RSRV_15_0 reserved */
+
+/*  TXMF_WPTR2                  0x0D20  Transmit MAC FIFO Write Pointer
+ *                                      Register
+ */
+/*      Bit(s) TXMF_WPTR2_RSRV_31_8 reserved */
+#define TXMF_WPTR2_MSK                  SHIFT0(0xff)        /* Write Pointer */
+#define TXMF_WPTR2_BASE                 0
+
+/*  TXMF_WSPTR2                 0x0D24  Transmit MAC FIFO Write Shadow Pointer
+ *                                      Register
+ */
+/*      Bit(s) TXMF_WSPTR2_RSRV_31_8 reserved */
+#define TXMF_WSPTR2_MSK                 SHIFT0(0xff)        /* Write Shadow Pointer */
+#define TXMF_WSPTR2_BASE                0
+
+/*  TXMF_WLEV2                  0x0D28  Transmit MAC FIFO Write Level Register */
+/*      Bit(s) TXMF_WLEV2_RSRV_31_8 reserved */
+#define TXMF_WLEV2_MSK                  SHIFT0(0xff)        /* Write Level */
+#define TXMF_WLEV2_BASE                 0
+
+/*  TXMF_RPTR2                  0x0D30  Transmit MAC FIFO Read Pointer Register */
+/*      Bit(s) TXMF_RPTR2_RSRV_31_8 reserved */
+#define TXMF_RPTR2_MSK                  SHIFT0(0xff)        /* Read Pointer */
+#define TXMF_RPTR2_BASE                 0
+
+/*  TXMF_RES_PTR2               0x0D34  Transmit MAC FIFO Restart Pointer
+ *                                      Register
+ */
+/*      Bit(s) TXMF_RES_PTR2_RSRV_31_8 reserved */
+#define TXMF_RES_PTR2_MSK                   SHIFT0(0xff)        /* Restart Pointer */
+#define TXMF_RES_PTR2_BASE                  0
+
+/*  TXMF_RLEV2                  0x0D38  Transmit MAC FIFO Read Level Register */
+/*      Bit(s) TXMF_RLEV2_RSRV_31_8 reserved */
+#define TXMF_RLEV2_MSK                  SHIFT0(0xff)        /* Read Level */
+#define TXMF_RLEV2_BASE                 0
+
+/*  TX_AVB_ST                  0x0D3C  Transmit Queue 2 AVB Status Register */
+#define TX_AVB_ST_MONITOR_SEL_MSK      SHIFT30(0x3UL)    /* Monitor Status Selection */
+#define TX_AVB_ST_MONITOR_SEL_BASE     30
+/*      Bit(s) TX_AVB_ST_RSRV_29_16 reserved */
+#define TX_AVB_ST_MONITOR_ST_MSK       SHIFT0(0xffff)  /* Monitor Status */
+#define TX_AVB_ST_MONITOR_ST_BASE      0
+
+/*	TXMF_EADDR			0x0D40	Transmit MAC FIFO End Address Register */
+/*		Bit(s) TXMF_EADDR_RSRV_31_4 reserved */
+/* MAC Tx RAM Read Control */
+#define	TXMF_EADDR_MAC_TX_RAM_RD_CTRL		BIT_3
+/* BMU Tx RAM Read Control */
+#define	TXMF_EADDR_BMU_TX_RAM_RD_CTRL		BIT_2
+/*		Bit(s) TXMF_EADDR_RSRV_1_0 reserved */
+
+/*	TXMF_AETH			0x0D44	Transmit MAC FIFO Almost Empty Threshold
+ *								Register
+ */
+/*		Bit(s) TXMF_AETH_RSRV_31_27 reserved */
+#define	TXMF_AETH_JUMBO_WM_MSK			SHIFT16(0x7ffUL)	/* Jumbo Mode Watermark */
+#define	TXMF_AETH_JUMBO_WM_BASE			16
+/*		Bit(s) TXMF_AETH_RSRV_15_11 reserved */
+#define	TXMF_AETH_MSK					SHIFT0(0x7ff)	/* Almost Empty Threshold */
+#define	TXMF_AETH_BASE					0
+
+/*	TXMF_TCTL			0x0D48	Transmit MAC FIFO Control/Test Register */
+#define	TXMF_TCTL_JUMBO_ENA				BIT_31			/* Jumbo Mode Enable */
+/* Tx Store and Forward Mode Enable */
+#define	TXMF_TCTL_STORE_FW_ENA			BIT_30
+#define	TXMF_TCTL_FIX_440_OFF			BIT_29			/* Perf Fix #4.40 Off */
+#define	TXMF_TCTL_FIX_440_ON			BIT_28			/* Perf Fix #4.40 On */
+#define	TXMF_TCTL_TX_CSUM_DIS			BIT_27			/* Tx Checksum Disable */
+#define	TXMF_TCTL_TX_CSUM_ENA			BIT_26			/* Tx Checksum Enable */
+/* CHECKSUM SEL use CALSUM status bit */
+#define	TXMF_TCTL_CHKSUM_EN				BIT_26
+#define	TXMF_TCTL_VLAN_ENA				BIT_25			/* VLAN Enable */
+#define	TXMF_TCTL_VLAN_DIS				BIT_24			/* VLAN Disable */
+#define	TXMF_TCTL_PCI_JUMBO_ENA			BIT_23			/* PCI Jumbo Mode Enable */
+#define	TXMF_TCTL_PCI_JUMBO_DIS			BIT_22			/* PCI Jumbo Mode Disable */
+/*		Bit(s) TXMF_TCTL_RSRV_21_19 reserved */
+/* Write Shadow Pointer Test On */
+#define	TXMF_TCTL_WSPTR_TEST_ON			BIT_18
+/* Write Shadow Pointer Test Off */
+#define	TXMF_TCTL_WSPTR_TEST_OFF		BIT_17
+/* Write Shadow Pointer Step */
+#define	TXMF_TCTL_WSPTR_TEST_STEP		BIT_16
+/*		Bit(s) TXMF_TCTL_RSRV_15 reserved */
+#define	TXMF_TCTL_WPTR_TEST_ON			BIT_14			/* Write Pointer Test On */
+#define	TXMF_TCTL_WPTR_TEST_OFF			BIT_13			/* Write Pointer Test Off */
+#define	TXMF_TCTL_WPTR_TEST_STEP		BIT_12			/* Write Pointer Step */
+#define	TXMF_TCTL_FIX_440_ENA			BIT_11			/* 4.40 Fix Enable */
+#define	TXMF_TCTL_RPTR_TEST_ON			BIT_10			/* Read Pointer Test On */
+#define	TXMF_TCTL_RPTR_TEST_OFF			BIT_9			/* Read Pointer Test Off */
+#define	TXMF_TCTL_RPTR_TEST_STEP		BIT_8			/* Read Pointer Step */
+/*		Bit(s) TXMF_TCTL_RSRV_7 reserved */
+/* Clear IRQ Transmit FIFO Underrun */
+#define	TXMF_TCTL_CLR_IRQ_TX_UR			BIT_6
+/* Clear IRQ Frame Transmission Complete */
+#define	TXMF_TCTL_CLR_IRQ_TX_OK			BIT_5
+#define	TXMF_TCTL_CLR_IRQ_PAR			BIT_4			/* Clear IRQ Parity Error */
+#define	TXMF_TCTL_OP_ON					BIT_3			/* Operational Mode On */
+#define	TXMF_TCTL_OP_OFF				BIT_2			/* Operational Mode Off */
+#define	TXMF_TCTL_RST_CLR				BIT_1			/* MAC FIFO Reset Clear */
+#define	TXMF_TCTL_RST_SET				BIT_0			/* MAC FIFO Reset Set */
+
+/*	TXMF_VLTYP			0x0D5C	Transmit VLAN Type Register */
+/*		Bit(s) TXMF_VLTYP_RSRV_31_16 reserved */
+#define	TXMF_VLTYP_MSK					SHIFT0(0xffff)	/* Transmit VLAN Type */
+#define	TXMF_VLTYP_BASE					0
+
+/*	TXMF_WPTR			0x0D60	Transmit MAC FIFO Write Pointer Register */
+/*		Bit(s) TXMF_WPTR_RSRV_31_11 reserved */
+#define	TXMF_WPTR_MSK					SHIFT0(0x7ff)		/* Write Pointer */
+#define	TXMF_WPTR_BASE					0
+
+/*	TXMF_WSPTR			0x0D64	Transmit MAC FIFO Write Shadow Pointer Register */
+/*		Bit(s) TXMF_WSPTR_RSRV_31_11 reserved */
+#define	TXMF_WSPTR_MSK					SHIFT0(0x7ff)		/* Write Shadow Pointer */
+#define	TXMF_WSPTR_BASE					0
+
+/*	TXMF_WLEV			0x0D68	Transmit MAC FIFO Write Level Register */
+/*		Bit(s) TXMF_WLEV_RSRV_31_11 reserved */
+#define	TXMF_WLEV_MSK					SHIFT0(0x7ff)		/* Write Level */
+#define	TXMF_WLEV_BASE					0
+
+/*	TXMF_RPTR			0x0D70	Transmit MAC FIFO Read Pointer Register */
+/*		Bit(s) TXMF_RPTR_RSRV_31_11 reserved */
+#define	TXMF_RPTR_MSK					SHIFT0(0x7ff)		/* Read Pointer */
+#define	TXMF_RPTR_BASE					0
+
+/*	TXMF_RES_PTR		0x0D74	Transmit MAC FIFO Restart Pointer Register */
+/*		Bit(s) TXMF_RES_PTR_RSRV_31_11 reserved */
+#define	TXMF_RES_PTR_MSK					SHIFT0(0x7ff)		/* Restart Pointer */
+#define	TXMF_RES_PTR_BASE					0
+
+/*	TXMF_RLEV			0x0D78	Transmit MAC FIFO Read Level Register */
+/*		Bit(s) TXMF_RLEV_RSRV_31_11 reserved */
+#define	TXMF_RLEV_MSK					SHIFT0(0x7ff)		/* Read Level */
+#define	TXMF_RLEV_BASE					0
+
+/*	DPOL_TIM_INIT		0x0E00	Descriptor Poll Timer Init Value Register */
+/* Descriptor Poll Timer Init Value */
+#define	DPOL_TIM_INIT_INIT_VALUE_MSK		SHIFT0(0xffffffff)
+#define	DPOL_TIM_INIT_INIT_VALUE_BASE		0
+
+/*	DPOL_TIM_CNT		0x0E04	Descriptor Poll Timer Register */
+#define	DPOL_TIM_CNT_MSK		SHIFT0(0xffffffff)	/* Descriptor Poll Timer */
+#define	DPOL_TIM_CNT_BASE		0
+
+/*	DPOL_TCTL			0x0E08	Descriptor Poll Timer Control/Test Register */
+/*		Bit(s) DPOL_TCTL_RSRV_31_11 reserved */
+/* Descriptor Poll Timer Test On */
+#define	DPOL_TCTL_ON					BIT_10
+/* Descriptor Poll Timer Test Off */
+#define	DPOL_TCTL_OFF					BIT_9
+/* Descriptor Poll Timer Step */
+#define	DPOL_TCTL_STEP					BIT_8
+/*		Bit(s) DPOL_TCTL_RSRV_7_3 reserved */
+/* Descriptor Poll Timer Start */
+#define	DPOL_TCTL_STRT					BIT_2
+/* Descriptor Poll Timer Stop */
+#define	DPOL_TCTL_STOP					BIT_1
+/*		Bit(s) DPOL_TCTL_RSRV_0 reserved */
+
+/*	TSP_TIM_CNT			0x0E14	Timestamp Timer Registers */
+#define	TSP_TIM_CNT_MSK			SHIFT0(0xffffffff)	/* Timestamp Timer */
+#define	TSP_TIM_CNT_BASE		0
+
+/*	TSP_TIM_TCTL		0x0E18	Timestamp Timer Control/Test Register */
+/*		Bit(s) TSP_TIM_TCTL_RSRV_31_11 reserved */
+/* Timestamp Timer Test On */
+#define	TSP_TIM_TCTL_TST_ON					BIT_10
+/* Timestamp Timer Test Off */
+#define	TSP_TIM_TCTL_TST_OFF				BIT_9
+/* Timestamp Timer Step */
+#define	TSP_TIM_TCTL_STEP					BIT_8
+/*		Bit(s) TSP_TIM_TCTL_RSRV_7_5 reserved */
+/* Timestamp List Element Generation Enable */
+#define	TSP_TIM_TCTL_ON						BIT_4
+/* Timestamp List Element Generation Disable */
+#define	TSP_TIM_TCTL_OFF					BIT_3
+/* Timestamp Timer Start */
+#define	TSP_TIM_TCTL_STRT					BIT_2
+/* Timestamp Timer Stop */
+#define	TSP_TIM_TCTL_STOP					BIT_1
+/* Timestamp Timer Clear IRQ */
+#define	TSP_TIM_TCTL_CLR_IRQ				BIT_0
+
+/*	POLL_CTRL			0x0E20	Poll Control Register */
+/*		Bit(s) POLL_CTRL_RSRV_31_6 reserved */
+#define	POLL_CTRL_CLR_IRQ				BIT_5				/* Clear IRQ */
+#define	POLL_CTRL_POLL_REQ				BIT_4				/* Poll Request */
+#define	POLL_CTRL_OP_ON					BIT_3				/* Operational Mode On */
+#define	POLL_CTRL_OP_OFF				BIT_2				/* Operational Mode Off */
+#define	POLL_CTRL_POLL_RST_CLR			BIT_1				/* POLLU Reset Clear */
+#define	POLL_CTRL_POLL_RST_SET			BIT_0				/* POLLU Reset Set */
+
+/*	POLL_LAST_IDX		0x0E24	List Last Index Register */
+/*		Bit(s) POLL_LAST_IDX_RSRV_31_1 reserved */
+#define	POLL_LAST_IDX_BIT					BIT_0				/* List Last Index */
+
+/*	POLL_LADR_LO		0x0E28	List Start Address Low Register */
+/* List Start Address Low */
+#define	POLL_LADR_LO_MSK				SHIFT3(0x1fffffffUL)
+#define	POLL_LADR_LO_BASE				3
+/* List Start Address Low Fixed */
+#define	POLL_LADR_LO_VAL_FIX_MSK		SHIFT0(0x7)
+#define	POLL_LADR_LO_VAL_FIX_BASE		0
+
+/*	POLL_LADR_HI		0x0E2C	List Start Address High Register */
+#define	POLL_LADR_HI_MSK		SHIFT0(0xffffffff)	/* List Start Address High */
+#define	POLL_LADR_HI_BASE		0
+
+/*	CPU_ISRC			0x0E30	Interrupt Source Register */
+/*		Bit(s) CPU_ISRC_RSRV_31_13 reserved */
+#define	CPU_ISRC_UART					BIT_12				/* UART  Interrupt */
+#define	CPU_ISRC_SM_CSTO				BIT_11				/* SMBUS CSTO Interrupt */
+#define	CPU_ISRC_FLASH					BIT_10				/* Flash Interrupt */
+#define	CPU_ISRC_USB					BIT_9				/* USB Interrupt */
+#define	CPU_ISRC_PHY					BIT_8				/* PHY Interrupt */
+#define	CPU_ISRC_MAC					BIT_7				/* MAC interrupt */
+#define	CPU_ISRC_TIM2					BIT_6				/* Timer 2 Interrupt */
+#define	CPU_ISRC_CPU					BIT_5				/* CPU Interrupt */
+#define	CPU_ISRC_TIM					BIT_4				/* Timer Interrupt */
+#define	CPU_ISRC_SMB					BIT_3				/* SMBus Interrupt */
+/* ASF Rx Queue Interrupt */
+#define	CPU_ISRC_RX						BIT_2
+/* ASF Tx Queue Interrupt */
+#define	CPU_ISRC_TX						BIT_1
+/* Host Communication Unit Interrupt */
+#define	CPU_ISRC_HCU					BIT_0
+
+/*	CPU_IMSK			0x0E34	Interrupt Mask Register */
+/*		Bit(s) CPU_IMSK_RSRV_31_29 reserved */
+/* UARTInterrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_UART				BIT_28
+/* SMBUS Strech clock time-out Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_SM_CSTO			BIT_27
+/* Flash Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_FLASH				BIT_26
+/* USB Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_USB				BIT_25
+/* PHY Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_PHY				BIT_24
+/* MAC Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_MAC				BIT_23
+/* TIME2 Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_TIM2				BIT_22
+/* CPU Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_CPU				BIT_21
+/* TIM Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_TIM				BIT_20
+/* SMB Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_SMB				BIT_19
+/* RX Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_RX					BIT_18
+/* TX Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_TX					BIT_17
+/* HCU Interrupt Mapped to FIQ */
+#define	CPU_IMSK_FIQ_HCU				BIT_16
+/*		Bit(s) CPU_IMSK_RSRV_15_13 reserved */
+/* UART Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_UART				BIT_12
+/* SMBUS Strech clock time-out Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_SM_CSTO			BIT_11
+/* Flash Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_FLASH				BIT_10
+/* USB Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_USB				BIT_9
+/* PHY Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_PHY				BIT_8
+/* MAC Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_MAC				BIT_7
+/* TIME2 Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_TIM2				BIT_6
+/* CPU Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_CPU				BIT_5
+/* TIM Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_TIM				BIT_4
+/* SMB Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_SMB				BIT_3
+/* RX Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_RX					BIT_2
+/* TX Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_TX					BIT_1
+/* HCU Interrupt Mapped to IRQ */
+#define	CPU_IMSK_IRQ_HCU				BIT_0
+
+/*	SMB_CFG				0x0E40	SMBus Config Register */
+#define	SMB_CFG_PS_MSK			SHIFT30(0x3UL)	/* SMBus Prescaler Bits */
+#define	SMB_CFG_PS_BASE			30
+#define	SMB_CFG_CSE				BIT_29			/* SMBus Clock Stretching Enable */
+#define	SMB_CFG_BR_MSK			SHIFT16(0x1fffUL)	/* SMBus Bit Rate */
+#define	SMB_CFG_BR_BASE			16
+#define	SMB_CFG_SADDR_MSK		SHIFT9(0x7f)	/* SMBus Slave Address */
+#define	SMB_CFG_SADDR_BASE		9
+#define	SMB_CFG_SADDR_ENA		BIT_8			/* SMBus Slave Address Enable */
+/* SMBus Device Default Address Enable */
+#define	SMB_CFG_DADDR_ENA		BIT_7
+/* SMBus General Call Recognition Enable Bit */
+#define	SMB_CFG_GC_ENA			BIT_6
+#define	SMB_CFG_ACK_ENA			BIT_5			/* SMBus Enable Acknowledge */
+#define	SMB_CFG_IRQ_ENA			BIT_4			/* SMBus Interrupt Enable */
+#define	SMB_CFG_OP_ON			BIT_3			/* Operational Mode On */
+#define	SMB_CFG_OP_OFF			BIT_2			/* Operational Mode Off */
+#define	SMB_CFG_RST_CLR			BIT_1			/* SMBus Reset Clear */
+#define	SMB_CFG_RST_SET			BIT_0			/* SMBus Reset Set */
+
+/*	SMB_CSR				0x0E44	SMBus Control/Status Register */
+#define	SMB_CSR_AL					BIT_31			/* Arbitration Lost */
+#define	SMB_CSR_RX_ACK				BIT_30			/* SMBRxACK */
+#define	SMB_CSR_RX_FULL				BIT_29			/* SMBRxFull */
+#define	SMB_CSR_TX_EMPTY			BIT_28			/* SMBTxEmpty */
+#define	SMB_CSR_TX_DONE				BIT_27			/* SMBTxDone */
+#define	SMB_CSR_STOP				BIT_26			/* SMBSTOP */
+#define	SMB_CSR_IF					BIT_25			/* SMBIF */
+#define	SMB_CSR_RX_STRT				BIT_24			/* SMBRxSTA */
+#define	SMB_CSR_TIP					BIT_23			/* SMBTIP */
+#define	SMB_CSR_BUSY				BIT_22			/* SMBBusy */
+#define	SMB_CSR_SPEEDUP				BIT_21			/* SMBUS Timer SpeedUp */
+#define	SMB_CSR_ALERT				BIT_20			/* SMBALERT */
+#define	SMB_CSR_TX_CLR				BIT_19			/* SMBTxCLR */
+#define	SMB_CSR_TX					BIT_18			/* SMBTx */
+#define	SMB_CSR_TX_STOP				BIT_17			/* SMBTxSTO */
+#define	SMB_CSR_TX_STRT				BIT_16			/* SMBTxSTA */
+#define	SMB_CSR_RX_DATA_MSK			SHIFT8(0xff)	/* SMBRxData */
+#define	SMB_CSR_RX_DATA_BASE		8
+#define	SMB_CSR_TX_DATA_MSK			SHIFT0(0xff)	/* SMBTxData */
+#define	SMB_CSR_TX_DATA_BASE		0
+
+/*	CPU_WDOG			0x0E48	Watchdog Register */
+#define	CPU_WDOG_MSK		SHIFT0(0xffffffff)	/* Watchdog Counter */
+#define	CPU_WDOG_BASE		0
+
+/*	CPU_CNTR			0x0E4C	Counter Register */
+#define	CPU_CNTR_MSK		SHIFT0(0xffffffff)	/* Counter */
+#define	CPU_CNTR_BASE		0
+
+/*	CPU_TIM				0x0E50	Timer Compare Register */
+#define	CPU_TIM_MSK			SHIFT0(0xffffffff)	/* Timer Compare */
+#define	CPU_TIM_BASE		0
+
+/*	CPU_TIM_2			0x0E54	Timer Compare Register */
+#define	CPU_TIM_2_MSK		SHIFT0(0xffffffff)	/* Timer2 Compare */
+#define	CPU_TIM_2_BASE		0
+
+/*	CPU_AHB_WDATA		0x0E58	CPU AHB Debug Register */
+/* Probe AHB wdata or AHB Address */
+#define	CPU_AHB_WDATA_MSK		SHIFT0(0xffffffff)
+#define	CPU_AHB_WDATA_BASE		0
+
+/*	CPU_AHB_RDATA		0x0E5C	CPU AHB Debug Register */
+#define	CPU_AHB_RDATA_MSK		SHIFT0(0xffffffff)	/* Probe AHB rdata */
+#define	CPU_AHB_RDATA_BASE		0
+
+/*	HCU_MAP_BASE		0x0E60	Reset Mapping Base */
+/* Reset Mapping Base Address */
+#define	HCU_MAP_BASE_MSK				SHIFT12(0xfffffUL)
+#define	HCU_MAP_BASE_BASE				12
+/*		Bit(s) HCU_MAP_BASE_RSRV_11_0 reserved */
+
+/*	CPU_AHB_CTRL		0x0E64	CPU AHB Debug Register */
+/* Embedded CPU SRAM Write Setting */
+#define	CPU_AHB_CTRL_SRAM_WTC1				BIT_31
+#define	CPU_AHB_CTRL_TDO					BIT_30			/* TDO */
+#define	CPU_AHB_CTRL_TMS					BIT_29			/* TMS */
+#define	CPU_AHB_CTRL_TDI					BIT_28			/* TDI */
+#define	CPU_AHB_CTRL_TRST					BIT_27			/* TRST */
+#define	CPU_AHB_CTRL_TCLK					BIT_26			/* TCLK */
+#define	CPU_AHB_CTRL_SET_JTAG_TEST_MSK		SHIFT24(0x3UL)	/* CPU's JTAG Test Mode */
+#define	CPU_AHB_CTRL_SET_JTAG_TEST_BASE		24
+/* Embedded CPU SRAM Read Setting */
+#define	CPU_AHB_CTRL_SRAM_RTC1				BIT_23
+/* Embedded CPU SRAM Write Setting */
+#define	CPU_AHB_CTRL_SRAM_WTC2_MSK			SHIFT21(0x3UL)
+#define	CPU_AHB_CTRL_SRAM_WTC2_BASE			21
+/* Switch AHB Dump Data and Address */
+#define	CPU_AHB_CTRL_SW_DUMP				BIT_20
+#define	CPU_AHB_CTRL_FCE_HRESP_MSK			SHIFT18(0x3UL)	/* Force AHB HRESP */
+#define	CPU_AHB_CTRL_FCE_HRESP_BASE			18
+#define	CPU_AHB_CTRL_FCE_HRDY				BIT_17			/* Force AHB HREADY */
+/* Enable Force AHB Response */
+#define	CPU_AHB_CTRL_FCE_RESP_EN			BIT_16
+/* Embedded CPU SRAM Read Setting */
+#define	CPU_AHB_CTRL_SRAM_RTC2_MSK			SHIFT14(0x3)
+#define	CPU_AHB_CTRL_SRAM_RTC2_BASE			14
+/*		Bit(s) CPU_AHB_CTRL_RSRV_13 reserved */
+#define	CPU_AHB_CTRL_PRB_HBURST_MSK			SHIFT10(0x7)	/* Probe AHB HBURST */
+#define	CPU_AHB_CTRL_PRB_HBURST_BASE		10
+#define	CPU_AHB_CTRL_PRB_HSIZE_MSK			SHIFT7(0x7)		/* Probe AHB HSIZE */
+#define	CPU_AHB_CTRL_PRB_HSIZE_BASE			7
+#define	CPU_AHB_CTRL_PRB_HTRANS_MSK			SHIFT5(0x3)		/* Probe AHB HTRANS */
+#define	CPU_AHB_CTRL_PRB_HTRANS_BASE		5
+#define	CPU_AHB_CTRL_PRB_HBUSREQ			BIT_4			/* Probe AHB HBUSREQ */
+#define	CPU_AHB_CTRL_PRB_HRESP_MSK			SHIFT2(0x3)		/* Probe AHB HRESP */
+#define	CPU_AHB_CTRL_PRB_HRESP_BASE			2
+#define	CPU_AHB_CTRL_PRB_HRDY				BIT_1			/* Probe AHB HREADY */
+#define	CPU_AHB_CTRL_PRB_HCLK				BIT_0			/* Probe AHB HCLK */
+
+/*	HCU_CCSR			0x0E68	CPU Control and Status Register */
+/* AHB SRAM Bridge Switch */
+#define	HCU_CCSR_AHB_BRIDGE_SWITCH_MSK		SHIFT30(0x3UL)
+#define	HCU_CCSR_AHB_BRIDGE_SWITCH_BASE		30
+/* USB AHB Bridge Switch */
+#define	HCU_CCSR_USB_BRIDGE_SWITCH_MSK		SHIFT28(0x3UL)
+#define	HCU_CCSR_USB_BRIDGE_SWITCH_BASE		28
+#define	HCU_CCSR_SMBALERT_MONITOR			BIT_27			/* SMBALERT Pin Monitor */
+#define	HCU_CCSR_CPU_SLEEP					BIT_26			/* CPU Sleep Status */
+/* Clock Stretching Timeout */
+#define	HCU_CCSR_CS_TO						BIT_25
+#define	HCU_CCSR_WDOG						BIT_24			/* Watchdog Reset */
+/* Switch AHB Dump Data and Address */
+#define	HCU_CCSR_SW_DUMP					BIT_23
+/*		Bit(s) HCU_CCSR_RSRV_22_19 reserved */
+/* Select FCU Clock Frequency */
+#define	HCU_CCSR_FCU_CLK_SEL				BIT_18
+#define	HCU_CCSR_CLR_IRQ_HOST				BIT_17			/* Clear IRQ_HOST */
+#define	HCU_CCSR_SET_IRQ_HCU				BIT_16			/* Set IRQ_HCU */
+/*		Bit(s) HCU_CCSR_RSRV_15_12 reserved */
+#define	HCU_CCSR_ARM_MRVL_ID				BIT_11			/* Enable ARM MRVL ID */
+/* Enable ARM ITCM after CPU Reset */
+#define	HCU_CCSR_EN_ARM_ITCM				BIT_10
+#define	HCU_CCSR_AHB_RST					BIT_9			/* Reset AHB Bridge */
+/* CPU Reset Mode when Watchdog Expired */
+#define	HCU_CCSR_CPU_RST_MODE				BIT_8
+/* Enable flash controller clock */
+#define	HCU_CCSR_FLASH_CLK_EN_MSK			SHIFT6(0x3)
+#define	HCU_CCSR_FLASH_CLK_EN_BASE			6
+/* Enable Sync Datapath inside AHB Bridge */
+#define	HCU_CCSR_SET_SYNC_CPU				BIT_5
+/* Enable CPU Clock Divide */
+#define	HCU_CCSR_CPU_CLK_DIVIDE_MSK			SHIFT3(0x3)
+#define	HCU_CCSR_CPU_CLK_DIVIDE_BASE		3
+#define	HCU_CCSR_OS_PRSNT					BIT_2			/* ASF OS Present */
+/* Microcontroller State of CPU Subsystem */
+#define	HCU_CCSR_UC_STATE_MSK				SHIFT0(0x3)
+#define	HCU_CCSR_UC_STATE_BASE				0
+#define HCU_CCSR_ASF_RUNNING				BIT_0
+#define HCU_CCSR_ASF_HALTED					BIT_1
+#define HCU_CCSR_ASF_RESET					0
+
+/*	HCU_HCSR			0x0E6C	Host Control and Status Register */
+/* CPU Release Timer after Watchdog Expired */
+#define	HCU_HCSR_CPU_RST_WDOG_TIMER_MSK			SHIFT24(0xffUL)
+#define	HCU_HCSR_CPU_RST_WDOG_TIMER_BASE		24
+/*		Bit(s) HCU_HCSR_RSRV_23_17 reserved */
+#define	HCU_HCSR_SET_IRQ_CPU					BIT_16			/* Set IRQ_CPU */
+/*		Bit(s) HCU_HCSR_RSRV_15_2 reserved */
+#define	HCU_HCSR_CLR_IRQ_HCU					BIT_1			/* Clear IRQ_HCU */
+#define	HCU_HCSR_SET_IRQ_HOST					BIT_0			/* Set IRQ_HOST */
+
+/*	HCU_DATA1			0x0E70	Data Register 1 */
+#define	HCU_DATA1_MSK		SHIFT0(0xffffffff)	/* DATA1 */
+#define	HCU_DATA1_BASE		0
+
+/*	HCU_DATA2			0x0E74	Data Register 2 */
+#define	HCU_DATA2_MSK		SHIFT0(0xffffffff)	/* DATA2 */
+#define	HCU_DATA2_BASE		0
+
+/*	HCU_DATA3			0x0E78	Data Register 3 */
+#define	HCU_DATA3_MSK		SHIFT0(0xffffffff)	/* DATA3 */
+#define	HCU_DATA3_BASE		0
+
+/*	HCU_DATA4			0x0E7C	Data Register 4 */
+#define	HCU_DATA4_MSK		SHIFT0(0xffffffff)	/* DATA4 */
+#define	HCU_DATA4_BASE		0
+
+/*	STAT_CTRL			0x0E80	Status BMU Control Register */
+/*		Bit(s) STAT_CTRL_RSRV_31_19 reserved */
+/* Master Request Loopback Test On */
+#define	STAT_CTRL_MST_REQ_LPBK_ON		BIT_18
+/* Master Request Loopback Test Off */
+#define	STAT_CTRL_MST_REQ_LPBK_OFF		BIT_17
+/* Master Request Loopback Step */
+#define	STAT_CTRL_MST_REQ_LPBK_STEP		BIT_16
+/*		Bit(s) STAT_CTRL_RSRV_15 reserved */
+/* FIFO Read Pointer Test On */
+#define	STAT_CTRL_RPTR_TEST_ON			BIT_14
+/* FIFO Read Pointer Test Off */
+#define	STAT_CTRL_RPTR_TEST_OFF			BIT_13
+#define	STAT_CTRL_RPTR_TEST_STEP		BIT_12			/* FIFO Read Pointer Step */
+/*		Bit(s) STAT_CTRL_RSRV_11 reserved */
+/* FIFO Write Pointer Test On */
+#define	STAT_CTRL_WPTR_TEST_ON			BIT_10
+/* FIFO Write Pointer Test Off */
+#define	STAT_CTRL_WPTR_TEST_OFF			BIT_9
+#define	STAT_CTRL_WPTR_TEST_STEP		BIT_8			/* FIFO Write Pointer Step */
+/*		Bit(s) STAT_CTRL_RSRV_7_5 reserved */
+#define	STAT_CTRL_CLR_IRQ_STAT			BIT_4			/* Clear IRQ Status BMU */
+#define	STAT_CTRL_OP_ON					BIT_3			/* Operational On */
+#define	STAT_CTRL_OP_OFF				BIT_2			/* Operational Off */
+#define	STAT_CTRL_ENA					BIT_1			/* Enable */
+#define	STAT_CTRL_RST					BIT_0			/* Reset */
+
+/*	STAT_LAST_IDX		0x0E84	Last Index Register */
+/*		Bit(s) STAT_LAST_IDX_RSRV_31_12 reserved */
+#define	STAT_LAST_IDX_MSK					SHIFT2(0x3ff)		/* Last Index */
+#define	STAT_LAST_IDX_BASE					2
+#define	STAT_LAST_IDX_VAL_FIX_MSK			SHIFT0(0x3)			/* Last Index Fix */
+#define	STAT_LAST_IDX_VAL_FIX_BASE			0
+
+/*	STAT_LADR_LO		0x0E88	List Start Address Lower Register */
+/* List Start Address Lo */
+#define	STAT_LADR_LO_MSK				SHIFT5(0x7ffffff)
+#define	STAT_LADR_LO_BASE				5
+/* List Start Address Lo Fix */
+#define	STAT_LADR_LO_VAL_FIX_MSK		SHIFT0(0x1f)
+#define	STAT_LADR_LO_VAL_FIX_BASE		0
+
+/*	STAT_LADR_HI		0x0E8C	List Start Address Upper Register */
+#define	STAT_LADR_HI_MSK		SHIFT0(0xffffffff)	/* List Start Address Hi */
+#define	STAT_LADR_HI_BASE		0
+
+/*	STAT_TXA_REP		0x0E90	TXA Report Index Register */
+/*		Bit(s) STAT_TXA_REP_RSRV_15_12 reserved */
+#define	STAT_TXA_REP_MSK					SHIFT0(0xfffU)	/* TXA Report Index */
+#define	STAT_TXA_REP_BASE					0
+
+/*	STAT_TXTH			0x0E98	TX Index Threshold Register */
+/*		Bit(s) STAT_TXTH_RSRV_15_12 reserved */
+#define	STAT_TXTH_MSK					SHIFT0(0xfffU)	/* TX Index Threshold */
+#define	STAT_TXTH_BASE					0
+
+/*	STAT_PUT			0x0E9C	Put Index Register */
+/*		Bit(s) STAT_PUT_RSRV_31_12 reserved */
+#define	STAT_PUT_MSK					SHIFT0(0xfff)		/* Put Index */
+#define	STAT_PUT_BASE					0
+
+/*	STAT_FIFO_WPTR		0x0EA0	FIFO Write Pointer Register */
+/*		Bit(s) STAT_FIFO_WPTR_RSRV_31_5 reserved */
+/* FIFO Write Pointer */
+#define	STAT_FIFO_WPTR_MSK					SHIFT0(0x1f)
+#define	STAT_FIFO_WPTR_BASE					0
+
+/*	STAT_FIFO_RPTR		0x0EA4	FIFO Read Pointer Register */
+/*		Bit(s) STAT_FIFO_RPTR_RSRV_31_21 reserved */
+#define	STAT_FIFO_RPTR_WSPTR_MSK			SHIFT16(0x1fUL)	/* FIFO Rd Shadow Ptr */
+#define	STAT_FIFO_RPTR_WSPTR_BASE			16
+/*		Bit(s) STAT_FIFO_RPTR_RSRV_15_5 reserved */
+#define	STAT_FIFO_RPTR_MSK					SHIFT0(0x1f)	/* FIFO Read Pointer */
+#define	STAT_FIFO_RPTR_BASE					0
+
+/*	STAT_FIFO_LEV		0x0EA8	FIFO Level Register */
+/*		Bit(s) STAT_FIFO_LEV_RSRV_31_21 reserved */
+#define	STAT_FIFO_LEV_SLEV_MSK				SHIFT16(0x1fUL)	/* FIFO Shadow Level */
+#define	STAT_FIFO_LEV_SLEV_BASE				16
+/*		Bit(s) STAT_FIFO_LEV_RSRV_15_5 reserved */
+#define	STAT_FIFO_LEV_MSK					SHIFT0(0x1f)	/* FIFO Level */
+#define	STAT_FIFO_LEV_BASE					0
+
+/*	STAT_FIFO_WM		0x0EAC	FIFO Watermark Register */
+/*		Bit(s) STAT_FIFO_WM_RSRV_7_5 reserved */
+#define	STAT_FIFO_WM_MSK				SHIFT0(0x1fU)	/* FIFO Watermark */
+#define	STAT_FIFO_WM_BASE				0
+
+/*	STAT_FIFO_WM_ISR	0x0EAD	FIFO ISR Watermark Register */
+/*		Bit(s) STAT_FIFO_WM_ISR_RSRV_7_5 reserved */
+#define	STAT_FIFO_WM_ISR_MSK				SHIFT0(0x1fU)	/* FIFO ISR Watermark */
+#define	STAT_FIFO_WM_ISR_BASE				0
+
+/*	LEV_TIM_INIT		0x0EB0	Level Timer Init Value Register */
+#define	LEV_TIM_INIT_MSK		SHIFT0(0xffffffff)	/* Level Timer Init Value */
+#define	LEV_TIM_INIT_BASE		0
+
+/*	LEV_TIM_CNT			0x0EB4	Level Timer Counter Register */
+#define	LEV_TIM_CNT_MSK			SHIFT0(0xffffffff)	/* Level Timer */
+#define	LEV_TIM_CNT_BASE		0
+
+/*	LEV_TIM_TCTL		0x0EB8	Level Timer Control/Test Register */
+/*		Bit(s) LEV_TIM_TCTL_RSRV_31_11 reserved */
+/* Level Timer Test On */
+#define	LEV_TIM_TCTL_TST_ON					BIT_10
+/* Level Timer Test Off */
+#define	LEV_TIM_TCTL_TST_OFF				BIT_9
+#define	LEV_TIM_TCTL_STEP					BIT_8				/* Level Timer Step */
+/*		Bit(s) LEV_TIM_TCTL_RSRV_7_6 reserved */
+/* Deviation 5.4 fix enable */
+#define	LEV_TIM_TCTL_ON						BIT_5
+/* Deviation 5.4 fix enable */
+#define	LEV_TIM_TCTL_OFF					BIT_4
+/*		Bit(s) LEV_TIM_TCTL_RSRV_3 reserved */
+/* Level Timer Start */
+#define	LEV_TIM_TCTL_STRT					BIT_2
+#define	LEV_TIM_TCTL_STOP					BIT_1				/* Level Timer Stop */
+/*		Bit(s) LEV_TIM_TCTL_RSRV_0 reserved */
+
+/*	TX_TIM_INIT			0x0EC0	TX TImer Init Value Register */
+#define	TX_TIM_INIT_MSK			SHIFT0(0xffffffff)	/* TX Timer Init Value */
+#define	TX_TIM_INIT_BASE		0
+
+/*	TX_TIM_CNT			0x0EC4	TX Timer Counter Register */
+#define	TX_TIM_CNT_MSK		SHIFT0(0xffffffff)	/* TX Timer */
+#define	TX_TIM_CNT_BASE		0
+
+/*	TX_TIM_TCTL			0x0EC8	TX Timer Control/Test Register */
+/*		Bit(s) TX_TIM_TCTL_RSRV_31_11 reserved */
+#define	TX_TIM_TCTL_TST_ON				BIT_10				/* TX Timer Test On */
+#define	TX_TIM_TCTL_TST_OFF				BIT_9				/* TX Timer Test Off */
+#define	TX_TIM_TCTL_STEP				BIT_8				/* TX Timer Step */
+/*		Bit(s) TX_TIM_TCTL_RSRV_7_6 reserved */
+/* Deviation 5.4 fix enable */
+#define	TX_TIM_TCTL_ON					BIT_5
+/* Deviation 5.4 fix enable */
+#define	TX_TIM_TCTL_OFF					BIT_4
+/*		Bit(s) TX_TIM_TCTL_RSRV_3 reserved */
+#define	TX_TIM_TCTL_STRT				BIT_2				/* TX Timer Start */
+#define	TX_TIM_TCTL_STOP				BIT_1				/* TX Timer Stop */
+/*		Bit(s) TX_TIM_TCTL_RSRV_0 reserved */
+
+/*	ISR_TIM_INIT		0x0ED0	ISR Timer Init Value Register */
+#define	ISR_TIM_INIT_MSK		SHIFT0(0xffffffff)	/* ISR Timer Init Value */
+#define	ISR_TIM_INIT_BASE		0
+
+/*	ISR_TIM_CNT			0x0ED4	ISR Timer Counter Register */
+#define	ISR_TIM_CNT_MSK			SHIFT0(0xffffffff)	/* ISR Timer */
+#define	ISR_TIM_CNT_BASE		0
+
+/*	ISR_TIM_TCTL		0x0ED8	ISR Timer Control/Test Register */
+/*		Bit(s) ISR_TIM_TCTL_RSRV_31_11 reserved */
+/* ISR Timer Test On */
+#define	ISR_TIM_TCTL_TST_ON					BIT_10
+/* ISR Timer Test Off */
+#define	ISR_TIM_TCTL_TST_OFF				BIT_9
+#define	ISR_TIM_TCTL_STEP					BIT_8				/* ISR Timer Step */
+/*		Bit(s) ISR_TIM_TCTL_RSRV_7_6 reserved */
+/* Deviation 5.4 fix enable */
+#define	ISR_TIM_TCTL_ON						BIT_5
+/* Deviation 5.4 fix enable */
+#define	ISR_TIM_TCTL_OFF					BIT_4
+/*		Bit(s) ISR_TIM_TCTL_RSRV_3 reserved */
+#define	ISR_TIM_TCTL_STRT					BIT_2				/* ISR Timer Start */
+#define	ISR_TIM_TCTL_STOP					BIT_1				/* ISR Timer Stop */
+/*		Bit(s) ISR_TIM_TCTL_RSRV_0 reserved */
+
+/*  STAT_TX_REP               0x0EE0  TX ODD/EVEN Report Index Register */
+/*      Bit(s) STAT_TX_REP_RSRV_31_28 reserved */
+/* TX EVEN Report Index */
+#define STAT_TX_REP_EVEN_REPORT_INDEX_MSK      SHIFT16(0xfffUL)
+#define STAT_TX_REP_EVEN_REPORT_INDEX_BASE     16
+/*      Bit(s) STAT_TX56_REP_RSRV_15_12 reserved */
+/* TX ODD Report Index */
+#define STAT_TX_REP_ODD_REPORT_INDEX_MSK      SHIFT0(0xfff)
+#define STAT_TX_REP_ODD_REPORT_INDEX_BASE     0
+
+/*	MAC_CTRL			0x0F00	MAC Control Registers */
+#define MAC_CTRL_PD_PWRDN_CLK50_A       BIT_31          /* Power Down CLK50 */
+#define MAC_CTRL_GIG_CLASS_SEL_S        BIT_30          /* Gig Class Selection */
+#define MAC_CTRL_PD_CONFIG_REFCLK_A     BIT_29          /* Configure Ref Clk Source */
+#define MAC_CTRL_PD_FIFO_DEEP_MSK       SHIFT27(0x3UL)    /* FIFO Deep Default */
+#define MAC_CTRL_PD_FIFO_DEEP_BASE      27              /* FIFO Deep Default */
+#define MAC_CTRL_PD_CFG_ASM_PAUSE_A     BIT_26          /* Configure ASM Pause */
+#define MAC_CTRL_PD_ANEG_NOW_A          BIT_25          /* Restart Autoneg Now */
+#define MAC_CTRL_PS_A1000_DIS_S         BIT_24          /* Disable Gigabit */
+#define MAC_CTRL_PD_REV_ANEG_A          BIT_23          /* Reverse Autoneg */
+#define MAC_CTRL_PM_DOING_GIGABIT_S     BIT_18          /* Power Up Gigabit Circuit */
+#define MAC_CTRL_PM_SENSE_S             BIT_17          /* Energy Detect PHY Sensing */
+#define MAC_CTRL_TX_FRD_REG_EN_R        BIT_16          /* Transmit Latency Timing Point */
+
+#define	MAC_CTRL_MAC_SEC_RST			BIT_15S			/* MACsec RST */
+#define	MAC_CTRL_MAC_SEC_RST_OFF		BIT_14S			/* MAC SEC RSt OFF */
+#define	MAC_CTRL_BYP_MACSECRX_ON		BIT_13S			/* Bypass MACsec RX */
+#define	MAC_CTRL_BYP_MACSECRX_OFF		BIT_12S			/* Bypass MACsec RX Off */
+#define	MAC_CTRL_BYP_MACSECTX_ON		BIT_11S			/* Bypass MACsec TX */
+#define	MAC_CTRL_BYP_MACSECTX_OFF		BIT_10S			/* Bypass MACsec TX Off */
+#define	MAC_CTRL_BYP_RETR_ON			BIT_9S			/* Bypass Retransmit FIFO */
+/* Bypass Retransmit FIFO Off */
+#define	MAC_CTRL_BYP_RETR_OFF			BIT_8S
+#define	MAC_CTRL_BURST_ON				BIT_7S			/* En Burstmode On */
+#define	MAC_CTRL_BURST_OFF				BIT_6S			/* En Burstmode Off */
+#define	MAC_CTRL_LPBK_ON				BIT_5S			/* Loopback On */
+#define	MAC_CTRL_LPBK_OFF				BIT_4S			/* Loopback Off */
+#define	MAC_CTRL_PAUSE_ON				BIT_3S			/* En Pause On */
+#define	MAC_CTRL_PAUSE_OFF				BIT_2S			/* En Pause Off */
+#define	MAC_CTRL_RST_CLR				BIT_1S			/* GMAC Reset Clear */
+#define	MAC_CTRL_RST_SET				BIT_0S			/* GMAC Reset Set */
+
+/*	PHY_CFG				0x0F04	PHY Config Register, loaded from external
+ *								memory
+ */
+#define	PHY_CFG_STAT_MSK				SHIFT24(0xffUL)	/* PHY Status */
+#define	PHY_CFG_STAT_BASE				24
+/* Internal Regulator 2.5 Power Down Enable */
+#define	PHY_CFG_INT_REG_PD_ENA			BIT_23
+#define	PHY_CFG_TEST					BIT_22			/* Testmode */
+#define	PHY_CFG_REG18_PD				BIT_21			/* Reg18 Power Down */
+#define	PHY_CFG_REG12_SEL_MSK			SHIFT19(0x3UL)	/* Reg12 Sel */
+#define	PHY_CFG_REG12_SEL_BASE			19
+#define	PHY_CFG_REG18_SEL_MSK			SHIFT17(0x3UL)	/* Reg18 Sel */
+#define	PHY_CFG_REG18_SEL_BASE			17
+#define	PHY_CFG_SPI_LOCK				BIT_16			/* SPI Lock */
+
+/* Yukon-Supreme */
+/* #define	PHY_CFG_PHY_LED_CFG_MSK			SHIFT14(0x3)	* GPHY Config for LED Mux * */
+/* #define	PHY_CFG_PHY_LED_CFG_BASE		14 */
+/* GPHY Config for Int Polarity */
+#define	PHY_CFG_PHY_INT_POL				BIT_13
+/* GPHY Config for Energy Detect */
+#define	PHY_CFG_PHY_EDET				BIT_12
+#define	PHY_CFG_PHY_1000HD				BIT_11			/* GPHY Config for 1000M/HD */
+/* GPHY Config for Master/Slave */
+#define	PHY_CFG_PHY_MS					BIT_10
+/* GPHY Config for Pause Enable */
+#define	PHY_CFG_PHY_PAUSE_EN			BIT_9
+
+/* Yukon-Extreme */
+/* #define	PHY_CFG_PHY_LED_CFG_MSK			SHIFT6(0x7)		* GPHY LED Config * */
+/* #define	PHY_CFG_PHY_LED_CFG_BASE		6 */
+/*		Bit(s) PHY_CFG_RSRV_5_2 reserved */
+#define	PHY_CFG_RST_CLR					BIT_1			/* PHY Reset Clear */
+#define	PHY_CFG_RST_SET					BIT_0			/* PHY Reset Set */
+
+/* Yukon-Supreme */
+#define	PHY_CFG_REG25_SEL_MSK			SHIFT17(0x3UL)	/* Reg25 Sel */
+#define	PHY_CFG_REG25_SEL_BASE			17
+
+/* Yukon-FE+ */
+/* #define	PHY_CFG_PHY_LED_CFG_MSK			SHIFT11(0x7)	* PHY LED CONFIG * */
+/* #define	PHY_CFG_PHY_ENA_EDET			BIT_10			* PHY enable energydetect * */
+#define	PHY_CFG_PHY_ENA_XC				BIT_9			/* PHY enable cross-copper */
+#define	PHY_CFG_PHY_ANEG_CFG_MSK		SHIFT6(0x7)		/* PHY aneg mode */
+
+/*	MAC_ISRC			0x0F08	MAC Interrupt Source Register */
+/*		Bit(s) MAC_ISRC_RSRV_31_6 reserved */
+/* Receive Counter Overflow Interrupt */
+#define	MAC_ISRC_RX_CNT_OF			BIT_5
+/* Transmit Counter Overflow Interrupt */
+#define	MAC_ISRC_TX_CNT_OF			BIT_4
+#define	MAC_ISRC_TX_UR				BIT_3				/* Transmit FIFO Underrun */
+/* Frame Transmission Complete */
+#define	MAC_ISRC_TX_OK				BIT_2
+#define	MAC_ISRC_RX_OF				BIT_1				/* Receive FIFO Overrun */
+#define	MAC_ISRC_RX_OK				BIT_0				/* Frame Reception Complete */
+
+/*	MAC_IMSK			0x0F0C	MAC Interrupt Mask Register */
+/*		Bit(s) MAC_IMSK_RSRV_31_6 reserved */
+/* En IRQ Receive Counter Overflow Interrupt */
+#define	MAC_IMSK_RX_CNT_OF			BIT_5
+/* En IRQ Transmit Counter Overflow Interrupt */
+#define	MAC_IMSK_TX_CNT_OF			BIT_4
+/* En IRQ Transmit FIFO Underrun */
+#define	MAC_IMSK_TX_UR				BIT_3
+/* En IRQ Frame Transmission Complete */
+#define	MAC_IMSK_TX_OK				BIT_2
+/* En IRQ Receive FIFO Overrun */
+#define	MAC_IMSK_RX_OF				BIT_1
+/* En IRQ Frame Reception Complete */
+#define	MAC_IMSK_RX_OK				BIT_0
+
+/*	LINK_CTRL			0x0F10	Link Control Register */
+/*		Bit(s) LINK_CTRL_RSRV_15_2 reserved */
+#define MAC_CTRL_AVB_MODE_ON            BIT_3S          /* Enable AVB Mode */
+#define MAC_CTRL_AVB_MODE_OFF           BIT_2S          /* Disable AVB Mode */
+#define	LINK_CTRL_RST_CLR				BIT_1S			/* Link Reset Clear */
+#define	LINK_CTRL_RST_SET				BIT_0S			/* Link Reset Set */
+
+/*	WOL_CSR				0x0F20	WOL Control/Status Register */
+#define	WOL_CSR_LC_STAT			BIT_15S	/* Link Up Status */
+#define	WOL_CSR_MP_STAT			BIT_14S	/* Magic Pattern Status */
+#define	WOL_CSR_WF_STAT			BIT_13S	/* Wake up Frame Status */
+#define	WOL_CSR_CLR_RSLT		BIT_12S	/* Clear Match Result */
+#define	WOL_CSR_LC_PME_ENA		BIT_11S	/* Enable PME on Link Up */
+#define	WOL_CSR_LC_PME_DIS		BIT_10S	/* Disable PME on Link Up */
+#define	WOL_CSR_MP_PME_ENA		BIT_9S	/* Enable PME on Magic Pattern */
+#define	WOL_CSR_MP_PME_DIS		BIT_8S	/* Disable PME on Magic Pattern */
+#define	WOL_CSR_WF_PME_ENA		BIT_7S	/* Enable PME on Wake up Frame */
+#define	WOL_CSR_WF_PME_DIS		BIT_6S	/* Disable PME on Wake up Frame */
+#define	WOL_CSR_LC_ENA			BIT_5S	/* Enable Link Up Unit */
+#define	WOL_CSR_LC_DIS			BIT_4S	/* Disable Link Up Unit */
+#define	WOL_CSR_MP_ENA			BIT_3S	/* Enable Magic Pattern Unit */
+#define	WOL_CSR_MP_DIS			BIT_2S	/* Disable Magic Pattern Unit */
+#define	WOL_CSR_WF_ENA			BIT_1S	/* Enable Pattern Match Unit */
+#define	WOL_CSR_WF_DIS			BIT_0S	/* Disable Pattern Match Unit */
+
+/*	WOL_MCTRL			0x0F22	Match Control Register */
+/*		Bit(s) WOL_MCTRL_RSRV_15_14 reserved */
+#define WOL_MCTRL_P13_ENA           BIT_13S         /* Pattern 13 Enable */
+#define WOL_MCTRL_P12_ENA           BIT_12S         /* Pattern 12 Enable */
+#define WOL_MCTRL_P11_ENA           BIT_11S         /* Pattern 11 Enable */
+#define WOL_MCTRL_P10 ENA           BIT_10S         /* Pattern 10 Enable */
+#define WOL_MCTRL_P9_ENA            BIT_9S          /* Pattern 9 Enable */
+#define	WOL_MCTRL_P8_ENA			BIT_8S			/* Pattern 8 Enable */
+#define	WOL_MCTRL_P7_ENA			BIT_7S			/* Pattern 7 Enable */
+#define	WOL_MCTRL_P6_ENA			BIT_6S			/* Pattern 6 Enable */
+#define	WOL_MCTRL_P5_ENA			BIT_5S			/* Pattern 5 Enable */
+#define	WOL_MCTRL_P4_ENA			BIT_4S			/* Pattern 4 Enable */
+#define	WOL_MCTRL_P3_ENA			BIT_3S			/* Pattern 3 Enable */
+#define	WOL_MCTRL_P2_ENA			BIT_2S			/* Pattern 2 Enable */
+#define	WOL_MCTRL_P1_ENA			BIT_1S			/* Pattern 1 Enable */
+#define	WOL_MCTRL_P0_ENA			BIT_0S			/* Pattern 0 Enable */
+
+/*	WOL_MADDR_LO		0x0F24	MAC Address Register Low Register */
+#define	WOL_MADDR_LO_MAC_3_MSK		SHIFT24(0xffUL)	/* MAC<3> */
+#define	WOL_MADDR_LO_MAC_3_BASE		24
+#define	WOL_MADDR_LO_MAC_2_MSK		SHIFT16(0xffUL)	/* MAC<2> */
+#define	WOL_MADDR_LO_MAC_2_BASE		16
+#define	WOL_MADDR_LO_MAC_1_MSK		SHIFT8(0xff)	/* MAC<1> */
+#define	WOL_MADDR_LO_MAC_1_BASE		8
+#define	WOL_MADDR_LO_MAC_0_MSK		SHIFT0(0xff)	/* MAC<0> */
+#define	WOL_MADDR_LO_MAC_0_BASE		0
+
+/*	WOL_MADDR_HI		0x0F28	MAC Address Register High Register */
+#define	WOL_MADDR_HI_MAC_5_MSK		SHIFT8(0xffU)	/* MAC<5> */
+#define	WOL_MADDR_HI_MAC_5_BASE		8
+#define	WOL_MADDR_HI_MAC_4_MSK		SHIFT0(0xffU)	/* MAC<4> */
+#define	WOL_MADDR_HI_MAC_4_BASE		0
+
+/*	WOL_PME_MEN			0x0F2A	PME Match Enable Register */
+#define	WOL_PME_MEN_FRC_PME				BIT_15S			/* Force PME */
+/*		Bit(s) WOL_PME_MEN_RSRV_14 reserved */
+#define WOL_PME_MEN_P13_PME_ENA         BIT_13S         /* PME 13 Enable */
+#define WOL_PME_MEM_P12_PME_ENA         BIT_12S         /* PME 12 Enable */
+#define WOL_PME_MEM_P11_PME_ENA         BIT_11S         /* PME 11 Enable */
+#define WOL_PME_MEM_P10_PME_ENA         BIT_10S         /* PME 10 Enable */
+#define WOL_PME_MEM_P9_PME_ENA          BIT_9S          /* PME 9 Enable */
+#define	WOL_PME_MEN_P8_PME_ENA			BIT_8S			/* PME 8 Enable */
+#define	WOL_PME_MEN_P7_PME_ENA			BIT_7S			/* PME 7 Enable */
+#define	WOL_PME_MEN_P6_PME_ENA			BIT_6S			/* PME 6 Enable */
+#define	WOL_PME_MEN_P5_PME_ENA			BIT_5S			/* PME 5 Enable */
+#define	WOL_PME_MEN_P4_PME_ENA			BIT_4S			/* PME 4 Enable */
+#define	WOL_PME_MEN_P3_PME_ENA			BIT_3S			/* PME 3 Enable */
+#define	WOL_PME_MEN_P2_PME_ENA			BIT_2S			/* PME 2 Enable */
+#define	WOL_PME_MEN_P1_PME_ENA			BIT_1S			/* PME 1 Enable */
+#define	WOL_PME_MEN_P0_PME_ENA			BIT_0S			/* PME 0 Enable */
+
+/*	WOL_ASF_MEN			0x0F2C	ASF Match Enable Register */
+/*		Bit(s) WOL_ASF_MEN_RSRV_15_14 reserved */
+#define WOL_ASF_MEM_P13_ASF_ENA         BIT_13S         /* ASF 13 Eanble */
+#define WOL_ASF_MEM_P12_ASF_ENA         BIT_12S         /* ASF 12 Enable */
+#define WOL_ASF_MEM_P11_ASF_ENA         BIT_11S         /* ASF 11 Enable */
+#define WOL_ASF_MEM_P9_ASF_ENA          BIT_9S          /* ASF 9 Enabel */
+#define	WOL_ASF_MEN_P8_ASF_ENA			BIT_8S			/* ASF 8 Enable */
+#define	WOL_ASF_MEN_P7_ASF_ENA			BIT_7S			/* ASF 7 Enable */
+#define	WOL_ASF_MEN_P6_ASF_ENA			BIT_6S			/* ASF 6 Enable */
+#define	WOL_ASF_MEN_P5_ASF_ENA			BIT_5S			/* ASF 5 Enable */
+#define	WOL_ASF_MEN_P4_ASF_ENA			BIT_4S			/* ASF 4 Enable */
+#define	WOL_ASF_MEN_P3_ASF_ENA			BIT_3S			/* ASF 3 Enable */
+#define	WOL_ASF_MEN_P2_ASF_ENA			BIT_2S			/* ASF 2 Enable */
+#define	WOL_ASF_MEN_P1_ASF_ENA			BIT_1S			/* ASF 1 Enable */
+#define	WOL_ASF_MEN_P0_ASF_ENA			BIT_0S			/* ASF 0 Enable */
+
+/*	WOL_MRSL			0x0F2E	Match Result Register */
+/*		Bit(s) WOL_MRSL_RSRV_15_14 reserved */
+#define WOL_MRSL_P13_MATCH          BIT_13S         /* Pattern 13 Match */
+#define WOL_MRSL_P12_MATCH          BIT_12S         /* Pattern 12 Match */
+#define WOL_MRSL_P11_MATCH          BIT_11S         /* Pattern 11 Match */
+#define WOL_MRSL_P9_MATCH           BIT_9S          /* Pattern 9 Match */
+#define	WOL_MRSL_P8_MATCH			BIT_8S			/* Pattern 8 Match */
+#define	WOL_MRSL_P7_MATCH			BIT_7S			/* Pattern 7 Match */
+#define	WOL_MRSL_P6_MATCH			BIT_6S			/* Pattern 6 Match */
+#define	WOL_MRSL_P5_MATCH			BIT_5S			/* Pattern 5 Match */
+#define	WOL_MRSL_P4_MATCH			BIT_4S			/* Pattern 4 Match */
+#define	WOL_MRSL_P3_MATCH			BIT_3S			/* Pattern 3 Match */
+#define	WOL_MRSL_P2_MATCH			BIT_2S			/* Pattern 2 Match */
+#define	WOL_MRSL_P1_MATCH			BIT_1S			/* Pattern 1 Match */
+#define	WOL_MRSL_P0_MATCH			BIT_0S			/* Pattern 0 Match */
+
+/*	WOL_PLEN0			0x0F30	Pattern Length Register 0 (0-3) */
+/*		Bit(s) WOL_PLEN0_RSRV_31 reserved */
+#define	WOL_PLEN0_P3_LEN_MSK		SHIFT24(0x7fUL)	/* Pattern 3 Length */
+#define	WOL_PLEN0_P3_LEN_BASE		24
+/*		Bit(s) WOL_PLEN0_RSRV_23 reserved */
+#define	WOL_PLEN0_P2_LEN_MSK		SHIFT16(0x7fUL)	/* Pattern 2 Length */
+#define	WOL_PLEN0_P2_LEN_BASE		16
+/*		Bit(s) WOL_PLEN0_RSRV_15 reserved */
+#define	WOL_PLEN0_P1_LEN_MSK		SHIFT8(0x7f)	/* Pattern 1 Length */
+#define	WOL_PLEN0_P1_LEN_BASE		8
+/*		Bit(s) WOL_PLEN0_RSRV_7 reserved */
+#define	WOL_PLEN0_P0_LEN_MSK		SHIFT0(0x7f)	/* Pattern 0 Length */
+#define	WOL_PLEN0_P0_LEN_BASE		0
+
+/*	WOL_PLEN1			0x0F34	Pattern Length Register 1 (4-7) */
+/*		Bit(s) WOL_PLEN1_RSRV_31 reserved */
+#define	WOL_PLEN1_P7_LEN_MSK		SHIFT24(0x7fUL)	/* Pattern 7 Length */
+#define	WOL_PLEN1_P7_LEN_BASE		24
+/*		Bit(s) WOL_PLEN1_RSRV_23 reserved */
+#define	WOL_PLEN1_P6_LEN_MSK		SHIFT16(0x7fUL)	/* Pattern 6 Length */
+#define	WOL_PLEN1_P6_LEN_BASE		16
+/*		Bit(s) WOL_PLEN1_RSRV_15 reserved */
+#define	WOL_PLEN1_P5_LEN_MSK		SHIFT8(0x7f)	/* Pattern 5 Length */
+#define	WOL_PLEN1_P5_LEN_BASE		8
+/*		Bit(s) WOL_PLEN1_RSRV_7 reserved */
+#define	WOL_PLEN1_P4_LEN_MSK		SHIFT0(0x7f)	/* Pattern 4 Length */
+#define	WOL_PLEN1_P4_LEN_BASE		0
+
+/*	WOL_PLEN2			0x0F38	Pattern Length Register 2 (8-11) */
+/*		Bit(s) WOL_PLEN2_RSRV_31 reserved */
+#define	WOL_PLEN2_P11_LEN_MSK		SHIFT24(0x7fUL)	/* Pattern 11 Length */
+#define	WOL_PLEN2_P11_LEN_BASE		24
+/*		Bit(s) WOL_PLEN2_RSRV_23 reserved */
+#define	WOL_PLEN2_P10_LEN_MSK		SHIFT16(0x7fUL)	/* Pattern 10 Length */
+#define	WOL_PLEN2_P10_LEN_BASE		16
+/*		Bit(s) WOL_PLEN2_RSRV_15 reserved */
+#define	WOL_PLEN2_P9_LEN_MSK		SHIFT8(0x7f)	/* Pattern 9 Length */
+#define	WOL_PLEN2_P9_LEN_BASE		8
+/*		Bit(s) WOL_PLEN2_RSRV_7 reserved */
+#define	WOL_PLEN2_P8_LEN_MSK		SHIFT0(0x7f)	/* Pattern 8 Length */
+#define	WOL_PLEN2_P8_LEN_BASE		0
+
+/*	WOL_PLEN3			0x0F3C	Pattern Length Register 3 (12-13) */
+/*		Bit(s) WOL_PLEN3_RSRV_31_15 reserved */
+#define	WOL_PLEN3_P13_LEN_MSK			SHIFT8(0x7f)		/* Pattern 13 Length */
+#define	WOL_PLEN3_P13_LEN_BASE			8
+/*		Bit(s) WOL_PLEN3_RSRV_7 reserved */
+#define	WOL_PLEN3_P12_LEN_MSK			SHIFT0(0x7f)		/* Pattern 12 Length */
+#define	WOL_PLEN3_P12_LEN_BASE			0
+
+/*	WOL_PCNT0			0x0F40	Pattern Counter Register 0 (0-3) */
+/*		Bit(s) WOL_PCNT0_RSRV_31 reserved */
+#define	WOL_PCNT0_P3_CNTR_MSK		SHIFT24(0x7fUL)	/* Pattern 3 Counter */
+#define	WOL_PCNT0_P3_CNTR_BASE		24
+/*		Bit(s) WOL_PCNT0_RSRV_23 reserved */
+#define	WOL_PCNT0_P2_CNTR_MSK		SHIFT16(0x7fUL)	/* Pattern 2 Counter */
+#define	WOL_PCNT0_P2_CNTR_BASE		16
+/*		Bit(s) WOL_PCNT0_RSRV_15 reserved */
+#define	WOL_PCNT0_P1_CNTR_MSK		SHIFT8(0x7f)	/* Pattern 1 Counter */
+#define	WOL_PCNT0_P1_CNTR_BASE		8
+/*		Bit(s) WOL_PCNT0_RSRV_7 reserved */
+#define	WOL_PCNT0_P0_CNTR_MSK		SHIFT0(0x7f)	/* Pattern 0 Counter */
+#define	WOL_PCNT0_P0_CNTR_BASE		0
+
+/*	WOL_PCNT1			0x0F44	Pattern Counter Register 1 (4-7) */
+/*		Bit(s) WOL_PCNT1_RSRV_31 reserved */
+#define	WOL_PCNT1_P7_CNTR_MSK		SHIFT24(0x7fUL)	/* Pattern 7 Counter */
+#define	WOL_PCNT1_P7_CNTR_BASE		24
+/*		Bit(s) WOL_PCNT1_RSRV_23 reserved */
+#define	WOL_PCNT1_P6_CNTR_MSK		SHIFT16(0x7fUL)	/* Pattern 6 Counter */
+#define	WOL_PCNT1_P6_CNTR_BASE		16
+/*		Bit(s) WOL_PCNT1_RSRV_15 reserved */
+#define	WOL_PCNT1_P5_CNTR_MSK		SHIFT8(0x7f)	/* Pattern 5 Counter */
+#define	WOL_PCNT1_P5_CNTR_BASE		8
+/*		Bit(s) WOL_PCNT1_RSRV_7 reserved */
+#define	WOL_PCNT1_P4_CNTR_MSK		SHIFT0(0x7f)	/* Pattern 4 Counter */
+#define	WOL_PCNT1_P4_CNTR_BASE		0
+
+/*	WOL_PCNT2			0x0F48	Pattern Counter Register 2 (8-11) */
+/*		Bit(s) WOL_PCNT2_RSRV_31 reserved */
+#define	WOL_PCNT2_P11_CNTR_MSK		SHIFT24(0x7fUL)	/* Pattern 11 Counter */
+#define	WOL_PCNT2_P11_CNTR_BASE		24
+/*		Bit(s) WOL_PCNT2_RSRV_23 reserved */
+#define	WOL_PCNT2_P10_CNTR_MSK		SHIFT16(0x7fUL)	/* Pattern 10 Counter */
+#define	WOL_PCNT2_P10_CNTR_BASE		16
+/*		Bit(s) WOL_PCNT2_RSRV_15 reserved */
+#define	WOL_PCNT2_P9_CNTR_MSK		SHIFT8(0x7f)	/* Pattern 9 Counter */
+#define	WOL_PCNT2_P9_CNTR_BASE		8
+/*		Bit(s) WOL_PCNT2_RSRV_7 reserved */
+#define	WOL_PCNT2_P8_CNTR_MSK		SHIFT0(0x7f)	/* Pattern 8 Counter */
+#define	WOL_PCNT2_P8_CNTR_BASE		0
+
+/*	WOL_PCNT3			0x0F4C	Pattern Counter Register 2 (12-13) */
+/*		Bit(s) WOL_PCNT3_RSRV_31_15 reserved */
+#define	WOL_PCNT3_P13_CNTR_MSK			SHIFT8(0x7f)		/* Pattern 13 Counter */
+#define	WOL_PCNT3_P13_CNTR_BASE			8
+/*		Bit(s) WOL_PCNT3_RSRV_7 reserved */
+#define	WOL_PCNT3_P12_CNTR_MSK			SHIFT0(0x7f)		/* Pattern 12 Counter */
+#define	WOL_PCNT3_P12_CNTR_BASE			0
+
+/*	PAT_CSR				0x0F50	Pattern RAM Control/Status Register */
+/*		Bit(s) PAT_CSR_RSRV_31_23 reserved */
+#define	PAT_CSR_RPTR_MSK			SHIFT16(0x7fUL)	/* Pattern Read Pointer */
+#define	PAT_CSR_RPTR_BASE			16
+/*		Bit(s) PAT_CSR_RSRV_15_1 reserved */
+#define	PAT_CSR_BSEL				BIT_0			/* Pattern RAM Bank Select */
+
+/*	PAT_P12PPMC			0x0F5C	Pattern 12 Port Pattern Match Control Register */
+/*		Bit(s) PAT_P12PPMC_RSRV_31_16 reserved */
+/* Port Match Pattern Enable */
+#define	PAT_P12PPMC_PMP_ENA_MSK			SHIFT8(0xff)
+#define	PAT_P12PPMC_PMP_ENA_BASE		8
+/*		Bit(s) PAT_P12PPMC_RSRV_7 reserved */
+#define	PAT_P12PPMC_PMO_MSK				SHIFT1(0x3f)	/* Port Match Offset */
+#define	PAT_P12PPMC_PMO_BASE			1
+/*		Bit(s) PAT_P12PPMC_RSRV_0 reserved */
+
+/*	PAT_P12PPMDR0		0x0F60	Pattern 12 Port Pattern Match Data 0 Register */
+#define	PAT_P12PPMDR0_PMP1_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 1 */
+#define	PAT_P12PPMDR0_PMP1_BASE		16
+#define	PAT_P12PPMDR0_PMP0_MSK		SHIFT0(0xffff)	/* Port Match Pattern 0 */
+#define	PAT_P12PPMDR0_PMP0_BASE		0
+
+/*	PAT_P12PPMDR1		0x0F64	Pattern 12 Port Pattern Match Data 1 Register */
+#define	PAT_P12PPMDR1_PMP3_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 3 */
+#define	PAT_P12PPMDR1_PMP3_BASE		16
+#define	PAT_P12PPMDR1_PMP2_MSK		SHIFT0(0xffff)	/* Port Match Pattern 2 */
+#define	PAT_P12PPMDR1_PMP2_BASE		0
+
+/*	PAT_P12PPMDR2		0x0F68	Pattern 12 Port Pattern Match Data 2 Register */
+#define	PAT_P12PPMDR2_PMP5_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 5 */
+#define	PAT_P12PPMDR2_PMP5_BASE		16
+#define	PAT_P12PPMDR2_PMP4_MSK		SHIFT0(0xffff)	/* Port Match Pattern 4 */
+#define	PAT_P12PPMDR2_PMP4_BASE		0
+
+/*	PAT_P12PPMDR3		0x0F6C	Pattern 12 Port Pattern Match Data 3 Register */
+#define	PAT_P12PPMDR3_PMP7_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 7 */
+#define	PAT_P12PPMDR3_PMP7_BASE		16
+#define	PAT_P12PPMDR3_PMP6_MSK		SHIFT0(0xffff)	/* Port Match Pattern 6 */
+#define	PAT_P12PPMDR3_PMP6_BASE		0
+
+/*	PAT_P13PPMC			0x0F7C	Pattern 13 Port Pattern Match Control Register */
+/*		Bit(s) PAT_P13PPMC_RSRV_31_16 reserved */
+/* Port Match Pattern Enable */
+#define	PAT_P13PPMC_PMP_ENA_MSK			SHIFT8(0xff)
+#define	PAT_P13PPMC_PMP_ENA_BASE		8
+/*		Bit(s) PAT_P13PPMC_RSRV_7 reserved */
+#define	PAT_P13PPMC_PMO_MSK				SHIFT1(0x3f)	/* Port Match Offset */
+#define	PAT_P13PPMC_PMO_BASE			1
+/*		Bit(s) PAT_P13PPMC_RSRV_0 reserved */
+
+/*	PAT_P13PPMDR0		0x0F80	Pattern 13 Port Pattern Match Data 0 Register */
+#define	PAT_P13PPMDR0_PMP1_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 1 */
+#define	PAT_P13PPMDR0_PMP1_BASE		16
+#define	PAT_P13PPMDR0_PMP0_MSK		SHIFT0(0xffff)	/* Port Match Pattern 0 */
+#define	PAT_P13PPMDR0_PMP0_BASE		0
+
+/*	PAT_P13PPMDR1		0x0F84	Pattern 13 Port Pattern Match Data 1 Register */
+#define	PAT_P13PPMDR1_PMP3_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 3 */
+#define	PAT_P13PPMDR1_PMP3_BASE		16
+#define	PAT_P13PPMDR1_PMP2_MSK		SHIFT0(0xffff)	/* Port Match Pattern 2 */
+#define	PAT_P13PPMDR1_PMP2_BASE		0
+
+/*	PAT_P13PPMDR2		0x0F88	Pattern 13 Port Pattern Match Data 2 Register */
+#define	PAT_P13PPMDR2_PMP5_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 5 */
+#define	PAT_P13PPMDR2_PMP5_BASE		16
+#define	PAT_P13PPMDR2_PMP4_MSK		SHIFT0(0xffff)	/* Port Match Pattern 4 */
+#define	PAT_P13PPMDR2_PMP4_BASE		0
+
+/*	PAT_P13PPMDR3		0x0F8C	Pattern 13 Port Pattern Match Data 3 Register */
+#define	PAT_P13PPMDR3_PMP7_MSK		SHIFT16(0xffffUL)	/* Port Match Pattern 7 */
+#define	PAT_P13PPMDR3_PMP7_BASE		16
+#define	PAT_P13PPMDR3_PMP6_MSK		SHIFT0(0xffff)	/* Port Match Pattern 6 */
+#define	PAT_P13PPMDR3_PMP6_BASE		0
+
+/*  CLASS_A_RATE_INT            0x0FA0  Class A Rate Integer Register */
+/* K Factor Enable */
+#define CLASS_A_RATE_INT_K_FACTOR_EN                BIT_31
+/*      Bit(s) CLASS_A_RATE_INT_RSRV_30_22 reserved */
+/* K Factor/Tx 4 Rate Integer for 1/K Scheme */
+#define CLASS_A_RATE_INT_K_FACTOR_RATE_INT_MSK      SHIFT0(0x3fffff)
+#define CLASS_A_RATE_INT_K_FACTOR_RATE_INT_BASE     0
+
+/*  CLASS_A_RATE_FRAC           0x0FA4  Class A Rate Fraction Register */
+/* Class A Rate Denominator for 1/K Factor Scheme */
+#define CLASS_A_RATE_FRAC_CLASS_A_RATE_DEN_MSK      SHIFT16(0xffffUL)
+#define CLASS_A_RATE_FRAC_CLASS_A_RATE_DEN_BASE     16
+/* Class A Rate Numerator for 1/K Factor Scheme */
+#define CLASS_A_RATE_FRAC_CLASS_A_RATE_NUM_MSK      SHIFT0(0xffff)
+#define CLASS_A_RATE_FRAC_CLASS_A_RATE_NUM_BASE     0
+
+/*  CLASSA_RATE_LIMIT           0x0FA8  Class A Rate Limiter Register */
+/* Class A Low Limit */
+#define CLASSA_RATE_LIMIT_CLASS_A_LO_LIMIT_MSK      SHIFT16(0xffffUL)
+#define CLASSA_RATE_LIMIT_CLASS_A_LO_LIMIT_BASE     16
+/* Class A High Limit */
+#define CLASSA_RATE_LIMIT_CLASS_A_HI_LIMIT_MSK      SHIFT0(0xffff)
+#define CLASSA_RATE_LIMIT_CLASS_A_HI_LIMIT_BASE     0
+
+/*  CLASS_A_ST                  0x0FB0  Class A Status Register */
+#define CLASS_A_ST_MONITOR_SEL_MSK      SHIFT30(0x3UL)    /* Monitor Status Selection */
+#define CLASS_A_ST_MONITOR_SEL_BASE     30
+/*      Bit(s) CLASS_A_ST_RSRV_29_16 reserved */
+#define CLASS_A_ST_MONITOR_ST_MSK       SHIFT0(0xffff)  /* Monitor Status */
+#define CLASS_A_ST_MONITOR_ST_BASE      0
+
+/*  CLASS_B_RATE_INT            0x0FC0  Class B Rate Integer Register */
+/* K Factor Enable */
+#define CLASS_B_RATE_INT_K_FACTOR_EN                BIT_31
+/*      Bit(s) CLASS_B_RATE_INT_RSRV_30_22 reserved */
+/* K Factor/Class B Rate Integer for 1/K Scheme */
+#define CLASS_B_RATE_INT_K_FACTOR_RATE_INT_MSK      SHIFT0(0x3fffff)
+#define CLASS_B_RATE_INT_K_FACTOR_RATE_INT_BASE     0
+
+/*  CLASS_B_RATE_FRAC           0x0FC4  Class B Rate Fraction Register */
+/* Class B Rate Denominator for 1/K Factor Scheme */
+#define CLASS_B_RATE_FRAC_CLASS_B_RATE_DEN_MSK      SHIFT16(0xffffUL)
+#define CLASS_B_RATE_FRAC_CLASS_B_RATE_DEN_BASE     16
+/* Class B Rate Numerator for 1/K Factor Scheme */
+#define CLASS_B_RATE_FRAC_CLASS_B_RATE_NUM_MSK      SHIFT0(0xffff)
+#define CLASS_B_RATE_FRAC_CLASS_B_RATE_NUM_BASE     0
+
+/*  CLASSB_RATE_LIMIT           0x0FC8  Class B Rate Limiter Register */
+/* Class B Low Limit */
+#define CLASSB_RATE_LIMIT_CLASS_B_LO_LIMIT_MSK      SHIFT16(0xffffUL)
+#define CLASSB_RATE_LIMIT_CLASS_B_LO_LIMIT_BASE     16
+/* Class B High Limit */
+#define CLASSB_RATE_LIMIT_CLASS_B_HI_LIMIT_MSK      SHIFT0(0xffff)
+#define CLASSB_RATE_LIMIT_CLASS_B_HI_LIMIT_BASE     0
+
+/*  CLASS_B_ST                  0x0FD0  Class B Status Register */
+#define CLASS_B_ST_MONITOR_SEL_MSK      SHIFT30(0x3UL)    /* Monitor Status Selection */
+#define CLASS_B_ST_MONITOR_SEL_BASE     30
+/*      Bit(s) CLASS_B_ST_RSRV_29_16 reserved */
+#define CLASS_B_ST_MONITOR_ST_MSK       SHIFT0(0xffff)  /* Monitor Status */
+#define CLASS_B_ST_MONITOR_ST_BASE      0
+
+/*  PTP_ADJ_CTRL1               0x0FE0  PTP Rate Clock Adjust Control 1
+ *                                      Register
+ */
+/* PTP Clock/Credit Increase Pulse */
+#define PTP_ADJ_CTRL1_PTP_CLK_UP_PLUS                   BIT_31
+/* PTP Clock Adjust Timer Enable */
+#define PTP_ADJ_CTRL1_PTP_UP_TIMER_EN                   BIT_30
+/* PTP Clock/Credit Delta Selection */
+#define PTP_ADJ_CTRL1_PTP_CLK_CREDIT_UP_SEL             BIT_29
+/*      Bit(s) PTP_ADJ_CTRL1_RSRV_28_22 reserved */
+/* PTP Clock/Credit Increase Amount */
+#define PTP_ADJ_CTRL1_PTP_CLK_CREDIT_UP_AMT_MSK         SHIFT0(0x3fffff)
+#define PTP_ADJ_CTRL1_PTP_CLK_CREDIT_UP_AMT_BASE        0
+
+/*  PTP_ADJ_CTRL2               0x0FE4  PTP Rate Clock Adjust Control 2
+ *                                      Register
+ */
+/* PTP Clock Decrease Pulse */
+#define PTP_ADJ_CTRL2_PTP_CLK_DN_PLUS                   BIT_31
+/* PTP Clock Adjust Timer Enable */
+#define PTP_ADJ_CTRL2_PTP_DN_TIMER_EN                   BIT_30
+/* PTP Clock/Credit Delta Selection */
+#define PTP_ADJ_CTRL2_PTP_CLK_CREDIT_DN_SEL             BIT_29
+/*      Bit(s) PTP_ADJ_CTRL2_RSRV_28_22 reserved */
+/* PTP Clock/Credit Decrease Amount */
+#define PTP_ADJ_CTRL2_PTP_CLK_CREDIT_DN_AMT_MSK         SHIFT0(0x3fffff)
+#define PTP_ADJ_CTRL2_PTP_CLK_CREDIT_DN_AMT_BASE        0
+
+/*  PTP_ADJ_CTRL3               0x0FE8  PTP Rate Clock Adjust Control 3
+ *                                      Register
+ */
+/* PTP Clock Adjust Timer Value */
+#define PTP_ADJ_CTRL3_PTP_CLK_ADJUST_TIMER_MSK      SHIFT0(0xffffffff)
+#define PTP_ADJ_CTRL3_PTP_CLK_ADJUST_TIMER_BASE     0
+
+/*	THDR0_LO			0x1900	TCP Segmentation Header Register 0 Lo */
+#define	THDR0_LO_MAC_HDR_0_MSK		SHIFT0(0xffffffff)	/* Word 0/1 of MAC Header */
+#define	THDR0_LO_MAC_HDR_0_BASE		0
+
+/*	THDR0_HI			0x1904	TCP Segmentation Header Register 0 Hi */
+#define	THDR0_HI_MAC_HDR_1_MSK		SHIFT0(0xffffffff)	/* Word 2/3 of MAC Header */
+#define	THDR0_HI_MAC_HDR_1_BASE		0
+
+/*	THDR1_LO			0x1908	TCP Segmentation Header Register 1 Lo */
+#define	THDR1_LO_MAC_HDR_2_MSK		SHIFT0(0xffffffff)	/* Word 4/5 of MAC Header */
+#define	THDR1_LO_MAC_HDR_2_BASE		0
+
+/*	THDR1_HI			0x190C	TCP Segmentation Header Register 1 Hi */
+#define	THDR1_HI_IP_HDR_0_MSK		SHIFT16(0xffffUL)	/* Word 0 of IPv4/IPv6 Header */
+#define	THDR1_HI_IP_HDR_0_BASE		16
+#define	THDR1_HI_MAC_HDR_3_MSK		SHIFT0(0xffff)	/* Word 6 of MAC Header */
+#define	THDR1_HI_MAC_HDR_3_BASE		0
+
+/*	THDR2_LO			0x1910	TCP Segmentation Header Register 2 Lo */
+/* Word 1/2 of IPv4/IPv6 Header */
+#define	THDR2_LO_IP_HDR_1_MSK		SHIFT0(0xffffffff)
+#define	THDR2_LO_IP_HDR_1_BASE		0
+
+/*	THDR2_HI			0x1914	TCP Segmentation Header Register 2 Hi */
+/* Word 3/4 of IPv4/IPv6 Header */
+#define	THDR2_HI_IP_HDR_2_MSK		SHIFT0(0xffffffff)
+#define	THDR2_HI_IP_HDR_2_BASE		0
+
+/*	THDR3_LO			0x1918	TCP Segmentation Header Register 3 Lo */
+/* Word 5/6 of IPv4/IPv6 Header */
+#define	THDR3_LO_IP_HDR_3_MSK		SHIFT0(0xffffffff)
+#define	THDR3_LO_IP_HDR_3_BASE		0
+
+/*	THDR3_HI			0x191C	TCP Segmentation Header Register 3 Hi */
+/* Word 7/8 of IPv4/IPv6 Header */
+#define	THDR3_HI_IP_HDR_4_MSK		SHIFT0(0xffffffff)
+#define	THDR3_HI_IP_HDR_4_BASE		0
+
+/*	THDR4_LO			0x1920	TCP Segmentation Header Register 4 Lo */
+/* Word 9/10 of IPv4/IPv6 Header */
+#define	THDR4_LO_IP_HDR_5_MSK		SHIFT0(0xffffffff)
+#define	THDR4_LO_IP_HDR_5_BASE		0
+
+/*	THDR4_HI			0x1924	TCP Segmentation Header Register 4 Hi */
+/* Word 11/12 of IPv4/IPv6 Header */
+#define	THDR4_HI_IP_HDR_6_MSK		SHIFT0(0xffffffff)
+#define	THDR4_HI_IP_HDR_6_BASE		0
+
+/*	THDR5_LO			0x1928	TCP Segmentation Header Register 5 Lo */
+/* Word 13/14 of IPv4/IPv6 Header */
+#define	THDR5_LO_IP_HDR_7_MSK		SHIFT0(0xffffffff)
+#define	THDR5_LO_IP_HDR_7_BASE		0
+
+/*	THDR5_HI			0x192C	TCP Segmentation Header Register 5 Hi */
+/* Word 15/16 of IPv4/IPv6 Header */
+#define	THDR5_HI_IP_HDR_8_MSK		SHIFT0(0xffffffff)
+#define	THDR5_HI_IP_HDR_8_BASE		0
+
+/*	THDR6_LO			0x1930	TCP Segmentation Header Register 6 Lo */
+/* Word 17/18 of IPv4/IPv6 Header */
+#define	THDR6_LO_IP_HDR_9_MSK		SHIFT0(0xffffffff)
+#define	THDR6_LO_IP_HDR_9_BASE		0
+
+/*	THDR6_HI			0x1934	TCP Segmentation Header Register 6 Hi */
+/* Word 19/20 of IPv4/IPv6 Header */
+#define	THDR6_HI_IP_HDR_10_MSK		SHIFT0(0xffffffff)
+#define	THDR6_HI_IP_HDR_10_BASE		0
+
+/*	THDR7_LO			0x1938	TCP Segmentation Header Register 7 Lo */
+/* Word 21/22 of IPv4/IPv6 Header */
+#define	THDR7_LO_IP_HDR_11_MSK		SHIFT0(0xffffffff)
+#define	THDR7_LO_IP_HDR_11_BASE		0
+
+/*	THDR7_HI			0x193C	TCP Segmentation Header Register 7 Hi */
+/* Word 23/24 of IPv4/IPv6 Header */
+#define	THDR7_HI_IP_HDR_12_MSK		SHIFT0(0xffffffff)
+#define	THDR7_HI_IP_HDR_12_BASE		0
+
+/*	THDR8_LO			0x1940	TCP Segmentation Header Register 8 Lo */
+/* Word 25/26 of IPv4/IPv6 Header */
+#define	THDR8_LO_IP_HDR_13_MSK		SHIFT0(0xffffffff)
+#define	THDR8_LO_IP_HDR_13_BASE		0
+
+/*	THDR8_HI			0x1944	TCP Segmentation Header Register 8 Hi */
+/* Word 27/28 of IPv4/IPv6 Header */
+#define	THDR8_HI_IP_HDR_14_MSK		SHIFT0(0xffffffff)
+#define	THDR8_HI_IP_HDR_14_BASE		0
+
+/*	THDR9_LO			0x1948	TCP Segmentation Header Register 9 Lo */
+/* Word 29/30 of IPv4/IPv6 Header */
+#define	THDR9_LO_IP_HDR_15_MSK		SHIFT0(0xffffffff)
+#define	THDR9_LO_IP_HDR_15_BASE		0
+
+/*	THDR9_HI			0x194C	TCP Segmentation Header Register 9 Hi */
+/* Word 31/32 of IPv4/IPv6 Header */
+#define	THDR9_HI_IP_HDR_16_MSK		SHIFT0(0xffffffff)
+#define	THDR9_HI_IP_HDR_16_BASE		0
+
+/*	THDR10_LO			0x1950	TCP Segmentation Header Register 10 Lo */
+/* Word 33/34 of IPv4/IPv6 Header */
+#define	THDR10_LO_IP_HDR_17_MSK			SHIFT0(0xffffffff)
+#define	THDR10_LO_IP_HDR_17_BASE		0
+
+/*	THDR10_HI			0x1954	TCP Segmentation Header Register 10 Hi */
+/* Word 35/36 of IPv4/IPv6 Header */
+#define	THDR10_HI_IP_HDR_18_MSK			SHIFT0(0xffffffff)
+#define	THDR10_HI_IP_HDR_18_BASE		0
+
+/*	THDR11_LO			0x1958	TCP Segmentation Header Register 11 Lo */
+/* Word 37/38 of IPv4/IPv6 Header */
+#define	THDR11_LO_IP_HDR_19_MSK			SHIFT0(0xffffffff)
+#define	THDR11_LO_IP_HDR_19_BASE		0
+
+/*	THDR11_HI			0x195C	TCP Segmentation Header Register 11 Hi */
+/* Word 39/40 of IPv4/IPv6 Header */
+#define	THDR11_HI_IP_HDR_20_MSK			SHIFT0(0xffffffff)
+#define	THDR11_HI_IP_HDR_20_BASE		0
+
+/*	THDR12_LO			0x1960	TCP Segmentation Header Register 12 Lo */
+/* Word 41/42 of IPv4/IPv6 Header */
+#define	THDR12_LO_IP_HDR_21_MSK			SHIFT0(0xffffffff)
+#define	THDR12_LO_IP_HDR_21_BASE		0
+
+/*	THDR12_HI			0x1964	TCP Segmentation Header Register 12 Hi */
+/* Word 43/44 of IPv4/IPv6 Header */
+#define	THDR12_HI_IP_HDR_22_MSK			SHIFT0(0xffffffff)
+#define	THDR12_HI_IP_HDR_22_BASE		0
+
+/*	THDR13_LO			0x1968	TCP Segmentation Header Register 13 Lo */
+/* Word 45/46 of IPv4/IPv6 Header */
+#define	THDR13_LO_IP_HDR_23_MSK			SHIFT0(0xffffffff)
+#define	THDR13_LO_IP_HDR_23_BASE		0
+
+/*	THDR13_HI			0x196C	TCP Segmentation Header Register 13 Hi */
+/* Word 47/48 of IPv4/IPv6 Header */
+#define	THDR13_HI_IP_HDR_24_MSK			SHIFT0(0xffffffff)
+#define	THDR13_HI_IP_HDR_24_BASE		0
+
+/*	THDR14_LO			0x1970	TCP Segmentation Header Register 14 Lo */
+/* Word 49/50 of IPv4/IPv6 Header */
+#define	THDR14_LO_IP_HDR_25_MSK			SHIFT0(0xffffffff)
+#define	THDR14_LO_IP_HDR_25_BASE		0
+
+/*	THDR14_HI			0x1974	TCP Segmentation Header Register 14 Hi */
+/* Word 51/52 of IPv4/IPv6 Header */
+#define	THDR14_HI_IP_HDR_26_MSK			SHIFT0(0xffffffff)
+#define	THDR14_HI_IP_HDR_26_BASE		0
+
+/*	THDR15_LO			0x1978	TCP Segmentation Header Register 15 Lo */
+/* Word 53/54 of IPv4/IPv6 Header */
+#define	THDR15_LO_IP_HDR_27_MSK			SHIFT0(0xffffffff)
+#define	THDR15_LO_IP_HDR_27_BASE		0
+
+/*	THDR15_HI			0x197C	TCP Segmentation Header Register 15 Hi */
+/* Word 55/56 of IPv4/IPv6 Header */
+#define	THDR15_HI_IP_HDR_28_MSK			SHIFT0(0xffffffff)
+#define	THDR15_HI_IP_HDR_28_BASE		0
+
+/*	THDR16_LO			0x1980	TCP Segmentation Header Register 16 Lo */
+/* Word 57/58 of IPv4/IPv6 Header */
+#define	THDR16_LO_IP_HDR_29_MSK			SHIFT0(0xffffffff)
+#define	THDR16_LO_IP_HDR_29_BASE		0
+
+/*	THDR16_HI			0x1984	TCP Segmentation Header Register 16 Hi */
+/* Word 59/60 of IPv4/IPv6 Header */
+#define	THDR16_HI_IP_HDR_30_MSK			SHIFT0(0xffffffff)
+#define	THDR16_HI_IP_HDR_30_BASE		0
+
+/*	THDR17_LO			0x1988	TCP Segmentation Header Register 17 Lo */
+/* Word 61/62 of IPv4/IPv6 Header */
+#define	THDR17_LO_IP_HDR_31_MSK			SHIFT0(0xffffffff)
+#define	THDR17_LO_IP_HDR_31_BASE		0
+
+/*	THDR17_HI			0x198C	TCP Segmentation Header Register 17 Hi */
+/* Word 63/64 of IPv4/IPv6 Header */
+#define	THDR17_HI_IP_HDR_32_MSK			SHIFT0(0xffffffff)
+#define	THDR17_HI_IP_HDR_32_BASE		0
+
+/*	THDR18_LO			0x1990	TCP Segmentation Header Register 18 Lo */
+/* Word 65/66 of IPv4/IPv6 Header */
+#define	THDR18_LO_IP_HDR_33_MSK			SHIFT0(0xffffffff)
+#define	THDR18_LO_IP_HDR_33_BASE		0
+
+/*	THDR18_HI			0x1994	TCP Segmentation Header Register 18 Hi */
+/* Word 67/68 of IPv4/IPv6 Header */
+#define	THDR18_HI_IP_HDR_34_MSK			SHIFT0(0xffffffff)
+#define	THDR18_HI_IP_HDR_34_BASE		0
+
+/*	THDR19_LO			0x1998	TCP Segmentation Header Register 19 Lo */
+/* Word 69/70 of IPv4/IPv6 Header */
+#define	THDR19_LO_IP_HDR_35_MSK			SHIFT0(0xffffffff)
+#define	THDR19_LO_IP_HDR_35_BASE		0
+
+/*	THDR19_HI			0x199C	TCP Segmentation Header Register 19 Hi */
+/* Word 71/72 of IPv4/IPv6 Header */
+#define	THDR19_HI_IP_HDR_36_MSK			SHIFT0(0xffffffff)
+#define	THDR19_HI_IP_HDR_36_BASE		0
+
+/*	THDR20_LO			0x19A0	TCP Segmentation Header Register 20 Lo */
+/* Word 73/74 of IPv4/IPv6 Header */
+#define	THDR20_LO_IP_HDR_37_MSK			SHIFT0(0xffffffff)
+#define	THDR20_LO_IP_HDR_37_BASE		0
+
+/*	THDR20_HI			0x19A4	TCP Segmentation Header Register 20 Hi */
+/* Word 75/76 of IPv4/IPv6 Header */
+#define	THDR20_HI_IP_HDR_38_MSK			SHIFT0(0xffffffff)
+#define	THDR20_HI_IP_HDR_38_BASE		0
+
+/*	THDR21_LO			0x19A8	TCP Segmentation Header Register 21 Lo */
+/* Word 77/78 of IPv4/IPv6 Header */
+#define	THDR21_LO_IP_HDR_39_MSK			SHIFT0(0xffffffff)
+#define	THDR21_LO_IP_HDR_39_BASE		0
+
+/*	THDR21_HI			0x19AC	TCP Segmentation Header Register 21 Hi */
+/* Word 79/80 of IPv4/IPv6 Header */
+#define	THDR21_HI_IP_HDR_40_MSK			SHIFT0(0xffffffff)
+#define	THDR21_HI_IP_HDR_40_BASE		0
+
+/*	THDR22_LO			0x19B0	TCP Segmentation Header Register 22 Lo */
+/* Word 81/82 of IPv4/IPv6 Header */
+#define	THDR22_LO_IP_HDR_41_MSK			SHIFT0(0xffffffff)
+#define	THDR22_LO_IP_HDR_41_BASE		0
+
+/*	THDR22_HI			0x19B4	TCP Segmentation Header Register 22 Hi */
+#define	THDR22_HI_TCP_HDR_0_MSK			SHIFT16(0xffffUL)	/* Word 0 of TCP Header */
+#define	THDR22_HI_TCP_HDR_0_BASE		16
+/* Word 83 of IPv4/IPv6 Header */
+#define	THDR22_HI_IP_HDR_42_MSK			SHIFT0(0xffff)
+#define	THDR22_HI_IP_HDR_42_BASE		0
+
+/*	THDR23_LO			0x19B8	TCP Segmentation Header Register 23 Lo */
+/* Word 1/2 of TCP Header */
+#define	THDR23_LO_TCP_HDR_1_MSK			SHIFT0(0xffffffff)
+#define	THDR23_LO_TCP_HDR_1_BASE		0
+
+/*	THDR23_HI			0x19BC	TCP Segmentation Header Register 23 Hi */
+/* Word 3/4 of TCP Header */
+#define	THDR23_HI_TCP_HDR_2_MSK			SHIFT0(0xffffffff)
+#define	THDR23_HI_TCP_HDR_2_BASE		0
+
+/*	THDR24_LO			0x19C0	TCP Segmentation Header Register 24 Lo */
+/* Word 5/6 of TCP Header */
+#define	THDR24_LO_TCP_HDR_3_MSK			SHIFT0(0xffffffff)
+#define	THDR24_LO_TCP_HDR_3_BASE		0
+
+/*	THDR24_HI			0x19C4	TCP Segmentation Header Register 24 Hi */
+/* Word 7/8 of TCP Header */
+#define	THDR24_HI_TCP_HDR_4_MSK			SHIFT0(0xffffffff)
+#define	THDR24_HI_TCP_HDR_4_BASE		0
+
+/*	THDR25_LO			0x19C8	TCP Segmentation Header Register 25 Lo */
+/* Word 9/10 of TCP Header */
+#define	THDR25_LO_TCP_HDR_5_MSK			SHIFT0(0xffffffff)
+#define	THDR25_LO_TCP_HDR_5_BASE		0
+
+/*	THDR25_HI			0x19CC	TCP Segmentation Header Register 25 Hi */
+/* Word 11/12 of TCP Header */
+#define	THDR25_HI_TCP_HDR_6_MSK			SHIFT0(0xffffffff)
+#define	THDR25_HI_TCP_HDR_6_BASE		0
+
+/*	THDR26_LO			0x19D0	TCP Segmentation Header Register 26 Lo */
+/* Word 13/14 of TCP Header */
+#define	THDR26_LO_TCP_HDR_7_MSK			SHIFT0(0xffffffff)
+#define	THDR26_LO_TCP_HDR_7_BASE		0
+
+/*	THDR26_HI			0x19D4	TCP Segmentation Header Register 26 Hi */
+/* Word 15/16 of TCP Header */
+#define	THDR26_HI_TCP_HDR_8_MSK			SHIFT0(0xffffffff)
+#define	THDR26_HI_TCP_HDR_8_BASE		0
+
+/*	THDR27_LO			0x19D8	TCP Segmentation Header Register 27 Lo */
+/* Word 17/18 of TCP Header */
+#define	THDR27_LO_TCP_HDR_9_MSK			SHIFT0(0xffffffff)
+#define	THDR27_LO_TCP_HDR_9_BASE		0
+
+/*	THDR27_HI			0x19DC	TCP Segmentation Header Register 27 Hi */
+/* Word 19/20 of TCP Header */
+#define	THDR27_HI_TCP_HDR_10_MSK		SHIFT0(0xffffffff)
+#define	THDR27_HI_TCP_HDR_10_BASE		0
+
+/*	THDR28_LO			0x19E0	TCP Segmentation Header Register 28 Lo */
+/* Word 21/22 of TCP Header */
+#define	THDR28_LO_TCP_HDR_11_MSK		SHIFT0(0xffffffff)
+#define	THDR28_LO_TCP_HDR_11_BASE		0
+
+/*	THDR28_HI			0x19E4	TCP Segmentation Header Register 28 Hi */
+/* Word 23/24 of TCP Header */
+#define	THDR28_HI_TCP_HDR_12_MSK		SHIFT0(0xffffffff)
+#define	THDR28_HI_TCP_HDR_12_BASE		0
+
+/*	THDR29_LO			0x19E8	TCP Segmentation Header Register 29 Lo */
+/* Word 25/26 of TCP Header */
+#define	THDR29_LO_TCP_HDR_13_MSK		SHIFT0(0xffffffff)
+#define	THDR29_LO_TCP_HDR_13_BASE		0
+
+/*	THDR29_HI			0x19EC	TCP Segmentation Header Register 29 Hi */
+/* Word 27/28 of TCP Header */
+#define	THDR29_HI_TCP_HDR_14_MSK		SHIFT0(0xffffffff)
+#define	THDR29_HI_TCP_HDR_14_BASE		0
+
+/*	THDR30_LO			0x19F0	TCP Segmentation Header Register 30 Lo */
+/*		Bit(s) THDR30_LO_RSRV_31_16 reserved */
+#define	THDR30_LO_TCP_HDR_15_MSK		SHIFT0(0xffff)	/* Word 29 of TCP Header */
+#define	THDR30_LO_TCP_HDR_15_BASE		0
+
+/*	CFG_VLAN_ET1		0x2000	VLAN Ethernet Type Configuration Register 1 */
+/*		Bit(s) CFG_VLAN_ET1_RSRV_31_8 reserved */
+#define	CFG_VLAN_ET1_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_VLAN_ET1_BASE				0
+
+/*	CFG_VLAN_ET0		0x2004	VLAN Ethernet Type Configuration Register 0 */
+/*		Bit(s) CFG_VLAN_ET0_RSRV_31_8 reserved */
+#define	CFG_VLAN_ET0_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_VLAN_ET0_BASE				0
+
+/*	CFG_MACSEC_ET1		0x2008	802.1AE Ethernet Type Configuration Register 1 */
+/*		Bit(s) CFG_MACSEC_ET1_RSRV_31_8 reserved */
+#define	CFG_MACSEC_ET1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_MACSEC_ET1_BASE					0
+
+/*	CFG_MACSEC_ET0		0x200C	802.1AE Ethernet Type Configuration Register 0 */
+/*		Bit(s) CFG_MACSEC_ET0_RSRV_31_8 reserved */
+#define	CFG_MACSEC_ET0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_MACSEC_ET0_BASE					0
+
+/*	CFG_TRAIL_SZ		0x2010	Trail Size Configuration Register */
+/*		Bit(s) CFG_TRAIL_SZ_RSRV_31_8 reserved */
+#define	CFG_TRAIL_SZ_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_TRAIL_SZ_BASE				0
+
+/*	CFG_DEFAULT_VLAN0	0x2014	Default VLAN Register 0 */
+/*		Bit(s) CFG_DEFAULT_VLAN0_RSRV_31_8 reserved */
+#define	CFG_DEFAULT_VLAN0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_DEFAULT_VLAN0_BASE					0
+
+/*	CFG_DEFAULT_VLAN1	0x2018	Default VLAN Register 1 */
+/*		Bit(s) CFG_DEFAULT_VLAN1_RSRV_31_4 reserved */
+#define	CFG_DEFAULT_VLAN1_MSK					SHIFT0(0xf)			/* Val */
+#define	CFG_DEFAULT_VLAN1_BASE					0
+
+/*	CFG_MACSEC_SL_SZ	0x201C	MACsec Size Configuration Register */
+/*		Bit(s) CFG_MACSEC_SL_SZ_RSRV_31_8 reserved */
+#define	CFG_MACSEC_SL_SZ_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_MACSEC_SL_SZ_BASE				0
+
+/*	CFG_MIN_PKT_LEN		0x2020	Minimum Packet Length Configuration Register */
+/*		Bit(s) CFG_MIN_PKT_LEN_RSRV_31_8 reserved */
+#define	CFG_MIN_PKT_LEN_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_MIN_PKT_LEN_BASE				0
+
+/*	SEC_CLK_RST			0x2024	MACsec Clock Reset Register */
+/*		Bit(s) SEC_CLK_RST_RSRV_31_4 reserved */
+#define	SEC_CLK_RST_GATE_DIS			BIT_3				/* Gate Disable */
+#define	SEC_CLK_RST_INGRESS_RST			BIT_2				/* Ingress Reset */
+#define	SEC_CLK_RST_EGRESS_RST			BIT_1				/* Egress Reset */
+#define	SEC_CLK_RST_STAT_RST			BIT_0				/* Stat Reset */
+
+/*	EGR_KS_SELECT		0x2028	Egress Key Store Select Register */
+/*		Bit(s) EGR_KS_SELECT_RSRV_31_6 reserved */
+#define	EGR_KS_SELECT_CTXT_NUM_MSK			SHIFT4(0x3)			/* Context Number */
+#define	EGR_KS_SELECT_CTXT_NUM_BASE			4
+/* Byte Number in Entry */
+#define	EGR_KS_SELECT_BYTE_NUM_MSK			SHIFT0(0xf)
+#define	EGR_KS_SELECT_BYTE_NUM_BASE			0
+
+/*	EGR_KS_WRDATA		0x202C	Egress Key Store Write Data Register */
+/*		Bit(s) EGR_KS_WRDATA_RSRV_31_8 reserved */
+#define	EGR_KS_WRDATA_MSK					SHIFT0(0xff)		/* Val */
+#define	EGR_KS_WRDATA_BASE					0
+
+/*	IGR_KS_SELECT		0x2030	Ingress Key Store Select Register */
+/*		Bit(s) IGR_KS_SELECT_RSRV_31_6 reserved */
+#define	IGR_KS_SELECT_CTXT_NUM_MSK			SHIFT4(0x3)			/* Context Number */
+#define	IGR_KS_SELECT_CTXT_NUM_BASE			4
+/* Byte Number in Entry */
+#define	IGR_KS_SELECT_BYTE_NUM_MSK			SHIFT0(0xf)
+#define	IGR_KS_SELECT_BYTE_NUM_BASE			0
+
+/*	IGR_KS_WRDATA		0x2034	Ingress Key Store Write Data Register */
+/*		Bit(s) IGR_KS_WRDATA_RSRV_31_8 reserved */
+#define	IGR_KS_WRDATA_MSK					SHIFT0(0xff)		/* Val */
+#define	IGR_KS_WRDATA_BASE					0
+
+/*	CFG_ELU_MC_HIGH0	0x2038	Multicast Match Register 0 */
+/*		Bit(s) CFG_ELU_MC_HIGH0_RSRV_31_4 reserved */
+#define	CFG_ELU_MC_HIGH0_MSK				SHIFT0(0xf)			/* Val */
+#define	CFG_ELU_MC_HIGH0_BASE				0
+
+/*	CFG_ELU_MC_HIGH1	0x203C	Multicast Match Register 1 */
+/*		Bit(s) CFG_ELU_MC_HIGH1_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_HIGH1_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_HIGH1_BASE				0
+
+/*	CFG_ELU_MC_HIGH2	0x2040	Multicast Match Register 2 */
+/*		Bit(s) CFG_ELU_MC_HIGH2_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_HIGH2_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_HIGH2_BASE				0
+
+/*	CFG_ELU_MC_HIGH3	0x2044	Multicast Match Register 3 */
+/*		Bit(s) CFG_ELU_MC_HIGH3_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_HIGH3_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_HIGH3_BASE				0
+
+/*	CFG_ELU_MC_HIGH4	0x2048	Multicast Match Register 4 */
+/*		Bit(s) CFG_ELU_MC_HIGH4_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_HIGH4_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_HIGH4_BASE				0
+
+/*	CFG_ELU_MC_HIGH5	0x204C	Multicast Match Register 5 */
+/*		Bit(s) CFG_ELU_MC_HIGH5_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_HIGH5_MSK				SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_HIGH5_BASE				0
+
+/*	CFG_ELU_MC_LOW_MSK0	0x2050	Multicast Match Mask Register 0 */
+/*		Bit(s) CFG_ELU_MC_LOW_MSK0_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_LOW_MSK0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_LOW_BASE0_BASE				0
+
+/*	CFG_ELU_MC_LOW_MSK1	0x2054	Multicast Match Mask Register 1 */
+/*		Bit(s) CFG_ELU_MC_LOW_MSK1_RSRV_31_8 reserved */
+#define	CFG_ELU_MC_LOW_MSK1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_ELU_MC_LOW_BASE1_BASE				0
+
+/*	CFG_DEFAULT_PORT0	0x2058	Default Port Configuration Register 0 */
+/*		Bit(s) CFG_DEFAULT_PORT0_RSRV_31_8 reserved */
+#define	CFG_DEFAULT_PORT0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_DEFAULT_PORT0_BASE					0
+
+/*	CFG_DEFAULT_PORT1	0x205C	Default Port Configuration Register 1 */
+/*		Bit(s) CFG_DEFAULT_PORT1_RSRV_31_8 reserved */
+#define	CFG_DEFAULT_PORT1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_DEFAULT_PORT1_BASE					0
+
+/*	CFG_SCB_PORT0		0x2060	SCB Port Configuration Register 0 */
+/*		Bit(s) CFG_SCB_PORT0_RSRV_31_8 reserved */
+#define	CFG_SCB_PORT0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_SCB_PORT0_BASE					0
+
+/*	CFG_SCB_PORT1		0x2064	SCB Port Configuration Register 1 */
+/*		Bit(s) CFG_SCB_PORT1_RSRV_31_8 reserved */
+#define	CFG_SCB_PORT1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_SCB_PORT1_BASE					0
+
+/*	CFG_AUTH_ADJUST		0x2068	Authentication Adjustment Register */
+/*		Bit(s) CFG_AUTH_ADJUST_RSRV_31_8 reserved */
+#define	CFG_AUTH_ADJUST_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_AUTH_ADJUST_BASE				0
+
+/*	CFG_ELU_GEN			0x206C	ELU Default Configuration Register */
+/*		Bit(s) CFG_ELU_GEN_RSRV_31_4 reserved */
+/* Minimum Bypass Length */
+#define	CFG_ELU_GEN_MIN_BYPASS_LEN_MSK		SHIFT2(0x3)
+#define	CFG_ELU_GEN_MIN_BYPASS_LEN_BASE		2
+/*		Bit(s) CFG_ELU_GEN_RSRV_1_0 reserved */
+
+/*	CFG_ELUC_ADDR		0x2070	ELU Address Configuration Register */
+/*		Bit(s) CFG_ELUC_ADDR_RSRV_31_6 reserved */
+#define	CFG_ELUC_ADDR_CTXT_NUM_MSK			SHIFT4(0x3)			/* Context Number */
+#define	CFG_ELUC_ADDR_CTXT_NUM_BASE			4
+#define	CFG_ELUC_ADDR_BYTE_NUM_MSK			SHIFT0(0xf)			/* Byte Number */
+#define	CFG_ELUC_ADDR_BYTE_NUM_BASE			0
+
+/*	CFG_ELUC_DATA		0x2074	ELU Context Data Configuration Register */
+/*		Bit(s) CFG_ELUC_DATA_RSRV_31_8 reserved */
+#define	CFG_ELUC_DATA_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_ELUC_DATA_BASE					0
+
+/*	CFG_ELUE_ADDR		0x2078	ELU Entry Configuration Register */
+/*		Bit(s) CFG_ELUE_ADDR_RSRV_31_8 reserved */
+/* Lookup Entry Number */
+#define	CFG_ELUE_ADDR_LKUP_NUM_MSK			SHIFT5(0x7)
+#define	CFG_ELUE_ADDR_LKUP_NUM_BASE			5
+#define	CFG_ELUE_ADDR_BYTE_NUM_MSK			SHIFT0(0x1f)		/* Byte Number */
+#define	CFG_ELUE_ADDR_BYTE_NUM_BASE			0
+
+/*	CFG_ELUE_DATA		0x207C	ELU Lookup Entry Access Configuration Register */
+/*		Bit(s) CFG_ELUE_DATA_RSRV_31_8 reserved */
+#define	CFG_ELUE_DATA_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_ELUE_DATA_BASE					0
+
+/*	CFG_EPR_GEN			0x2080	General Egress Parser Configuration Register */
+/*		Bit(s) CFG_EPR_GEN_RSRV_31_3 reserved */
+#define	CFG_EPR_GEN_PARSE_VLAN				BIT_2				/* Parse VLAN */
+/*		Bit(s) CFG_EPR_GEN_RSRV_1 reserved */
+#define	CFG_EPR_GEN_PREAMBLE_PRESENT		BIT_0				/* Preamble Present */
+
+/*	EGR_HR_SELECT		0x2084	Egress Write Select for H-Store Register */
+/*		Bit(s) EGR_HR_SELECT_RSRV_31_6 reserved */
+#define	EGR_HR_SELECT_KEY_NUM_MSK			SHIFT4(0x3)			/* Key number */
+#define	EGR_HR_SELECT_KEY_NUM_BASE			4
+/* Byte Number within Each Key */
+#define	EGR_HR_SELECT_BYTE_NUM_MSK			SHIFT0(0xf)
+#define	EGR_HR_SELECT_BYTE_NUM_BASE			0
+
+/*	EGR_HR_WRDATA		0x2088	Egress Header Write Data Register */
+/*		Bit(s) EGR_HR_WRDATA_RSRV_31_8 reserved */
+#define	EGR_HR_WRDATA_MSK					SHIFT0(0xff)		/* Val */
+#define	EGR_HR_WRDATA_BASE					0
+
+/*	IGR_HR_SELECT		0x208C	Ingress Write Select for H-Store Register */
+/*		Bit(s) IGR_HR_SELECT_RSRV_31_6 reserved */
+#define	IGR_HR_SELECT_KEY_NUM_MSK			SHIFT4(0x3)			/* Key number */
+#define	IGR_HR_SELECT_KEY_NUM_BASE			4
+/* Byte Number within Each Key */
+#define	IGR_HR_SELECT_BYTE_NUM_MSK			SHIFT0(0xf)
+#define	IGR_HR_SELECT_BYTE_NUM_BASE			0
+
+/*	IGR_HR_WRDATA		0x2090	Ingress Header Write Data Register */
+/*		Bit(s) IGR_HR_WRDATA_RSRV_31_6 reserved */
+#define	IGR_HR_WRDATA_2_MSK					SHIFT0(0xff)		/* Val */
+#define	IGR_HR_WRDATA_2_BASE				BIT_0
+
+/*	CFG_IMPLICIT_SCI0	0x2098	Implicit SCI Register 0 */
+/*		Bit(s) CFG_IMPLICIT_SCI0_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI0_BASE					0
+
+/*	CFG_IMPLICIT_SCI1	0x209C	Implicit SCI Register 1 */
+/*		Bit(s) CFG_IMPLICIT_SCI1_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI1_BASE					0
+
+/*	CFG_IMPLICIT_SCI2	0x20A0	Implicit SCI Register 2 */
+/*		Bit(s) CFG_IMPLICIT_SCI2_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI2_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI2_BASE					0
+
+/*	CFG_IMPLICIT_SCI3	0x20A4	Implicit SCI Register 3 */
+/*		Bit(s) CFG_IMPLICIT_SCI3_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI3_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI3_BASE					0
+
+/*	CFG_IMPLICIT_SCI4	0x20A8	Implicit SCI Register 4 */
+/*		Bit(s) CFG_IMPLICIT_SCI4_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI4_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI4_BASE					0
+
+/*	CFG_IMPLICIT_SCI5	0x20AC	Implicit SCI Register 5 */
+/*		Bit(s) CFG_IMPLICIT_SCI5_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI5_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI5_BASE					0
+
+/*	CFG_IMPLICIT_SCI6	0x20B0	Implicit SCI Register 6 */
+/*		Bit(s) CFG_IMPLICIT_SCI6_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI6_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI6_BASE					0
+
+/*	CFG_IMPLICIT_SCI7	0x20B4	Implicit SCI Register 7 */
+/*		Bit(s) CFG_IMPLICIT_SCI7_RSRV_31_8 reserved */
+#define	CFG_IMPLICIT_SCI7_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_IMPLICIT_SCI7_BASE					0
+
+/*	CFG_REPLAY_WINDOW0	0x20B8	Replay Window Register 0 */
+/*		Bit(s) CFG_REPLAY_WINDOW0_RSRV_31_8 reserved */
+#define	CFG_REPLAY_WINDOW0_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_REPLAY_WINDOW0_BASE					0
+
+/*	CFG_REPLAY_WINDOW1	0x20BC	Replay Window Register 1 */
+/*		Bit(s) CFG_REPLAY_WINDOW1_RSRV_31_8 reserved */
+#define	CFG_REPLAY_WINDOW1_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_REPLAY_WINDOW1_BASE					0
+
+/*	CFG_REPLAY_WINDOW2	0x20C0	Replay Window Register 2 */
+/*		Bit(s) CFG_REPLAY_WINDOW2_RSRV_31_8 reserved */
+#define	CFG_REPLAY_WINDOW2_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_REPLAY_WINDOW2_BASE					0
+
+/*	CFG_REPLAY_WINDOW3	0x20C4	Replay Window Register 3 */
+/*		Bit(s) CFG_REPLAY_WINDOW3_RSRV_31_8 reserved */
+#define	CFG_REPLAY_WINDOW3_MSK					SHIFT0(0xff)		/* Val */
+#define	CFG_REPLAY_WINDOW3_BASE					0
+
+/*	CFG_IPR_GEN			0x20C8	Ingress Primary Parser Register */
+/*		Bit(s) CFG_IPR_GEN_RSRV_31_3 reserved */
+#define	CFG_IPR_GEN_PREAMBLE_PRESENT		BIT_2				/* Preamble Present */
+#define	CFG_IPR_GEN_PARSE_VLAN				BIT_1				/* Parse VLAN */
+/* Extract Header Field */
+#define	CFG_IPR_GEN_EXTRACT_HDR_FIELD		BIT_0
+
+/*	CFG_ISC_GEN			0x20CC	Ingress Security Check Block Register */
+/*		Bit(s) CFG_ISC_GEN_RSRV_31_8 reserved */
+/* Statistics Clear on Read */
+#define	CFG_ISC_GEN_BLANK_7						BIT_7
+/*		Bit(s) CFG_ISC_GEN_RSRV_6 reserved */
+/*		Bit(s) CFG_ISC_GEN_RSRV_5 reserved */
+/*		Bit(s) CFG_ISC_GEN_RSRV_4_3 reserved */
+/* Replay Protect */
+#define	CFG_ISC_GEN_RPY_PROTECT					BIT_2
+/* Validate Frames */
+#define	CFG_ISC_GEN_VALIDATE_FRAMES_MSK			SHIFT0(0x3)
+#define	CFG_ISC_GEN_VALIDATE_FRAMES_BASE		0
+
+/*	CFG_RPY_ADDR		0x20D0	Replay Protect Table Access Register */
+/*		Bit(s) CFG_RPY_ADDR_RSRV_31_4 reserved */
+/* Replay Table Entry */
+#define	CFG_RPY_ADDR_RPY_TAB_NUM_MSK		SHIFT2(0x3)
+#define	CFG_RPY_ADDR_RPY_TAB_NUM_BASE		2
+#define	CFG_RPY_ADDR_BYTE_NUM_MSK			SHIFT0(0x3)			/* Byte Number */
+#define	CFG_RPY_ADDR_BYTE_NUM_BASE			0
+
+/*	CFG_RPY_DATA		0x20D4	ELU Context Data Register */
+/*		Bit(s) CFG_RPY_DATA_RSRV_31_8 reserved */
+/* Read/write Register for Accessing ELU Context */
+#define	CFG_RPY_DATA_MSK				SHIFT0(0xff)
+#define	CFG_RPY_DATA_BASE				0
+
+/*	CFG_ILUT_ADDR		0x20E0	Ingress Lookup Table Access Address
+ *								Configuration Register
+ */
+/*		Bit(s) CFG_ILUT_ADDR_RSRV_31_8 reserved */
+/* Address for Accessing Lookup Entry */
+#define	CFG_ILUT_ADDR_LOOKUP_NUM_MSK		SHIFT5(0x7)
+#define	CFG_ILUT_ADDR_LOOKUP_NUM_BASE		5
+#define	CFG_ILUT_ADDR_BYTE_NUM_MSK			SHIFT0(0x1f)		/* Byte Number */
+#define	CFG_ILUT_ADDR_BYTE_NUM_BASE			0
+
+/*	CFG_ILUT_DATA		0x20E4	ILU Table Data Register */
+/*		Bit(s) CFG_ILUT_DATA_RSRV_31_8 reserved */
+/* Read/write Register for Accessing ILU Table */
+#define	CFG_ILUT_DATA_MSK					SHIFT0(0xff)
+#define	CFG_ILUT_DATA_BASE					0
+
+/*	STAT_ADDR			0x20E8	Statistic Register Address */
+/*		Bit(s) STAT_ADDR_RSRV_31_6 reserved */
+/* Statistic Register Address */
+#define	STAT_ADDR_MSK					SHIFT0(0x3f)
+#define	STAT_ADDR_BASE					0
+
+/*	STAT_DATA0			0x20EC	Statistic Data Register 0 */
+/*		Bit(s) STAT_DATA0_RSRV_31_8 reserved */
+#define	STAT_DATA0_MSK					SHIFT0(0xff)		/* Statistic Data [7:0] */
+#define	STAT_DATA0_BASE					0
+
+/*	STAT_DATA1			0x20F0	Statistic Data Register 1 */
+/*		Bit(s) STAT_DATA1_RSRV_31_8 reserved */
+/* Statistic Data [15:8] */
+#define	STAT_DATA1_MSK					SHIFT0(0xff)
+#define	STAT_DATA1_BASE					0
+
+/*	STAT_DATA2			0x20F4	Statistic Data Register 2 */
+/*		Bit(s) STAT_DATA2_RSRV_31_8 reserved */
+/* Statistic Data [23:16] */
+#define	STAT_DATA2_MSK					SHIFT0(0xff)
+#define	STAT_DATA2_BASE					0
+
+/*	CFG_OVER_LEN1		0x20F8	Over-Length Configuration Register 1 */
+/*		Bit(s) CFG_OVER_LEN1_RSRV_31_8 reserved */
+/* High byte of Over-length Compare Value */
+#define	CFG_OVER_LEN1_MSK					SHIFT0(0xff)
+#define	CFG_OVER_LEN1_BASE					0
+
+/*	CNT_TX_ERR			0x2100	MACsec TX Processing Error Count */
+/*		Bit(s) CNT_TX_ERR_RSRV_31_8 reserved */
+#define	CNT_TX_ERR_MSK					SHIFT0(0xff)		/* err_cnt */
+#define	CNT_TX_ERR_BASE					0
+
+/*	CFG_IPAR_HYST		0x2104	Ingress Parse FIFO Hystersis */
+/*		Bit(s) CFG_IPAR_HYST_RSRV_31_4 reserved */
+/* Hystersis of Ingress Parse FIFO */
+#define	CFG_IPAR_HYST_MSK					SHIFT0(0xf)
+#define	CFG_IPAR_HYST_BASE					0
+
+/*	CFG_EPAR_HYST		0x2108	Egress Parse FIFO Hystersis */
+/*		Bit(s) CFG_EPAR_HYST_RSRV_31_4 reserved */
+/* Hystersis of Egress Parse FIFO */
+#define	CFG_EPAR_HYST_MSK					SHIFT0(0xf)
+#define	CFG_EPAR_HYST_BASE					0
+
+/*	RE_TRF_TCTL			0x2200	MACsec Retransmit FIFO Control */
+/*		Bit(s) RE_TRF_TCTL_RSRV_31_4 reserved */
+#define	RE_TRF_TCTL_RETRAN_OP_ON		BIT_3				/* Operational On */
+#define	RE_TRF_TCTL_RETRAN_OP_OFF		BIT_2				/* Operational Off */
+#define	RE_TRF_TCTL_RETRAN_RST_CLR		BIT_1				/* Reset Clear */
+#define	RE_TRF_TCTL_RETRAN_RST_SET		BIT_0				/* Reset Set */
+
+/*	RE_TRF_PCNT			0x2204	Retransmit FIFO Packet Counter */
+/*		Bit(s) RE_TRF_PCNT_RSRV_31_12 reserved */
+#define	RE_TRF_PCNT_MACSEC_RXTH_MSK			SHIFT8(0xf)			/* macsec_rxth */
+#define	RE_TRF_PCNT_MACSEC_RXTH_BASE		8
+#define	RE_TRF_PCNT_MSK						SHIFT0(0xff)		/* Packet Counter */
+#define	RE_TRF_PCNT_BASE					0
+
+/*	RE_TRF_TTH			0x2208	Retransmit FIFO Transmit Start Threshold */
+/*		Bit(s) RE_TRF_TTH_RSRV_31_5 reserved */
+/* Transmit Start Threshold */
+#define	RE_TRF_TTH_MSK					SHIFT0(0x1f)
+#define	RE_TRF_TTH_BASE					0
+
+/*	RE_TRF_WPTR			0x2210	Retransmit FIFO Write Pointer Register */
+/*		Bit(s) RE_TRF_WPTR_RSRV_31_5 reserved */
+#define	RE_TRF_WPTR_MSK					SHIFT0(0x1f)		/* Write Pointer */
+#define	RE_TRF_WPTR_BASE				0
+
+/*	RE_TRF_WLEV			0x2218	Retransmit FIFO Write Level Register */
+/*		Bit(s) RE_TRF_WLEV_RSRV_31_5 reserved */
+#define	RE_TRF_WLEV_MSK					SHIFT0(0x1f)		/* Write Level */
+#define	RE_TRF_WLEV_BASE				0
+
+/*	RE_TRF_RPTR			0x2220	Retransmit FIFO Read Pointer Register */
+/*		Bit(s) RE_TRF_RPTR_RSRV_31_5 reserved */
+#define	RE_TRF_RPTR_MSK					SHIFT0(0x1f)		/* Read Pointer */
+#define	RE_TRF_RPTR_BASE				0
+
+/*	RE_TRF_RES_PTR		0x2224	Transmit FIFO Restart Pointer Register */
+/*		Bit(s) RE_TRF_RES_PTR_RSRV_31_5 reserved */
+#define	RE_TRF_RES_PTR_MSK					SHIFT0(0x1f)		/* Restart Pointer */
+#define	RE_TRF_RES_PTR_BASE					0
+
+/*	RE_TRF_RLEV			0x2228	Retransmit FIFO Read Level Register */
+/*		Bit(s) RE_TRF_RLEV_RSRV_31_5 reserved */
+#define	RE_TRF_RLEV_MSK					SHIFT0(0x1f)		/* Read Level */
+#define	RE_TRF_RLEV_BASE				0
+
+/*	RE_TRF_RSPTR		0x222C	Retransmit FIFO Read Shadow Level Register */
+/*		Bit(s) RE_TRF_RSPTR_RSRV_31_5 reserved */
+#define	RE_TRF_RSPTR_MSK				SHIFT0(0x1f)		/* Read Shadow Level */
+#define	RE_TRF_RSPTR_BASE				0
+
+/*	USB_CTRL1			0x2280	USB Control Register 1 */
+/*		Bit(s) USB_CTRL1_RSRV_31_20 reserved */
+#define	USB_CTRL1_FS_RX_ERROR_MODE		BIT_19			/* USB_REG_FS_RX_ERROR_MODE */
+#define	USB_CTRL1_FORCE_END_EN			BIT_18			/* USB_REG_FORCE_END_EN */
+/* USB_REG_FS_RX_ERROR_MODE2 */
+#define	USB_CTRL1_FS_RX_ERROR_MODE2		BIT_17
+/* USB_REG_FS_RX_ERROR_MODE1 */
+#define	USB_CTRL1_FS_RX_ERROR_MODE1		BIT_16
+/*		Bit(s) USB_CTRL1_RSRV_15_9 reserved */
+#define	USB_CTRL1_EN_DEBUG				BIT_8			/* Debug mode */
+/*		Bit(s) USB_CTRL1_RSRV_7_5 reserved */
+#define	USB_CTRL1_EN_CLK60_TX			BIT_4			/* Disable CLK60MHZ to TX */
+#define	USB_CTRL1_SM_RST_CLR			BIT_3			/* USB SM Reset Clear */
+#define	USB_CTRL1_SM_RST_SET			BIT_2			/* USB SM Reset Set */
+#define	USB_CTRL1_RST_CLR				BIT_1			/* USB Reset Clear */
+#define	USB_CTRL1_RST_SET				BIT_0			/* USB Reset Set */
+
+/*	USB_CTRL2			0x2284	USB Control Register 2 */
+#define	USB_CTRL2_UDU2_IP_REV_ID_MSK		SHIFT16(0xffffUL)	/* UDU2 IP Rev ID */
+#define	USB_CTRL2_UDU2_IP_REV_ID_BASE		16
+#define	USB_CTRL2_PHY_IP_REV_ID_MSK			SHIFT0(0xffff)	/* USB PHY IP REV ID */
+#define	USB_CTRL2_PHY_IP_REV_ID_BASE		0
+
+/*	USB_STAT1			0x2288	USB Statistics Register */
+/*		Bit(s) USB_STAT1_RSRV_31_17 reserved */
+#define	USB_STAT1_RESUME				BIT_16			/* USB_RESUME */
+#define	USB_STAT1_MON_BUS_MSK			SHIFT0(0xffff)	/* USB MONITOR BUS */
+#define	USB_STAT1_MON_BUS_BASE			0
+
+/*	USB_IP_REV			0x22C0	USB PHY Revision Register */
+#define	USB_IP_REV_IP_REV_MSK			SHIFT16(0xffffUL)	/* udu2_phy_ip_rev */
+#define	USB_IP_REV_IP_REV_BASE			16
+#define	USB_IP_REV_MAC_IP_REV_MSK		SHIFT0(0xffff)	/* udu2_ip_rev */
+#define	USB_IP_REV_MAC_IP_REV_BASE		0
+
+/*	USB_PHY_CTRL		0x22C4	USB Control Register */
+#define	USB_PHY_CTRL_CTL_IPG_MSK			SHIFT30(0x3UL)	/* usb_ctl_ipg */
+#define	USB_PHY_CTRL_CTL_IPG_BASE			30
+#define	USB_PHY_CTRL_CTL_IPG_SOF_MSK		SHIFT28(0x3UL)	/* usb_ctl_ipg_sof */
+#define	USB_PHY_CTRL_CTL_IPG_SOF_BASE		28
+#define	USB_PHY_CTRL_CERR_COUNTER			BIT_27			/* CERR Counter */
+/*		Bit(s) USB_PHY_CTRL_RSRV_26_15 reserved */
+#define	USB_PHY_CTRL_DP_PULLDOWN			BIT_14			/* REG_DP_PULLDOWN */
+#define	USB_PHY_CTRL_DM_PULLDOWN			BIT_13			/* REG_DM_PULLDOWN */
+#define	USB_PHY_CTRL_ARC_DPDM_MODE			BIT_12			/* REG_ARC_DPDM_MODE */
+/*		Bit(s) USB_PHY_CTRL_RSRV_11_2 reserved */
+#define	USB_PHY_CTRL_PU_PLL					BIT_1			/* PU_PLL */
+#define	USB_PHY_CTRL_PU						BIT_0			/* PU */
+
+/*	USB_PHY_PLL			0x22C8	PLL Register */
+/*		Bit(s) USB_PHY_PLL_RSRV_31_28 reserved */
+#define	USB_PHY_PLL_ICHGPBUF_SEL		BIT_27			/* ICHGPBUF_SEL */
+#define	USB_PHY_PLL_VPLLCAL_MSK			SHIFT25(0x3UL)	/* VPLLCAL */
+#define	USB_PHY_PLL_VPLLCAL_BASE		25
+#define	USB_PHY_PLL_CLK_BLK_EN			BIT_24			/* CLK_BLK_EN */
+#define	USB_PHY_PLL_PLL_FBSPD_S			BIT_23			/* PLL_FBSPD_S */
+#define	USB_PHY_PLL_KVCO_EXT_			BIT_22			/* KVCO_EXT */
+#define	USB_PHY_PLL_VCOCAL_START		BIT_21			/* VCOCAL_START */
+#define	USB_PHY_PLL_VR_CPBUF_MSK		SHIFT19(0x3UL)	/* VR_CPBUF[1:0] */
+#define	USB_PHY_PLL_VR_CPBUF_BASE		19
+#define	USB_PHY_PLL_LOCKDET_ISEL		BIT_18			/* LOCKDET_ISEL */
+#define	USB_PHY_PLL_KVCO_MSK			SHIFT15(0x7UL)	/* KVCO[2:0] */
+#define	USB_PHY_PLL_KVCO_BASE			15
+#define	USB_PHY_PLL_ICP_MSK				SHIFT12(0x7)	/* ICP[2:0] */
+#define	USB_PHY_PLL_ICP_BASE			12
+#define	USB_PHY_PLL_FBDIV_MSK			SHIFT4(0xff)	/* FBDIV[8:0] */
+#define	USB_PHY_PLL_FBDIV_BASE			4
+#define	USB_PHY_PLL_REFDIV_MSK			SHIFT0(0xf)		/* REFDIV[1:0] */
+#define	USB_PHY_PLL_REFDIV_BASE			0
+
+/*	USB_PHY_TX			0x22CC	Tx Register */
+/*		Bit(s) USB_PHY_TX_RSRV_31_26 reserved */
+#define	USB_PHY_TX_HOST_DISCON_SEL1		BIT_25			/* REG_HOST_DISCON_SEL1 */
+#define	USB_PHY_TX_HOST_DISCON_SEL0		BIT_24			/* REG_HOST_DISCON_SEL0 */
+#define	USB_PHY_TX_TXVDRV_MSK			SHIFT22(0x3UL)	/* TXVDRV */
+#define	USB_PHY_TX_TXVDRV_BASE			22
+#define	USB_PHY_TX_TXDATA_BLOCK_EN		BIT_21			/* TXDATA_BLOCK_EN */
+#define	USB_PHY_TX_CK60_PHSEL_MSK		SHIFT17(0xfUL)	/* CK60_PHSEL */
+#define	USB_PHY_TX_CK60_PHSEL_BASE		17
+#define	USB_PHY_TX_IMPCAL_VTH_MSK		SHIFT14(0x7UL)	/* IMPCAL_VTH[2:0] */
+#define	USB_PHY_TX_IMPCAL_VTH_BASE		14
+#define	USB_PHY_TX_REG_EXT_RCAL_EN		BIT_13			/* REG_EXT_RCAL_EN */
+#define	USB_PHY_TX_REG_RCAL_START		BIT_12			/* REG_RCAL_START */
+#define	USB_PHY_TX_LOWVDD_EN			BIT_11			/* LOWVDD_EN */
+#define	USB_PHY_TX_HSDRV_EN_MSK			SHIFT7(0xf)		/* HSDRV_EN[3:0] */
+#define	USB_PHY_TX_HSDRV_EN_BASE		7
+/* IMP_CAL[3:0] (REG_EXT_RCAL[3:0]) */
+#define	USB_PHY_TX_IMP_CAL_MSK			SHIFT3(0xf)
+#define	USB_PHY_TX_IMP_CAL_BASE			3
+#define	USB_PHY_TX_AMP_MSK				SHIFT0(0x7)		/* AMP[2:0] */
+#define	USB_PHY_TX_AMP_BASE				0
+
+/*	USB_PHY_RX			0x22D0	Rx Register */
+/*		Bit(s) USB_PHY_RX_RSRV_31 reserved */
+#define	USB_PHY_RX_RXDATA_BLOCK_EN				BIT_30			/* RXDATA_BLOCK_EN */
+/* RXDATA_BLOCK_LENGTH[1:0] */
+#define	USB_PHY_RX_RXDATA_BLOCK_LENGTH_MSK		SHIFT28(0x3UL)
+#define	USB_PHY_RX_RXDATA_BLOCK_LENGTH_BASE		28
+#define	USB_PHY_RX_EDGE_DET_EN					BIT_27			/* EDGE_DET_EN */
+/* S2TO3_DLY_SEL[1:0] */
+#define	USB_PHY_RX_S2TO3_DLY_SEL_MSK			SHIFT25(0x3UL)
+#define	USB_PHY_RX_S2TO3_DLY_SEL_BASE			25
+/*		Bit(s) USB_PHY_RX_RSRV_24_23 reserved */
+#define	USB_PHY_RX_CDR_COEF_SEL					BIT_22			/* CDR_COEF_SEL */
+#define	USB_PHY_RX_CDR_FASTLOCK_EN				BIT_21			/* CDR_FASTLOCK_EN */
+#define	USB_PHY_RX_PHASE_FREEZE_DLY				BIT_20			/* PHASE_FREEZE_DLY */
+#define	USB_PHY_RX_REG_USQ_LENGTH				BIT_19			/* REG_USQ_LENGTH */
+/* REG_ACQ_LENGTH[1:0] */
+#define	USB_PHY_RX_REG_ACQ_LENGTH_MSK			SHIFT17(0x3UL)
+#define	USB_PHY_RX_REG_ACQ_LENGTH_BASE			17
+/* REG_SQ_LENGTH[1:0] */
+#define	USB_PHY_RX_REG_SQ_LENGTH_MSK			SHIFT15(0x3UL)
+#define	USB_PHY_RX_REG_SQ_LENGTH_BASE			15
+#define	USB_PHY_RX_DLL_SEL_MSK					SHIFT13(0x3)	/* DLL_SEL[1:0] */
+#define	USB_PHY_RX_DLL_SEL_BASE					13
+#define	USB_PHY_RX_CAP_SEL_MSK					SHIFT10(0x7)	/* CAP_SEL[2:0] */
+#define	USB_PHY_RX_CAP_SEL_BASE					10
+/* DISCON_THRESH[1:0] */
+#define	USB_PHY_RX_DISCON_THRESH_MSK			SHIFT8(0x3)
+#define	USB_PHY_RX_DISCON_THRESH_BASE			8
+#define	USB_PHY_RX_SQ_THRESH_MSK				SHIFT4(0xf)		/* SQ_THRESH[3:0] */
+#define	USB_PHY_RX_SQ_THRESH_BASE				4
+#define	USB_PHY_RX_LPF_COEF_MSK					SHIFT2(0x3)		/* LPF_COEF[1:0] */
+#define	USB_PHY_RX_LPF_COEF_BASE				2
+#define	USB_PHY_RX_INTPI_MSK					SHIFT0(0x3)		/* INTPI[1:0] */
+#define	USB_PHY_RX_INTPI_BASE					0
+
+/*	USB_PHY_IVREF		0x22D4	IVREF Register */
+/*		Bit(s) USB_PHY_IVREF_RSRV_31_14 reserved */
+#define	USB_PHY_IVREF_SAMPLER_CTRL			BIT_13				/* SAMPLER_CTRL */
+#define	USB_PHY_IVREF_ISAMPLE_SEL_MSK		SHIFT11(0x3)		/* ISAMPLE_SEL */
+#define	USB_PHY_IVREF_ISAMPLE_SEL_BASE		11
+#define	USB_PHY_IVREF_EARLY_VOS_ON_EN		BIT_10				/* EARLY_VOS_ON_EN */
+/* EDGE_DET_SEL[1:0] */
+#define	USB_PHY_IVREF_EDGE_DET_SEL_MSK		SHIFT8(0x3)
+#define	USB_PHY_IVREF_EDGE_DET_SEL_BASE		8
+/*		Bit(s) USB_PHY_IVREF_RSRV_7_6 reserved */
+#define	USB_PHY_IVREF_RXVDD_MSK				SHIFT4(0x3)			/* RXVDD[1:0] */
+#define	USB_PHY_IVREF_RXVDD_BASE			4
+#define	USB_PHY_IVREF_PLLVDD15_MSK			SHIFT2(0x3)			/* PLLVDD15[1:0] */
+#define	USB_PHY_IVREF_PLLVDD15_BASE			2
+#define	USB_PHY_IVREF_PLLVDD12_MSK			SHIFT0(0x3)			/* PLLVDD12[1:0] */
+#define	USB_PHY_IVREF_PLLVDD12_BASE			0
+
+/*	USB_PHY_TEST_GRP_0	0x22D8	Test Group 0 Register */
+#define	USB_PHY_TEST_GRP_0_FIFO_OV					BIT_31			/* REG_FIFO_OV */
+#define	USB_PHY_TEST_GRP_0_FIFO_UF					BIT_30			/* REG_FIFO_UF */
+/*		Bit(s) USB_PHY_TEST_GRP_0_RSRV_29 reserved */
+/* REG_ARC_DPDM_MODE */
+#define	USB_PHY_TEST_GRP_0_ARC_DPDM_MODE			BIT_28
+/* REG_DP_PULLDOWN */
+#define	USB_PHY_TEST_GRP_0_DP_PULLDOWN				BIT_27
+/* REG_DM_PULLDOWN */
+#define	USB_PHY_TEST_GRP_0_DM_PULLDOWN				BIT_26
+/* REG_FIFO_S2P_SEL */
+#define	USB_PHY_TEST_GRP_0_FIFO_S2P_SEL				BIT_25
+/* REG_FIFO_FILL_NUM */
+#define	USB_PHY_TEST_GRP_0_FIFO_FILL_NUM_MSK		SHIFT21(0xfUL)
+#define	USB_PHY_TEST_GRP_0_FIFO_FILL_NUM_BASE		21
+/* REG_SQ_SYNC_SEL */
+#define	USB_PHY_TEST_GRP_0_SQ_SYNC_SEL				BIT_20
+/* REG_FIFO_FILL_SEL */
+#define	USB_PHY_TEST_GRP_0_FIFO_FILL_SEL			BIT_19
+/* REG_FIFO_OVUF_SEL */
+#define	USB_PHY_TEST_GRP_0_FIFO_OVUF_SEL			BIT_18
+#define	USB_PHY_TEST_GRP_0_UTMI_LAT					BIT_17			/* REG_UTMI_LAT */
+#define	USB_PHY_TEST_GRP_0_FIFO_SP					BIT_16			/* REG_FIFO_SP */
+/* REG_FIFO_SQ_RST */
+#define	USB_PHY_TEST_GRP_0_FIFO_SQ_RST				BIT_15
+/* REG_CLK_OUT_SEL */
+#define	USB_PHY_TEST_GRP_0_CLK_OUT_SEL				BIT_14
+/* REG_EARLY_TX_ENABLE */
+#define	USB_PHY_TEST_GRP_0_EARLY_TX_ENABLE			BIT_13
+/* REG_OVUF_RST_EN */
+#define	USB_PHY_TEST_GRP_0_OVUF_RST_EN				BIT_12
+/* REG_EOP_RST_EN */
+#define	USB_PHY_TEST_GRP_0_EOP_RST_EN				BIT_11
+/* REG_SYNC_NUM[1:0] */
+#define	USB_PHY_TEST_GRP_0_SYNC_NUM_MSK				SHIFT9(0x3)
+#define	USB_PHY_TEST_GRP_0_SYNC_NUM_BASE			9
+/* REG_TEST_FIFO_R_POL */
+#define	USB_PHY_TEST_GRP_0_TEST_FIFO_R_POL			BIT_8
+/* REG_TEST_FIFO_W_POL */
+#define	USB_PHY_TEST_GRP_0_TEST_FIFO_W_POL			BIT_7
+/* REG_TEST_FIFO_EN */
+#define	USB_PHY_TEST_GRP_0_TEST_FIFO_EN				BIT_6
+#define	USB_PHY_TEST_GRP_0_TESTMON_MSK				SHIFT0(0x3f)	/* TESTMON[5:0] */
+#define	USB_PHY_TEST_GRP_0_TESTMON_BASE				0
+
+/*	USB_PHY_TEST_GRP_1	0x22DC	Test Group 1 Register */
+/* REG_HS_HDL_SYNC */
+#define	USB_PHY_TEST_GRP_1_HS_HDL_SYNC				BIT_31
+/* REG_FS_HDL_OPMD */
+#define	USB_PHY_TEST_GRP_1_FS_HDL_OPMD				BIT_30
+/* REG_PAD_STRENGTH[4:0] */
+#define	USB_PHY_TEST_GRP_1_PAD_STRENGTH_MSK			SHIFT25(0x1fUL)
+#define	USB_PHY_TEST_GRP_1_PAD_STRENGTH_BASE		25
+/* REG_MON_SEL[3:0] */
+#define	USB_PHY_TEST_GRP_1_MON_SEL_MSK				SHIFT21(0xfUL)
+#define	USB_PHY_TEST_GRP_1_MON_SEL_BASE				21
+/* REG_TEST_DIG_LPBK */
+#define	USB_PHY_TEST_GRP_1_TEST_DIG_LPBK			BIT_20
+/* REG_TEST_SKIP[2:0] */
+#define	USB_PHY_TEST_GRP_1_TEST_SKIP_MSK			SHIFT17(0x7UL)
+#define	USB_PHY_TEST_GRP_1_TEST_SKIP_BASE			17
+/* REG_TEST_FLAG */
+#define	USB_PHY_TEST_GRP_1_TEST_FLAG				BIT_16
+/* REG_TEST_DONE */
+#define	USB_PHY_TEST_GRP_1_TEST_DONE				BIT_15
+/* REG_TEST_LENGTH[1:0] */
+#define	USB_PHY_TEST_GRP_1_TEST_LENGTH_MSK			SHIFT13(0x3)
+#define	USB_PHY_TEST_GRP_1_TEST_LENGTH_BASE			13
+/* REG_TEST_TX_PATTERN[7:0] */
+#define	USB_PHY_TEST_GRP_1_TEST_TX_PATTERN_MSK		SHIFT5(0xff)
+#define	USB_PHY_TEST_GRP_1_TEST_TX_PATTERN_BASE		5
+/* REG_TEST_MODE[1:0] */
+#define	USB_PHY_TEST_GRP_1_TEST_MODE_MSK			SHIFT3(0x3)
+#define	USB_PHY_TEST_GRP_1_TEST_MODE_BASE			3
+/* REG_TEST_LPBK_EN */
+#define	USB_PHY_TEST_GRP_1_TEST_LPBK_EN				BIT_2
+/* REG_TEST_BYPASS */
+#define	USB_PHY_TEST_GRP_1_TEST_BYPASS				BIT_1
+#define	USB_PHY_TEST_GRP_1_TEST_EN					BIT_0			/* REG_TEST_EN */
+
+/*	USB_PHY_TEST_GRP_2	0x22E0	Test Group 2 Register */
+/* REG_TEST_FIFO_R_PNT[15:0] */
+#define	USB_PHY_TEST_GRP_2_TEST_FIFO_R_PNT_MSK		SHIFT16(0xffffUL)
+#define	USB_PHY_TEST_GRP_2_TEST_FIFO_R_PNT_BASE		16
+/* REG_TEST_FIFO_W_PNT[15:0] */
+#define	USB_PHY_TEST_GRP_2_TEST_FIFO_W_PNT_MSK		SHIFT0(0xffff)
+#define	USB_PHY_TEST_GRP_2_TEST_FIFO_W_PNT_BASE		0
+
+/*	USB_PHY_ID_GRP		0x22E4	ID Group Register */
+#define	USB_PHY_ID_GRP_RESERVE_MSK		SHIFT16(0x3ffUL)	/* RESERVE[9:0] */
+#define	USB_PHY_ID_GRP_RESERVE_BASE		16
+#define	USB_PHY_ID_GRP_RESV_ID_MSK		SHIFT0(0xffffU)	/* RESV_ID[15:0] */
+#define	USB_PHY_ID_GRP_RESV_ID_BASE		0
+
+/*	USB_INT1			0x22E8	USB Internal Register 1 */
+/*		Bit(s) USB_INT1_RSRV_31_4 reserved */
+#define	USB_INT1_LINE_INT_REG		BIT_3				/* Line Act Interrupt */
+/*		Bit(s) USB_INT1_RSRV_2 reserved */
+/* Line Act Interrupt Enable */
+#define	USB_INT1_LINE_INT_EN		BIT_1
+/* Interrupt from ARC Device Controller */
+#define	USB_INT1_INT_USB_MAC		BIT_0
+
+/*	USB_INT2			0x22EC	USB Internal Register 2 */
+#define	USB_INT2_DEG_MON_MSK		SHIFT16(0xffffUL)	/* USB Debug MON */
+#define	USB_INT2_DEG_MON_BASE		16
+#define	USB_INT2_DEG_CTRL_MSK		SHIFT0(0xffff)	/* USB Debug Control */
+#define	USB_INT2_DEG_CTRL_BASE		0
+
+/*	USB_ID				0x2300	Identification Register */
+/*		Bit(s) USB_ID_RSRV_31_24 reserved */
+#define	USB_ID_REVISION_MSK			SHIFT16(0xffUL)	/* REVISION[7:0] */
+#define	USB_ID_REVISION_BASE		16
+/*		Bit(s) USB_ID_RSRV_15_14 reserved */
+#define	USB_ID_NID_MSK				SHIFT8(0x3f)	/* NID[5:0] */
+#define	USB_ID_NID_BASE				8
+/*		Bit(s) USB_ID_RSRV_7_6 reserved */
+#define	USB_ID_ID_MSK				SHIFT0(0x3f)	/* ID[5:0] */
+#define	USB_ID_ID_BASE				0
+
+/*	USB_HWGENERAL		0x2304	General Hardware Parameters Register */
+/*		Bit(s) USB_HWGENERAL_RSRV_31_10 reserved */
+#define	USB_HWGENERAL_SM					BIT_9				/* SM */
+#define	USB_HWGENERAL_PHYM_MSK				SHIFT6(0x7)			/* PHYM */
+#define	USB_HWGENERAL_PHYM_BASE				6
+#define	USB_HWGENERAL_PHYW_MSK				SHIFT4(0x3)			/* PHYW */
+#define	USB_HWGENERAL_PHYW_BASE				4
+#define	USB_HWGENERAL_BWT					BIT_3				/* BWT */
+#define	USB_HWGENERAL_CLKC_MSK				SHIFT1(0x3)			/* CLKC */
+#define	USB_HWGENERAL_CLKC_BASE				1
+#define	USB_HWGENERAL_RT					BIT_0				/* RT */
+
+/*	USB_HWHOST			0x2308	Host Hardware Parameters Register */
+#define	USB_HWHOST_TTPER_MSK			SHIFT24(0xffUL)	/* TTPER */
+#define	USB_HWHOST_TTPER_BASE			24
+#define	USB_HWHOST_TTASY_MSK			SHIFT16(0xffUL)	/* TTASY */
+#define	USB_HWHOST_TTASY_BASE			16
+/*		Bit(s) USB_HWHOST_RSRV_15_4 reserved */
+#define	USB_HWHOST_NPORT_MSK			SHIFT1(0x7)		/* NPORT */
+#define	USB_HWHOST_NPORT_BASE			1
+#define	USB_HWHOST_HC					BIT_0			/* HC */
+
+/*	USB_HWDEVICE		0x230C	Device Hardware Parameters Register */
+/*		Bit(s) USB_HWDEVICE_RSRV_31_6 reserved */
+#define	USB_HWDEVICE_DEVEP_MSK			SHIFT1(0x1f)		/* DEVEP */
+#define	USB_HWDEVICE_DEVEP_BASE			1
+#define	USB_HWDEVICE_DC					BIT_0				/* DC */
+
+/*	USB_HWTXBUF			0x2310	TX Buffer Hardware Parameters Register */
+#define	USB_HWTXBUF_TXLC				BIT_31			/* TXLC */
+/*		Bit(s) USB_HWTXBUF_RSRV_30_24 reserved */
+#define	USB_HWTXBUF_TXCHANADD_MSK		SHIFT16(0xffUL)	/* TXCHANADD */
+#define	USB_HWTXBUF_TXCHANADD_BASE		16
+#define	USB_HWTXBUF_TXADD_MSK			SHIFT8(0xff)	/* TXADD */
+#define	USB_HWTXBUF_TXADD_BASE			8
+#define	USB_HWTXBUF_TCBURST_MSK			SHIFT0(0xff)	/* TCBURST */
+#define	USB_HWTXBUF_TCBURST_BASE		0
+
+/*	USB_HWRXBUF			0x2314	RX Buffer Hardware Parameters Register */
+/*		Bit(s) USB_HWRXBUF_RSRV_31_16 reserved */
+#define	USB_HWRXBUF_RXADD_MSK			SHIFT8(0xff)	/* RXADD */
+#define	USB_HWRXBUF_RXADD_BASE			8
+#define	USB_HWRXBUF_RXBURST_MSK			SHIFT0(0xff)	/* RXBURST */
+#define	USB_HWRXBUF_RXBURST_BASE		0
+
+/*	USB_CAPLENGTH		0x2400	Capability Register Length - EHCI Compliant
+ *								Register
+ */
+/*		Bit(s) USB_CAPLENGTH_RSRV_15_8 reserved */
+#define	USB_CAPLENGTH_CAPLENGTH_MSK			SHIFT0(0xffU)	/* CAPLENGTH */
+#define	USB_CAPLENGTH_CAPLENGTH_BASE		0
+
+/*	USB_DCIVERSION		0x2420	Dev. Interface Version Number Register */
+/*		Bit(s) USB_DCIVERSION_RSRV_31_16 reserved */
+#define	USB_DCIVERSION_DCIVERSION_MSK		SHIFT0(0xffff)	/* DCIVERSION */
+#define	USB_DCIVERSION_DCIVERSION_BASE		0
+
+/*	USB_DCCPARAMS		0x2424	Device Ctrl. Capability Parameters Register */
+/*		Bit(s) USB_DCCPARAMS_RSRV_31_9 reserved */
+#define	USB_DCCPARAMS_HC					BIT_8				/* HC */
+#define	USB_DCCPARAMS_DC					BIT_7				/* DC */
+/*		Bit(s) USB_DCCPARAMS_RSRV_6_5 reserved */
+#define	USB_DCCPARAMS_DEN_MSK				SHIFT0(0x1f)		/* DEN[4:0] */
+#define	USB_DCCPARAMS_DEN_BASE				0
+
+/*	USB_CMD				0x2440	USB Command Register */
+/*		Bit(s) USB_CMD_RSRV_31_24 reserved */
+#define	USB_CMD_ITC_MSK				SHIFT16(0xffUL)	/* ITC[7:0] */
+#define	USB_CMD_ITC_BASE			16
+/*		Bit(s) USB_CMD_RSRV_15 reserved */
+#define	USB_CMD_ATDTW				BIT_14			/* ATDTW */
+#define	USB_CMD_SUTW				BIT_13			/* SUTW */
+/*		Bit(s) USB_CMD_RSRV_12_2 reserved */
+#define	USB_CMD_RST					BIT_1			/* RST */
+#define	USB_CMD_RS					BIT_0			/* RS */
+
+/*	USB_STS				0x2444	USB Status Register */
+/*		Bit(s) USB_STS_RSRV_31_17 reserved */
+#define	USB_STS_NAKI				BIT_16			/* NAKI */
+#define	USB_STS_AS					BIT_15			/* AS */
+#define	USB_STS_PS					BIT_14			/* PS */
+#define	USB_STS_RCL					BIT_13			/* RCL */
+#define	USB_STS_HCH					BIT_12			/* HCH */
+/*		Bit(s) USB_STS_RSRV_11 reserved */
+#define	USB_STS_ULPII				BIT_10			/* ULPII */
+/*		Bit(s) USB_STS_RSRV_9 reserved */
+#define	USB_STS_SLI					BIT_8			/* SLI */
+#define	USB_STS_SRI					BIT_7			/* SRI */
+#define	USB_STS_URI					BIT_6			/* URI */
+#define	USB_STS_AAI					BIT_5			/* AAI 0B-08H */
+#define	USB_STS_SEI					BIT_4			/* SEI */
+#define	USB_STS_FRI					BIT_3			/* FRI */
+#define	USB_STS_PCI					BIT_2			/* PCI */
+#define	USB_STS_UEI					BIT_1			/* UEI */
+#define	USB_STS_UI					BIT_0			/* UI */
+
+/*	USB_INTR			0x2448	USB Interrupt Enable Register */
+/*		Bit(s) USB_INTR_RSRV_31_17 reserved */
+#define	USB_INTR_NAKE					BIT_16			/* NAKE */
+/*		Bit(s) USB_INTR_RSRV_15_11 reserved */
+#define	USB_INTR_ULPIE					BIT_10			/* ULPIE */
+/*		Bit(s) USB_INTR_RSRV_9 reserved */
+#define	USB_INTR_SLE					BIT_8			/* SLE */
+#define	USB_INTR_SRE					BIT_7			/* SRE */
+#define	USB_INTR_URE					BIT_6			/* URE */
+/*		Bit(s) USB_INTR_RSRV_5 reserved */
+#define	USB_INTR_SEE					BIT_4			/* SEE */
+/*		Bit(s) USB_INTR_RSRV_3 reserved */
+#define	USB_INTR_PCE					BIT_2			/* PCE */
+#define	USB_INTR_UEE					BIT_1			/* UEE */
+#define	USB_INTR_UE						BIT_0			/* UE */
+
+/*	USB_FRINDEX			0x244C	USB Frame Index Register */
+/*		Bit(s) USB_FRINDEX_RSRV_31_14 reserved */
+#define	USB_FRINDEX_FRINDEX_MSK			SHIFT0(0x3fff)		/* FRINDEX */
+#define	USB_FRINDEX_FRINDEX_BASE		0
+
+/*	USB_DEVICEADDR		0x2454	Device Controller USB Device Address Register
+ *								(Device Mode)
+ */
+#define	USB_DEVICEADDR_USBADR_MSK			SHIFT25(0x7fUL)		/* USBADR */
+#define	USB_DEVICEADDR_USBADR_BASE			25
+/*		Bit(s) USB_DEVICEADDR_RSRV_24_0 reserved */
+
+/*	USB_EP_LISTADDR		0x2458	Address at Endpoint List in Memory Register */
+#define	USB_EP_LISTADDR_EPBASE_MSK			SHIFT11(0x1fffffUL)	/* EPBASE[31:11] */
+#define	USB_EP_LISTADDR_EPBASE_BASE			11
+/*		Bit(s) USB_EP_LISTADDR_RSRV_10_0 reserved */
+
+/*	USB_BURSTSIZE		0x2460	Programmable Burst Size Register - Host
+ *								Controller
+ */
+/*		Bit(s) USB_BURSTSIZE_RSRV_31_16 reserved */
+#define	USB_BURSTSIZE_TXPBURST_MSK			SHIFT8(0xff)	/* TXPBURST */
+#define	USB_BURSTSIZE_TXPBURST_BASE			8
+#define	USB_BURSTSIZE_RXPBURST_MSK			SHIFT0(0xff)	/* RXPBURST */
+#define	USB_BURSTSIZE_RXPBURST_BASE			0
+
+/*	USB_ENDPTNAK		0x2478	Endpoint NAK Register */
+#define	USB_ENDPTNAK_EPTN_MSK		SHIFT16(0xffffUL)	/* EPTN [15:0] */
+#define	USB_ENDPTNAK_EPTN_BASE		16
+#define	USB_ENDPTNAK_EPRN_MSK		SHIFT0(0xffff)	/* EPRN [15:0] */
+#define	USB_ENDPTNAK_EPRN_BASE		0
+
+/*	USB_PORTSC			0x2484	Port Status/Control Register */
+#define	USB_PORTSC_PTS_MSK				SHIFT30(0x3UL)	/* PTS */
+#define	USB_PORTSC_PTS_BASE				30
+#define	USB_PORTSC_STS					BIT_29			/* STS */
+#define	USB_PORTSC_PTW					BIT_28			/* PTW */
+#define	USB_PORTSC_PSPD_MSK				SHIFT26(0x3UL)	/* PSPD */
+#define	USB_PORTSC_PSPD_BASE			26
+/*		Bit(s) USB_PORTSC_RSRV_25 reserved */
+#define	USB_PORTSC_PFSC					BIT_24			/* PFSC */
+#define	USB_PORTSC_PHCD					BIT_23			/* PHCD */
+/*		Bit(s) USB_PORTSC_RSRV_22_20 reserved */
+#define	USB_PORTSC_PTC_MSK				SHIFT16(0xfUL)	/* PTC[3:0] */
+#define	USB_PORTSC_PTC_BASE				16
+/*		Bit(s) USB_PORTSC_RSRV_15_12 reserved */
+#define	USB_PORTSC_LS_MSK				SHIFT10(0x3)	/* LS[1:0] */
+#define	USB_PORTSC_LS_BASE				10
+#define	USB_PORTSC_HSP					BIT_9			/* HSP */
+#define	USB_PORTSC_PR					BIT_8			/* PR */
+#define	USB_PORTSC_SUSP					BIT_7			/* SUSP */
+#define	USB_PORTSC_FPR					BIT_6			/* FPR */
+/*		Bit(s) USB_PORTSC_RSRV_5_3 reserved */
+#define	USB_PORTSC_PE					BIT_2			/* PE */
+/*		Bit(s) USB_PORTSC_RSRV_1 reserved */
+#define	USB_PORTSC_CCS					BIT_0			/* CCS */
+
+/*	USB_MODE			0x24A8	USB Device Mode Register */
+/*		Bit(s) USB_MODE_RSRV_31_5 reserved */
+#define	USB_MODE_SDIS				BIT_4				/* SDIS */
+#define	USB_MODE_SLOM				BIT_3				/* SLOM */
+#define	USB_MODE_ES					BIT_2				/* ES */
+#define	USB_MODE_CM_MSK				SHIFT0(0x3)			/* CM[1:0] */
+#define	USB_MODE_CM_BASE			0
+
+/*	USB_ENDPTSETUPSTAT	0x24AC	Endpoint Setup Status Register */
+/*		Bit(s) USB_ENDPTSETUPSTAT_RSRV_31_16 reserved */
+/* Setup Endpoint Status */
+#define	USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT150_MSK		SHIFT0(0xffff)
+#define	USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT150_BASE		0
+
+/*	USB_ENDPTPRIME		0x24B0	Endpoint Initialization Register */
+/*		Bit(s) USB_ENDPTPRIME_RSRV_31_22 reserved */
+#define	USB_ENDPTPRIME_PETB_MSK				SHIFT16(0x3fUL)	/* PETB [5:0] */
+#define	USB_ENDPTPRIME_PETB_BASE			16
+/*		Bit(s) USB_ENDPTPRIME_RSRV_15_6 reserved */
+#define	USB_ENDPTPRIME_PERB_MSK				SHIFT0(0x3f)	/* PERB [5:0] */
+#define	USB_ENDPTPRIME_PERB_BASE			0
+
+/*	USB_ENDPTFLUSH		0x24B4	Endpoint De-Initialize Register */
+/*		Bit(s) USB_ENDPTFLUSH_RSRV_31_22 reserved */
+#define	USB_ENDPTFLUSH_FETB_MSK				SHIFT16(0x3fUL)	/* FETB [5:0] */
+#define	USB_ENDPTFLUSH_FETB_BASE			16
+/*		Bit(s) USB_ENDPTFLUSH_RSRV_15_6 reserved */
+#define	USB_ENDPTFLUSH_FERB_MSK				SHIFT0(0x3f)	/* FERB [5:0] */
+#define	USB_ENDPTFLUSH_FERB_BASE			0
+
+/*	USB_ENDPTSTAT		0x24B8	Endpoint STAT Register */
+/*		Bit(s) USB_ENDPTSTAT_RSRV_31_22 reserved */
+#define	USB_ENDPTSTAT_ETBR_MSK				SHIFT16(0x3fUL)	/* ETBR [5:0] */
+#define	USB_ENDPTSTAT_ETBR_BASE				16
+/*		Bit(s) USB_ENDPTSTAT_RSRV_15_6 reserved */
+#define	USB_ENDPTSTAT_ERBR_MSK				SHIFT0(0x3f)	/* ERBR [5:0] */
+#define	USB_ENDPTSTAT_ERBR_BASE				0
+
+/*	USB_EP_COMPL		0x24BC	Endpoint Complete Register */
+/*		Bit(s) USB_EP_COMPL_RSRV_31_22 reserved */
+#define	USB_EP_COMPL_ETCE_MSK				SHIFT16(0x3fUL)	/* ETCE [5:0] */
+#define	USB_EP_COMPL_ETCE_BASE				16
+/*		Bit(s) USB_EP_COMPL_RSRV_15_6 reserved */
+#define	USB_EP_COMPL_ERCE_MSK				SHIFT0(0x3f)	/* ERCE [5:0] */
+#define	USB_EP_COMPL_ERCE_BASE				0
+
+/*	USB_ENDPTCTRL0		0x24C0	Endpoint Control 0 Register */
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_31_24 reserved */
+#define	USB_ENDPTCTRL0_TXE					BIT_23			/* TXE */
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_22_20 reserved */
+#define	USB_ENDPTCTRL0_TXT_MSK				SHIFT18(0x3UL)	/* TXT[1:0] */
+#define	USB_ENDPTCTRL0_TXT_BASE				18
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_17 reserved */
+#define	USB_ENDPTCTRL0_TXS					BIT_16			/* TXS */
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_15_8 reserved */
+#define	USB_ENDPTCTRL0_RXE					BIT_7			/* RXE */
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_6_4 reserved */
+#define	USB_ENDPTCTRL0_RXT_MSK				SHIFT2(0x3)		/* RXT[1:0] */
+#define	USB_ENDPTCTRL0_RXT_BASE				2
+/*		Bit(s) USB_ENDPTCTRL0_RSRV_1 reserved */
+#define	USB_ENDPTCTRL0_RXS					BIT_0			/* RXS */
+
+/*	SIU_RBR				0x2500	Receive Buffer Register */
+/*		Bit(s) SIU_RBR_RSRV_31_8 reserved */
+#define	SIU_RBR_RBR_MSK				SHIFT0(0xff)		/* RBR[7:0] */
+#define	SIU_RBR_RBR_BASE			0
+
+/*	SIU_THR				0x2500	Transmit Holding Register */
+/*		Bit(s) SIU_THR_RSRV_31_8 reserved */
+#define	SIU_THR_THR_MSK				SHIFT0(0xff)		/* THR[7:0] */
+#define	SIU_THR_THR_BASE			0
+
+/*	SIU_DLL				0x2500	Divisor Latch Low Register */
+/*		Bit(s) SIU_DLL_RSRV_31_8 reserved */
+#define	SIU_DLL_DLL_MSK				SHIFT0(0xff)		/* DLL[7:0] */
+#define	SIU_DLL_DLL_BASE			0
+
+/*	SIU_DLH				0x2504	Divisor Latch High Register */
+/*		Bit(s) SIU_DLH_RSRV_31_8 reserved */
+#define	SIU_DLH_DLH_MSK				SHIFT0(0xff)		/* DLH[7:0] */
+#define	SIU_DLH_DLH_BASE			0
+
+/*	SIU_IER				0x2504	Interrupt Enable Register */
+/*		Bit(s) SIU_IER_RSRV_31_8 reserved */
+#define	SIU_IER_PTIME				BIT_7				/* PTIME */
+/*		Bit(s) SIU_IER_RSRV_6_4 reserved */
+#define	SIU_IER_EDSSI				BIT_3				/* EDSSI */
+#define	SIU_IER_ELSI				BIT_2				/* ELSI */
+#define	SIU_IER_ETBEI				BIT_1				/* ETBEI */
+#define	SIU_IER_ERBFI				BIT_0				/* ERBFI */
+
+/*	SIU_IIR				0x2508	Interrupt Identity Register */
+/*		Bit(s) SIU_IIR_RSRV_31_8 reserved */
+#define	SIU_IIR_FIFOSE_MSK			SHIFT6(0x3)			/* FIFOSE[1:0] */
+#define	SIU_IIR_FIFOSE_BASE			6
+/*		Bit(s) SIU_IIR_RSRV_5_4 reserved */
+#define	SIU_IIR_IID_MSK				SHIFT0(0xf)			/* IID[3:0] */
+#define	SIU_IIR_IID_BASE			0
+
+/*	SIU_FCR				0x2508	FIFO Control Register */
+/*		Bit(s) SIU_FCR_RSRV_31_8 reserved */
+#define	SIU_FCR_RT_MSK				SHIFT6(0x3)			/* RT[1:0] */
+#define	SIU_FCR_RT_BASE				6
+#define	SIU_FCR_TET_MSK				SHIFT4(0x3)			/* TET[1:0] */
+#define	SIU_FCR_TET_BASE			4
+#define	SIU_FCR_DMAM				BIT_3				/* DMAM */
+#define	SIU_FCR_XFIFOR				BIT_2				/* XFIFOR */
+#define	SIU_FCR_RFIFOR				BIT_1				/* RFIFOR */
+#define	SIU_FCR_FIFOE				BIT_0				/* FIFOE */
+
+/*	SIU_LCR				0x250C	Line Control Register */
+/*		Bit(s) SIU_LCR_RSRV_31_8 reserved */
+#define	SIU_LCR_DLAB				BIT_7				/* DLAB */
+#define	SIU_LCR_BC					BIT_6				/* BC */
+/*		Bit(s) SIU_LCR_RSRV_5 reserved */
+#define	SIU_LCR_EPS					BIT_4				/* EPS */
+#define	SIU_LCR_PEN					BIT_3				/* PEN */
+#define	SIU_LCR_STOP				BIT_2				/* STOP */
+#define	SIU_LCR_DLS_MSK				SHIFT0(0x3)			/* DLS[1:0] */
+#define	SIU_LCR_DLS_BASE			0
+
+/*	SIU_MCR				0x2510	Modem Control Register */
+/*		Bit(s) SIU_MCR_RSRV_31_7 reserved */
+#define	SIU_MCR_SIRE				BIT_6				/* SIRE */
+#define	SIU_MCR_AFCE				BIT_5				/* AFCE */
+#define	SIU_MCR_LB					BIT_4				/* LB */
+#define	SIU_MCR_OUT2				BIT_3				/* OUT2 */
+#define	SIU_MCR_OUT1				BIT_2				/* OUT1 */
+#define	SIU_MCR_RTS					BIT_1				/* RTS */
+#define	SIU_MCR_DTR					BIT_0				/* DTR */
+
+/*	SIU_LSR				0x2514	Line Status Register */
+/*		Bit(s) SIU_LSR_RSRV_31_8 reserved */
+#define	SIU_LSR_RFE					BIT_7				/* RFE */
+#define	SIU_LSR_TEMT				BIT_6				/* TEMT */
+#define	SIU_LSR_THRE				BIT_5				/* THRE */
+#define	SIU_LSR_BI					BIT_4				/* BI */
+#define	SIU_LSR_FE					BIT_3				/* FE */
+#define	SIU_LSR_PE					BIT_2				/* PE */
+#define	SIU_LSR_OE					BIT_1				/* OE */
+#define	SIU_LSR_DR					BIT_0				/* DR */
+
+/*	SIU_MSR				0x2518	Modem Status Register */
+/*		Bit(s) SIU_MSR_RSRV_31_8 reserved */
+#define	SIU_MSR_DCD					BIT_7				/* DCD */
+#define	SIU_MSR_RI					BIT_6				/* RI */
+#define	SIU_MSR_DSR					BIT_5				/* DSR */
+#define	SIU_MSR_CTS					BIT_4				/* CTS */
+#define	SIU_MSR_DDCD				BIT_3				/* DDCD */
+#define	SIU_MSR_TERI				BIT_2				/* TERI */
+#define	SIU_MSR_DDSR				BIT_1				/* DDSR */
+#define	SIU_MSR_DCTS				BIT_0				/* DCTS */
+
+/*	SIU_SCR				0x251C	Scratchpad Register */
+/*		Bit(s) SIU_SCR_RSRV_31_8 reserved */
+#define	SIU_SCR_SCRATCHPAD_MSK		SHIFT0(0xff)		/* Scratchpad[7:0] */
+#define	SIU_SCR_SCRATCHPAD_BASE		0
+
+/*	SIU_FAR				0x2570	FIFO Access Register */
+/*		Bit(s) SIU_FAR_RSRV_31_1 reserved */
+#define	SIU_FAR_FAR					BIT_0				/* FAR */
+
+/*	SIU_TFR				0x2574	Transmit FIFO Read */
+/*		Bit(s) SIU_TFR_RSRV_31_8 reserved */
+#define	SIU_TFR_TFR_MSK				SHIFT0(0xff)		/* TFR[7:0] */
+#define	SIU_TFR_TFR_BASE			0
+
+/*	SIU_RFW				0x2578	Receive FIFO Write */
+/*		Bit(s) SIU_RFW_RSRV_31_10 reserved */
+#define	SIU_RFW_RFFE				BIT_9				/* RFFE */
+#define	SIU_RFW_RFPE				BIT_8				/* RFPE */
+#define	SIU_RFW_RFWD_MSK			SHIFT0(0xff)		/* RFWD[7:0] */
+#define	SIU_RFW_RFWD_BASE			0
+
+/*	SIU_USR				0x257C	UART Status Register */
+/*		Bit(s) SIU_USR_RSRV_31_5 reserved */
+#define	SIU_USR_RFF					BIT_4				/* RFF */
+#define	SIU_USR_RFNE				BIT_3				/* RFNE */
+#define	SIU_USR_TFE					BIT_2				/* TFE */
+#define	SIU_USR_TFNF				BIT_1				/* TFNF */
+#define	SIU_USR_BUSY				BIT_0				/* BUSY */
+
+/*	SIU_TFL				0x2580	Transmit FIFO Level */
+/*		Bit(s) SIU_TFL_RSRV_31_8 reserved */
+#define	SIU_TFL_TFL_MSK				SHIFT0(0xff)		/* TFL */
+#define	SIU_TFL_TFL_BASE			0
+
+/*	SIU_RFL				0x2584	Receive FIFO Level */
+/*		Bit(s) SIU_RFL_RSRV_31_6 reserved */
+#define	SIU_RFL_RFL_MSK				SHIFT0(0x3f)		/* RFL */
+#define	SIU_RFL_RFL_BASE			0
+
+/*	SIU_SRR				0x2588	Software Reset Register */
+/*		Bit(s) SIU_SRR_RSRV_31_3 reserved */
+#define	SIU_SRR_XFR					BIT_2				/* XFR */
+#define	SIU_SRR_RFR					BIT_1				/* RFR */
+#define	SIU_SRR_UR					BIT_0				/* UR */
+
+/*	SIU_SRTS			0x258C	Shadow Request to Send */
+/*		Bit(s) SIU_SRTS_RSRV_31_1 reserved */
+#define	SIU_SRTS_SRTS				BIT_0				/* SRTS */
+
+/*	SIU_SBCR			0x2590	Shadow Break Control Register */
+/*		Bit(s) SIU_SBCR_RSRV_31_1 reserved */
+#define	SIU_SBCR_SBCR				BIT_0				/* SBCR */
+
+/*	SIU_SDMAM			0x2594	Shadow DMA Mode */
+/*		Bit(s) SIU_SDMAM_RSRV_31_1 reserved */
+#define	SIU_SDMAM_SDMAM					BIT_0				/* SDMAM */
+
+/*	SIU_SFE				0x2598	Shadow FIFO Enable */
+/*		Bit(s) SIU_SFE_RSRV_31_1 reserved */
+#define	SIU_SFE_SFE					BIT_0				/* SFE */
+
+/*	SIU_SRT				0x259C	Shadow RCVR Trigger */
+/*		Bit(s) SIU_SRT_RSRV_31_2 reserved */
+#define	SIU_SRT_SRT_MSK				SHIFT0(0x3)			/* SRT[1:0] */
+#define	SIU_SRT_SRT_BASE			0
+
+/*	SIU_STET			0x25A0	Shadow TX Empty Trigger */
+/*		Bit(s) SIU_STET_RSRV_31_2 reserved */
+#define	SIU_STET_STET_MSK			SHIFT0(0x3)			/* STET[1:0] */
+#define	SIU_STET_STET_BASE			0
+
+/*	SIU_HTX				0x25A4	Halt TX */
+/*		Bit(s) SIU_HTX_RSRV_31_1 reserved */
+#define	SIU_HTX_HTX					BIT_0				/* HTX */
+
+/*	SIU_DMASA			0x25A8	DMA Software Acknowledge */
+/*		Bit(s) SIU_DMASA_RSRV_31_1 reserved */
+#define	SIU_DMASA_DMASA					BIT_0				/* DMASA */
+
+/*	SIU_CPR				0x25F4	Component Parameter Register */
+/*		Bit(s) SIU_CPR_RSRV_31_24 reserved */
+#define	SIU_CPR_FIFO_MODE_MSK				SHIFT16(0xffUL)	/* FIFO_MODE */
+#define	SIU_CPR_FIFO_MODE_BASE				16
+/*		Bit(s) SIU_CPR_RSRV_15_14 reserved */
+#define	SIU_CPR_DMA_EXTRA					BIT_13			/* DMA_EXTRA */
+/* UART_ADD_ENCODED_PARAMS */
+#define	SIU_CPR_UART_ADD_ENCODED_PARAMS		BIT_12
+#define	SIU_CPR_SHADOW						BIT_11			/* SHADOW */
+#define	SIU_CPR_FIFO_STAT					BIT_10			/* FIFO_STAT */
+#define	SIU_CPR_FIFO_ACCESS					BIT_9			/* FIFO_ACCESS */
+#define	SIU_CPR_ADDITIONAL_FEAT				BIT_8			/* ADDITIONAL_FEAT */
+#define	SIU_CPR_SIR_LP_MODE					BIT_7			/* SIR_LP_MODE */
+#define	SIU_CPR_SIR_MODE					BIT_6			/* SIR_MODE */
+#define	SIU_CPR_THRE_MODE					BIT_5			/* THRE_MODE */
+#define	SIU_CPR_AFCE_MODE					BIT_4			/* AFCE_MODE */
+/*		Bit(s) SIU_CPR_RSRV_3_2 reserved */
+#define	SIU_CPR_APB_DATA_WIDTH_MSK			SHIFT0(0x3)		/* APB_DATA_WIDTH */
+#define	SIU_CPR_APB_DATA_WIDTH_BASE			0
+
+/*	SIU_UCV				0x25F8	UART Component Version */
+#define	SIU_UCV_UCV_MSK			SHIFT0(0xffffffff)	/* UCV */
+#define	SIU_UCV_UCV_BASE		0
+
+/*	SIU_CTR				0x25FC	Component Type Register */
+#define	SIU_CTR_CTR_MSK			SHIFT0(0xffffffff)	/* CTR */
+#define	SIU_CTR_CTR_BASE		0
+
+
+
+/*	PTP_CTRL_REG				0x2500	PTP Control */
+/*		Bit(s) PTP_CTRL_REG_RSRV_31_13 reserved */
+/* ptp_debug_addr */
+#define	PTP_CTRL_REG_PTP_DEBUG_ADDR_MSK		SHIFT8(0x1f)
+#define	PTP_CTRL_REG_PTP_DEBUG_ADDR_BASE		8
+/*		Bit(s) PTP_CTRL_REG_RSRV_7_6 reserved */
+/* resetn_h_sysp */
+#define	PTP_CTRL_REG_RESETN_H_SYSP				BIT_5
+/* resetn_hs_sysp */
+#define	PTP_CTRL_REG_RESETN_HS_SYSP				BIT_4
+/* resetn_hs_ptp_ts */
+#define	PTP_CTRL_REG_RESETN_HS_PTP_TS			BIT_3
+/* reset_hs_ptp_macp_tx */
+#define	PTP_CTRL_REG_RESET_HS_PTP_MACP_TX		BIT_2
+/* reset_hs_ptp_macp_rx */
+#define	PTP_CTRL_REG_RESET_HS_PTP_MACP_RX		BIT_1
+/* reset_n_h_ptp_ts */
+#define	PTP_CTRL_REG_RESET_N_H_PTP_TS			BIT_0
+/* clear all reset bits from above */
+#define PTP_CTRL_REG_RESET_ALL_CLR				(0x3f)
+
+/*	PTP_AVB_COMMAND				0x2510	PTP AVB COMMAND */
+/*		Bit(s) PTP_AVB_COMMAND_RSRV_31_16 reserved */
+#define	PTP_AVB_COMMAND_AVBBUSY				BIT_15			/* AVBBusy */
+#define	PTP_AVB_COMMAND_AVBOP_MSK			SHIFT12(0x7)	/* AVBOp */
+#define	PTP_AVB_COMMAND_AVBOP_BASE			12
+#define	PTP_AVB_COMMAND_AVBPORT_MSK			SHIFT8(0xf)		/* AVBPort */
+#define	PTP_AVB_COMMAND_AVBPORT_BASE		8
+#define	PTP_AVB_COMMAND_AVBBLOCK_MSK		SHIFT5(0x7)		/* AVBBlock */
+#define	PTP_AVB_COMMAND_AVBBLOCK_BASE		5
+#define	PTP_AVB_COMMAND_AVBADDR_MSK			SHIFT0(0x1f)	/* AVBAddr */
+#define	PTP_AVB_COMMAND_AVBADDR_BASE		0
+
+#define	PTP_PORT_CONF		0x0
+#define	PTP_PORT_GLOB		0xf
+#define	PTP_PORT_TAI		0xe
+
+#define	AVB_WRITE			3
+#define	AVB_READ			4
+#define	AVB_READ_INC		6
+
+
+/*	PTP_AVB_Data				0x2514	PTP AVB Data */
+/*		Bit(s) PTP_AVB_DATA_RSRV_31_16 reserved */
+#define	PTP_AVB_DATA_AVBDATA_MSK			SHIFT0(0xffff)	/* AVBData */
+#define	PTP_AVB_DATA_AVBDATA_BASE			0
+
+/* -------------------- */
+
+
+
+/*
+ *
+ *	THE BASE ADDRESSES
+ *
+ */
+
+/*
+ *
+ *	THE REGISTER DEFINES
+ *
+ */
+#define	GPSR		0x2800	/* 16 bit	General Purpose Status Register */
+#define	GPCR		0x2804	/* 16 bit	General Purpose Control Register */
+#define	TCR			0x2808	/* 16 bit	Transmit Control Register */
+#define	RCR			0x280C	/* 16 bit	Receive Control Register */
+#define	TFCR		0x2810	/* 16 bit	Transmit Flow Control Register */
+#define	TPR			0x2814	/* 16 bit	Transmit Parameter Register */
+#define	SMR			0x2818	/* 16 bit	Serial Mode Register */
+#define	SAL1		0x281C	/* 16 bit	Source Address Low */
+#define	SAM1		0x2820	/* 16 bit	Source Address Middle */
+#define	SA1H		0x2824	/* 16 bit	Source Address High */
+#define	SAL2		0x2828	/* 16 bit	Source Address Low */
+#define	SAM2		0x282C	/* 16 bit	Source Address Middle */
+#define	SAH2		0x2830	/* 16 bit	Source Address High */
+#define	MCAH1		0x2834	/* 16 bit	Multicast Address Hash Register 1 */
+#define	MCAH2		0x2838	/* 16 bit	Multicast Address Hash Register 2 */
+#define	MCAH3		0x283C	/* 16 bit	Multicast Address Hash Register 3 */
+#define	MCAH4		0x2840	/* 16 bit	Multicast Address Hash Register 4 */
+#define	TIR			0x2844	/* 16 bit	Transmit Interrupt Register */
+#define	RIR			0x2848	/* 16 bit	Receive Interrupt Register */
+#define	TIR_RIR		0x284C	/* 16 bit	Transmit and Receive Interrupt Register */
+#define	TIMR		0x2850	/* 16 bit	Transmit Interrupt Mask Register */
+#define	RIMR		0x2854	/* 16 bit	Receive Interrupt Mask Register */
+#define	TIMR_RIMR	0x2858	/* 16 bit	Transmit and Receive Interrupt Mask
+							 *			Register
+							 */
+#define	FC_TIMEOUT	0x285C	/* 16 bit	Flow Control Timeout Register */
+#define	SMICR		0x2880	/* 16 bit	SMI Control Register */
+#define	SMIDR		0x2884	/* 16 bit	SMI Data Register */
+#define	PAR			0x2888	/* 16 bit	PHY Address Register */
+
+/*
+ *
+ *	DEFINES FOR EEE
+ *
+ */
+#define EEE_CONTROL				0x28A0
+#define EEE_ASSERTION_TIMER		0x28A4
+#define EEE_TX_IDLE_TIMER		0x28A8
+#define EEE_COUNTER				0x28AC
+#define EEE_STATUS				0x28B0
+
+/*
+ *
+ *	THE BIT DEFINES
+ *
+ */
+/*	GPSR		0x2800	General Purpose Status Register */
+#define	GPSR_SPEED				BIT_15S	/* Port Speed */
+#define	GPSR_DUPLEX				BIT_14S	/* Port Duplex Mode */
+#define	GPSR_FCTLTX				BIT_13S	/* Transmit Flow Control Mode */
+#define	GPSR_LINK				BIT_12S	/* Link Status */
+#define	GPSR_PAUSE				BIT_11S	/* Pause */
+#define	GPSR_TXINPROG			BIT_10S	/* TX in Progress */
+#define	GPSR_EXCESSCOL			BIT_9S	/* Excessive Collisions Occurred */
+#define	GPSR_LATECOL			BIT_8S	/* Late Collision Occurred */
+#define	GPSR_TX_EN_STATUS		BIT_7S	/* Tx En Status */
+#define	GPSR_RX_EN_STATUS		BIT_6S	/* Rx En Status */
+#define	GPSR_MIIPHYSTC			BIT_5S	/* MII PHY Status Change */
+#define	GPSR_GIGSPEED			BIT_4S	/* Gig Speed */
+#define	GPSR_PARTITION			BIT_3S	/* Partition Mode */
+#define	GPSR_FCTLRX				BIT_2S	/* Receive Flow Control Mode */
+#define	GPSR_PROMISC_MODE		BIT_1S	/* Promiscuous Mode */
+/*		Bit(s) GPSR_RSRV_0 reserved */
+
+/*	GPCR		0x2804	General Purpose Control Register */
+#define	GPCR_MDIO_SPSEL			BIT_15S	/* MAC to PHY MDIO speed select */
+/*		Bit(s) GPCR_RSRV_14 reserved */
+#define	GPCR_FCTLTX					BIT_13S			/* Transmit Flow Control Mode */
+#define	GPCR_TXEN					BIT_12S			/* Transmit Enable */
+#define	GPCR_RXEN					BIT_11S			/* Receive Enable */
+/*		Bit(s) GPCR_RSRV_10 reserved */
+#define	GPCR_LPBK					BIT_9S			/* Loopback Mode */
+#define	GPCR_PAR					BIT_8S			/* Partition Enable */
+#define	GPCR_GIGSPEED				BIT_7S			/* Gig Speed */
+#define	GPCR_FLP					BIT_6S			/* Force Link Pass */
+#define	GPCR_HD						BIT_5S			/* Duplex Mode */
+#define	GPCR_FCTLRX					BIT_4S			/* Receive Flow Control Mode */
+#define	GPCR_SPEED					BIT_3S			/* Port Speed */
+/* Enable Auto-Update for Duplex Mode */
+#define	GPCR_DPLYXEN				BIT_2S
+/* Enable Auto-Update for 802.3x Flow Control */
+#define	GPCR_FCTLEN					BIT_1S
+#define	GPCR_SPEEDEN				BIT_0S			/* Enable Auto-Update for Speed */
+
+/*	TCR			0x2808	Transmit Control Register */
+#define	TCR_FJ					BIT_15S			/* Force Jam/Flow Control */
+#define	TCR_CRCD				BIT_14S			/* Insert CRC */
+#define	TCR_PADD				BIT_13S			/* Pad Packets */
+#define	TCR_COLTH_MSK			SHIFT10(0x7U)	/* Collision Threshold */
+#define	TCR_COLTH_BASE			10
+#define	TCR_HD_LPBK_DIS			BIT_9S			/* Half Duplex Loopback Enable */
+#define	TCR_JAM_FIX_EN			BIT_8S			/* Jam UNH Fix Enable */
+#define	TCR_PADD_PAT_MSK		SHIFT0(0xffU)	/* Padding Pattern */
+#define	TCR_PADD_PAT_BASE		0
+
+/*	RCR			0x280C	Receive Control Register */
+#define	RCR_UNFIEN				BIT_15S			/* Unicast Filter Enable */
+#define	RCR_MUFIEN				BIT_14S			/* Multicast Filter Enable */
+#define	RCR_CRCR				BIT_13S			/* Remove CRC from Receive Packets */
+/*		Bit(s) RCR_RSRV_12 reserved */
+/*		Bit(s) RCR_RSRV_11_0 reserved */
+
+/*	TFCR		0x2810	Transmit Flow Control Register */
+#define	TFCR_PAUSETIME_MSK		SHIFT0(0xffffU)	/* PauseTime */
+#define	TFCR_PAUSETIME_BASE		0
+
+/*	TPR			0x2814	Transmit Parameter Register */
+#define	TPR_JAM_LEN_MSK				SHIFT14(0x3U)	/* Jam Length */
+#define	TPR_JAM_LEN_BASE			14
+#define	TPR_JAM_IPG_MSK				SHIFT9(0x1fU)	/* Jam Inter Packet Gap */
+#define	TPR_JAM_IPG_BASE			9
+#define	TPR_IPGJAM2DATA_MSK			SHIFT4(0x1fU)	/* Inter Packet Jam Data */
+#define	TPR_IPGJAM2DATA_BASE		4
+#define	TPR_BACK_OFF_LIMIT_MSK		SHIFT0(0xfU)	/* Back-off Limit */
+#define	TPR_BACK_OFF_LIMIT_BASE		0
+
+/*	SMR			0x2818	Serial Mode Register */
+#define	SMR_DATA_BLINDER_MSK		SHIFT11(0x1fU)	/* Data Blinder */
+#define	SMR_DATA_BLINDER_BASE		11
+#define	SMR_LIMIT4					BIT_10S			/* Limit4 */
+/* VLAN Enabled, Maximum Frame Length */
+#define	SMR_VLAN_EN_MFL_MSK			SHIFT8(0x3U)
+#define	SMR_VLAN_EN_MFL_BASE		8
+/*		Bit(s) SMR_RSRV_7_5 reserved */
+#define	SMR_IPGDATA_MSK				SHIFT0(0x1fU)	/* Inter Packet Gap Data */
+#define	SMR_IPGDATA_BASE			0
+
+/*	SAL1		0x281C	Source Address Low */
+#define	SAL1_SA1_MSK		SHIFT0(0xffffU)	/* SA1 [15:0] */
+#define	SAL1_SA1_BASE		0
+
+/*	SAM1		0x2820	Source Address Middle */
+#define	SAM1_SA1_MSK		SHIFT0(0xffffU)	/* SA1 [31:16] */
+#define	SAM1_SA1_BASE		0
+
+/*	SA1H		0x2824	Source Address High */
+#define	SA1H_SA1_MSK		SHIFT0(0xffffU)	/* SA1 [47:32] */
+#define	SA1H_SA1_BASE		0
+
+/*	SAL2		0x2828	Source Address Low */
+#define	SAL2_SA2_MSK		SHIFT0(0xffffU)	/* SA2 [15:0] */
+#define	SAL2_SA2_BASE		0
+
+/*	SAM2		0x282C	Source Address Middle */
+#define	SAM2_SA2_MSK		SHIFT0(0xffffU)	/* SA2 [31:16] */
+#define	SAM2_SA2_BASE		0
+
+/*	SAH2		0x2830	Source Address High */
+#define	SAH2_SA2_MSK		SHIFT0(0xffffU)	/* SA 2[47:32] */
+#define	SAH2_SA2_BASE		0
+
+/*	MCAH1		0x2834	Multicast Address Hash Register 1 */
+#define	MCAH1_MCAH1_MSK			SHIFT0(0xffffU)	/* MCAH1[15:0] */
+#define	MCAH1_MCAH1_BASE		0
+
+/*	MCAH2		0x2838	Multicast Address Hash Register 2 */
+#define	MCAH2_MCAH2_MSK			SHIFT0(0xffffU)	/* MCAH2[15:0] */
+#define	MCAH2_MCAH2_BASE		0
+
+/*	MCAH3		0x283C	Multicast Address Hash Register 3 */
+#define	MCAH3__MCAH3_MSK		SHIFT0(0xffffU)	/* MCAH3[15:0] */
+#define	MCAH3__MCAH3_BASE		0
+
+/*	MCAH4		0x2840	Multicast Address Hash Register 4 */
+#define	MCAH4_MCAH4_MSK			SHIFT0(0xffffU)	/* MCAH4[15:0] */
+#define	MCAH4_MCAH4_BASE		0
+
+/*	TIR			0x2844	Transmit Interrupt Register */
+#define	TIR_LATE				BIT_15S			/* Late */
+#define	TIR_COLLISIONS			BIT_14S			/* Collisions */
+#define	TIR_DEFER				BIT_13S			/* Defer */
+#define	TIR_OUTMAXOCTETS		BIT_12S			/* OutMaxOctets */
+#define	TIR_OUT1518OCTETS		BIT_11S			/* Out1518Octets */
+#define	TIR_OUT1023OCTETS		BIT_10S			/* Out1023Octets */
+#define	TIR_OUT511OCTETS		BIT_9S			/* Out511Octets */
+#define	TIR_OUT255OCTETS		BIT_8S			/* Out255Octets */
+#define	TIR_OUT127OCTETS		BIT_7S			/* Out127Octets */
+#define	TIR_OUT64OCTETS			BIT_6S			/* Out64octets */
+#define	TIR_OUTOCTETS_MSK		SHIFT4(0x3U)	/* OutOctets */
+#define	TIR_OUTOCTETS_BASE		4
+#define	TIR_OUTMULTICASTS		BIT_3S			/* OutMulticasts */
+#define	TIR_OUTPAUSE			BIT_2S			/* OutPause */
+#define	TIR_OUTBROADCASTS		BIT_1S			/* OutBroadcasts */
+#define	TIR_OUTUNICASTS			BIT_0S			/* OutUnicasts */
+
+/*	RIR			0x2848	Receive Interrupt Register */
+#define	RIR_IN511OCTETS			BIT_15S			/* In511Octets */
+#define	RIR_IN255OCTETS			BIT_14S			/* In255Octets */
+#define	RIR_IN127OCTETS			BIT_13S			/* In127Octets */
+#define	RIR_IN64OCTETS			BIT_12S			/* In64Octets */
+#define	RIR_FRAGMENTS			BIT_11S			/* Fragments */
+#define	RIR_UNDERSIZE			BIT_10S			/* Undersize */
+#define	RIR_INBADOCTETS_MSK		SHIFT8(0x3U)	/* InBadOctets */
+#define	RIR_INBADOCTETS_BASE	8
+#define	RIR_INGOODOCTETS_MSK	SHIFT6(0x3U)	/* InGoodOctets */
+#define	RIR_INGOODOCTETS_BASE	6
+#define	RIR_SPARE				BIT_5S			/* Spare */
+#define	RIR_INFCSERR			BIT_4S			/* InFCSErr */
+#define	RIR_INMULTICASTS		BIT_3S			/* InMulticasts */
+#define	RIR_INPAUSE				BIT_2S			/* InPause */
+#define	RIR_INBROADCASTS		BIT_1S			/* InBroadcasts */
+#define	RIR_INUNICASTS			BIT_0S			/* InUnicasts */
+
+/*	TIR_RIR		0x284C	Transmit and Receive Interrupt Register */
+/*		Bit(s) TIR_RIR_RSRV_15_12 reserved */
+#define	TIR_RIR_UNDERFLOW			BIT_11S			/* Underflow */
+#define	TIR_RIR_SINGLE				BIT_10S			/* Single */
+#define	TIR_RIR_MULTIPLE			BIT_9S			/* Multiple */
+#define	TIR_RIR_EXCESSIVE			BIT_8S			/* Excessive */
+#define	TIR_RIR_ALIGMENT_ERROR		BIT_7S			/* Align_error */
+#define	TIR_RIR_OVERFLOW			BIT_6S			/* Overflow */
+#define	TIR_RIR_SYMBOL_ERR			BIT_5S			/* Symbol_error */
+#define	TIR_RIR_JABBER				BIT_4S			/* Jabber */
+#define	TIR_RIR_OVERSIZE			BIT_3S			/* OverSize */
+#define	TIR_RIR_INMAXOCTETS			BIT_2S			/* InMaxOctets */
+#define	TIR_RIR_IN1518OCTETS		BIT_1S			/* In1518Octets */
+#define	TIR_RIR_IN1023OCTETS		BIT_0S			/* In1023Octets */
+
+/*	TIMR		0x2850	Transmit Interrupt Mask Register */
+#define	TIMR_TIMR_MSK		SHIFT0(0xffffU)	/* TIMR[15:0] */
+#define	TIMR_TIMR_BASE		0
+
+/*	RIMR		0x2854	Receive Interrupt Mask Register */
+#define	RIMR_RIMR_MSK		SHIFT0(0xffffU)	/* RIMR[15:0] */
+#define	RIMR_RIMR_BASE		0
+
+/*	TIMR_RIMR	0x2858	Transmit and Receive Interrupt Mask Register */
+#define	TIMR_RIMR_TIMR_RIMR_MSK			SHIFT0(0xffffU)	/* TIMR_RIMR[15:0] */
+#define	TIMR_RIMR_TIMR_RIMR_BASE		0
+
+/*	FC_TIMEOUT	0x285C	Flow Control Timeout Register */
+#define	FC_TIMEOUT_FC_TIMEOUT_MSK		SHIFT0(0xffffU)	/* FC_TIMEOUT[15:0] */
+#define	FC_TIMEOUT_FC_TIMEOUT_BASE		0
+
+/*	SMICR		0x2880	SMI Control Register */
+#define	SMICR_PHYAD_MSK			SHIFT11(0x1fU)	/* PHY Device Address */
+#define	SMICR_PHYAD_BASE		11
+#define	SMICR_REGAD_MSK			SHIFT6(0x1fU)	/* PHY Device Register Address */
+#define	SMICR_REGAD_BASE		6
+#define	SMICR_OPCODE			BIT_5S			/* OpCode */
+#define	SMICR_READVALID			BIT_4S			/* Read Valid */
+#define	SMICR_BUSY				BIT_3S			/* Busy */
+/*		Bit(s) SMICR_RSRV_2_0 reserved */
+
+/*	SMIDR		0x2884	SMI Data Register */
+#define	SMIDR_DATA_MSK		SHIFT0(0xffffU)	/* SMI Read/Write Operation */
+#define	SMIDR_DATA_BASE		0
+
+/*	PAR			0x2888	PHY Address Register */
+/*		Bit(s) PAR_RSRV_15_6 reserved */
+#define	PAR_MIBCLRMODE			BIT_5S			/* MIB Counters Clear Mode */
+#define	PAR_LOADTSTCNT			BIT_4S			/* Load Test Count */
+/*		Bit(s) PAR_RSRV_3_0 reserved */
+
+/*
+ *	BIT DEFINES FOR EEE
+ */
+
+/*	EEE_CONTROL		0x28A0 */
+#define EEE_CONTROL_LPI_VALUE	BIT_7S
+#define EEE_CONTROL_FORCE_LPI	BIT_6S
+#define EEE_CONTROL_DEBUG_LPI	BIT_5S
+#define EEE_CONTROL_DISABLE10	BIT_3S
+#define EEE_CONTROL_RESET		BIT_2S
+#define EEE_CONTROL_TX_LPI_EN	BIT_1S
+#define EEE_CONTROL_CAPABLE		BIT_0S
+
+/*	EEE_STATUS		0x28B0 */
+#define EEE_STATUS_EEE_CAP		BIT_9S
+#define EEE_STATUS_LINK_UP		BIT_8S
+#define EEE_STATUS_TX_LPI		BIT_5S
+#define EEE_STATUS_RX_LPI		BIT_4S
+
+/* -------------------- */
+
+#endif	/* __INC_SKY3HW_H */
diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h
--- linux/drivers/net/sk98lin/h/skaddr.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skaddr.h	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,441 @@
+/******************************************************************************
+ *
+ * Name:	skaddr.h
+ * Project:	Gigabit Ethernet Adapters, ADDR-Modul
+ * Version:	$Revision: #4 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Header file for Address Management (MC, UC, Prom).
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skaddr.h,v $
+ *	Revision 2.6  2009/10/27 08:15:33  tschilli
+ *	Added changes to support compilation without RMLT (SK_NO_RLMT)
+ *	
+ *	Revision 2.5  2008/04/02 10:43:02  tschilli
+ *	Fix: Editorial changes.
+ *	
+ *	Revision 2.4  2008/03/20 08:24:23  tschilli
+ *	Removed support of GENESIS adapters.
+ *	
+ *	Revision 2.3  2005/12/21 08:55:06  tschilli
+ *	Added declarations of SkXmacMcHash() and SkGmacMcHash()
+ *	to get rid of FreeBSD compiler warnings.
+ *	
+ *	Revision 2.2  2005/12/14 16:11:44  ibrueder
+ *	added copyright header flags
+ *	
+ *	Revision 2.1  2003/10/27 14:16:07  amock
+ *	Promoted to major revision 2.1
+ *	
+ *	Revision 1.1  2003/10/27 14:14:17  amock
+ *	Copied to yukon2 module branch
+ *	
+ *	Revision 1.29  2003/05/13 16:57:24  mkarl
+ *	Changes for SLIM driver.
+ *	Editorial changes.
+ *	
+ *	Revision 1.28  2003/04/15 09:33:22  tschilli
+ *	Copyright messages changed.
+ *	
+ *	Revision 1.27  2003/04/14 15:55:11  tschilli
+ *	"#error C++ is not yet supported." removed.
+ *	
+ *	Revision 1.26  2002/11/15 07:24:42  tschilli
+ *	SK_ADDR_EQUAL macro fixed.
+ *	
+ *	Revision 1.25  2002/06/10 13:55:18  tschilli
+ *	Changes for handling YUKON.
+ *	All changes are internally and not visible to the programmer
+ *	using this module.
+ *	
+ *	Revision 1.24  2001/01/22 13:41:34  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *	
+ *	Revision 1.23  2000/08/10 11:27:50  rassmann
+ *	Editorial changes.
+ *	Preserving 32-bit alignment in structs for the adapter context.
+ *	
+ *	Revision 1.22  2000/08/07 11:10:40  rassmann
+ *	Editorial changes.
+ *	
+ *	Revision 1.21  2000/05/04 09:39:59  rassmann
+ *	Editorial changes.
+ *	Corrected multicast address hashing.
+ *	
+ *	Revision 1.20  1999/11/22 13:46:14  cgoos
+ *	Changed license header to GPL.
+ *	Allowing overwrite for SK_ADDR_EQUAL.
+ *	
+ *	Revision 1.19  1999/05/28 10:56:07  rassmann
+ *	Editorial changes.
+ *	
+ *	Revision 1.18  1999/04/06 17:22:04  rassmann
+ *	Added private "ActivePort".
+ *	
+ *	Revision 1.17  1999/01/14 16:18:19  rassmann
+ *	Corrected multicast initialization.
+ *	
+ *	Revision 1.16  1999/01/04 10:30:36  rassmann
+ *	SkAddrOverride only possible after SK_INIT_IO phase.
+ *	
+ *	Revision 1.15  1998/12/29 13:13:11  rassmann
+ *	An address override is now preserved in the SK_INIT_IO phase.
+ *	All functions return an int now.
+ *	Extended parameter checking.
+ *	
+ *	Revision 1.14  1998/11/24 12:39:45  rassmann
+ *	Reserved multicast entry for BPDU address.
+ *	13 multicast entries left for protocol.
+ *	
+ *	Revision 1.13  1998/11/13 17:24:32  rassmann
+ *	Changed return value of SkAddrOverride to int.
+ *	
+ *	Revision 1.12  1998/11/13 16:56:19  rassmann
+ *	Added macro SK_ADDR_COMPARE.
+ *	Changed return type of SkAddrOverride to SK_BOOL.
+ *	
+ *	Revision 1.11  1998/10/28 18:16:35  rassmann
+ *	Avoiding I/Os before SK_INIT_RUN level.
+ *	Aligning InexactFilter.
+ *	
+ *	Revision 1.10  1998/10/22 11:39:10  rassmann
+ *	Corrected signed/unsigned mismatches.
+ *	
+ *	Revision 1.9  1998/10/15 15:15:49  rassmann
+ *	Changed Flags Parameters from SK_U8 to int.
+ *	Checked with lint.
+ *	
+ *	Revision 1.8  1998/09/24 19:15:12  rassmann
+ *	Code cleanup.
+ *	
+ *	Revision 1.7  1998/09/18 20:22:13  rassmann
+ *	Added HW access.
+ *	
+ *	Revision 1.6  1998/09/04 19:40:20  rassmann
+ *	Interface enhancements.
+ *	
+ *	Revision 1.5  1998/09/04 12:40:57  rassmann
+ *	Interface cleanup.
+ *	
+ *	Revision 1.4  1998/09/04 12:14:13  rassmann
+ *	Interface cleanup.
+ *	
+ *	Revision 1.3  1998/09/02 16:56:40  rassmann
+ *	Updated interface.
+ *	
+ *	Revision 1.2  1998/08/27 14:26:09  rassmann
+ *	Updated interface.
+ *	
+ *	Revision 1.1  1998/08/21 08:31:08  rassmann
+ *	First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This module is intended to manage multicast addresses and promiscuous mode
+ * on Yukon adapters.
+ *
+ * Include File Hierarchy:
+ *
+ *	"skdrv1st.h"
+ *	...
+ *	"sktypes.h"
+ *	"skqueue.h"
+ *	"skaddr.h"
+ *	...
+ *	"skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKADDR_H
+#define __INC_SKADDR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* cplusplus */
+
+/* defines ********************************************************************/
+
+#define SK_MAC_ADDR_LEN				6	/* Length of MAC address. */
+#define	SK_MAX_ADDRS				14	/* #Addrs for exact match. */
+
+/* ----- Common return values ----- */
+
+#define SK_ADDR_SUCCESS				0	/* Function returned successfully. */
+#define SK_ADDR_ILLEGAL_PORT			100	/* Port number too high. */
+#define SK_ADDR_TOO_EARLY			101	/* Function called too early. */
+
+/* ----- Clear/Add flag bits ----- */
+
+#define SK_ADDR_PERMANENT			1	/* RLMT Address */
+
+/* ----- Additional Clear flag bits ----- */
+
+#define SK_MC_SW_ONLY				2	/* Do not update HW when clearing. */
+
+/* ----- Override flag bits ----- */
+
+#define SK_ADDR_LOGICAL_ADDRESS		0
+#define SK_ADDR_VIRTUAL_ADDRESS		(SK_ADDR_LOGICAL_ADDRESS)	/* old */
+#define SK_ADDR_PHYSICAL_ADDRESS	1
+#define SK_ADDR_CLEAR_LOGICAL		2
+#define SK_ADDR_SET_LOGICAL			4
+
+/* ----- Override return values ----- */
+
+#define SK_ADDR_OVERRIDE_SUCCESS	(SK_ADDR_SUCCESS)
+#define SK_ADDR_DUPLICATE_ADDRESS	1
+#define SK_ADDR_MULTICAST_ADDRESS	2
+
+/* ----- Partitioning of excact match table ----- */
+
+#define SK_ADDR_EXACT_MATCHES		16	/* #Exact match entries. */
+
+#define SK_ADDR_FIRST_MATCH_RLMT	1
+#define SK_ADDR_LAST_MATCH_RLMT		2
+#define SK_ADDR_FIRST_MATCH_DRV		3
+#define SK_ADDR_LAST_MATCH_DRV		(SK_ADDR_EXACT_MATCHES - 1)
+
+/* ----- SkAddrMcAdd/SkAddrMcUpdate return values ----- */
+
+#define SK_MC_FILTERING_EXACT		0	/* Exact filtering. */
+#define SK_MC_FILTERING_INEXACT		1	/* Inexact filtering. */
+
+/* ----- Additional SkAddrMcAdd return values ----- */
+
+#define SK_MC_ILLEGAL_ADDRESS		2	/* Illegal address. */
+#define SK_MC_ILLEGAL_PORT			3	/* Illegal port (not the active one). */
+#define SK_MC_RLMT_OVERFLOW			4	/* Too many RLMT mc addresses. */
+
+/* Promiscuous mode bits ----- */
+
+#define SK_PROM_MODE_NONE			0	/* Normal receive. */
+#define SK_PROM_MODE_LLC			1	/* Receive all LLC frames. */
+#define SK_PROM_MODE_ALL_MC			2	/* Receive all multicast frames. */
+/* #define SK_PROM_MODE_NON_LLC		4 */	/* Receive all non-LLC frames. */
+
+/* Macros */
+
+#ifdef OLD_STUFF
+#ifndef SK_ADDR_EQUAL
+/*
+ * "&" instead of "&&" allows better optimization on IA-64.
+ * The replacement is safe here, as all bytes exist.
+ */
+#ifndef SK_ADDR_DWORD_COMPARE
+#define SK_ADDR_EQUAL(A1,A2)	( \
+	(((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \
+	(((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \
+	(((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \
+	(((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \
+	(((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \
+	(((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0]))
+#else	/* SK_ADDR_DWORD_COMPARE */
+#define SK_ADDR_EQUAL(A1,A2)	( \
+	(*(SK_U32 *)&(((SK_U8 *)(A1))[2]) == *(SK_U32 *)&(((SK_U8 *)(A2))[2])) & \
+	(*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0])))
+#endif	/* SK_ADDR_DWORD_COMPARE */
+#endif	/* SK_ADDR_EQUAL */
+#endif /* 0 */
+
+#ifndef SK_ADDR_EQUAL
+#ifndef SK_ADDR_DWORD_COMPARE
+#define SK_ADDR_EQUAL(A1,A2)	( \
+	(((SK_U8 SK_FAR *)(A1))[5] == ((SK_U8 SK_FAR *)(A2))[5]) & \
+	(((SK_U8 SK_FAR *)(A1))[4] == ((SK_U8 SK_FAR *)(A2))[4]) & \
+	(((SK_U8 SK_FAR *)(A1))[3] == ((SK_U8 SK_FAR *)(A2))[3]) & \
+	(((SK_U8 SK_FAR *)(A1))[2] == ((SK_U8 SK_FAR *)(A2))[2]) & \
+	(((SK_U8 SK_FAR *)(A1))[1] == ((SK_U8 SK_FAR *)(A2))[1]) & \
+	(((SK_U8 SK_FAR *)(A1))[0] == ((SK_U8 SK_FAR *)(A2))[0]))
+#else	/* SK_ADDR_DWORD_COMPARE */
+#define SK_ADDR_EQUAL(A1,A2)	( \
+	(*(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[4]) == \
+	*(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[4])) && \
+	(*(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[0]) == \
+	*(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[0])))
+#endif	/* SK_ADDR_DWORD_COMPARE */
+#endif	/* SK_ADDR_EQUAL */
+
+/* typedefs *******************************************************************/
+
+typedef struct s_MacAddr {
+	SK_U8	a[SK_MAC_ADDR_LEN];
+} SK_MAC_ADDR;
+
+
+/* SK_FILTER is used to ensure alignment of the filter. */
+typedef union s_InexactFilter {
+	SK_U8	Bytes[8];
+	SK_U64	Val;	/* Dummy entry for alignment only. */
+} SK_FILTER64;
+
+
+typedef struct s_AddrNet SK_ADDR_NET;
+
+
+typedef struct s_AddrPort {
+
+/* ----- Public part (read-only) ----- */
+
+	SK_MAC_ADDR	CurrentMacAddress;	/* Current physical MAC Address. */
+	SK_MAC_ADDR	PermanentMacAddress;	/* Permanent physical MAC Address. */
+	int		PromMode;		/* Promiscuous Mode. */
+
+/* ----- Private part ----- */
+
+	SK_MAC_ADDR	PreviousMacAddress;	/* Prev. phys. MAC Address. */
+	SK_BOOL		CurrentMacAddressSet;	/* CurrentMacAddress is set. */
+	SK_U8		Align01;
+
+	SK_U32		FirstExactMatchRlmt;
+	SK_U32		NextExactMatchRlmt;
+	SK_U32		FirstExactMatchDrv;
+	SK_U32		NextExactMatchDrv;
+	SK_MAC_ADDR	Exact[SK_ADDR_EXACT_MATCHES];
+	SK_FILTER64	InexactFilter;			/* For 64-bit hash register. */
+	SK_FILTER64	InexactRlmtFilter;		/* For 64-bit hash register. */
+	SK_FILTER64	InexactDrvFilter;		/* For 64-bit hash register. */
+} SK_ADDR_PORT;
+
+
+struct s_AddrNet {
+/* ----- Public part (read-only) ----- */
+
+	SK_MAC_ADDR		CurrentMacAddress;	/* Logical MAC Address. */
+	SK_MAC_ADDR		PermanentMacAddress;	/* Logical MAC Address. */
+
+/* ----- Private part ----- */
+
+	SK_U32			ActivePort;		/* View of module ADDR. */
+	SK_BOOL			CurrentMacAddressSet;	/* CurrentMacAddress is set. */
+	SK_U8			Align01;
+	SK_U16			Align02;
+};
+
+
+typedef struct s_Addr {
+
+/* ----- Public part (read-only) ----- */
+
+	SK_ADDR_NET		Net[SK_MAX_NETS];
+	SK_ADDR_PORT	Port[SK_MAX_MACS];
+
+/* ----- Private part ----- */
+} SK_ADDR;
+
+/* function prototypes ********************************************************/
+
+#ifndef SK_KR_PROTO
+
+/* Functions provided by SkAddr */
+
+/* ANSI/C++ compliant function prototypes */
+
+extern	int	SkAddrInit(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int	Level);
+
+extern	int	SkAddrMcClear(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber,
+	int	Flags);
+
+extern	int	SkAddrGmacMcClear(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber,
+	int	Flags);
+
+extern	int	SkAddrMcAdd(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	SK_U32		PortNumber,
+	SK_MAC_ADDR	*pMc,
+	int		Flags);
+
+extern	int	SkAddrGmacMcAdd(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	SK_U32		PortNumber,
+	SK_MAC_ADDR	*pMc,
+	int		Flags);
+
+extern	SK_U32	SkGmacMcHash(
+	unsigned char *pMc);
+
+extern	int	SkAddrMcUpdate(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber);
+
+extern	int	SkAddrGmacMcUpdate(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber);
+
+extern	int	SkAddrOverride(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	SK_U32		PortNumber,
+	SK_MAC_ADDR	SK_FAR *pNewAddr,
+	int		Flags);
+
+extern	int	SkAddrPromiscuousChange(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber,
+	int	NewPromMode);
+
+extern	int	SkAddrGmacPromiscuousChange(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	PortNumber,
+	int	NewPromMode);	
+
+#ifndef SK_SLIM
+extern	int	SkAddrSwap(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	FromPortNumber,
+	SK_U32	ToPortNumber);
+#endif
+
+#else	/* defined(SK_KR_PROTO)) */
+
+/* Non-ANSI/C++ compliant function prototypes */
+
+#error KR-style prototypes are not yet provided.
+
+#endif	/* defined(SK_KR_PROTO)) */
+
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_SKADDR_H */
diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h
--- linux/drivers/net/sk98lin/h/skcsum.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skcsum.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,298 @@
+/******************************************************************************
+ *
+ * Name:	skcsum.h
+ * Project:	GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
+ * Version:	$Revision: #3 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Store/verify Internet checksum in send/receive packets.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skcsum.h,v $
+ *	Revision 2.5  2007/03/14 16:21:28  rassmann
+ *	Editorial changes.
+ *	
+ *	Revision 2.4  2007/02/16 13:06:54  rassmann
+ *	Merged changes from Windows Yukon-Extreme branch:
+ *	- Moved defines for IP header length to header file.
+ *	
+ *	Revision 2.3  2005/12/14 16:11:27  ibrueder
+ *	added copyright header flags
+ *	
+ *	Revision 2.2  2003/12/29 15:37:26  mkunz
+ *	Removed #ifdef TX_CSUM in csum struct
+ *	
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *	
+ *	Revision 1.1  2003/10/27 14:14:17  amock
+ *	Copied to yukon2 module branch
+ *	
+ *	Revision 1.10  2003/08/20 13:59:57  mschmid
+ *	Changed notation of #ifndef SkCsCalculateChecksum to
+ *	#ifndef SK_CS_CALCULATE_CHECKSUM
+ *	
+ *	Revision 1.9  2001/02/06 11:21:39  rassmann
+ *	Editorial changes.
+ *	
+ *	Revision 1.8  2001/02/06 11:15:36  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *	
+ *	Revision 1.7  2000/06/29 13:17:05  rassmann
+ *	Corrected reception of a packet with UDP checksum == 0 (which means there
+ *	is no UDP checksum).
+ *	
+ *	Revision 1.6  2000/02/28 12:33:44  cgoos
+ *	Changed C++ style comments to C style.
+ *	
+ *	Revision 1.5  2000/02/21 12:10:05  cgoos
+ *	Fixed license comment.
+ *	
+ *	Revision 1.4  2000/02/21 11:08:37  cgoos
+ *	Merged changes back into common source.
+ *	
+ *	Revision 1.1  1999/07/26 14:47:49  mkarl
+ *	changed from common source to windows specific source
+ *	added return SKCS_STATUS_IP_CSUM_ERROR_UDP and
+ *	SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester
+ *	changes for Tx csum offload
+ *	
+ *	Revision 1.2  1998/09/04 12:16:34  mhaveman
+ *	Checked in for Stephan to allow compilation.
+ *	-Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic
+ *	-Added prototype for SkCsEvent()
+ *	
+ *	Revision 1.1  1998/09/01 15:36:53  swolf
+ *	initial revision
+ *
+ *	01-Sep-1998 sw	Created.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * Public header file for the "GEnesis" common module "CSUM".
+ *
+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
+ * and is the code name of this SysKonnect project.
+ *
+ * Compilation Options:
+ *
+ *	SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
+ *	empty module.
+ *
+ *	SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
+ *	definitions. In this case, all SKCS_PROTO_xxx definitions must be made
+ *	external.
+ *
+ *	SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
+ *	definitions. In this case, all SKCS_STATUS_xxx definitions must be made
+ *	external.
+ *
+ * Include File Hierarchy:
+ *
+ *	"h/skcsum.h"
+ *	 "h/sktypes.h"
+ *	 "h/skqueue.h"
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKCSUM_H
+#define __INC_SKCSUM_H
+
+#include "h/sktypes.h"
+#include "h/skqueue.h"
+
+/* defines ********************************************************************/
+
+/* The size of the IP header without any option fields. */
+#define SKCS_IP_HEADER_SIZE						20
+
+#ifdef SK_IPV6_SUPPORT
+/* The size of the IPv6 header */
+#define SKCS_IP6_HEADER_SIZE					40
+#endif	/* SK_IPV6_SUPPORT */
+
+/*
+ * Define the default bit flags for 'SKCS_PACKET_INFO.ProtocolFlags'  if no user
+ * overwrite.
+ */
+#ifndef SKCS_OVERWRITE_PROTO	/* User overwrite? */
+#define SKCS_PROTO_IP		0x1		/* IP (Internet Protocol version 4) */
+#define SKCS_PROTO_TCP		0x2		/* TCP (Transmission Control Protocol) */
+#define SKCS_PROTO_UDP		0x4		/* UDP (User Datagram Protocol) */
+
+#define SKCS_PROTO_TCPV6	0x20	/* TCP for IPv6 packets */
+#define SKCS_PROTO_UDPV6	0x40	/* UDP for IPv6 packets */
+
+/* Indices for protocol statistics. */
+#define SKCS_PROTO_STATS_IP	0
+#define SKCS_PROTO_STATS_UDP	1
+#define SKCS_PROTO_STATS_TCP	2
+#define SKCS_NUM_PROTOCOLS	3	/* Number of supported protocols. */
+#endif	/* !SKCS_OVERWRITE_PROTO */
+
+/*
+ * Define the default SKCS_STATUS type and values if no user overwrite.
+ *
+ *	SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
+ *	SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
+ *	SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
+ *	SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
+ *	SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
+ *	SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
+ *	SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
+ *	SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
+ *	SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
+ *	SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
+ *	SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. 
+ *	SKCS_STATUS_NO_CSUM_POSSIBLE - Checksum could not be built (various reasons).
+ */
+#ifndef SKCS_OVERWRITE_STATUS	/* User overwrite? */
+#define SKCS_STATUS	int	/* Define status type. */
+
+#define SKCS_STATUS_UNKNOWN_IP_VERSION	1
+#define SKCS_STATUS_IP_CSUM_ERROR		2
+#define SKCS_STATUS_IP_FRAGMENT			3
+#define SKCS_STATUS_IP_CSUM_OK			4
+#define SKCS_STATUS_TCP_CSUM_ERROR		5
+#define SKCS_STATUS_UDP_CSUM_ERROR		6
+#define SKCS_STATUS_TCP_CSUM_OK			7
+#define SKCS_STATUS_UDP_CSUM_OK			8
+/* needed for Microsoft */
+#define SKCS_STATUS_IP_CSUM_ERROR_UDP	9
+#define SKCS_STATUS_IP_CSUM_ERROR_TCP	10
+/* UDP checksum may be omitted */
+#define SKCS_STATUS_IP_CSUM_OK_NO_UDP	11
+#define SKCS_STATUS_NO_CSUM_POSSIBLE	12
+#endif	/* !SKCS_OVERWRITE_STATUS */
+
+/* Clear protocol statistics event. */
+#define SK_CSUM_EVENT_CLEAR_PROTO_STATS	1
+
+/*
+ * Add two values in one's complement.
+ *
+ * Note: One of the two input values may be "longer" than 16-bit, but then the
+ * resulting sum may be 17 bits long. In this case, add zero to the result using
+ * SKCS_OC_ADD() again.
+ *
+ *	Result = Value1 + Value2
+ */
+#define SKCS_OC_ADD(Result, Value1, Value2) {				\
+	unsigned long Sum;						\
+									\
+	Sum = (unsigned long) (Value1) + (unsigned long) (Value2);	\
+	/* Add-in any carry. */						\
+	(Result) = (Sum & 0xffff) + (Sum >> 16);			\
+}
+
+/*
+ * Subtract two values in one's complement.
+ *
+ *	Result = Value1 - Value2
+ */
+#define SKCS_OC_SUB(Result, Value1, Value2)	\
+	SKCS_OC_ADD((Result), (Value1), ~(Value2) & 0xffff)
+
+/* typedefs *******************************************************************/
+
+/*
+ * SKCS_PROTO_STATS - The CSUM protocol statistics structure.
+ *
+ * There is one instance of this structure for each protocol supported.
+ */
+typedef struct s_CsProtocolStatistics {
+	SK_U64 RxOkCts;		/* Receive checksum ok. */
+	SK_U64 RxUnableCts;	/* Unable to verify receive checksum. */
+	SK_U64 RxErrCts;	/* Receive checksum error. */
+	SK_U64 TxOkCts;		/* Transmit checksum ok. */
+	SK_U64 TxUnableCts;	/* Unable to calculate checksum in hw. */
+} SKCS_PROTO_STATS;
+
+/*
+ * s_Csum - The CSUM module context structure.
+ */
+typedef struct s_Csum {
+	/* Enabled receive SK_PROTO_XXX bit flags. */
+	unsigned ReceiveFlags[SK_MAX_NETS];
+	unsigned TransmitFlags[SK_MAX_NETS];
+
+	/* The protocol statistics structure; one per supported protocol. */
+	SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
+} SK_CSUM;
+
+/*
+ * SKCS_PACKET_INFO - The packet information structure.
+ */
+typedef struct s_CsPacketInfo {
+	/* Bit field specifiying the desired/found protocols. */
+	unsigned ProtocolFlags;
+
+	/* Length of complete IP header, including any option fields. */
+	unsigned IpHeaderLength;
+
+	/* IP header checksum. */
+	unsigned IpHeaderChecksum;
+
+	/* TCP/UDP pseudo header checksum. */
+	unsigned PseudoHeaderChecksum;
+} SKCS_PACKET_INFO;
+
+/* function prototypes ********************************************************/
+
+#ifndef SK_CS_CALCULATE_CHECKSUM
+extern unsigned SkCsCalculateChecksum(
+	void		*pData,
+	unsigned	Length);
+#endif /* SK_CS_CALCULATE_CHECKSUM */
+
+extern int SkCsEvent(
+	SK_AC		*pAc,
+	SK_IOC		Ioc,
+	SK_U32		Event,
+	SK_EVPARA	Param);
+
+extern SKCS_STATUS SkCsGetReceiveInfo(
+	SK_AC		*pAc,
+	void		*pIpHeader,
+	unsigned	Checksum1,
+	unsigned	Checksum2,
+	int			NetNumber,
+	unsigned	Len);
+
+extern void SkCsGetSendInfo(
+	SK_AC				*pAc,
+	void				*pIpHeader,
+	SKCS_PACKET_INFO	*pPacketInfo,
+	int					NetNumber);
+
+extern void SkCsSetReceiveFlags(
+	SK_AC		*pAc,
+	unsigned	ReceiveFlags,
+	unsigned	*pChecksum1Offset,
+	unsigned	*pChecksum2Offset,
+	int			NetNumber);
+
+#endif	/* __INC_SKCSUM_H */
diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h
--- linux/drivers/net/sk98lin/h/skdebug.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skdebug.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,115 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skdebug.h#6 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #6 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	SK specific DEBUG support
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDEBUG_H
+#define __INC_SKDEBUG_H
+
+#ifndef _lint
+#if defined VCPU || defined HASE
+/******************************************************************************
+ *   Fix compiler warning regarding unused variable SysKonnectId
+ ******************************************************************************/
+#define FILE_ID(str) static const char MSGGFileId[] = str;\
+static char _AVOID_UNUSED_WARNING_1_(); \
+static char _AVOID_UNUSED_WARNING_2_ () { \
+	_AVOID_UNUSED_WARNING_1_(); \
+	return MSGGFileId[0]; \
+} \
+static char _AVOID_UNUSED_WARNING_1_() { \
+	return _AVOID_UNUSED_WARNING_2_(); \
+}
+#else
+#define FILE_ID(str) static const char MSGGFileId[] = str;
+#endif
+#else //_lint
+#define FILE_ID(x)
+#endif //_lint
+
+#ifdef	DEBUG
+#ifndef SK_DBG_MSG
+#define SK_DBG_MSG(pAC,comp,cat,arg) \
+		if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&	\
+			((cat) & SK_DBG_CHKCAT(pAC)) ) {	\
+			SK_DBG_PRINTF arg;		\
+		}
+#endif
+#ifndef SK_DBG_DMP
+#define SK_DBG_DMP(pAC,comp,cat,addr,len) \
+		if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&	\
+			((cat) & SK_DBG_CHKCAT(pAC)) &&	\
+			(SK_DBG_CHKCAT(pAC) & SK_DBGCAT_DUMP ) ) {	\
+			DUMP( addr, len );		\
+		}
+#endif
+#else
+#define SK_DBG_MSG(pAC,comp,lev,arg)
+#define SK_DBG_DMP(pAC,comp,cat,addr,len)
+#endif
+
+/* PLS NOTE:
+ * =========
+ * Due to any restrictions of kernel printf routines do not use other
+ * format identifiers as: %x %d %c %s .
+ * Never use any combined format identifiers such as: %lx %ld in your
+ * printf - argument (arg) because some OS specific kernel printfs may
+ * only support some basic identifiers.
+ */
+
+/* Debug modules */
+
+#define SK_DBGMOD_MERR	0x00000001L	/* general module error indication */
+#define SK_DBGMOD_HWM	0x00000002L	/* Hardware init module */
+#define SK_DBGMOD_RLMT	0x00000004L	/* RLMT module */
+#define SK_DBGMOD_VPD	0x00000008L	/* VPD module */
+#define SK_DBGMOD_I2C	0x00000010L	/* I2C module */
+#define SK_DBGMOD_PNMI	0x00000020L	/* PNMI module */
+#define SK_DBGMOD_CSUM	0x00000040L	/* CSUM module */
+#define SK_DBGMOD_ADDR	0x00000080L	/* ADDR module */
+#define SK_DBGMOD_PECP	0x00000100L	/* PECP module */
+#define SK_DBGMOD_POWM	0x00000200L	/* Power Management module */
+#ifdef SK_ASF
+#define SK_DBGMOD_ASF	0x00000400L	/* ASF module */
+#endif
+#ifdef SK_LBFO
+#define SK_DBGMOD_LACP	0x00000800L	/* link aggregation control protocol */
+#define SK_DBGMOD_FD	0x00001000L	/* frame distributor (link aggregation) */
+#endif /* SK_LBFO */
+#define SK_DBGMOD_MACS	0x00002000L	/* MACSec module */
+#define SK_DBGMOD_CFGUD	0x00004000L	/* Configuration Update Module */
+
+/* Debug events */
+
+#define SK_DBGCAT_INIT	0x00000001L	/* module/driver initialization */
+#define SK_DBGCAT_CTRL	0x00000002L	/* controlling devices */
+#define SK_DBGCAT_ERR	0x00000004L	/* error handling paths */
+#define SK_DBGCAT_TX	0x00000008L	/* transmit path */
+#define SK_DBGCAT_RX	0x00000010L	/* receive path */
+#define SK_DBGCAT_IRQ	0x00000020L	/* general IRQ handling */
+#define SK_DBGCAT_QUEUE	0x00000040L	/* any queue management */
+#define SK_DBGCAT_DUMP	0x00000080L	/* large data output e.g. hex dump */
+#define SK_DBGCAT_FATAL	0x00000100L	/* fatal error */
+
+#endif	/* __INC_SKDEBUG_H */
+
diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h
--- linux/drivers/net/sk98lin/h/skdrv1st.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skdrv1st.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,198 @@
+/******************************************************************************
+ *
+ * Name:	skdrv1st.h
+ * Project:	Yukon/Yukon2, PCI Gigabit Ethernet Adapter
+ * Purpose:	First header file for driver and all other modules
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDRV1ST_H
+#define __INC_SKDRV1ST_H
+
+/* Check kernel version */
+#include <linux/version.h>
+
+typedef struct s_AC	SK_AC;
+
+/* Set card versions */
+#define SK_FAR
+
+/* override some default functions with optimized linux functions */
+
+#define SK_PNMI_STORE_U16(p,v)		memcpy((char*)(p),(char*)&(v),2)
+#define SK_PNMI_STORE_U32(p,v)		memcpy((char*)(p),(char*)&(v),4)
+#define SK_PNMI_STORE_U64(p,v)		memcpy((char*)(p),(char*)&(v),8)
+#define SK_PNMI_READ_U16(p,v)		memcpy((char*)&(v),(char*)(p),2)
+#define SK_PNMI_READ_U32(p,v)		memcpy((char*)&(v),(char*)(p),4)
+#define SK_PNMI_READ_U64(p,v)		memcpy((char*)&(v),(char*)(p),8)
+
+#define SK_ADDR_EQUAL(a1,a2)		(!memcmp(a1,a2,6))
+
+#define SK_STRNCMP(s1,s2,len)		strncmp(s1,s2,len)
+#define SK_STRCPY(dest,src)		strcpy(dest,src)
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <asm/byteorder.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+
+#include <linux/init.h>
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,31)
+#include <linux/sched.h>
+#endif
+
+#include <asm/uaccess.h>
+#include <net/checksum.h>
+
+#define SK_CS_CALCULATE_CHECKSUM
+#define SkCsCalculateChecksum(p,l)	(~csum_fold(csum_partial(p, l, 0)))
+
+#include    "h/skversion.h"
+#include	"h/sktypes.h"
+#include	"h/skerror.h"
+#include	"h/skdebug.h"
+#include	"h/lm80.h"
+#include	"h/xmac_ii.h"
+
+#ifndef SK_BMU_RX_WM_PEX
+#define SK_BMU_RX_WM_PEX 0x80
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#define SK_LITTLE_ENDIAN
+#else
+#define SK_BIG_ENDIAN
+#define SK_USE_REV_DESC
+#endif
+
+#define SK_DEVINIT
+
+#define SK_NET_DEVICE	net_device
+#define SK_DRV_NAME     DRIVER_FILE_NAME
+
+/* we use gethrtime(), return unit: nanoseconds */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#define SK_TICKS_PER_SEC	100
+#else
+#define SK_TICKS_PER_SEC	HZ
+#endif
+
+#define	SK_MEM_MAPPED_IO
+
+#define SK_MAX_MACS		2
+#define SK_MAX_NETS		2
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
+#define SK_IOC			char*
+#else
+typedef void __iomem		*SK_IOC;
+#endif
+
+#define	SK_CONST64	INT64_C
+#define	SK_CONSTU64	UINT64_C
+
+#define SK_MEMCPY(dest,src,size)	memcpy(dest,src,size)
+#define SK_MEMCMP(s1,s2,size)		memcmp(s1,s2,size)
+#define SK_MEMSET(dest,val,size)	memset(dest,val,size)
+#define SK_STRLEN(pStr)			strlen((char*)(pStr))
+#define SK_STRNCPY(pDest,pSrc,size)	strncpy((char*)(pDest),(char*)(pSrc),size)
+#define SK_STRCMP(pStr1,pStr2)		strcmp((char*)(pStr1),(char*)(pStr2))
+
+/* macros to access the adapter */
+#define SK_OUT8(b,a,v)		writeb((v), ((b)+(a)))
+#define SK_OUT16(b,a,v)		writew((v), ((b)+(a)))
+#define SK_OUT32(b,a,v)		writel((v), ((b)+(a)))
+#define SK_IN8(b,a,pv)		(*(pv) = readb((b)+(a)))
+#define SK_IN16(b,a,pv)		(*(pv) = readw((b)+(a)))
+#define SK_IN32(b,a,pv)		(*(pv) = readl((b)+(a)))
+
+#define int8_t		char
+#define int16_t		short
+#define int32_t		long
+#define int64_t		long long
+#define uint8_t		u_char
+#define uint16_t	u_short
+#define uint32_t	u_long
+#define uint64_t	unsigned long long
+#define t_scalar_t	int
+#define t_uscalar_t	unsigned int
+#define uintptr_t	unsigned long
+
+#define __CONCAT__(A,B) A##B
+
+#define INT32_C(a)		__CONCAT__(a,L)
+#define INT64_C(a)		__CONCAT__(a,LL)
+#define UINT32_C(a)		__CONCAT__(a,UL)
+#define UINT64_C(a)		__CONCAT__(a,ULL)
+
+#define SK_DBG_PRINTF		printk
+
+#ifdef DEBUG
+#ifndef SK_DEBUG_CHKMOD
+#define SK_DEBUG_CHKMOD		0
+#endif
+#ifndef SK_DEBUG_CHKCAT
+#define SK_DEBUG_CHKCAT		0
+#endif
+/* those come from the makefile */
+#define SK_DBG_CHKMOD(pAC)	(SK_DEBUG_CHKMOD)
+#define SK_DBG_CHKCAT(pAC)	(SK_DEBUG_CHKCAT)
+
+extern void SkDbgPrintf(const char *format,...);
+
+#define SK_DBGMOD_DRV			0x00010000
+
+/**** possible driver debug categories ********************************/
+#define SK_DBGCAT_DRV_ENTRY		0x00010000
+#define SK_DBGCAT_DRV_SAP		0x00020000
+#define SK_DBGCAT_DRV_MCA		0x00040000
+#define SK_DBGCAT_DRV_TX_PROGRESS	0x00080000
+#define SK_DBGCAT_DRV_RX_PROGRESS	0x00100000
+#define SK_DBGCAT_DRV_PROGRESS		0x00200000
+#define SK_DBGCAT_DRV_MSG		0x00400000
+#define SK_DBGCAT_DRV_PROM		0x00800000
+#define SK_DBGCAT_DRV_TX_FRAME		0x01000000
+#define SK_DBGCAT_DRV_ERROR		0x02000000
+#define SK_DBGCAT_DRV_INT_SRC		0x04000000
+#define SK_DBGCAT_DRV_EVENT		0x08000000
+#endif
+
+#define SK_ERR_LOG		SkErrorLog
+
+extern void SkErrorLog(SK_AC*, int, int, char*);
+
+#endif
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h
--- linux/drivers/net/sk98lin/h/skdrv2nd.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1038 @@
+/******************************************************************************
+ *
+ * Name:        skdrv2nd.h
+ * Project:     Yukon/Yukon2, PCI Gigabit Ethernet Adapter
+ * Purpose:     Second header file for driver and all other modules
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the second include file of the driver, which includes all other
+ * neccessary files and defines all structures and constants used by the
+ * driver and the common modules.
+ *
+ * Include File Hierarchy:
+ *
+ *	see skge.c
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKDRV2ND_H
+#define __INC_SKDRV2ND_H
+
+#include "h/skqueue.h"
+#include "h/skgehwt.h"
+#include "h/sktimer.h"
+#include "h/sktwsi.h"
+#include "h/skgepnmi.h"
+#include "h/skvpd.h"
+#include "h/skgehw.h"
+#include "h/sky2le.h"
+#include "h/skgeinit.h"
+#include "h/skaddr.h"
+#include "h/skgesirq.h"
+#include "h/skcsum.h"
+#include "h/skgedrv.h"
+#include "h/mvyexhw.h"
+
+/* Disable ProcFS */
+#undef CONFIG_PROC_FS
+
+/* Enable SDK support */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+// #define VERBOSE_ASF_FIFO_DBUG_RPINTS
+// #define MV_SET_FW_IP_DRIVER
+#include "h/skspi.h"
+#include "h/skpflash.h"
+#include "h/skgeasfapi.h"
+#include "h/fwcommon.h"
+
+/* Set SDK parameters */
+#define MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+// #define MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+#endif
+
+/* Required for 64 bit division */
+#include "asm/div64.h"
+
+/* Define the priv structure */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+#define PRIV	dev->priv
+#define PPRIV	(DEV_NET*)dev->priv
+#else
+#define PRIV	netdev_priv(dev)
+#define PPRIV	netdev_priv(dev)
+#endif
+
+/* Defines for the poll cotroller */
+#if !defined(SK_NETDUMP_POLL)
+#define SK_NETDUMP_POLL
+#endif
+
+#if defined(SK_NETDUMP_POLL)
+#if defined(HAVE_POLL_CONTROLLER)
+#define SK_POLL_CONTROLLER
+#define CONFIG_SK98LIN_NAPI
+#elif defined(CONFIG_NET_POLL_CONTROLLER)
+#define SK_POLL_CONTROLLER
+#if !defined(CONFIG_SK98LIN_NAPI)
+#define CONFIG_SK98LIN_NAPI
+#endif
+#endif
+#endif
+
+/******************************************************************************
+ *
+ * SDK driver defines (CHANGE IT!!!!)
+ *
+ ******************************************************************************/
+#ifdef SK_NO_RLMT
+#undef SKGE_RLMT
+#define SKGE_RLMT SKGE_DRV
+#undef SK_RLMT_LINK_UP
+#define SK_RLMT_LINK_UP SK_DRV_LINK_UP
+#undef SK_RLMT_LINK_DOWN
+#define SK_RLMT_LINK_DOWN SK_DRV_LINK_DOWN
+#define SkRlmtEvent(a,b,c,d)	SkDrvEvent(a,b,c,d)
+#endif
+
+#define SKGE_ASF	14	/* ASF Event Class */
+
+/******************************************************************************
+ *
+ * Generic driver defines
+ *
+ ******************************************************************************/
+
+#define USE_TIST_FOR_RESET	/* Use timestamp for reset */
+#define Y2_RECOVERY		/* use specific recovery yukon2 functions */
+#define Y2_LE_CHECK		/* activate check for LE order */
+#define Y2_SYNC_CHECK		/* activate check for receiver in sync */
+
+// Disable RSS for older kernel versions
+#ifdef USE_SK_RSS_SUPPORT
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
+#undef USE_SK_RSS_SUPPORT
+#else
+#undef Y2_LE_CHECK		/* deactivate check for LE order */
+#undef Y2_SYNC_CHECK		/* deactivate check for receiver in sync */
+#endif
+#endif
+
+
+#define SK_YUKON2		/* Enable Yukon2 dual net support */
+#define USE_SK_TX_CHECKSUM	/* use the tx hw checksum driver functionality */
+#define USE_SK_RX_CHECKSUM	/* use the rx hw checksum driver functionality */
+#define USE_SK_TSO_FEATURE	/* use TCP segmentation offload if possible */
+#define SK_COPY_THRESHOLD 50	/* threshold for copying small RX frames;
+				 * 0 avoids copying, 9001 copies all */
+#define SK_MAX_CARD_PARAM 16	/* number of adapters that can be configured via
+				 * command line params */
+#if 0
+#define USE_TX_COMPLETE	/* use of a transmit complete interrupt */
+#endif
+#define Y2_RX_CHECK		/* RX Check timestamp */
+
+#define SK_REL_SPIN_LOCK(IoC)
+#define SK_ACQ_SPIN_LOCK(IoC)
+
+/*
+ * use those defines for a compile-in version of the driver instead
+ * of command line parameters
+ */
+// #define LINK_SPEED_A {"Auto",}
+// #define LINK_SPEED_B {"Auto",}
+// #define AUTO_NEG_A   {"Sense",}
+// #define AUTO_NEG_B   {"Sense"}
+// #define DUP_CAP_A    {"Both",}
+// #define DUP_CAP_B    {"Both",}
+// #define FLOW_CTRL_A  {"SymOrRem",}
+// #define FLOW_CTRL_B  {"SymOrRem",}
+// #define ROLE_A       {"Auto",}
+// #define ROLE_B       {"Auto",}
+// #define CON_TYPE     {"Auto",}
+// #define WOL_TYPE     {"Auto",}
+
+#ifdef Y2_RECOVERY
+#define CHECK_TRANSMIT_TIMEOUT
+#define Y2_RESYNC_WATERMARK     1000000L
+#endif
+
+/******************************************************************************
+ *
+ * Generic ISR defines
+ *
+ ******************************************************************************/
+
+#define SkIsrRetVar     irqreturn_t
+#define SkIsrRetNone    IRQ_NONE
+#define SkIsrRetHandled IRQ_HANDLED
+#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
+#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
+#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
+
+/******************************************************************************
+ *
+ * Global function prototypes
+ *
+ ******************************************************************************/
+
+extern SK_U64 SkOsGetTime(SK_AC*);
+extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
+extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
+extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
+extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
+extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
+extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
+extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
+extern int SkDrvEnterDiagMode(SK_AC *pAc);
+extern int SkDrvLeaveDiagMode(SK_AC *pAc);
+extern int spi_timer(SK_AC *pAC, unsigned int t);
+
+/******************************************************************************
+ *
+ * Linux specific TIME defines
+ *
+ ******************************************************************************/
+
+#if SK_TICKS_PER_SEC == 100
+#define SK_PNMI_HUNDREDS_SEC(t)	(t)
+#else
+#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
+#endif
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#define SK_FLASH_RESCHED cond_resched
+#endif
+
+#define SkOsGetTimeCurrent(pAC, pUsec) {\
+	static struct timeval prev_t; \
+	struct timeval t;\
+	do_gettimeofday(&t);\
+	if (prev_t.tv_sec == t.tv_sec) { \
+		if (prev_t.tv_usec > t.tv_usec) { \
+			t.tv_usec = prev_t.tv_usec; \
+		} else { \
+			prev_t.tv_usec = t.tv_usec; \
+		} \
+	} else { \
+		prev_t = t; \
+	} \
+	*pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
+}
+
+/******************************************************************************
+ *
+ * Linux specific IOCTL defines and typedefs
+ *
+ ******************************************************************************/
+
+#define	SK_IOCTL_BASE        (SIOCDEVPRIVATE)
+#define	SK_IOCTL_GETMIB      (SK_IOCTL_BASE + 0)
+#define	SK_IOCTL_SETMIB      (SK_IOCTL_BASE + 1)
+#define	SK_IOCTL_PRESETMIB   (SK_IOCTL_BASE + 2)
+#define	SK_IOCTL_GEN         (SK_IOCTL_BASE + 3)
+#define	SK_IOCTL_DIAG        (SK_IOCTL_BASE + 4)
+
+/* Embedded SDK driver ioctl */
+#define SK_IOCTL_GETLINKCAP  (SK_IOCTL_BASE + 14)
+#define SK_AUTONEG_SUCCESS 0
+#define SK_AUTONEG_FAIL    1
+#define SK_AUTONEG_OFF     2
+#define SK_AUTONEG_NOLINK  3
+
+/* Firmware ioctl defines and commands */
+#define SK_IOCTL_APPTOFW     (SK_IOCTL_BASE + 5)
+#define SK_IOCTL_APPTODRV    (SK_IOCTL_BASE + 6)
+#define SK_IOCTL_FW_SEND	1
+#define SK_IOCTL_FW_RECEIVE	2
+#define SK_IOCTL_COMMAND	5
+
+typedef struct s_FWIOCTL SK_GE_FWIOCTL;
+struct s_FWIOCTL {
+	unsigned int	Command;
+	unsigned int	Len;
+	char  __user *	pData;
+};
+
+typedef struct _DrvCmd SK_GE_CMDIOCTL;
+struct _DrvCmd {
+	SK_U32   Command;
+};
+
+typedef struct s_IOCTL SK_GE_IOCTL;
+struct s_IOCTL {
+	char __user *	pData;
+	unsigned int	Len;
+};
+
+/******************************************************************************
+ *
+ * Generic sizes and length definitions
+ *
+ ******************************************************************************/
+
+#define TX_RING_SIZE  (24*1024)			/* Yukon */
+#define RX_RING_SIZE  (24*1024)			/* Yukon */
+#define RX_MAX_NBR_BUFFERS   128		/* Yukon-EC/-II */
+#define TX_MAX_NBR_BUFFERS   128		/* Yukon-EC/-II */
+#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF		/* Max. low address */
+
+#define	ETH_BUF_SIZE        1560		/* multiples of 8 bytes */
+#define	ETH_MAX_MTU         1500
+#define	ETH_MAX_LEN         1518
+#define ETH_MIN_MTU         60
+#define ETH_MULTICAST_BIT   0x01
+#define SK_JUMBO_MTU        9000
+
+#define TX_PRIO_LOW    0 /* asynchronous queue */
+#define TX_PRIO_HIGH   1 /* synchronous queue */
+#define DESCR_ALIGN   64 /* alignment of Rx/Tx descriptors */
+
+/******************************************************************************
+ *
+ * PNMI related definitions
+ *
+ ******************************************************************************/
+
+#define SK_DRIVER_RESET(pAC, IoC)	0
+#define SK_DRIVER_SENDEVENT(pAC, IoC)	0
+#define SK_DRIVER_SELFTEST(pAC, IoC)	0
+/* For get mtu you must add an own function */
+#define SK_DRIVER_GET_MTU(pAc,IoC,i)	0
+#define SK_DRIVER_SET_MTU(pAc,IoC,i,v)	0
+#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v)	0
+
+
+/******************************************************************************
+ *
+ * Various offsets and sizes
+ *
+ ******************************************************************************/
+
+#define	SK_DRV_MODERATION_TIMER         1   /* id */
+#define SK_DRV_MODERATION_TIMER_LENGTH  1   /* 1 second */
+
+#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
+#define C_LEN_ETHERMAC_HEADER_SRC_ADDR  6
+#define C_LEN_ETHERMAC_HEADER_LENTYPE   2
+#define C_LEN_ETHERMAC_HEADER           ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \
+                                          (C_LEN_ETHERMAC_HEADER_SRC_ADDR)  + \
+                                          (C_LEN_ETHERMAC_HEADER_LENTYPE) )
+
+#define C_LEN_ETHERMTU_MINSIZE          46
+#define C_LEN_ETHERMTU_MAXSIZE_STD      1500
+#define C_LEN_ETHERMTU_MAXSIZE_JUMBO    9000
+
+#define C_LEN_ETHERNET_MINSIZE          ( (C_LEN_ETHERMAC_HEADER) + \
+                                          (C_LEN_ETHERMTU_MINSIZE) )
+
+#define C_OFFSET_IPHEADER               C_LEN_ETHERMAC_HEADER
+#define C_OFFSET_IPHEADER_IPPROTO       9
+#define C_OFFSET_TCPHEADER_TCPCS        16
+#define C_OFFSET_UDPHEADER_UDPCS        6
+
+#define C_OFFSET_IPPROTO                ( (C_LEN_ETHERMAC_HEADER) + \
+                                          (C_OFFSET_IPHEADER_IPPROTO) )
+
+#define C_PROTO_ID_UDP                  17       /* refer to RFC 790 or Stevens'   */
+#define C_PROTO_ID_TCP                  6        /* TCP/IP illustrated for details */
+
+/******************************************************************************
+ *
+ * Tx and Rx descriptor definitions
+ *
+ ******************************************************************************/
+
+typedef struct s_RxD RXD; /* the receive descriptor */
+struct s_RxD {
+	volatile SK_U32  RBControl;     /* Receive Buffer Control            */
+	SK_U32           VNextRxd;      /* Next receive descriptor,low dword */
+	SK_U32           VDataLow;      /* Receive buffer Addr, low dword    */
+	SK_U32           VDataHigh;     /* Receive buffer Addr, high dword   */
+	SK_U32           FrameStat;     /* Receive Frame Status word         */
+	SK_U32           TimeStamp;     /* Time stamp from XMAC              */
+	SK_U32           TcpSums;       /* TCP Sum 2 / TCP Sum 1             */
+	SK_U32           TcpSumStarts;  /* TCP Sum Start 2 / TCP Sum Start 1 */
+	RXD             *pNextRxd;      /* Pointer to next Rxd               */
+	struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer   */
+};
+
+typedef struct s_TxD TXD; /* the transmit descriptor */
+struct s_TxD {
+	volatile SK_U32  TBControl;     /* Transmit Buffer Control            */
+	SK_U32           VNextTxd;      /* Next transmit descriptor,low dword */
+	SK_U32           VDataLow;      /* Transmit Buffer Addr, low dword    */
+	SK_U32           VDataHigh;     /* Transmit Buffer Addr, high dword   */
+	SK_U32           FrameStat;     /* Transmit Frame Status Word         */
+	SK_U32           TcpSumOfs;     /* Reserved / TCP Sum Offset          */
+#ifndef SK_USE_REV_DESC
+	SK_U16           TcpSumWr;      /* TCP Sum Write                      */
+	SK_U16           TcpSumSt;      /* TCP Sum Start                      */
+#else
+	SK_U16           TcpSumSt;      /* TCP Sum Start                      */
+	SK_U16           TcpSumWr;      /* TCP Sum Write                      */
+#endif
+	SK_U32           TcpReserved;   /* not used                           */
+	TXD             *pNextTxd;      /* Pointer to next Txd                */
+	struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer    */
+};
+
+/******************************************************************************
+ *
+ * Generic Yukon-II defines
+ *
+ ******************************************************************************/
+
+
+/* Number of Status LE which will be allocated at init time. */
+#define NUMBER_OF_ST_LE 4096L
+
+/* Number of revceive LE which will be allocated at init time. */
+#define NUMBER_OF_RX_LE 512
+
+/* Number of transmit LE which will be allocated at init time. */
+#define NUMBER_OF_TX_LE 1024L
+
+#define LE_SIZE   sizeof(SK_HWLE)
+#define MAX_NUM_FRAGS   (MAX_SKB_FRAGS + 1)
+#define MIN_LEN_OF_LE_TAB   128
+#define MAX_UNUSED_RX_LE_WORKING   8
+#ifdef MAX_FRAG_OVERHEAD
+#undef MAX_FRAG_OVERHEAD
+#define MAX_FRAG_OVERHEAD   4
+#endif
+// as we have a maximum of 16 physical fragments,
+// maximum 1 ADDR64 per physical fragment
+// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
+#define MIN_LE_FREE_REQUIRED   ((16*2) + 4)
+//#define IS_GMAC(pAc)   (!pAc->GIni.GIGenesis)
+#define IS_GMAC(pAc)   (0)
+#ifdef USE_SYNC_TX_QUEUE
+#define TXS_MAX_LE   256
+#else /* !USE_SYNC_TX_QUEUE */
+#define TXS_MAX_LE   0
+#endif
+
+#define ETHER_MAC_HDR_LEN   (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
+#define IP_HDR_LEN   20
+#define TCP_CSUM_OFFS   0x10
+#define UDP_CSUM_OFFS   0x06
+
+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
+/* event for recovery from rx out of sync */
+#define SK_DRV_RECOVER    SK_DRV_PRIVATE_BASE + 1
+#endif
+/******************************************************************************
+ *
+ * Structures specific for Yukon-II
+ *
+ ******************************************************************************/
+
+typedef	struct s_frag SK_FRAG;
+struct s_frag {
+ 	SK_FRAG       *pNext;
+ 	char          *pVirt;
+  	SK_U64         pPhys;
+ 	unsigned int   FragLen;
+};
+
+typedef	struct s_packet SK_PACKET;
+struct s_packet {
+	/* Common infos: */
+	SK_PACKET       *pNext;         /* pointer for packet queues          */
+	unsigned int     PacketLen;     /* length of packet                   */
+	unsigned int     NumFrags;      /* nbr of fragments (for Rx always 1) */
+	SK_FRAG         *pFrag;         /* fragment list                      */
+	SK_FRAG          FragArray[MAX_NUM_FRAGS]; /* TX fragment array       */
+	unsigned int     NextLE;        /* next LE to use for the next packet */
+
+	/* Private infos: */
+	struct sk_buff	*pMBuf;         /* Pointer to Linux' socket buffer    */
+};
+
+typedef	struct s_queue SK_PKT_QUEUE;
+struct s_queue {
+ 	SK_PACKET       *pHead;
+ 	SK_PACKET       *pTail;
+	spinlock_t       QueueLock;     /* serialize packet accesses          */
+};
+
+/*******************************************************************************
+ *
+ * Macros specific for Yukon-II queues
+ *
+ ******************************************************************************/
+
+#define IS_Q_EMPTY(pQueue)  ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
+#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
+
+#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket)	{	\
+        if ((pQueue)->pHead != NULL) {				\
+		(pPacket)       = (pQueue)->pHead;		\
+		(pQueue)->pHead = (pPacket)->pNext;		\
+		if ((pQueue)->pHead == NULL) {			\
+			(pQueue)->pTail = NULL;			\
+		}						\
+		(pPacket)->pNext = NULL;			\
+	} else {						\
+		(pPacket) = NULL;				\
+	}							\
+}
+
+#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) {	\
+	if ((pQueue)->pHead != NULL) {				\
+		(pPacket)->pNext = (pQueue)->pHead;		\
+	} else {						\
+		(pPacket)->pNext = NULL;			\
+		(pQueue)->pTail  = (pPacket);			\
+	}							\
+      	(pQueue)->pHead  = (pPacket);				\
+}
+
+#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) {	\
+	(pPacket)->pNext = NULL;				\
+	if ((pQueue)->pTail != NULL) {				\
+		(pQueue)->pTail->pNext = (pPacket);		\
+	} else {						\
+		(pQueue)->pHead        = (pPacket);		\
+	}							\
+	(pQueue)->pTail = (pPacket);				\
+}
+
+#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
+	if ((pPktGrpStart) != NULL) {					\
+		if ((pQueue)->pTail != NULL) {				\
+			(pQueue)->pTail->pNext = (pPktGrpStart);	\
+		} else {						\
+			(pQueue)->pHead = (pPktGrpStart);		\
+		}							\
+		(pQueue)->pTail = (pPktGrpEnd);				\
+	}								\
+}
+
+/* Required: 'Flags' */
+#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket)	{	\
+	spin_lock_irqsave(&((pQueue)->QueueLock), Flags);	\
+	if ((pQueue)->pHead != NULL) {				\
+		(pPacket)       = (pQueue)->pHead;		\
+		(pQueue)->pHead = (pPacket)->pNext;		\
+		if ((pQueue)->pHead == NULL) {			\
+			(pQueue)->pTail = NULL;			\
+		}						\
+		(pPacket)->pNext = NULL;			\
+	} else {						\
+		(pPacket) = NULL;				\
+	}							\
+	spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags);	\
+}
+
+/* Required: 'Flags' */
+#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket)	{	\
+	spin_lock_irqsave(&(pQueue)->QueueLock, Flags);		\
+	if ((pQueue)->pHead != NULL) {				\
+		(pPacket)->pNext = (pQueue)->pHead;		\
+	} else {						\
+		(pPacket)->pNext = NULL;			\
+		(pQueue)->pTail  = (pPacket);			\
+	}							\
+	(pQueue)->pHead = (pPacket);				\
+	spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);	\
+}
+
+/* Required: 'Flags' */
+#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket)	{	\
+	spin_lock_irqsave(&(pQueue)->QueueLock, Flags);		\
+	(pPacket)->pNext = NULL;				\
+	if ((pQueue)->pTail != NULL) {				\
+		(pQueue)->pTail->pNext = (pPacket);		\
+	} else {						\
+		(pQueue)->pHead = (pPacket);			\
+	}							\
+	(pQueue)->pTail = (pPacket);				\
+	spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);	\
+}
+
+/* Required: 'Flags' */
+#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) {	\
+	if ((pPktGrpStart) != NULL) {					\
+		spin_lock_irqsave(&(pQueue)->QueueLock, Flags);		\
+		if ((pQueue)->pTail != NULL) {				\
+			(pQueue)->pTail->pNext = (pPktGrpStart);	\
+		} else {						\
+			(pQueue)->pHead = (pPktGrpStart);		\
+		}							\
+		(pQueue)->pTail = (pPktGrpEnd);				\
+		spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);	\
+	}								\
+}
+
+/*
+ *Check if the low address (32 bit) is near the 4G limit or over it.
+ * Set the high address to a wrong value.
+ * Doing so we force to write the ADDR64 LE.
+ */
+#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) {	\
+	if ((~0-_LowAddress) <_Length) {				\
+		_HighAddress= MAXIMUM_LOW_ADDRESS;			\
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,			\
+			("High Address must be set for HW. LowAddr = %d  Length = %d\n",	\
+			_LowAddress, _Length));				\
+	}								\
+}
+
+/*******************************************************************************
+ *
+ * Macros specific for Yukon-II queues (tist)
+ *
+ ******************************************************************************/
+
+#ifdef USE_TIST_FOR_RESET
+/* port is fully operational */
+#define SK_PSTATE_NOT_WAITING_FOR_TIST                  0
+/* port in reset until any tist LE */
+#define SK_PSTATE_WAITING_FOR_ANY_TIST          BIT_0
+/* port in reset until timer reaches pAC->MinTistLo */
+#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST     BIT_1
+#define SK_PSTATE_PORT_SHIFT    4
+#define SK_PSTATE_PORT_MASK             ((1 << SK_PSTATE_PORT_SHIFT) - 1)
+
+/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
+#define OP_MOD_TXINDEX 0x71
+/* opcode for a TX_INDEX LE in which Port A has to be ignored */
+#define OP_MOD_TXINDEX_NO_PORT_A 0x71
+/* opcode for a TX_INDEX LE in which Port B has to be ignored */
+#define OP_MOD_TXINDEX_NO_PORT_B 0x72
+/* opcode for LE to be ignored because port is still in reset */
+#define OP_MOD_LE 0x7F
+
+/* set tist wait mode Bit for port */
+#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port)        \
+	{ \
+		(pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
+	}
+
+/* reset tist waiting for specified port */
+#define SK_CLR_STATE_FOR_PORT(pAC, Port)        \
+	{ \
+		(pAC)->AdapterResetState &= \
+			~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
+	}
+
+/* return SK_TRUE when port is in reset waiting for tist */
+#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
+	((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
+		SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
+
+/* return SK_TRUE when port is in reset waiting for any tist */
+#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
+	((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
+		SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
+
+/* return SK_TRUE when port is in reset waiting for a specific tist */
+#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
+	((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
+		SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
+		SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
+
+/* return whether adapter is expecting a tist LE */
+#define SK_ADAPTER_WAITING_FOR_TIST(pAC)        ((pAC)->AdapterResetState != 0)
+
+/* enable timestamp timer and force creation of tist LEs */
+#define Y2_ENABLE_TIST(IoC) \
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
+
+/* disable timestamp timer and stop creation of tist LEs */
+#define Y2_DISABLE_TIST(IoC) \
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
+
+/* get current value of timestamp timer */
+#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
+	SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
+
+#endif
+
+
+/*******************************************************************************
+ *
+ * Used interrupt bits in the interrupts source register
+ *
+ ******************************************************************************/
+
+#define DRIVER_IRQS	((IS_IRQ_SW) | \
+			 (IS_R1_F)   | (IS_R2_F)  | \
+			 (IS_XS1_F)  | (IS_XA1_F) | \
+			 (IS_XS2_F)  | (IS_XA2_F))
+
+#define TX_COMPL_IRQS	((IS_XS1_B)  | (IS_XS1_F) | \
+			 (IS_XA1_B)  | (IS_XA1_F) | \
+			 (IS_XS2_B)  | (IS_XS2_F) | \
+			 (IS_XA2_B)  | (IS_XA2_F))
+
+#define NAPI_DRV_IRQS	((IS_R1_F)   | (IS_R2_F) | \
+			 (IS_XS1_F)  | (IS_XA1_F)| \
+			 (IS_XS2_F)  | (IS_XA2_F))
+
+#define Y2_DRIVER_IRQS	((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
+
+#define SPECIAL_IRQS	((IS_HW_ERR)    |(IS_I2C_READY)  | \
+			 (IS_EXT_REG)   |(IS_TIMINT)     | \
+			 (IS_PA_TO_RX1) |(IS_PA_TO_RX2)  | \
+			 (IS_PA_TO_TX1) |(IS_PA_TO_TX2)  | \
+			 (IS_MAC1)      |(IS_LNK_SYNC_M1)| \
+			 (IS_MAC2)      |(IS_LNK_SYNC_M2)| \
+			 (IS_R1_C)      |(IS_R2_C)       | \
+			 (IS_XS1_C)     |(IS_XA1_C)      | \
+			 (IS_XS2_C)     |(IS_XA2_C))
+
+#define Y2_SPECIAL_IRQS	((Y2_IS_HW_ERR)   |(Y2_IS_ASF)      | \
+			 (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT)   | \
+			 (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
+			 (Y2_IS_CHK_RX2)  |(Y2_IS_CHK_TXS2) | \
+			 (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
+			 (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1)  | \
+			 (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
+
+#define IRQ_MASK	((IS_IRQ_SW)    | \
+			 (IS_R1_F)      |(IS_R2_F)     | \
+			 (IS_XS1_F)     |(IS_XA1_F)    | \
+			 (IS_XS2_F)     |(IS_XA2_F)    | \
+			 (IS_HW_ERR)    |(IS_I2C_READY)| \
+			 (IS_EXT_REG)   |(IS_TIMINT)   | \
+			 (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
+			 (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
+			 (IS_MAC1)      |(IS_MAC2)     | \
+			 (IS_R1_C)      |(IS_R2_C)     | \
+			 (IS_XS1_C)     |(IS_XA1_C)    | \
+			 (IS_XS2_C)     |(IS_XA2_C))
+
+#define Y2_IRQ_MASK	((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
+
+#define IRQ_HWE_MASK	(IS_ERR_MSK)		/* enable all HW irqs */
+#define Y2_IRQ_HWE_MASK	(Y2_HWE_ALL_MSK)	/* enable all HW irqs */
+#define Y2_IS_BASE      ((Y2_IS_HW_ERR) | (Y2_IS_STAT_BMU))
+
+typedef struct s_DevNet DEV_NET;
+
+struct s_DevNet {
+	struct      proc_dir_entry *proc;
+	int         PortNr;
+	int         NetNr;
+	char        InitialDevName[20];
+	char        CurrentName[20];
+	SK_BOOL     NetConsoleMode;
+#ifdef Y2_RECOVERY
+	struct      timer_list KernelTimer;	/* Kernel timer struct  */
+	int         TransmitTimeoutTimer; 	/* Transmit timer       */
+	SK_BOOL     TimerExpired;		/* Transmit timer       */
+	SK_BOOL     InRecover;		/* Recover flag		*/
+#ifdef Y2_RX_CHECK
+	SK_U32      PreviousMACFifoRP;	/* Backup of the FRP    */
+	SK_U32      PreviousMACFifoRLev;	/* Backup of the FRL    */
+	SK_U32      PreviousRXFifoRP;	/* Backup of the RX FRP */
+	SK_U8       PreviousRXFifoRLev;	/* Backup of the RX FRL */
+	SK_U32      LastJiffies;		/* Backup of the jiffies*/
+#endif
+#endif
+	SK_AC       *pAC;
+	struct      timer_list ProcfsTimer;	/* Procfs timer struct  */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	struct      napi_struct napi;	/* NAPI structure */
+#endif
+};
+
+/*******************************************************************************
+ *
+ * Rx/Tx Port structures
+ *
+ ******************************************************************************/
+
+typedef struct s_TxPort	TX_PORT;
+struct s_TxPort {                       /* the transmit descriptor rings */
+	caddr_t         pTxDescrRing;   /* descriptor area memory        */
+	SK_U64          VTxDescrRing;   /* descr. area bus virt. addr.   */
+	TXD            *pTxdRingHead;   /* Head of Tx rings              */
+	TXD            *pTxdRingTail;   /* Tail of Tx rings              */
+	TXD            *pTxdRingPrev;   /* descriptor sent previously    */
+	int             TxdRingPrevFree;/* previously # of free entrys   */
+	int             TxdRingFree;    /* # of free entrys              */
+	spinlock_t      TxDesRingLock;  /* serialize descriptor accesses */
+	SK_IOC          HwAddr;         /* bmu registers address         */
+	int             PortIndex;      /* index number of port (0 or 1) */
+	SK_PACKET      *TransmitPacketTable;
+	SK_LE_TABLE     TxALET;         /* tx (async) list element table */
+	SK_LE_TABLE     TxSLET;         /* tx (sync) list element table  */
+	SK_PKT_QUEUE    TxQ_free;
+	SK_PKT_QUEUE    TxAQ_waiting;
+	SK_PKT_QUEUE    TxSQ_waiting;
+	SK_PKT_QUEUE    TxAQ_working;
+	SK_PKT_QUEUE    TxSQ_working;
+	unsigned        LastDone;
+};
+
+typedef struct s_RxPort	RX_PORT;
+struct s_RxPort {                       /* the receive descriptor rings  */
+	caddr_t         pRxDescrRing;   /* descriptor area memory        */
+	SK_U64          VRxDescrRing;   /* descr. area bus virt. addr.   */
+	RXD            *pRxdRingHead;   /* Head of Rx rings              */
+	RXD            *pRxdRingTail;   /* Tail of Rx rings              */
+	RXD            *pRxdRingPrev;   /* descr given to BMU previously */
+	int             RxdRingFree;    /* # of free entrys              */
+	spinlock_t      RxDesRingLock;  /* serialize descriptor accesses */
+	int             RxFillLimit;    /* limit for buffers in ring     */
+	SK_IOC          HwAddr;         /* bmu registers address         */
+	int             PortIndex;      /* index number of port (0 or 1) */
+	SK_BOOL         UseRxCsum;      /* use Rx checksumming (yes/no)  */
+	SK_PACKET      *ReceivePacketTable;
+	SK_LE_TABLE     RxLET;          /* rx list element table         */
+	SK_PKT_QUEUE    RxQ_working;
+	SK_PKT_QUEUE    RxQ_waiting;
+	int             RxBufSize;
+};
+
+/*******************************************************************************
+ *
+ * Interrupt masks used in combination with interrupt moderation
+ *
+ ******************************************************************************/
+
+#define IRQ_EOF_AS_TX     ((IS_XA1_F)     | (IS_XA2_F))
+#define IRQ_EOF_SY_TX     ((IS_XS1_F)     | (IS_XS2_F))
+#define IRQ_MASK_TX_ONLY  ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))
+#define IRQ_MASK_RX_ONLY  ((IS_R1_F)      | (IS_R2_F))
+#define IRQ_MASK_SP_ONLY  (SPECIAL_IRQS)
+#define IRQ_MASK_TX_RX    ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
+#define IRQ_MASK_SP_RX    ((SPECIAL_IRQS)    | (IRQ_MASK_RX_ONLY))
+#define IRQ_MASK_SP_TX    ((SPECIAL_IRQS)    | (IRQ_MASK_TX_ONLY))
+#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS)    | (IRQ_MASK_TX_RX))
+
+#define IRQ_MASK_Y2_TX_ONLY  (Y2_IS_STAT_BMU)
+#define IRQ_MASK_Y2_RX_ONLY  (Y2_IS_STAT_BMU)
+#define IRQ_MASK_Y2_SP_ONLY  (SPECIAL_IRQS)
+#define IRQ_MASK_Y2_TX_RX    ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
+#define IRQ_MASK_Y2_SP_RX    ((SPECIAL_IRQS)    | (IRQ_MASK_RX_ONLY))
+#define IRQ_MASK_Y2_SP_TX    ((SPECIAL_IRQS)    | (IRQ_MASK_TX_ONLY))
+#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS)    | (IRQ_MASK_TX_RX))
+
+/*******************************************************************************
+ *
+ * Defines and typedefs regarding interrupt moderation
+ *
+ ******************************************************************************/
+
+#define C_INT_MOD_NONE			1
+#define C_INT_MOD_STATIC		2
+#define C_INT_MOD_DYNAMIC		4
+
+#define C_CLK_FREQ_GENESIS		 53215000 /* or:  53.125 MHz */
+#define C_CLK_FREQ_YUKON		 78215000 /* or:  78.125 MHz */
+#define C_CLK_FREQ_YUKON_EC		125000000 /* or: 125.000 MHz */
+
+#define C_Y2_INTS_PER_SEC_DEFAULT	5000
+#define C_INTS_PER_SEC_DEFAULT		2000
+#define C_INT_MOD_IPS_LOWER_RANGE	30        /* in IRQs/second */
+#define C_INT_MOD_IPS_UPPER_RANGE	40000     /* in IRQs/second */
+
+#define C_TX_INT_MOD_UPPER_RANGE	4095     /* in IRQs/second */
+
+
+typedef struct s_DynIrqModInfo {
+	SK_U64     PrevPort0RxIntrCts;
+	SK_U64     PrevPort1RxIntrCts;
+	SK_U64     PrevPort0TxIntrCts;
+	SK_U64     PrevPort1TxIntrCts;
+	SK_U64     PrevPort0StatusLeIntrCts;
+	SK_U64     PrevPort1StatusLeIntrCts;
+	int        MaxModIntsPerSec;            /* Moderation Threshold   */
+	int        MaxModIntsPerSecUpperLimit;  /* Upper limit for DIM    */
+	int        MaxModIntsPerSecLowerLimit;  /* Lower limit for DIM    */
+	long       MaskIrqModeration;           /* IRQ Mask (eg. 'TxRx')  */
+	int        IntModTypeSelect;            /* Type  (eg. 'dynamic')  */
+	int        DynIrqModSampleInterval;     /* expressed in seconds!  */
+	SK_TIMER   ModTimer;                    /* Timer for dynamic mod. */
+} DIM_INFO;
+
+/*******************************************************************************
+ *
+ * Defines and typedefs regarding wake-on-lan
+ *
+ ******************************************************************************/
+
+typedef struct s_WakeOnLanInfo {
+	SK_U32     SupportedWolOptions;         /* e.g. WAKE_PHY...         */
+	SK_U32     ConfiguredWolOptions;        /* e.g. WAKE_PHY...         */
+} WOL_INFO;
+
+/*******************************************************************************
+ *
+ * Defines and typedefs regarding link configuration
+ *
+ ******************************************************************************/
+#define SKL_DC_BOTH	0
+#define SKL_DC_FULL 1
+#define SKL_DC_HALF 2
+#define SKL_AN_OFF	0
+#define SKL_AN_ON	1
+#define SKL_AN_SENS	2
+
+typedef struct s_LinkInfo	LINK_INFO;
+struct s_LinkInfo {
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	SK_BOOL		LinkMaintenance; 	/* Link maintenance */
+	SK_BOOL		PLinkMaintenance; 	/* Link maintenance parameter */
+#endif
+	SK_U8		PLinkModeConf;		/* Link Mode configured */
+	SK_U8		PFlowCtrlMode;		/* Flow Control Mode */
+	SK_U8		PMSMode;		    /* Master/Slave Mode */
+	SK_U8		PLinkSpeed;		    /* configured Link Speed */
+	SK_U8		PAutoNeg;		    /* Auto negotiation */
+	SK_U8		PDuplexCap;		    /* Duplex */
+    SK_BOOL		RSS;				/* Receive-Side Scaling parameter */
+};
+
+/* Alloc flags */
+#define SK_ALLOC_IRQ	0x00000001
+#define SK_ALLOC_MSI    0x00000002
+
+#define	DIAG_ACTIVE		1
+#define	DIAG_NOTACTIVE		0
+
+/****************************************************************************
+ *
+ * Per board structure / Adapter Context structure:
+ * Contains all 'per device' necessary handles, flags, locks etc.:
+ *
+ ******************************************************************************/
+
+struct s_AC  {
+	SK_GEINIT                GIni;          /* GE init struct             */
+	SK_PNMI                  Pnmi;          /* PNMI data struct           */
+	SK_VPD                   vpd;           /* vpd data struct            */
+	SK_QUEUE                 Event;         /* Event queue                */
+	SK_HWT                   Hwt;           /* Hardware Timer ctrl struct */
+	SK_TIMCTRL               Tim;           /* Software Timer ctrl struct */
+	SK_I2C                   I2c;           /* I2C relevant data structure*/
+	SK_ADDR                  Addr;          /* for Address module         */
+	SK_CSUM                  Csum;          /* for checksum module        */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	SK_U64                   timebuf;
+	SK_FWOS                  FwOs;
+	SK_FWCOMMON              FwCommon;
+	SK_FWAPP                 FwApp;
+	SK_SPI                   spi;           /* structure for SPI flash */
+	SK_PFL                   pfl;
+	SK_U32                   RamAddr;
+	SK_U32                   RamSelect;
+#endif
+	spinlock_t               SlowPathLock;  /* Normal IRQ lock            */
+	spinlock_t               InitLock;      /* Init lock                  */
+	spinlock_t               TxQueueLock;   /* TX Queue lock              */
+	SK_PNMI_STRUCT_DATA      PnmiStruct;    /* struct for all Pnmi-Data   */
+	int                      RlmtNets;      /* Number of nets             */
+	SK_IOC                   IoBase;        /* register set of adapter    */
+	int                      BoardLevel;    /* level of hw init (0-2)     */
+	char                     DeviceStr[80]; /* adapter string from vpd    */
+	struct pci_dev          *PciDev;        /* for access to pci cfg space*/
+	SK_U32                   PciDevId;      /* pci device id              */
+	struct SK_NET_DEVICE    *dev[2];        /* pointer to device struct   */
+	struct SK_NET_DEVICE    *IrqDev;        /* pointer to device struct   */
+	char                     Name[30];      /* driver name                */
+	struct SK_NET_DEVICE    *Next;          /* link all devs for cleanup  */
+	struct net_device_stats  stats;         /* linux 'netstat -i' stats   */
+	int                      Index;         /* internal board idx number  */
+	int                      RxQueueSize;   /* memory used for RX queue   */
+	int                      TxSQueueSize;  /* memory used for TXS queue  */
+	int                      TxAQueueSize;  /* memory used for TXA queue  */
+	int                      PromiscCount;  /* promiscuous mode counter   */
+	int                      AllMultiCount; /* allmulticast mode counter  */
+	int                      MulticCount;   /* number of MC addresses used*/
+	int                      HWRevision;	/* Hardware revision          */
+	int                      ActivePort;	/* the active XMAC port       */
+	int                      MaxPorts;      /* number of activated ports  */
+	int                      TxDescrPerRing;/* # of descriptors TX ring   */
+	int                      RxDescrPerRing;/* # of descriptors RX ring   */
+	caddr_t                  pDescrMem;     /* Ptr to the descriptor area */
+	dma_addr_t               pDescrMemDMA;  /* PCI DMA address of area    */
+	SK_U32                   PciState[16];  /* PCI state */
+	TX_PORT                  TxPort[SK_MAX_MACS][2];
+	RX_PORT                  RxPort[SK_MAX_MACS];
+	SK_LE_TABLE              StatusLETable;
+	unsigned                 SizeOfAlignedLETables;
+	spinlock_t               SetPutIndexLock;
+	int                      MaxUnusedRxLeWorking;
+	int                      InterfaceUp[2];
+	unsigned int             CsOfs1;        /* for checksum calculation   */
+	unsigned int             CsOfs2;        /* for checksum calculation   */
+	SK_U32                   CsOfs;         /* for checksum calculation   */
+	SK_BOOL                  CheckQueue;    /* check event queue soon     */
+	DIM_INFO                 DynIrqModInfo; /* all data related to IntMod */
+	LINK_INFO                LinkInfo[SK_MAX_MACS];
+	WOL_INFO                 WolInfo;       /* all info regarding WOL     */
+	int                      ChipsetType;   /* 1=Yukon, 2=Yukon2          */
+	SK_BOOL                  LowLatency;    /* LowLatency optimization on?*/
+	SK_BOOL                  MsiIrq;        /* MSI Irq handling on?       */
+	SK_U32                   TxModeration;  /* TxModeration optimization  */
+	SK_U32                   DiagModeActive;/* is diag active?            */
+	SK_BOOL                  DiagFlowCtrl;  /* for control purposes       */
+	SK_PNMI_STRUCT_DATA      PnmiBackup;    /* backup structure for PNMI  */
+	SK_BOOL                  WasIfUp[SK_MAX_MACS];
+	SK_U32                   WolSpeedType;   /* Wol speed type */
+	SK_U32                   WolDuplexType;  /* Wol type; TRUE==FD; FALSE==HD */
+	char                     *pVirtMemAddr;
+	wait_queue_head_t        msi_wait;
+	SK_U32                   AllocFlag;     /* alloc flag of resources    */
+#ifdef USE_TIST_FOR_RESET
+	int                      AdapterResetState;
+	SK_U32                   MinTistLo;
+	SK_U32                   MinTistHi;
+#endif
+#ifdef Y2_RECOVERY
+	int                      LastPort;       /* port for curr. handled rx */
+	int                      LastOpc;        /* last rx LEs opcode	      */
+#endif
+#ifdef Y2_SYNC_CHECK
+	unsigned long            FramesWithoutSyncCheck; /* since last check  */
+#endif
+	SK_BOOL                  RequestedIrq;
+	unsigned int             InterruptSource;
+	SK_BOOL                  Suspended;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	SK_BOOL                  FwRun;
+	SK_BOOL                  FwState;
+	SK_U32                   SdkQH;
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	SK_U16                   DriverLinkStat;
+#endif
+	spinlock_t               FwFifoLock;
+	SK_U32                   *pFwBuffer;
+	int                      FwBufferLen;
+	SK_U64                   TimeBuf;
+#endif
+};
+
+#endif
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
+
diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h
--- linux/drivers/net/sk98lin/h/skerror.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skerror.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skerror.h#6 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #6 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	SK specific Error log support
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef _INC_SKERROR_H_
+#define _INC_SKERROR_H_
+
+/*
+ * Define Error Classes
+ */
+#define SK_ERRCL_OTHER		(0)		/* Other error */
+#define SK_ERRCL_CONFIG		(1L<<0)	/* Configuration error */
+#define SK_ERRCL_INIT		(1L<<1)	/* Initialization error */
+#define SK_ERRCL_NORES		(1L<<2)	/* Out of Resources error */
+#define SK_ERRCL_SW			(1L<<3)	/* Internal Software error */
+#define SK_ERRCL_HW			(1L<<4)	/* Hardware Failure */
+#define SK_ERRCL_COMM		(1L<<5)	/* Communication error */
+#define SK_ERRCL_INFO		(1L<<6)	/* Information */
+
+/*
+ * Define Error Code Bases
+ */
+#define SK_ERRBASE_RLMT		 100	/* Base Error number for RLMT */
+#define SK_ERRBASE_HWINIT	 200	/* Base Error number for HWInit */
+#define SK_ERRBASE_VPD		 300	/* Base Error number for VPD */
+#define SK_ERRBASE_PNMI		 400	/* Base Error number for PNMI */
+#define SK_ERRBASE_CSUM		 500	/* Base Error number for Checksum */
+#define SK_ERRBASE_SIRQ		 600	/* Base Error number for Special IRQ */
+#define SK_ERRBASE_I2C		 700	/* Base Error number for I2C module */
+#define SK_ERRBASE_QUEUE	 800	/* Base Error number for Scheduler */
+#define SK_ERRBASE_ADDR		 900	/* Base Error number for Address module */
+#define SK_ERRBASE_PECP		1000	/* Base Error number for PECP */
+#define SK_ERRBASE_DRV		1100	/* Base Error number for Driver */
+#define SK_ERRBASE_ASF		1200	/* Base Error number for ASF */
+#define	SK_ERRBASE_MACSEC	1300	/* Base Error number for MACSec module */
+
+#endif	/* _INC_SKERROR_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/skgeasfapi.h linux-new/drivers/net/sk98lin/h/skgeasfapi.h
--- linux/drivers/net/sk98lin/h/skgeasfapi.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgeasfapi.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,145 @@
+/******************************************************************************
+ *
+ * Name:    skgeasfapi.h
+ * Project: asf/ipmi
+ * Purpose: asf/ipmi interface in windows driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *	Server Adapters.
+ *
+ *	Address all question to: gr-msgg-linux@marvell.com
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ *****************************************************************************/
+
+#ifndef _INC_SKGEASFAPI_H_
+#define _INC_SKGEASFAPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+
+/* Function definitions */
+extern int   SkFwApiGet (SK_AC *pAC , SK_IOC IoC);
+extern void  SkFwIsr (SK_AC *pAC , SK_IOC IoC);
+extern void  SetRamAddr(SK_AC *, int, int, int);
+extern SK_U8 SkAccessRamBuf(SK_AC  *pAC, SK_U32 RamAddrOffset, SK_U32 RamAddrMaxValue);
+
+
+/* Buffer defines */
+#define HOST_ROM_ADDR          0x8300000
+#define HOST_READ_OFFSET       0x27000
+#define HOST_READ_ADDR         HOST_ROM_ADDR+HOST_READ_OFFSET
+#define HOST_READ_QWORD        HOST_READ_OFFSET/8
+#define HOST_READ_BUFSIZE      0x5000 /* 20*1024 */
+#define HOST_READ_LAST_QWORD   ((HOST_READ_BUFSIZE+0x10)/0x8)+HOST_READ_QWORD
+#define HOST_WRITE_ADDR        HOST_READ_ADDR+HOST_READ_BUFSIZE+0x18
+#define HOST_WRITE_QWORD       ((HOST_READ_BUFSIZE+0x18)/0x8)+HOST_READ_QWORD
+#define HOST_WRITE_BUFSIZE     0x800 /* 2*1024 */
+#define HOST_WRITE_LAST_QWORD  ((HOST_WRITE_BUFSIZE+0x8)/0x8)+HOST_WRITE_QWORD
+
+/* Additional defines for new driver/firmware FIFO interface */
+#define HOST_READ_DATA_BUFSIZE      0x810  /* 0x800  (data) + 0x10 (pointer/status) */
+#define HOST_READ_PACKET_BUFSIZE    0x4800 /* 0x47f0 (data) + 0x10 (pointer/status) */
+#define HOST_READ_DATA_QWORD        0x4e01 /* 0x27008/8 */
+#define HOST_READ_DATA_LAST_QWORD   0x4f02 /* 0x27810/8 */
+#define HOST_READ_PACKET_QWORD      0x4f03 /* 0x27818/8 */
+#define HOST_READ_PACKET_LAST_QWORD 0x5802 /* 0x2c010/8 */
+#define HOST_WRITE_DATA_QWORD       0x5803 /* 0x2c018/8 */
+
+#define SK_ST_FIFOTYPE        3
+#define SK_ST_BUFADDR_LOW     0x0 /* To be defined if needed... */
+#define SK_ST_BUFADDR_HIGH    0x0
+
+#define SKGE_DGRAM_CMD         1    /* Command */
+#define SKGE_DGRAM_RESULT      2    /* Command result */
+#define SKGE_DGRAM_PACKET      3    /* Packet */
+#define SKGE_DGRAM_MSG2FW      4    /* Message to FW application */
+#define SKGE_DGRAM_MSGFW       5    /* Message from FW application */
+#define SKGE_DGRAM_STATUS      7    /* Status from the FW to DRV */
+#define SKGE_DGRAM_APP_VERSION 8    /* Version string of the firmware application code */
+
+/* FIFO communication path command section */
+#define	FW_CMD_SET_IPV4_CONFIG        0x0001
+#define	FW_CMD_SET_LINK_MODE          0x0003
+
+#define	FW_CMD_SET_IPV4_CONFIG_LENGTH 16
+#define	FW_CMD_SET_LINK_MODE_LENGTH   5
+
+#define	FW_RESULT                     0x8000
+
+#define	FW_CMD_RESULT_LENGTH      6
+
+#define	FW_RESULT_OK              0
+#define	FW_RESULT_ERR             1
+#define	FW_RESULT_ERR_UNKNOWN_CMD 2
+
+
+/* Driver commands */
+#define SK_COMMAND_SLEEP           1
+#define SK_COMMAND_SA_UPDATE       2
+
+
+/* Datagram structure */
+struct _FwCmdHdr {  /* Main message header */
+#ifdef SK_LITTLE_ENDIAN
+	SK_U16 Cmd;     /* Command type */
+	SK_U16 Len;     /* Complete command length (hdr+payload) */
+#else
+	SK_U16 Len;     /* Complete command length (hdr+payload) */
+	SK_U16 Cmd;     /* Command type */
+#endif
+};
+typedef struct _FwCmdHdr FwCmdHdr;
+
+struct _FifoDgram {
+	SK_U16 DgramLen;		/* len FifoDgram + Payload + Padding */
+	SK_U16 PayloadLen;		/* len of Payload */
+	SK_U32 Id;				/* Id of Payload */
+};
+typedef struct _FifoDgram FifoDgram;
+
+struct _DgamMsg {			/* main message header */
+	SK_U16 cmd;				/* message type */
+	SK_U16 len;				/* complete message length (hdr+payload) */
+	SK_U16 data;
+};
+typedef struct _DgamMsg DgamMsg;
+
+struct _CmdSetIpv4Config {  /* Set IPv4 configuration */
+	FwCmdHdr Hdr;
+	SK_U32   Ip;            /* IPv4 */
+	SK_U32   Mask;          /* IPv4 */
+	SK_U32   Gateway;       /* IPv4 */
+};
+typedef struct _CmdSetIpv4Config CmdSetIpv4Config;
+
+struct _FwCmdResult {  /* Pass results back */
+	FwCmdHdr Hdr;
+#ifdef SK_LITTLE_ENDIAN
+	SK_U16   Result;
+	SK_U16   Endianess;
+#else
+	SK_U16   Endianess;
+	SK_U16   Result;
+#endif
+};
+typedef struct _FwCmdResult FwCmdResult;
+
+
+#endif  /* _INC_SKGEASF_H_ */
diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h
--- linux/drivers/net/sk98lin/h/skgedrv.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgedrv.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skgedrv.h#6 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #6 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	Interface with the driver
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEDRV_H_
+#define __INC_SKGEDRV_H_
+
+/* defines ********************************************************************/
+
+/*
+ * Define the driver events.
+ * Usually the events are defined by the destination module.
+ * In case of the driver we put the definition of the events here.
+ */
+#define SK_DRV_PORT_RESET		 1	/* The port needs to be reset */
+#define SK_DRV_NET_UP			 2	/* The net is operational */
+#define SK_DRV_NET_DOWN			 3	/* The net is down */
+#define SK_DRV_SWITCH_SOFT		 4	/* Ports switch with both links connected */
+#define SK_DRV_SWITCH_HARD		 5	/* Port switch due to link failure */
+#define SK_DRV_RLMT_SEND		 6	/* Send a RLMT packet */
+#define SK_DRV_ADAP_FAIL		 7	/* The whole adapter fails */
+#define SK_DRV_PORT_FAIL		 8	/* One port fails */
+#define SK_DRV_SWITCH_INTERN	 9	/* Port switch by the driver itself */
+#define SK_DRV_POWER_DOWN		10	/* Power down mode */
+#define SK_DRV_TIMER			11	/* Timer for free use */
+#define SK_DRV_LINK_UP			12	/* Link Up event for driver */
+#ifdef SK_NO_RLMT
+#define SK_DRV_LINK_DOWN		13	/* Link Down event for driver */
+#endif
+#define SK_DRV_DOWNSHIFT_DET	14	/* Downshift 4-Pair / 2-Pair (YUKON only) */
+#define SK_DRV_RX_OVERFLOW		15	/* Receive Overflow */
+#define SK_DRV_LIPA_NOT_AN_ABLE	16	/* Link Partner not Auto-Negotiation able */
+#define SK_DRV_PEX_LINK_WIDTH	17	/* PEX negotiated Link width not maximum */
+#define SK_DRV_TX_UNDERRUN		18	/* Transmit Underrun */
+
+#define SK_DRV_PRIVATE_BASE		100	/* Base for driver private events */
+#endif /* __INC_SKGEDRV_H_ */
diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h
--- linux/drivers/net/sk98lin/h/skgehw.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgehw.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,3514 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skgehw.h#9 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #9 $, $Change: 5903 $
+ * Date:	$DateTime: 2011/03/29 15:10:31 $
+ * Purpose:	Defines and Macros for the Gigabit Ethernet Adapter Product Family
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEHW_H
+#define __INC_SKGEHW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+#define BIT_31		(1UL << 31)
+#define BIT_30		(1L << 30)
+#define BIT_29		(1L << 29)
+#define BIT_28		(1L << 28)
+#define BIT_27		(1L << 27)
+#define BIT_26		(1L << 26)
+#define BIT_25		(1L << 25)
+#define BIT_24		(1L << 24)
+#define BIT_23		(1L << 23)
+#define BIT_22		(1L << 22)
+#define BIT_21		(1L << 21)
+#define BIT_20		(1L << 20)
+#define BIT_19		(1L << 19)
+#define BIT_18		(1L << 18)
+#define BIT_17		(1L << 17)
+#define BIT_16		(1L << 16)
+#define BIT_15		(1L << 15)
+#define BIT_14		(1L << 14)
+#define BIT_13		(1L << 13)
+#define BIT_12		(1L << 12)
+#define BIT_11		(1L << 11)
+#define BIT_10		(1L << 10)
+#define BIT_9		(1L << 9)
+#define BIT_8		(1L << 8)
+#define BIT_7		(1L << 7)
+#define BIT_6		(1L << 6)
+#define BIT_5		(1L << 5)
+#define BIT_4		(1L << 4)
+#define BIT_3		(1L << 3)
+#define BIT_2		(1L << 2)
+#define BIT_1		(1L << 1)
+#define BIT_0		1L
+
+#define BIT_15S		(1U << 15)
+#define BIT_14S		(1 << 14)
+#define BIT_13S		(1 << 13)
+#define BIT_12S		(1 << 12)
+#define BIT_11S		(1 << 11)
+#define BIT_10S		(1 << 10)
+#define BIT_9S		(1 << 9)
+#define BIT_8S		(1 << 8)
+#define BIT_7S		(1 << 7)
+#define BIT_6S		(1 << 6)
+#define BIT_5S		(1 << 5)
+#define BIT_4S		(1 << 4)
+#define BIT_3S		(1 << 3)
+#define BIT_2S		(1 << 2)
+#define BIT_1S		(1 << 1)
+#define BIT_0S		1
+
+#define SHIFT31(x)	((x) << 31)
+#define SHIFT30(x)	((x) << 30)
+#define SHIFT29(x)	((x) << 29)
+#define SHIFT28(x)	((x) << 28)
+#define SHIFT27(x)	((x) << 27)
+#define SHIFT26(x)	((x) << 26)
+#define SHIFT25(x)	((x) << 25)
+#define SHIFT24(x)	((x) << 24)
+#define SHIFT23(x)	((x) << 23)
+#define SHIFT22(x)	((x) << 22)
+#define SHIFT21(x)	((x) << 21)
+#define SHIFT20(x)	((x) << 20)
+#define SHIFT19(x)	((x) << 19)
+#define SHIFT18(x)	((x) << 18)
+#define SHIFT17(x)	((x) << 17)
+#define SHIFT16(x)	((x) << 16)
+#define SHIFT15(x)	((x) << 15)
+#define SHIFT14(x)	((x) << 14)
+#define SHIFT13(x)	((x) << 13)
+#define SHIFT12(x)	((x) << 12)
+#define SHIFT11(x)	((x) << 11)
+#define SHIFT10(x)	((x) << 10)
+#define SHIFT9(x)	((x) << 9)
+#define SHIFT8(x)	((x) << 8)
+#define SHIFT7(x)	((x) << 7)
+#define SHIFT6(x)	((x) << 6)
+#define SHIFT5(x)	((x) << 5)
+#define SHIFT4(x)	((x) << 4)
+#define SHIFT3(x)	((x) << 3)
+#define SHIFT2(x)	((x) << 2)
+#define SHIFT1(x)	((x) << 1)
+#define SHIFT0(x)	((x) << 0)
+
+#define SHIFTX(x, pos)	((x) << pos)
+#define IS_SET(x, pos)	(((x) & (1 << pos)) > 0)
+
+#define ALL_32_BITS	0xffffffffUL
+
+/* Macro for arbitrary alignment of a given pointer */
+#define ALIGN_ADDR(Address, Granularity) { \
+	SK_UPTR addr = (SK_UPTR)(Address); \
+	if (addr & ((Granularity) - 1)) { \
+		addr += (Granularity); \
+		addr &= ~(SK_UPTR)((Granularity) - 1); \
+		Address = (void *)addr; \
+	}\
+}
+
+/*
+ * Configuration Space header
+ * Since this module is used for different OS', those may be
+ * duplicate on some of them (e.g. Linux). But to keep the
+ * common source, we have to live with this...
+ */
+#define PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */
+#define PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */
+#define PCI_COMMAND		0x04	/* 16 bit	Command */
+#define PCI_STATUS		0x06	/* 16 bit	Status */
+#define PCI_REV_ID		0x08	/*  8 bit	Revision ID */
+#define PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */
+#define PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */
+#define PCI_LAT_TIM		0x0d	/*  8 bit	Latency Timer */
+#define PCI_HEADER_T	0x0e	/*  8 bit	Header Type */
+#define PCI_BIST		0x0f	/*  8 bit	Built-in selftest */
+#define PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */
+#define PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */
+	/* Bytes 0x18..0x2b:	reserved */
+#define PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */
+#define PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */
+#define PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
+#define PCI_CAP_PTR		0x34	/*  8 bit	Capabilities Pointer */
+	/* Bytes 0x35..0x3b:	reserved */
+#define PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
+#define PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */
+#define PCI_MIN_GNT		0x3e	/*  8 bit	Min. Grant */
+#define PCI_MAX_LAT		0x3f	/*  8 bit	Max. Latency */
+	/* Device Dependent Region */
+#ifdef YUK_USB
+#define PCI_OUR_REG_1	0x940	/* 32 bit	Our Register 1 */
+#define PCI_OUR_REG_2	0x944	/* 32 bit	Our Register 2 */
+#else	/* !YUK_USB */
+#define PCI_OUR_REG_1	0x40	/* 32 bit	Our Register 1 */
+#define PCI_OUR_REG_2	0x44	/* 32 bit	Our Register 2 */
+#endif
+	/* Power Management Region */
+#define PCI_PM_CAP_ID	0x48	/*  8 bit	Power Management Cap. ID */
+#define PCI_PM_NITEM	0x49	/*  8 bit	PM Next Item Pointer */
+#define PCI_PM_CAP_REG	0x4a	/* 16 bit	Power Management Capabilities */
+#define PCI_PM_CTL_STS	0x4c	/* 16 bit	Power Manag. Control/Status */
+	/* Byte 0x4e:	reserved */
+#define PCI_PM_DAT_REG	0x4f	/*  8 bit	Power Manag. Data Register */
+	/* VPD Region */
+#define PCI_VPD_CAP_ID	0x50	/*  8 bit	VPD Cap. ID */
+#define PCI_VPD_NITEM	0x51	/*  8 bit	VPD Next Item Pointer */
+#define PCI_VPD_ADR_REG	0x52	/* 16 bit	VPD Address Register */
+#define PCI_VPD_DAT_REG	0x54	/* 32 bit	VPD Data Register */
+	/* Bytes 0x58..0x59:	reserved */
+#ifdef YUK_USB
+#define PCI_SER_LD_CTRL	0x95a	/* 16 bit	SEEPROM Loader Ctrl (YUKON only) */
+#else	/* !YUK_USB */
+#define PCI_SER_LD_CTRL	0x5a	/* 16 bit	SEEPROM Loader Ctrl (YUKON only) */
+#endif	/* !YUK_USB */
+	/* Bytes 0x5c..0xfc:	used by Yukon-2 */
+#define PCI_MSI_CAP_ID	0x5c	/*  8 bit	MSI Capability ID Register */
+#define PCI_MSI_NITEM	0x5d	/*  8 bit	MSI Next Item Pointer */
+#define PCI_MSI_CTRL	0x5e	/* 16 bit	MSI Message Control */
+#define PCI_MSI_ADR_LO	0x60	/* 32 bit	MSI Message Address (Lower) */
+#define PCI_MSI_ADR_HI	0x64	/* 32 bit	MSI Message Address (Upper) */
+#define PCI_MSI_DATA	0x68	/* 16 bit	MSI Message Data */
+	/* Bytes 0x6a..0x6b:	reserved */
+#define PCI_X_CAP_ID	0x6c	/*  8 bit	PCI-X Capability ID Register */
+#define PCI_X_NITEM		0x6d	/*  8 bit	PCI-X Next Item Pointer */
+#define PCI_X_COMMAND	0x6e	/* 16 bit	PCI-X Command */
+#define PCI_X_PE_STAT	0x70	/* 32 bit	PCI-X / PE Status */
+#define PCI_CAL_CTRL	0x74	/* 16 bit	PCI Calibration Control Register */
+#define PCI_CAL_STAT	0x76	/* 16 bit	PCI Calibration Status Register */
+#define PCI_DISC_CNT	0x78	/* 16 bit	PCI Discard Counter */
+#define PCI_RETRY_CNT	0x7a	/*  8 bit	PCI Retry Counter */
+	/* Byte 0x7b:	reserved */
+#define PCI_OUR_STATUS	0x7c	/* 32 bit	Adapter Status Register */
+#define PCI_ERR_REP_MSK	0x8c	/* 32 bit	Error Rep. Mask (Yukon-ECU A1b) */
+#ifdef YUK_USB
+#define PCI_OUR_REG_3	0x980	/* 32 bit	Our Register 3 (Yukon-ECU only) */
+#define PCI_OUR_REG_4	0x984	/* 32 bit	Our Register 4 (Yukon-ECU only) */
+#define PCI_OUR_REG_5	0x988	/* 32 bit	Our Register 5 (Yukon-ECU only) */
+#define PCI_CFG_REG_0	0x990	/* 32 bit	Config Register 0 (Yukon-Ext only) */
+#define PCI_CFG_REG_1	0x994	/* 32 bit	Config Register 1 (Yukon-Ext only) */
+#else	/* !YUK_USB */
+#define PCI_OUR_REG_3	0x80	/* 32 bit	Our Register 3 (Yukon-ECU only) */
+#define PCI_OUR_REG_4	0x84	/* 32 bit	Our Register 4 (Yukon-ECU only) */
+#define PCI_OUR_REG_5	0x88	/* 32 bit	Our Register 5 (Yukon-ECU only) */
+#define PCI_CFG_REG_0	0x90	/* 32 bit	Config Register 0 (Yukon-Ext only) */
+#define PCI_CFG_REG_1	0x94	/* 32 bit	Config Register 1 (Yukon-Ext only) */
+#endif	/* !YUK_USB */
+	/* Bytes 0x98..0xdf:	reserved */
+
+/* PCI Express Capability */
+#define PEX_CAP_ID		0xe0	/*  8 bit	PEX Capability ID */
+#define PEX_NITEM		0xe1	/*  8 bit	PEX Next Item Pointer */
+#define PEX_CAP_REG		0xe2	/* 16 bit	PEX Capability Register */
+#define PEX_DEV_CAP		0xe4	/* 32 bit	PEX Device Capabilities */
+#define PEX_DEV_CTRL	0xe8	/* 16 bit	PEX Device Control */
+#define PEX_DEV_STAT	0xea	/* 16 bit	PEX Device Status */
+#define PEX_LNK_CAP		0xec	/* 32 bit	PEX Link Capabilities */
+#define PEX_LNK_CTRL	0xf0	/* 16 bit	PEX Link Control */
+#define PEX_LNK_STAT	0xf2	/* 16 bit	PEX Link Status */
+	/* Bytes 0xf4..0xff:	reserved */
+
+/*
+ * Yukon-Extreme B0: These registers have been moved to 0xc0..0xd2.
+ *					 Use PEX_CAP_REGS() macro to access
+ */
+#define PEX_CAP_REG_OFFS	0x20
+#define PEX_CAP_REGS(Reg)	((Reg) - (pAC->GIni.GIPexCapOffs))
+
+/* PCI Express Extended Capabilities */
+#define PEX_ADV_ERR_REP		0x100	/* 32 bit	PEX Advanced Error Reporting */
+#define PEX_UNC_ERR_STAT	0x104	/* 32 bit	PEX Uncorr. Errors Status */
+#define PEX_UNC_ERR_MASK	0x108	/* 32 bit	PEX Uncorr. Errors Mask */
+#define PEX_UNC_ERR_SEV		0x10c	/* 32 bit	PEX Uncorr. Errors Severity */
+#define PEX_COR_ERR_STAT	0x110	/* 32 bit	PEX Correc. Errors Status */
+#define PEX_COR_ERR_MASK	0x114	/* 32 bit	PEX Correc. Errors Mask */
+#define PEX_ADV_ERR_CAP_C	0x118	/* 32 bit	PEX Advanced Error Cap./Ctrl */
+#define PEX_HEADER_LOG		0x11c	/* 4x32 bit	PEX Header Log Register */
+
+#define PEX_COMPL_TIMEOUT	0x220	/* 32 bit	PEX Completion Timeout */
+#define PEX_FLOW_CONTROL	0x224	/* 32 bit	PEX Flow Control */
+
+/* PCI Express Ack Timer for 1x Link */
+#define PEX_ACK_LAT_TOX1	0x228	/* 16 bit	PEX Ack Latency Timeout x1 */
+#define PEX_ACK_RPLY_TOX1	0x22a	/* 16 bit	PEX Ack Reply Timeout val x1 */
+
+#define PCI_CFG_SIZE	(PCI_IRQ_LINE / 4 + 1)
+
+/*
+ * I2C Address (PCI Config)
+ *
+ * Note:
+ *	The temperature and voltage sensors are relocated on a different I2C bus
+ */
+#define I2C_ADDR_VPD	0xa0	/* I2C address for the VPD EEPROM */
+
+/*
+ * Define Bits and Values of the registers
+ */
+/*	PCI_COMMAND	16 bit	Command */
+								/* Bit 15..11:	reserved */
+#define PCI_INT_DIS		BIT_10S		/* Interrupt INTx# disable (PCI 2.3) */
+#define PCI_FBTEN		BIT_9S		/* Fast Back-To-Back enable */
+#define PCI_SERREN		BIT_8S		/* SERR enable */
+#define PCI_ADSTEP		BIT_7S		/* Address Stepping */
+#define PCI_PERREN		BIT_6S		/* Parity Report Response enable */
+#define PCI_VGA_SNOOP	BIT_5S		/* VGA palette snoop */
+#define PCI_MWIEN		BIT_4S		/* Memory write an inv cycl enable */
+#define PCI_SCYCEN		BIT_3S		/* Special Cycle enable */
+#define PCI_BMEN		BIT_2S		/* Bus Master enable */
+#define PCI_MEMEN		BIT_1S		/* Memory Space Access enable */
+#define PCI_IOEN		BIT_0S		/* I/O Space Access enable */
+
+#define PCI_COMMAND_VAL	(PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
+						 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
+
+/*	PCI_STATUS	16 bit	Status */
+#define PCI_PERR		BIT_15S		/* Parity Error */
+#define PCI_SERR		BIT_14S		/* Signaled SERR */
+#define PCI_RMABORT		BIT_13S		/* Received Master Abort */
+#define PCI_RTABORT		BIT_12S		/* Received Target Abort */
+								/* Bit 11:	reserved */
+#define PCI_DEVSEL		(3<<9)		/* Bit 10.. 9:	DEVSEL Timing */
+#define PCI_DEV_FAST	(0<<9)		/*		fast */
+#define PCI_DEV_MEDIUM	(1<<9)		/*		medium */
+#define PCI_DEV_SLOW	(2<<9)		/*		slow */
+#define PCI_DATAPERR	BIT_8S		/* DATA Parity error detected */
+#define PCI_FB2BCAP		BIT_7S		/* Fast Back-to-Back Capability */
+#define PCI_UDF			BIT_6S		/* User Defined Features */
+#define PCI_66MHZCAP	BIT_5S		/* 66 MHz PCI bus clock capable */
+#define PCI_NEWCAP		BIT_4S		/* New cap. list implemented */
+#define PCI_INT_STAT	BIT_3S		/* Interrupt INTx# Status (PCI 2.3) */
+								/* Bit  2.. 0:	reserved */
+
+#define PCI_ERRBITS	(PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
+					 PCI_DATAPERR)
+
+/*	PCI_CLASS_CODE	24 bit	Class Code */
+/*	Byte 2:		Base Class		(02) */
+/*	Byte 1:		SubClass		(00) */
+/*	Byte 0:		Programming Interface	(00) */
+
+/*	PCI_CACHE_LSZ	8 bit	Cache Line Size */
+/*	Possible values: 0, 2, 4, 8, 16, 32, 64, 128 */
+
+/*	PCI_HEADER_T	8 bit	Header Type */
+#define PCI_HD_MF_DEV	BIT_7S	/* 0= single, 1= multi-func dev */
+#define PCI_HD_TYPE		0x7f	/* Bit 6..0:	Header Layout (0=normal) */
+
+/*	PCI_BIST	8 bit	Built-in selftest */
+/*	Built-in Self test not supported (optional) */
+
+/*	PCI_BASE_1ST	32 bit	1st Base address */
+#define PCI_MEMSIZE		0x4000L		/* use 16 kB Memory Base */
+#define PCI_MEMBASE_MSK 0xffffc000L	/* Bit 31..14:	Memory Base Address */
+#define PCI_MEMSIZE_MSK 0x00003ff0L	/* Bit 13.. 4:	Memory Size Req. */
+#define PCI_PREFEN		BIT_3		/* Prefetch enable */
+#define PCI_MEM_TYP_MSK	(3L<<1)		/* Bit	2.. 1:	Memory Type Mask */
+#define PCI_MEMSPACE	BIT_0		/* Memory Space Indicator */
+
+#define PCI_MEM32BIT	(0L<<1)		/* Base addr anywhere in 32 Bit range */
+#define PCI_MEM1M		(1L<<1)		/* Base addr below 1 MegaByte */
+#define PCI_MEM64BIT	(2L<<1)		/* Base addr anywhere in 64 Bit range */
+
+/*	PCI_BASE_2ND	32 bit	2nd Base address */
+#define PCI_IOBASE		0xffffff00L	/* Bit 31.. 8:	I/O Base address */
+#define PCI_IOSIZE		0x000000fcL	/* Bit	7.. 2:	I/O Size Requirements */
+								/* Bit	1:	reserved */
+#define PCI_IOSPACE		BIT_0		/* I/O Space Indicator */
+
+/*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */
+#define PCI_ROMBASE_MSK	0xfffe0000L	/* Bit 31..17:	ROM Base address */
+#define PCI_ROMBASE_SIZ	(0x1cL<<14)	/* Bit 16..14:	Treat as Base or Size */
+#define PCI_ROMSIZE		(0x38L<<11)	/* Bit 13..11:	ROM Size Requirements */
+								/* Bit 10.. 1:	reserved */
+#define PCI_ROMEN		BIT_0		/* Address Decode enable */
+
+/* Device Dependent Region */
+/*	PCI_OUR_REG_1		32 bit	Our Register 1 */
+								/* Bit 31..29:	reserved */
+#define PCI_PHY_COMA	BIT_28		/* Set PHY to Coma Mode (YUKON only) */
+#define PCI_TEST_CAL	BIT_27		/* Test PCI buffer calib. (YUKON only) */
+#define PCI_EN_CAL		BIT_26		/* Enable PCI buffer calib. (YUKON only) */
+#define PCI_VIO			BIT_25		/* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
+/* Yukon-2 */
+#define PCI_Y2_PIG_ENA		BIT_31	/* Enable Plug-in-Go (YUKON-2) */
+#define PCI_Y2_DLL_DIS		BIT_30	/* Disable PCI DLL (YUKON-2) */
+#define PCI_SW_PWR_ON_RST	BIT_30	/* SW Power-on-reset (Yukon-Ext only) */
+#define PCI_Y2_PHY2_COMA	BIT_29	/* Set PHY 2 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY1_COMA	BIT_28	/* Set PHY 1 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY2_POWD	BIT_27	/* Set PHY 2 to Power Down (YUKON-2) */
+#define PCI_Y2_PHY1_POWD	BIT_26	/* Set PHY 1 to Power Down (YUKON-2) */
+								/* Bit 25:	reserved */
+#define PCI_DIS_BOOT	BIT_24		/* Disable BOOT via ROM */
+#define PCI_EN_IO		BIT_23		/* Mapping to I/O space */
+#define PCI_EN_FPROM	BIT_22		/* Enable FLASH mapping to memory */
+									/*		1 = Map Flash to memory */
+									/*		0 = Disable addr. dec */
+#define PCI_PAGESIZE	(3L<<20)	/* Bit 21..20:	FLASH Page Size */
+#define PCI_PAGE_16		(0L<<20)	/*		 16 k pages */
+#define PCI_PAGE_32K	(1L<<20)	/*		 32 k pages */
+#define PCI_PAGE_64K	(2L<<20)	/*		 64 k pages */
+#define PCI_PAGE_128K	(3L<<20)	/*		128 k pages */
+								/* Bit 19:	reserved */
+#define PCI_PAGEREG		(7L<<16)	/* Bit 18..16:	Page Register */
+#define PCI_NOTAR		BIT_15		/* No turnaround cycle */
+#define PCI_PEX_LEGNAT	BIT_15		/* PEX PM legacy/native mode (YUKON-2) */
+#define PCI_FORCE_BE	BIT_14		/* Assert all BEs on MR */
+#define PCI_DIS_MRL		BIT_13		/* Disable Mem Read Line */
+#define PCI_DIS_MRM		BIT_12		/* Disable Mem Read Multiple */
+#define PCI_DIS_MWI		BIT_11		/* Disable Mem Write & Invalidate */
+#define PCI_DISC_CLS	BIT_10		/* Disc: cacheLsz bound */
+#define PCI_BURST_DIS	BIT_9		/* Burst Disable */
+#define PCI_DIS_PCI_CLK	BIT_8		/* Disable PCI clock driving */
+#define PCI_SKEW_DAS	(0xfL<<4)	/* Bit	7.. 4:	Skew Ctrl, DAS Ext */
+#define PCI_SKEW_BASE	0xfL		/* Bit	3.. 0:	Skew Ctrl, Base */
+#define PCI_CLS_OPT		BIT_3		/* Cache Line Size opt. PCI-X (YUKON-2) */
+
+/* Yukon-EC Ultra only */
+								/* Bit 14..10:	reserved */
+#define PCI_PHY_LNK_TIM_MSK	(3L<<8)	/* Bit  9.. 8:	GPHY Link Trigger Timer */
+#define PCI_ENA_L1_EVENT	BIT_7	/* Enable PEX L1 Event */
+#define PCI_ENA_GPHY_LNK	BIT_6	/* Enable PEX L1 on GPHY Link down */
+#define PCI_FORCE_PEX_L1	BIT_5	/* Force to PEX L1 */
+								/* Bit  4.. 0:	reserved */
+
+/*	PCI_OUR_REG_2		32 bit	Our Register 2 */
+#define PCI_VPD_WR_THR	(0xffL<<24)	/* Bit 31..24:	VPD Write Threshold */
+#define PCI_DEV_SEL		(0x7fL<<17)	/* Bit 23..17:	EEPROM Device Select */
+#define PCI_VPD_ROM_SZ	(7L<<14)	/* Bit 16..14:	VPD ROM Size */
+								/* Bit 13..12:	reserved */
+#define PCI_PATCH_DIR	(0xfL<<8)	/* Bit 11.. 8:	Ext Patches dir 3..0 */
+#define PCI_PATCH_DIR_3	BIT_11
+#define PCI_PATCH_DIR_2	BIT_10
+#define PCI_PATCH_DIR_1	BIT_9
+#define PCI_PATCH_DIR_0	BIT_8
+#define PCI_EXT_PATCHS	(0xfL<<4)	/* Bit	7.. 4:	Extended Patches 3..0 */
+#define PCI_EXT_PATCH_3	BIT_7
+#define PCI_EXT_PATCH_2	BIT_6
+#define PCI_EXT_PATCH_1	BIT_5
+#define PCI_EXT_PATCH_0	BIT_4
+#define PCI_EN_DUMMY_RD	BIT_3		/* Enable Dummy Read */
+#define PCI_REV_DESC	BIT_2		/* Reverse Descriptor Bytes */
+								/* Bit	1:	reserved */
+#define PCI_USEDATA64	BIT_0		/* Use 64Bit Data bus ext */
+
+/* Power Management (PM) Region */
+/*	PCI_PM_CAP_REG		16 bit	Power Management Capabilities */
+#define PCI_PME_SUP_MSK	(0x1f<<11)	/* Bit 15..11:	PM Event (PME) Supp. Mask */
+#define PCI_PME_D3C_SUP	BIT_15S		/* PME from D3cold Support (if VAUX) */
+#define PCI_PME_D3H_SUP	BIT_14S		/* PME from D3hot Support */
+#define PCI_PME_D2_SUP	BIT_13S		/* PME from D2 Support */
+#define PCI_PME_D1_SUP	BIT_12S		/* PME from D1 Support */
+#define PCI_PME_D0_SUP	BIT_11S		/* PME from D0 Support */
+#define PCI_PM_D2_SUP	BIT_10S		/* D2 Support in 33 MHz mode */
+#define PCI_PM_D1_SUP	BIT_9S		/* D1 Support */
+								/* Bit	8.. 6:	reserved */
+#define PCI_PM_DSI		BIT_5S		/* Device Specific Initialization */
+#define PCI_PM_APS		BIT_4S		/* Auxialiary Power Source */
+#define PCI_PME_CLOCK	BIT_3S		/* PM Event Clock */
+#define PCI_PM_VER_MSK		7		/* Bit	2.. 0:	PM PCI Spec. version */
+
+/*	PCI_PM_CTL_STS		16 bit	Power Management Control/Status */
+#define PCI_PME_STATUS	BIT_15S		/* PME Status (YUKON only) */
+#define PCI_PM_DAT_SCL	(3<<13)		/* Bit 14..13:	Data Reg. scaling factor */
+#define PCI_PM_DAT_SEL	(0xf<<9)	/* Bit 12.. 9:	PM data selector field */
+#define PCI_PME_EN		BIT_8S		/* Enable PME# generation (YUKON only) */
+								/* Bit	7.. 2:	reserved */
+#define PCI_PM_STATE_MSK	3		/* Bit	1.. 0:	Power Management State */
+
+#define PCI_PM_STATE_D0		0		/* D0:	Operational (default) */
+#define PCI_PM_STATE_D1		1		/* D1:	(YUKON only) */
+#define PCI_PM_STATE_D2		2		/* D2:	(YUKON only) */
+#define PCI_PM_STATE_D3		3		/* D3:	HOT, Power Down and Reset */
+
+/* VPD Region */
+/*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */
+#define PCI_VPD_FLAG	BIT_15S		/* starts VPD rd/wr cycle */
+#define PCI_VPD_ADR_MSK	0x7fff		/* Bit 14.. 0:	VPD Address Mask */
+
+/* Serial EEPROM Loader Control Register */
+/*	PCI_SER_LD_CTRL			16 bit		Serial EEPROM Loader Control Register */
+#define	PCI_SER_LD_FLAG	BIT_15S		/* Bit 15		starts EEPROM cfg loader */
+#define PCI_SER_LD_ADDR	0x3fff		/* Bit  0..14	config loader start addr */
+
+/*	PCI_OUR_STATUS		32 bit	Adapter Status Register (Yukon-2) */
+#define PCI_OS_PCI64B	BIT_31		/* Conventional PCI 64 bits Bus */
+#define PCI_OS_PCIX		BIT_30		/* PCI-X Bus */
+#define PCI_OS_MODE_MSK	(3L<<28)	/* Bit 29..28:	PCI-X Bus Mode Mask */
+#define PCI_OS_PCI66M	BIT_27		/* PCI 66 MHz Bus */
+#define PCI_OS_PCI_X	BIT_26		/* PCI/PCI-X Bus (0 = PEX) */
+#define PCI_OS_DLLE_MSK	(3L<<24)	/* Bit 25..24:	DLL Status Indication */
+#define PCI_OS_DLLR_MSK	(0xfL<<20)	/* Bit 23..20:	DLL Row Counters Values */
+#define PCI_OS_DLLC_MSK	(0xfL<<16)	/* Bit 19..16:	DLL Col. Counters Values */
+								/* Bit 15.. 8:	reserved */
+
+#define PCI_OS_SPEED(val)	((val & PCI_OS_MODE_MSK) >> 28)	/* PCI-X Speed */
+/* possible values for the speed field of the register */
+#define PCI_OS_SPD_PCI		0		/* PCI Conventional Bus */
+#define PCI_OS_SPD_X66		1		/* PCI-X 66MHz Bus */
+#define PCI_OS_SPD_X100		2		/* PCI-X 100MHz Bus */
+#define PCI_OS_SPD_X133		3		/* PCI-X 133MHz Bus */
+
+/*	PCI_OUR_REG_3		32 bit	Our Register 3 (Yukon-ECU only) */
+								/* Bit 31..18:	reserved */
+#define P_CLK_ASF_REGS_DIS		BIT_18	/* Disable Clock ASF (Yukon-Ext.) */
+#define P_CLK_COR_REGS_D0_DIS	BIT_17	/* Disable Clock Core Regs D0 */
+#define P_CLK_MACSEC_DIS		BIT_17	/* Disable Clock MACSec (Yukon-Ext.) */
+#define P_CLK_PCI_REGS_D0_DIS	BIT_16	/* Disable Clock PCI  Regs D0 */
+#define P_CLK_COR_YTB_ARB_DIS	BIT_15	/* Disable Clock YTB  Arbiter */
+#define P_CLK_MAC_LNK1_D3_DIS	BIT_14	/* Disable Clock MAC  Link1 D3 */
+#define P_CLK_COR_LNK1_D0_DIS	BIT_13	/* Disable Clock Core Link1 D0 */
+#define P_CLK_MAC_LNK1_D0_DIS	BIT_12	/* Disable Clock MAC  Link1 D0 */
+#define P_CLK_COR_LNK1_D3_DIS	BIT_11	/* Disable Clock Core Link1 D3 */
+#define P_CLK_PCI_MST_ARB_DIS	BIT_10	/* Disable Clock PCI  Master Arb. */
+#define P_CLK_COR_REGS_D3_DIS	BIT_9	/* Disable Clock Core Regs D3 */
+#define P_CLK_PCI_REGS_D3_DIS	BIT_8	/* Disable Clock PCI  Regs D3 */
+#define P_CLK_REF_LNK1_GM_DIS	BIT_7	/* Disable Clock Ref. Link1 GMAC */
+#define P_CLK_COR_LNK1_GM_DIS	BIT_6	/* Disable Clock Core Link1 GMAC */
+#define P_CLK_PCI_COMMON_DIS	BIT_5	/* Disable Clock PCI  Common */
+#define P_CLK_COR_COMMON_DIS	BIT_4	/* Disable Clock Core Common */
+#define P_CLK_PCI_LNK1_BMU_DIS	BIT_3	/* Disable Clock PCI  Link1 BMU */
+#define P_CLK_COR_LNK1_BMU_DIS	BIT_2	/* Disable Clock Core Link1 BMU */
+#define P_CLK_PCI_LNK1_BIU_DIS	BIT_1	/* Disable Clock PCI  Link1 BIU */
+#define P_CLK_COR_LNK1_BIU_DIS	BIT_0	/* Disable Clock Core Link1 BIU */
+
+#define PCIE_OUR3_WOL_D3_COLD_SET	( \
+							P_CLK_ASF_REGS_DIS | \
+							P_CLK_COR_REGS_D0_DIS | \
+							P_CLK_COR_LNK1_D0_DIS | \
+							P_CLK_MAC_LNK1_D0_DIS | \
+							P_CLK_PCI_MST_ARB_DIS | \
+							P_CLK_COR_COMMON_DIS | \
+							P_CLK_COR_LNK1_BMU_DIS)
+
+/*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
+#define P_PEX_LTSSM_STAT_MSK	(0x7fL<<25)	/* Bit 31..25:	PEX LTSSM Mask */
+									/* (Link Training & Status State Machine) */
+#define P_ASPM_GPHY_INT_ENA		BIT_24	/* GPHY Interrupt (Yukon-Ext. only) */
+#define P_TIMER_VALUE_MSK		(0xffL<<16)	/* Bit 23..16:	Timer Value Mask */
+#define P_FORCE_ASPM_REQUEST	BIT_15	/* Force ASPM Request (A1 only) */
+										/* (Active State Power Management) */
+										/* Bit 14..12: Force ASPM on Event */
+#define P_ASPM_GPHY_LINK_DOWN	BIT_14	/* GPHY Link Down (A1 only) */
+#define P_ASPM_INT_FIFO_EMPTY	BIT_13	/* Internal FIFO Empty (A1 only) */
+#define P_ASPM_CLKRUN_REQUEST	BIT_12	/* CLKRUN Request (A1 only) */
+								/* Bit 11.. 7:	reserved */
+#define P_PIN63_LINK_LED_ENA	BIT_8	/* Enable Pin #63 as Link LED (A3) */
+#define P_ASPM_FORCE_ASPM_L1	BIT_7	/* Force ASPM L1  Enable (A1b only) */
+#define P_ASPM_FORCE_ASPM_L0S	BIT_6	/* Force ASPM L0s Enable (A1b only) */
+#define P_ASPM_FORCE_CLKREQ_PIN	BIT_5	/* Force CLKREQn pin low (A1b only) */
+#define P_ASPM_FORCE_CLKREQ_ENA	BIT_4	/* Force CLKREQ Enable (A1b only) */
+#define P_ASPM_CLKREQ_PAD_CTL	BIT_3	/* CLKREQ PAD Control (A1 only) */
+#define P_ASPM_A1_MODE_SELECT	BIT_2	/* A1 Mode Select (A1 only) */
+#define P_CLK_GATE_PEX_UNIT_ENA	BIT_1	/* Enable Gate PEX Unit Clock */
+#define P_CLK_GATE_ROOT_COR_ENA	BIT_0	/* Enable Gate Root Core Clock */
+
+#define P_PEX_LTSSM_STAT(x)		(SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
+#define P_PEX_LTSSM_L1_STAT		0x34
+#define P_PEX_LTSSM_DET_STAT	0x01
+
+#define P_ASPM_CONTROL_MSK	(P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
+							 P_ASPM_INT_FIFO_EMPTY | P_ASPM_CLKRUN_REQUEST | \
+							 P_PIN63_LINK_LED_ENA)
+
+#define PCIE_OUR4_DYN_CLK_GATE_SET	( \
+							P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) | \
+							P_TIMER_VALUE_MSK | \
+							P_ASPM_INT_FIFO_EMPTY | \
+							P_ASPM_CLKRUN_REQUEST | \
+							P_ASPM_A1_MODE_SELECT | \
+							P_CLK_GATE_ROOT_COR_ENA)
+
+/*	PCI_OUR_REG_5		32 bit	Our Register 5 (Yukon-ECU only) */
+										/* Bit 31..27:	for A3 & later */
+#define P_CTL_DIV_CORE_CLK_ENA	BIT_31	/* Divide Core Clock Enable */
+#define P_CTL_SRESET_VMAIN_AV	BIT_30	/* Soft Reset for Vmain_av De-Glitch */
+#define P_CTL_BYPASS_VMAIN_AV	BIT_29	/* Bypass En. for Vmain_av De-Glitch */
+#define P_CTL_TIM_VMAIN_AV_MSK	(3<<27)	/* Bit 28..27: Timer Vmain_av Mask */
+										/* Bit 26..14: Release Clock on Event */
+#define P_REL_PCIE_RST_DE_ASS	BIT_26	/* PCIe Reset De-Asserted */
+#define P_REL_GPHY_REC_PACKET	BIT_25	/* GPHY Received Packet */
+#define P_REL_INT_FIFO_N_EMPTY	BIT_24	/* Internal FIFO Not Empty */
+#define P_REL_MAIN_PWR_AVAIL	BIT_23	/* Main Power Available */
+#define P_REL_CLKRUN_REQ_REL	BIT_22	/* CLKRUN Request Release */
+#define P_REL_PCIE_RESET_ASS	BIT_21	/* PCIe Reset Asserted */
+#define P_REL_PME_ASSERTED		BIT_20	/* PME Asserted */
+#define P_REL_PCIE_EXIT_L1_ST	BIT_19	/* PCIe Exit L1 State */
+#define P_REL_LOADER_NOT_FIN	BIT_18	/* EPROM Loader Not Finished */
+#define P_REL_PCIE_RX_EX_IDLE	BIT_17	/* PCIe Rx Exit Electrical Idle State */
+#define P_REL_GPHY_LINK_UP		BIT_16	/* GPHY Link Up */
+#define P_REL_CPU_TO_SLEEP		BIT_15	/* CPU Goes to Sleep */
+#define P_REL_GPHY_ASS_IRQ		BIT_14	/* GPHY Asserts IRQ */
+#define P_REL_EN_RX_DV			BIT_13	/* Enable RX_DV to quick release clock */
+										/* Bit 12.. 0: Mask for Gate Clock */
+#define P_GAT_GPHY_ASS_IRQ		BIT_12	/* GPHY Asserts IRQ */
+#define P_GAT_CPU_TO_SLEEP		BIT_11	/* CPU Goes to Sleep and Events */
+#define P_GAT_PCIE_RST_ASSERTED	BIT_10	/* PCIe Reset Asserted */
+#define P_GAT_GPHY_N_REC_PACKET	BIT_9	/* GPHY Not Received Packet */
+#define P_GAT_INT_FIFO_EMPTY	BIT_8	/* Internal FIFO Empty */
+#define P_GAT_MAIN_PWR_N_AVAIL	BIT_7	/* Main Power Not Available */
+#define P_GAT_CLKRUN_REQ_REL	BIT_6	/* CLKRUN Not Requested */
+#define P_GAT_PCIE_RESET_ASS	BIT_5	/* PCIe Reset Asserted */
+#define P_GAT_PME_DE_ASSERTED	BIT_4	/* PME De-Asserted */
+#define P_GAT_PCIE_ENTER_L1_ST	BIT_3	/* PCIe Enter L1 State */
+#define P_GAT_LOADER_FINISHED	BIT_2	/* EPROM Loader Finished */
+#define P_GAT_PCIE_RX_EL_IDLE	BIT_1	/* PCIe Rx Electrical Idle State */
+#define P_GAT_GPHY_LINK_DOWN	BIT_0	/* GPHY Link Down */
+
+#define PCIE_OUR5_EVENT_CLK_D3_SET	( \
+							P_REL_GPHY_REC_PACKET | \
+							P_REL_INT_FIFO_N_EMPTY | \
+							P_REL_CLKRUN_REQ_REL | \
+							P_REL_PCIE_EXIT_L1_ST | \
+							P_REL_PCIE_RX_EX_IDLE | \
+							P_GAT_GPHY_N_REC_PACKET | \
+							P_GAT_INT_FIFO_EMPTY | \
+							P_GAT_CLKRUN_REQ_REL | \
+							P_GAT_PCIE_ENTER_L1_ST | \
+							P_GAT_PCIE_RX_EL_IDLE)
+
+/*	PCI_CFG_REG_1			32 bit	Config Register 1 (Yukon-Ext only) */
+#define P_CF1_DIS_REL_EVT_RST	BIT_24	/* Dis. Rel. Event during PCIE reset */
+										/* Bit 23..21: Release Clock on Event */
+#define P_CF1_REL_LDR_NOT_FIN	BIT_23	/* EEPROM Loader Not Finished */
+#define P_CF1_REL_VMAIN_AVLBL	BIT_22	/* Vmain available */
+#define P_CF1_REL_PCIE_RESET	BIT_21	/* PCI-E reset */
+										/* Bit 20..18: Gate Clock on Event */
+#define P_CF1_GAT_LDR_NOT_FIN	BIT_20	/* EEPROM Loader Finished */
+#define P_CF1_GAT_PCIE_RX_IDLE	BIT_19	/* PCI-E Rx Electrical idle */
+#define P_CF1_GAT_PCIE_RESET	BIT_18	/* PCI-E Reset */
+#define P_CF1_PRST_PHY_CLKREQ	BIT_17	/* Enable PCI-E rst & PM2PHY gen. CLKREQ */
+#define P_CF1_PCIE_RST_CLKREQ	BIT_16	/* Enable PCI-E rst generate CLKREQ */
+
+#define P_CF1_ENA_CFG_LDR_DONE	BIT_8	/* Enable core level Config loader done */
+
+#define P_CF1_ENA_TXBMU_RD_IDLE	BIT_1	/* Enable TX BMU Read  IDLE for ASPM */
+#define P_CF1_ENA_TXBMU_WR_IDLE	BIT_0	/* Enable TX BMU Write IDLE for ASPM */
+
+#define PCIE_CFG1_EVENT_CLK_D3_SET	( \
+							P_CF1_DIS_REL_EVT_RST | \
+							P_CF1_REL_LDR_NOT_FIN | \
+							P_CF1_REL_VMAIN_AVLBL | \
+							P_CF1_REL_PCIE_RESET | \
+							P_CF1_GAT_LDR_NOT_FIN | \
+							P_CF1_GAT_PCIE_RESET | \
+							P_CF1_PRST_PHY_CLKREQ | \
+							P_CF1_ENA_CFG_LDR_DONE | \
+							P_CF1_ENA_TXBMU_RD_IDLE | \
+							P_CF1_ENA_TXBMU_WR_IDLE)
+
+/*	PEX_DEV_CTRL			16 bit	PEX Device Control (Yukon-2) */
+								/* Bit 15	reserved */
+#define PEX_DC_MAX_RRS_MSK	(7<<12)	/* Bit 14..12:	Max. Read Request Size */
+#define PEX_DC_EN_NO_SNOOP	BIT_11S	/* Enable No Snoop */
+#define PEX_DC_EN_AUX_POW	BIT_10S	/* Enable AUX Power */
+#define PEX_DC_EN_PHANTOM	BIT_9S	/* Enable Phantom Functions */
+#define PEX_DC_EN_EXT_TAG	BIT_8S	/* Enable Extended Tag Field */
+#define PEX_DC_MAX_PLS_MSK	(7<<5)	/* Bit  7.. 5:	Max. Payload Size Mask */
+#define PEX_DC_EN_REL_ORD	BIT_4S	/* Enable Relaxed Ordering */
+#define PEX_DC_EN_UNS_RQ_RP	BIT_3S	/* Enable Unsupported Request Reporting */
+#define PEX_DC_EN_FAT_ER_RP	BIT_2S	/* Enable Fatal Error Reporting */
+#define PEX_DC_EN_NFA_ER_RP	BIT_1S	/* Enable Non-Fatal Error Reporting */
+#define PEX_DC_EN_COR_ER_RP	BIT_0S	/* Enable Correctable Error Reporting */
+
+#define PEX_DC_MAX_RD_RQ_SIZE(x)	(SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
+
+/*	PEX_LNK_CAP			32 bit	PEX Link Capabilities */
+#define PEX_CAP_MAX_WI_MSK	(0x3f<<4)	/* Bit  9.. 4:	Max. Link Width Mask */
+#define PEX_CAP_MAX_SP_MSK	0x0f	/* Bit  3.. 0:	Max. Link Speed Mask */
+
+/*	PEX_LNK_CTRL			16 bit	PEX Link Control (Yukon-2) */
+#define PEX_LC_CLK_PM_ENA	BIT_8S	/* Enable Clock Power Management (CLKREQ) */
+#define PEX_LC_ASPM_LC_L1	BIT_1S	/* Enable ASPM Entry L1  */
+#define PEX_LC_ASPM_LC_L0S	BIT_0S	/* Enable ASPM Entry L0s */
+#define PEX_LC_ASPM_LC_MSK	0x03	/* Bit  1.. 0:	ASPM Link Control Mask */
+
+/*	PEX_LNK_STAT			16 bit	PEX Link Status (Yukon-2) */
+								/* Bit 15..13	reserved */
+#define PEX_LS_SLOT_CLK_CFG	BIT_12S	/* Slot Clock Config */
+#define PEX_LS_LINK_TRAIN	BIT_11S	/* Link Training */
+#define PEX_LS_TRAIN_ERROR	BIT_10S	/* Training Error */
+#define PEX_LS_LINK_WI_MSK	(0x3f<<4)	/* Bit  9.. 4:	Neg. Link Width Mask */
+#define PEX_LS_LINK_SP_MSK	0x0f	/* Bit  3.. 0:	Link Speed Mask */
+
+/*	PEX_UNC_ERR_STAT		32 bit	PEX Uncorrectable Errors Status (Yukon-2) */
+								/* Bit 31..21	reserved */
+#define PEX_UNSUP_REQ	BIT_20		/* Unsupported Request Error */
+									/* ECRC Error (not supported) */
+#define PEX_MALFOR_TLP	BIT_18		/* Malformed TLP */
+#define PEX_RX_OV		BIT_17		/* Receiver Overflow (not supported) */
+#define PEX_UNEXP_COMP	BIT_16		/* Unexpected Completion */
+									/* Completer Abort (not supported) */
+#define PEX_COMP_TO		BIT_14		/* Completion Timeout */
+#define PEX_FLOW_CTRL_P	BIT_13		/* Flow Control Protocol Error */
+#define PEX_POIS_TLP	BIT_12		/* Poisoned TLP */
+								/* Bit 11.. 5:	reserved */
+#define PEX_DATA_LINK_P BIT_4		/* Data Link Protocol Error */
+								/* Bit  3.. 1:	reserved */
+									/* Training Error (not supported) */
+
+#define PEX_FATAL_ERRORS	(PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
+
+/*	Control Register File (Address Map) */
+
+/*
+ *	Bank 0
+ */
+#define B0_RAP			0x0000	/*  8 bit	Register Address Port */
+	/* 0x0001 - 0x0003:	reserved */
+#define B0_CTST			0x0004	/* 16 bit	Control/Status Register */
+#define B0_LED			0x0006	/*  8 Bit	LED Register */
+#define B0_POWER_CTRL	0x0007	/*  8 Bit	Power Control reg (YUKON only) */
+#define B0_ISRC			0x0008	/* 32 bit	Interrupt Source Register */
+#define B0_IMSK			0x000c	/* 32 bit	Interrupt Mask Register */
+#define B0_HWE_ISRC		0x0010	/* 32 bit	HW Error Interrupt Source Reg */
+#define B0_HWE_IMSK		0x0014	/* 32 bit	HW Error Interrupt Mask Reg */
+#define B0_SP_ISRC		0x0018	/* 32 bit	Special Interrupt Source Reg 1 */
+
+/* Special ISR registers (Yukon-2 only) */
+#define B0_Y2_SP_ISRC2	0x001c	/* 32 bit	Special Interrupt Source Reg 2 */
+#define B0_Y2_SP_ISRC3	0x0020	/* 32 bit	Special Interrupt Source Reg 3 */
+#define B0_Y2_SP_EISR	0x0024	/* 32 bit	Enter ISR Register */
+#define B0_Y2_SP_LISR	0x0028	/* 32 bit	Leave ISR Register */
+#define B0_Y2_SP_ICR	0x002c	/* 32 bit	Interrupt Control Register */
+
+/* B0 XMAC 1 registers (GENESIS only) */
+#define B0_XM1_IMSK		0x0020	/* 16 bit r/w	XMAC 1 Interrupt Mask Register*/
+	/* 0x0022 - 0x0027:	reserved */
+#define B0_XM1_ISRC		0x0028	/* 16 bit ro	XMAC 1 Interrupt Status Reg */
+	/* 0x002a - 0x002f:	reserved */
+#define B0_XM1_PHY_ADDR 0x0030	/* 16 bit r/w	XMAC 1 PHY Address Register */
+	/* 0x0032 - 0x0033:	reserved */
+#define B0_XM1_PHY_DATA 0x0034	/* 16 bit r/w	XMAC 1 PHY Data Register */
+	/* 0x0036 - 0x003f:	reserved */
+
+/* B0 XMAC 2 registers (GENESIS only) */
+#define B0_XM2_IMSK		0x0040	/* 16 bit r/w	XMAC 2 Interrupt Mask Register*/
+	/* 0x0042 - 0x0047:	reserved */
+#define B0_XM2_ISRC		0x0048	/* 16 bit ro	XMAC 2 Interrupt Status Reg */
+	/* 0x004a - 0x004f:	reserved */
+#define B0_XM2_PHY_ADDR 0x0050	/* 16 bit r/w	XMAC 2 PHY Address Register */
+	/* 0x0052 - 0x0053:	reserved */
+#define B0_XM2_PHY_DATA 0x0054	/* 16 bit r/w	XMAC 2 PHY Data Register */
+	/* 0x0056 - 0x005f:	reserved */
+
+/* BMU Control Status Registers (Yukon and Genesis) */
+#define B0_R1_CSR		0x0060	/* 32 bit	BMU Ctrl/Stat Rx Queue 1 */
+#define B0_R2_CSR		0x0064	/* 32 bit	BMU Ctrl/Stat Rx Queue 2 */
+#define B0_XS1_CSR		0x0068	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
+#define B0_XA1_CSR		0x006c	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 1*/
+#define B0_XS2_CSR		0x0070	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
+#define B0_XA2_CSR		0x0074	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 2*/
+	/* 0x0078 - 0x007f:	reserved */
+
+/*
+ *	Bank 1
+ *	- completely empty (this is the RAP Block window)
+ *	Note: if RAP = 1 this page is reserved
+ */
+
+/*
+ *	Bank 2
+ */
+/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
+#define B2_MAC_1		0x0100	/* NA reg	 MAC Address 1 */
+	/* 0x0106 - 0x0107:	reserved */
+#define B2_MAC_2		0x0108	/* NA reg	 MAC Address 2 */
+	/* 0x010e - 0x010f:	reserved */
+#define B2_MAC_3		0x0110	/* NA reg	 MAC Address 3 */
+	/* 0x0116 - 0x0117:	reserved */
+#define B2_CONN_TYP		0x0118	/*  8 bit	Connector type */
+#define B2_PMD_TYP		0x0119	/*  8 bit	PMD type */
+#define B2_MAC_CFG		0x011a	/*  8 bit	MAC Configuration / Chip Revision */
+#define B2_CHIP_ID		0x011b	/*  8 bit	Chip Identification Number */
+	/* Eprom registers */
+#define B2_E_0			0x011c	/*  8 bit	EPROM Byte 0 (ext. SRAM size */
+/* Yukon and Genesis */
+#define B2_E_1			0x011d	/*  8 bit	EPROM Byte 1 (PHY type) */
+#define B2_E_2			0x011e	/*  8 bit	EPROM Byte 2 */
+/* Yukon-2 */
+#define B2_Y2_CLK_GATE	0x011d	/*  8 bit	Clock Gating (Yukon-2) */
+#define B2_Y2_HW_RES	0x011e	/*  8 bit	HW Resources (Yukon-2) */
+
+#define B2_E_3			0x011f	/*  8 bit	EPROM Byte 3 */
+
+/* Yukon and Genesis */
+#define B2_FAR			0x0120	/* 32 bit	Flash-Prom Addr Reg/Cnt */
+#define B2_FDP			0x0124	/*  8 bit	Flash-Prom Data Port */
+/* Yukon-2 */
+#define B2_Y2_CLK_CTRL	0x0120	/* 32 bit	Core Clock Frequency Control */
+	/* 0x0125 - 0x0127:	reserved */
+#define B2_LD_CTRL		0x0128	/*  8 bit	EPROM loader control register */
+#define B2_LD_TEST		0x0129	/*  8 bit	EPROM loader test register */
+	/* 0x012a - 0x012f:	reserved */
+#define B2_TI_INI		0x0130	/* 32 bit	Timer Init Value */
+#define B2_TI_VAL		0x0134	/* 32 bit	Timer Value */
+#define B2_TI_CTRL		0x0138	/*  8 bit	Timer Control */
+#define B2_TI_TEST		0x0139	/*  8 Bit	Timer Test */
+	/* 0x013a - 0x013f:	reserved */
+#define B2_IRQM_INI		0x0140	/* 32 bit	IRQ Moderation Timer Init Reg.*/
+#define B2_IRQM_VAL		0x0144	/* 32 bit	IRQ Moderation Timer Value */
+#define B2_IRQM_CTRL	0x0148	/*  8 bit	IRQ Moderation Timer Control */
+#define B2_IRQM_TEST	0x0149	/*  8 bit	IRQ Moderation Timer Test */
+#define B2_IRQM_MSK		0x014c	/* 32 bit	IRQ Moderation Mask */
+#define B2_IRQM_HWE_MSK 0x0150	/* 32 bit	IRQ Moderation HW Error Mask */
+	/* 0x0154 - 0x0157:	reserved */
+#define B2_TST_CTRL1	0x0158	/*  8 bit	Test Control Register 1 */
+#define B2_TST_CTRL2	0x0159	/*  8 bit	Test Control Register 2 */
+	/* 0x015a - 0x015b:	reserved */
+#define B2_GP_IO		0x015c	/* 32 bit	General Purpose I/O Register */
+#define B2_I2C_CTRL		0x0160	/* 32 bit	I2C HW Control Register */
+#define B2_I2C_DATA		0x0164	/* 32 bit	I2C HW Data Register */
+#define B2_I2C_IRQ		0x0168	/* 32 bit	I2C HW IRQ Register */
+#define B2_I2C_SW		0x016c	/* 32 bit	I2C SW Port Register */
+
+/* Blink Source Counter (GENESIS only) */
+#define B2_BSC_INI		0x0170	/* 32 bit	Blink Source Counter Init Val */
+#define B2_BSC_VAL		0x0174	/* 32 bit	Blink Source Counter Value */
+#define B2_BSC_CTRL		0x0178	/*  8 bit	Blink Source Counter Control */
+#define B2_BSC_STAT		0x0179	/*  8 bit	Blink Source Counter Status */
+#define B2_BSC_TST		0x017a	/* 16 bit	Blink Source Counter Test Reg */
+
+/* Yukon-2 */
+#define Y2_PEX_PHY_DATA	0x0170	/* 16 bit	PEX PHY Data Register */
+#define Y2_PEX_PHY_ADDR	0x0172	/* 16 bit	PEX PHY Address Register */
+	/* 0x017c - 0x017f:	reserved */
+
+/*
+ *	Bank 3
+ */
+/* RAM Random Registers */
+#define B3_RAM_ADDR		0x0180	/* 32 bit	RAM Address, to read or write */
+#define B3_RAM_DATA_LO	0x0184	/* 32 bit	RAM Data Word (low dWord) */
+#define B3_RAM_DATA_HI	0x0188	/* 32 bit	RAM Data Word (high dWord) */
+#define B3_RAM_PARITY	0x018c	/*  8 bit	RAM Parity (Yukon-ECU A1) */
+
+#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6))	/* Yukon-2 only */
+
+/* Indices for RAM types (Yukon-EC Ultra and later) */
+#define SK_ECU_MAC_TX_RAM_IDX	0
+#define SK_ECU_MAC_RX_RAM_IDX	1
+#define SK_ECU_PCI_TX_RAM_IDX	2
+#define SK_YEX_ASF_FIFO_IDX		3
+
+	/* 0x018c - 0x018f:	reserved */
+
+/* RAM Interface Registers */
+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
+/*
+ * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
+ * not usable in SW. Please notice these are NOT real timeouts, these are
+ * the number of qWords transferred continuously.
+ */
+#define B3_RI_WTO_R1	0x0190	/*  8 bit	WR Timeout Queue R1		(TO0) */
+#define B3_RI_WTO_XA1	0x0191	/*  8 bit	WR Timeout Queue XA1	(TO1) */
+#define B3_RI_WTO_XS1	0x0192	/*  8 bit	WR Timeout Queue XS1	(TO2) */
+#define B3_RI_RTO_R1	0x0193	/*  8 bit	RD Timeout Queue R1		(TO3) */
+#define B3_RI_RTO_XA1	0x0194	/*  8 bit	RD Timeout Queue XA1	(TO4) */
+#define B3_RI_RTO_XS1	0x0195	/*  8 bit	RD Timeout Queue XS1	(TO5) */
+#define B3_RI_WTO_R2	0x0196	/*  8 bit	WR Timeout Queue R2		(TO6) */
+#define B3_RI_WTO_XA2	0x0197	/*  8 bit	WR Timeout Queue XA2	(TO7) */
+#define B3_RI_WTO_XS2	0x0198	/*  8 bit	WR Timeout Queue XS2	(TO8) */
+#define B3_RI_RTO_R2	0x0199	/*  8 bit	RD Timeout Queue R2		(TO9) */
+#define B3_RI_RTO_XA2	0x019a	/*  8 bit	RD Timeout Queue XA2	(TO10) */
+#define B3_RI_RTO_XS2	0x019b	/*  8 bit	RD Timeout Queue XS2	(TO11) */
+#define B3_RI_TO_VAL	0x019c	/*  8 bit	Current Timeout Count Val */
+	/* 0x019d - 0x019f:	reserved */
+#define B3_RI_CTRL		0x01a0	/* 16 bit	RAM Interface Control Register */
+#define B3_RI_TEST		0x01a2	/*  8 bit	RAM Interface Test Register */
+	/* 0x01a3 - 0x01af:	reserved */
+
+/* MAC Arbiter Registers (GENESIS only) */
+/* these are the no. of qWord transferred continuously and NOT real timeouts */
+#define B3_MA_TOINI_RX1	0x01b0	/*  8 bit	Timeout Init Val Rx Path MAC 1 */
+#define B3_MA_TOINI_RX2	0x01b1	/*  8 bit	Timeout Init Val Rx Path MAC 2 */
+#define B3_MA_TOINI_TX1	0x01b2	/*  8 bit	Timeout Init Val Tx Path MAC 1 */
+#define B3_MA_TOINI_TX2	0x01b3	/*  8 bit	Timeout Init Val Tx Path MAC 2 */
+#define B3_MA_TOVAL_RX1	0x01b4	/*  8 bit	Timeout Value Rx Path MAC 1 */
+#define B3_MA_TOVAL_RX2	0x01b5	/*  8 bit	Timeout Value Rx Path MAC 1 */
+#define B3_MA_TOVAL_TX1	0x01b6	/*  8 bit	Timeout Value Tx Path MAC 2 */
+#define B3_MA_TOVAL_TX2	0x01b7	/*  8 bit	Timeout Value Tx Path MAC 2 */
+#define B3_MA_TO_CTRL	0x01b8	/* 16 bit	MAC Arbiter Timeout Ctrl Reg */
+#define B3_MA_TO_TEST	0x01ba	/* 16 bit	MAC Arbiter Timeout Test Reg */
+	/* 0x01bc - 0x01bf:	reserved */
+#define B3_MA_RCINI_RX1	0x01c0	/*  8 bit	Recovery Init Val Rx Path MAC 1 */
+#define B3_MA_RCINI_RX2	0x01c1	/*  8 bit	Recovery Init Val Rx Path MAC 2 */
+#define B3_MA_RCINI_TX1	0x01c2	/*  8 bit	Recovery Init Val Tx Path MAC 1 */
+#define B3_MA_RCINI_TX2	0x01c3	/*  8 bit	Recovery Init Val Tx Path MAC 2 */
+#define B3_MA_RCVAL_RX1	0x01c4	/*  8 bit	Recovery Value Rx Path MAC 1 */
+#define B3_MA_RCVAL_RX2	0x01c5	/*  8 bit	Recovery Value Rx Path MAC 1 */
+#define B3_MA_RCVAL_TX1	0x01c6	/*  8 bit	Recovery Value Tx Path MAC 2 */
+#define B3_MA_RCVAL_TX2	0x01c7	/*  8 bit	Recovery Value Tx Path MAC 2 */
+#define B3_MA_RC_CTRL	0x01c8	/* 16 bit	MAC Arbiter Recovery Ctrl Reg */
+#define B3_MA_RC_TEST	0x01ca	/* 16 bit	MAC Arbiter Recovery Test Reg */
+	/* 0x01cc - 0x01cf:	reserved */
+
+/* Packet Arbiter Registers (GENESIS only) */
+/* these are real timeouts */
+#define B3_PA_TOINI_RX1	0x01d0	/* 16 bit	Timeout Init Val Rx Path MAC 1 */
+	/* 0x01d2 - 0x01d3:	reserved */
+#define B3_PA_TOINI_RX2	0x01d4	/* 16 bit	Timeout Init Val Rx Path MAC 2 */
+	/* 0x01d6 - 0x01d7:	reserved */
+#define B3_PA_TOINI_TX1	0x01d8	/* 16 bit	Timeout Init Val Tx Path MAC 1 */
+	/* 0x01da - 0x01db:	reserved */
+#define B3_PA_TOINI_TX2	0x01dc	/* 16 bit	Timeout Init Val Tx Path MAC 2 */
+	/* 0x01de - 0x01df:	reserved */
+#define B3_PA_TOVAL_RX1	0x01e0	/* 16 bit	Timeout Val Rx Path MAC 1 */
+	/* 0x01e2 - 0x01e3:	reserved */
+#define B3_PA_TOVAL_RX2	0x01e4	/* 16 bit	Timeout Val Rx Path MAC 2 */
+	/* 0x01e6 - 0x01e7:	reserved */
+#define B3_PA_TOVAL_TX1	0x01e8	/* 16 bit	Timeout Val Tx Path MAC 1 */
+	/* 0x01ea - 0x01eb:	reserved */
+#define B3_PA_TOVAL_TX2	0x01ec	/* 16 bit	Timeout Val Tx Path MAC 2 */
+	/* 0x01ee - 0x01ef:	reserved */
+#define B3_PA_CTRL		0x01f0	/* 16 bit	Packet Arbiter Ctrl Register */
+#define B3_PA_TEST		0x01f2	/* 16 bit	Packet Arbiter Test Register */
+	/* 0x01f4 - 0x01ff:	reserved */
+
+/*
+ *	Bank 4 - 5
+ */
+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+#define TXA_ITI_INI		0x0200	/* 32 bit	Tx Arb Interval Timer Init Val*/
+#define TXA_ITI_VAL		0x0204	/* 32 bit	Tx Arb Interval Timer Value */
+#define TXA_LIM_INI		0x0208	/* 32 bit	Tx Arb Limit Counter Init Val */
+#define TXA_LIM_VAL		0x020c	/* 32 bit	Tx Arb Limit Counter Value */
+#define TXA_CTRL		0x0210	/*  8 bit	Tx Arbiter Control Register */
+#define TXA_TEST		0x0211	/*  8 bit	Tx Arbiter Test Register */
+#define TXA_STAT		0x0212	/*  8 bit	Tx Arbiter Status Register */
+	/* 0x0213 - 0x021f:	reserved */
+
+	/* RSS key registers for Yukon-2 Family */
+#define B4_RSS_KEY		0x0220	/* 4x32 bit RSS Key register (Yukon-2) */
+	/* RSS key register offsets */
+#define KEY_IDX_0		 0		/* offset for location of KEY 0 */
+#define KEY_IDX_1		 4		/* offset for location of KEY 1 */
+#define KEY_IDX_2		 8		/* offset for location of KEY 2 */
+#define KEY_IDX_3		12		/* offset for location of KEY 3 */
+
+	/* 0x0280 - 0x0292:	MAC 2 */
+	/* 0x0213 - 0x027f:	reserved */
+
+/*
+ *	Bank 6
+ */
+/* External registers (GENESIS only) */
+#define B6_EXT_REG		0x0300
+
+/*
+ *	Bank 7
+ */
+/* This is a copy of the Configuration register file (lower half) */
+#define B7_CFG_SPC		0x0380
+
+/*
+ *	Bank 8 - 15
+ */
+/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
+#define B8_Q_REGS		0x0400
+
+/* Queue Register Offsets, use Q_ADDR() to access */
+#define Q_D		0x00	/* 8*32	bit	Current Descriptor */
+#define Q_DA_L	0x20	/* 32 bit	Current Descriptor Address Low DWord */
+#define Q_DA_H	0x24	/* 32 bit	Current Descriptor Address High DWord */
+#define Q_AC_L	0x28	/* 32 bit	Current Address Counter Low DWord */
+#define Q_AC_H	0x2c	/* 32 bit	Current Address Counter High DWord */
+#define Q_BC	0x30	/* 32 bit	Current Byte Counter */
+#define Q_CSR	0x34	/* 32 bit	BMU Control/Status Register */
+#define Q_F		0x38	/* 32 bit	Flag Register */
+#define Q_T1	0x3c	/* 32 bit	Test Register 1 */
+#define Q_T1_TR	0x3c	/*  8 bit	Test Register 1 Transfer SM */
+#define Q_T1_WR	0x3d	/*  8 bit	Test Register 1 Write Descriptor SM */
+#define Q_T1_RD	0x3e	/*  8 bit	Test Register 1 Read Descriptor SM */
+#define Q_T1_SV	0x3f	/*  8 bit	Test Register 1 Supervisor SM */
+#define Q_T2	0x40	/* 32 bit	Test Register 2 */
+#define Q_T3	0x44	/* 32 bit	Test Register 3 */
+
+/* Yukon-2 */
+#define Q_DONE		0x24	/* 16 bit	Done Index */
+
+#define Q_WM		0x40	/* 16 bit	FIFO Watermark */
+#define Q_AL		0x42	/*  8 bit	FIFO Alignment */
+	/* 0x43:	reserved */
+/* RX Queue */
+#define Q_RX_RSP	0x44	/* 16 bit	FIFO Read Shadow Pointer */
+#define Q_RX_RSL	0x46	/*  8 bit	FIFO Read Shadow Level */
+	/* 0x47:	reserved */
+#define Q_RX_RP		0x48	/*  8 bit	FIFO Read Pointer */
+	/* 0x49:	reserved */
+#define Q_RX_RL		0x4a	/*  8 bit	FIFO Read Level */
+	/* 0x4b:	reserved */
+#define Q_RX_WP		0x4c	/*  8 bit	FIFO Write Pointer */
+#define Q_RX_WSP	0x4d	/*  8 bit	FIFO Write Shadow Pointer */
+#define Q_RX_WL		0x4e	/*  8 bit	FIFO Write Level */
+#define Q_RX_WSL	0x4f	/*  8 bit	FIFO Write Shadow Level */
+/* TX Queue */
+#define Q_TX_WSP	0x44	/* 16 bit	FIFO Write Shadow Pointer */
+#define Q_TX_WSL	0x46	/*  8 bit	FIFO Write Shadow Level */
+	/* 0x47:	reserved */
+#define Q_TX_WP		0x48	/*  8 bit	FIFO Write Pointer */
+	/* 0x49:	reserved */
+#define Q_TX_WL		0x4a	/*  8 bit	FIFO Write Level */
+	/* 0x4b:	reserved */
+#define Q_TX_RP		0x4c	/*  8 bit	FIFO Read Pointer */
+	/* 0x4d:	reserved */
+#define Q_TX_RL		0x4e	/*  8 bit	FIFO Read Level */
+	/* 0x4f:	reserved */
+
+	/* 0x48 - 0x7f:	reserved */
+
+/* Queue Prefetch Unit Offs, use Y2_PREF_Q_ADDR() to address (Yukon-2 only) */
+#define Y2_B8_PREF_REGS			0x0450
+
+#define PREF_UNIT_CTRL_REG		0x00	/* 32 bit	Prefetch Control register */
+#define PREF_UNIT_LAST_IDX_REG	0x04	/* 16 bit	Last Index */
+#define PREF_UNIT_ADDR_LOW_REG	0x08	/* 32 bit	List start addr, low part */
+#define PREF_UNIT_ADDR_HI_REG	0x0c	/* 32 bit	List start addr, high part*/
+#define PREF_UNIT_GET_IDX_REG	0x10	/* 16 bit	Get Index */
+#define PREF_UNIT_PUT_IDX_REG	0x14	/* 16 bit	Put Index */
+#define PREF_UNIT_FIFO_WP_REG	0x20	/*  8 bit	FIFO write pointer */
+#define PREF_UNIT_FIFO_RP_REG	0x24	/*  8 bit	FIFO read pointer */
+#define PREF_UNIT_FIFO_WM_REG	0x28	/*  8 bit	FIFO watermark */
+#define PREF_UNIT_FIFO_LEV_REG	0x2c	/*  8 bit	FIFO level */
+
+#define PREF_UNIT_MASK_IDX		0x0fff
+
+/*
+ *	Bank 16 - 23
+ */
+/* RAM Buffer Registers */
+#define B16_RAM_REGS	0x0800
+
+/* RAM Buffer Register Offsets, use RB_ADDR() to access */
+#define RB_START		0x00	/* 32 bit	RAM Buffer Start Address */
+#define RB_END			0x04	/* 32 bit	RAM Buffer End Address */
+#define RB_WP			0x08	/* 32 bit	RAM Buffer Write Pointer */
+#define RB_RP			0x0c	/* 32 bit	RAM Buffer Read Pointer */
+#define RB_RX_UTPP		0x10	/* 32 bit	Rx Upper Threshold, Pause Packet */
+#define RB_RX_LTPP		0x14	/* 32 bit	Rx Lower Threshold, Pause Packet */
+#define RB_RX_UTHP		0x18	/* 32 bit	Rx Upper Threshold, High Prio */
+#define RB_RX_LTHP		0x1c	/* 32 bit	Rx Lower Threshold, High Prio */
+	/* 0x10 - 0x1f:	reserved at Tx RAM Buffer Registers */
+#define RB_PC			0x20	/* 32 bit	RAM Buffer Packet Counter */
+#define RB_LEV			0x24	/* 32 bit	RAM Buffer Level Register */
+#define RB_CTRL			0x28	/* 32 bit	RAM Buffer Control Register */
+#define RB_TST1			0x29	/*  8 bit	RAM Buffer Test Register 1 */
+#define RB_TST2			0x2a	/*  8 bit	RAM Buffer Test Register 2 */
+	/* 0x2b - 0x7f:	reserved */
+
+/*
+ *	Bank 24
+ */
+/*
+ * Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only)
+ * use MR_ADDR() to access
+ */
+#define RX_MFF_EA		0x0c00	/* 32 bit	Receive MAC FIFO End Address */
+#define RX_MFF_WP		0x0c04	/* 32 bit	Receive MAC FIFO Write Pointer */
+	/* 0x0c08 - 0x0c0b:	reserved */
+#define RX_MFF_RP		0x0c0c	/* 32 bit	Receive MAC FIFO Read Pointer */
+#define RX_MFF_PC		0x0c10	/* 32 bit	Receive MAC FIFO Packet Cnt */
+#define RX_MFF_LEV		0x0c14	/* 32 bit	Receive MAC FIFO Level */
+#define RX_MFF_CTRL1	0x0c18	/* 16 bit	Receive MAC FIFO Control Reg 1*/
+#define RX_MFF_STAT_TO	0x0c1a	/*  8 bit	Receive MAC Status Timeout */
+#define RX_MFF_TIST_TO	0x0c1b	/*  8 bit	Receive MAC Time Stamp Timeout */
+#define RX_MFF_CTRL2	0x0c1c	/*  8 bit	Receive MAC FIFO Control Reg 2*/
+#define RX_MFF_TST1		0x0c1d	/*  8 bit	Receive MAC FIFO Test Reg 1 */
+#define RX_MFF_TST2		0x0c1e	/*  8 bit	Receive MAC FIFO Test Reg 2 */
+	/* 0x0c1f:	reserved */
+#define RX_LED_INI		0x0c20	/* 32 bit	Receive LED Cnt Init Value */
+#define RX_LED_VAL		0x0c24	/* 32 bit	Receive LED Cnt Current Value */
+#define RX_LED_CTRL		0x0c28	/*  8 bit	Receive LED Cnt Control Reg */
+#define RX_LED_TST		0x0c29	/*  8 bit	Receive LED Cnt Test Register */
+	/* 0x0c2a - 0x0c2f:	reserved */
+#define LNK_SYNC_INI	0x0c30	/* 32 bit	Link Sync Cnt Init Value */
+#define LNK_SYNC_VAL	0x0c34	/* 32 bit	Link Sync Cnt Current Value */
+#define LNK_SYNC_CTRL	0x0c38	/*  8 bit	Link Sync Cnt Control Register */
+#define LNK_SYNC_TST	0x0c39	/*  8 bit	Link Sync Cnt Test Register */
+	/* 0x0c3a - 0x0c3b:	reserved */
+#define LNK_LED_REG		0x0c3c	/*  8 bit	Link LED Register */
+	/* 0x0c3d - 0x0c3f:	reserved */
+
+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define RX_GMF_EA		0x0c40	/* 32 bit	Rx GMAC FIFO End Address */
+#define RX_GMF_AF_THR	0x0c44	/* 32 bit	Rx GMAC FIFO Almost Full Thresh. */
+#define RX_GMF_CTRL_T	0x0c48	/* 32 bit	Rx GMAC FIFO Control/Test */
+#define RX_GMF_FL_MSK	0x0c4c	/* 32 bit	Rx GMAC FIFO Flush Mask */
+#define RX_GMF_FL_THR	0x0c50	/* 16 bit	Rx GMAC FIFO Flush Threshold */
+#define RX_GMF_FL_CTRL	0x0c52	/* 16 bit	Rx GMAC FIFO Flush Control */
+#define RX_GMF_TR_THR	0x0c54	/* 32 bit	Rx Truncation Threshold (Yukon-2) */
+#define RX_GMF_UP_THR	0x0c58	/* 16 bit	Rx Upper Pause Thr (Yukon-Ultra) */
+#define RX_GMF_LP_THR	0x0c5a	/* 16 bit	Rx Lower Pause Thr (Yukon-Ultra) */
+#define RX_GMF_VLAN		0x0c5c	/* 32 bit	Rx VLAN Type Register (Yukon-2) */
+#define RX_GMF_WP		0x0c60	/* 32 bit	Rx GMAC FIFO Write Pointer */
+	/* 0x0c64 - 0x0c67:	reserved */
+#define RX_GMF_WLEV		0x0c68	/* 32 bit	Rx GMAC FIFO Write Level */
+	/* 0x0c6c - 0x0c6f:	reserved */
+#define RX_GMF_RP		0x0c70	/* 32 bit	Rx GMAC FIFO Read Pointer */
+	/* 0x0c74 - 0x0c77:	reserved */
+#define RX_GMF_RLEV		0x0c78	/* 32 bit	Rx GMAC FIFO Read Level */
+	/* 0x0c7c - 0x0c7f:	reserved */
+
+/*
+ *	Bank 25
+ */
+	/* 0x0c80 - 0x0cbf:	MAC 2 */
+	/* 0x0cc0 - 0x0cff:	reserved */
+
+/*
+ *	Bank 26
+ */
+/*
+ * Transmit MAC FIFO and Transmit LED Registers (GENESIS only),
+ * use MR_ADDR() to access
+ */
+#define TX_MFF_EA		0x0d00	/* 32 bit	Transmit MAC FIFO End Address */
+#define TX_MFF_WP		0x0d04	/* 32 bit	Transmit MAC FIFO WR Pointer */
+#define TX_MFF_WSP		0x0d08	/* 32 bit	Transmit MAC FIFO WR Shadow Ptr */
+#define TX_MFF_RP		0x0d0c	/* 32 bit	Transmit MAC FIFO RD Pointer */
+#define TX_MFF_PC		0x0d10	/* 32 bit	Transmit MAC FIFO Packet Cnt */
+#define TX_MFF_LEV		0x0d14	/* 32 bit	Transmit MAC FIFO Level */
+#define TX_MFF_CTRL1	0x0d18	/* 16 bit	Transmit MAC FIFO Ctrl Reg 1 */
+#define TX_MFF_WAF		0x0d1a	/*  8 bit	Transmit MAC Wait after flush */
+	/* 0x0c1b:	reserved */
+#define TX_MFF_CTRL2	0x0d1c	/*  8 bit	Transmit MAC FIFO Ctrl Reg 2 */
+#define TX_MFF_TST1		0x0d1d	/*  8 bit	Transmit MAC FIFO Test Reg 1 */
+#define TX_MFF_TST2		0x0d1e	/*  8 bit	Transmit MAC FIFO Test Reg 2 */
+	/* 0x0d1f:	reserved */
+#define TX_LED_INI		0x0d20	/* 32 bit	Transmit LED Cnt Init Value */
+#define TX_LED_VAL		0x0d24	/* 32 bit	Transmit LED Cnt Current Val */
+#define TX_LED_CTRL		0x0d28	/*  8 bit	Transmit LED Cnt Control Reg */
+#define TX_LED_TST		0x0d29	/*  8 bit	Transmit LED Cnt Test Reg */
+	/* 0x0d2a - 0x0d3f:	reserved */
+
+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define TX_GMF_EA		0x0d40	/* 32 bit	Tx GMAC FIFO End Address */
+#define TX_GMF_AE_THR	0x0d44	/* 32 bit	Tx GMAC FIFO Almost Empty Thresh. */
+#define TX_GMF_CTRL_T	0x0d48	/* 32 bit	Tx GMAC FIFO Control/Test */
+	/* 0x0d4c - 0x0d5b:	reserved */
+#define TX_GMF_VLAN		0x0d5c	/* 32 bit	Tx VLAN Type Register (Yukon-2) */
+#define TX_GMF_WP		0x0d60	/* 32 bit	Tx GMAC FIFO Write Pointer */
+#define TX_GMF_WSP		0x0d64	/* 32 bit	Tx GMAC FIFO Write Shadow Pointer */
+#define TX_GMF_WLEV		0x0d68	/* 32 bit	Tx GMAC FIFO Write Level */
+	/* 0x0d6c - 0x0d6f:	reserved */
+#define TX_GMF_RP		0x0d70	/* 32 bit	Tx GMAC FIFO Read Pointer */
+#define TX_GMF_RSTP		0x0d74	/* 32 bit	Tx GMAC FIFO Restart Pointer */
+#define TX_GMF_RLEV		0x0d78	/* 32 bit	Tx GMAC FIFO Read Level */
+	/* 0x0d7c - 0x0d7f:	reserved */
+
+/*
+ *	Bank 27
+ */
+	/* 0x0d80 - 0x0dbf:	MAC 2 */
+	/* 0x0daa - 0x0dff:	reserved */
+
+/*
+ *	Bank 28
+ */
+/* Descriptor Poll Timer Registers */
+#define B28_DPT_INI		0x0e00	/* 24 bit	Descriptor Poll Timer Init Val */
+#define B28_DPT_VAL		0x0e04	/* 24 bit	Descriptor Poll Timer Curr Val */
+#define B28_DPT_CTRL	0x0e08	/*  8 bit	Descriptor Poll Timer Ctrl Reg */
+	/* 0x0e09:	reserved */
+#define B28_DPT_TST		0x0e0a	/*  8 bit	Descriptor Poll Timer Test Reg */
+	/* 0x0e0b:	reserved */
+
+/* Time Stamp Timer Registers (YUKON only) */
+	/* 0x0e10:	reserved */
+#define GMAC_TI_ST_VAL	0x0e14	/* 32 bit	Time Stamp Timer Curr Val */
+#define GMAC_TI_ST_CTRL	0x0e18	/*  8 bit	Time Stamp Timer Ctrl Reg */
+	/* 0x0e19:	reserved */
+#define GMAC_TI_ST_TST	0x0e1a	/*  8 bit	Time Stamp Timer Test Reg */
+	/* 0x0e1b - 0x0e1f:	reserved */
+
+/* Polling Unit Registers (Yukon-2 only) */
+#define POLL_CTRL			0x0e20	/* 32 bit	Polling Unit Control Reg */
+#define POLL_LAST_IDX		0x0e24	/* 16 bit	Polling Unit List Last Index */
+	/* 0x0e26 - 0x0e27:	reserved */
+#define POLL_LIST_ADDR_LO	0x0e28	/* 32 bit	Poll. List Start Addr (low) */
+#define POLL_LIST_ADDR_HI	0x0e2c	/* 32 bit	Poll. List Start Addr (high) */
+	/* 0x0e30 - 0x0e3f:	reserved */
+
+/* ASF Subsystem Registers (Yukon-2 only) */
+#define B28_Y2_SMB_CONFIG	0x0e40	/* 32 bit	ASF SMBus Config Register */
+#define B28_Y2_SMB_CSD_REG	0x0e44	/* 32 bit	ASF SMB Control/Status/Data */
+	/* 0x0e48 - 0x0e5f: reserved */
+#define B28_Y2_ASF_IRQ_V_BASE	0x0e60	/* 32 bit	ASF IRQ Vector Base */
+	/* 0x0e64 - 0x0e67: reserved */
+#define B28_Y2_ASF_STAT_CMD	0x0e68	/* 32 bit	ASF Status and Command Reg */
+#define B28_Y2_ASF_HOST_COM	0x0e6c	/* 32 bit	ASF Host Communication Reg */
+#define B28_Y2_DATA_REG_1	0x0e70	/* 32 bit	ASF/Host Data Register 1 */
+#define B28_Y2_DATA_REG_2	0x0e74	/* 32 bit	ASF/Host Data Register 2 */
+#define B28_Y2_DATA_REG_3	0x0e78	/* 32 bit	ASF/Host Data Register 3 */
+#define B28_Y2_DATA_REG_4	0x0e7c	/* 32 bit	ASF/Host Data Register 4 */
+
+/*
+ *	Bank 29
+ */
+/* Status BMU Registers (Yukon-2 only) */
+#define STAT_CTRL			0x0e80	/* 32 bit	Status BMU Control Reg */
+#define STAT_LAST_IDX		0x0e84	/* 16 bit	Status BMU Last Index */
+	/* 0x0e85 - 0x0e86:	reserved */
+#define STAT_LIST_ADDR_LO	0x0e88	/* 32 bit	Status List Start Addr (low) */
+#define STAT_LIST_ADDR_HI	0x0e8c	/* 32 bit	Status List Start Addr (high) */
+#define STAT_TXA1_RIDX		0x0e90	/* 16 bit	Status TxA1 Report Index Reg */
+#define STAT_TXS1_RIDX		0x0e92	/* 16 bit	Status TxS1 Report Index Reg */
+#define STAT_TXA2_RIDX		0x0e94	/* 16 bit	Status TxA2 Report Index Reg */
+#define STAT_TXS2_RIDX		0x0e96	/* 16 bit	Status TxS2 Report Index Reg */
+#define STAT_TX_IDX_TH		0x0e98	/* 16 bit	Status Tx Index Threshold Reg */
+	/* 0x0e9a - 0x0e9b:	reserved */
+#define STAT_PUT_IDX		0x0e9c	/* 16 bit	Status Put Index Reg */
+	/* 0x0e9e - 0x0e9f:	reserved */
+
+/* FIFO Control/Status Registers (Yukon-2 only) */
+#define STAT_FIFO_WP		0x0ea0	/*  8 bit	Status FIFO Write Pointer Reg */
+	/* 0x0ea1 - 0x0ea3:	reserved */
+#define STAT_FIFO_RP		0x0ea4	/*  8 bit	Status FIFO Read Pointer Reg */
+	/* 0x0ea5:	reserved */
+#define STAT_FIFO_RSP		0x0ea6	/*  8 bit	Status FIFO Read Shadow Ptr */
+	/* 0x0ea7:	reserved */
+#define STAT_FIFO_LEVEL		0x0ea8	/*  8 bit	Status FIFO Level Reg */
+	/* 0x0ea9:	reserved */
+#define STAT_FIFO_SHLVL		0x0eaa	/*  8 bit	Status FIFO Shadow Level Reg */
+	/* 0x0eab:	reserved */
+#define STAT_FIFO_WM		0x0eac	/*  8 bit	Status FIFO Watermark Reg */
+#define STAT_FIFO_ISR_WM	0x0ead	/*  8 bit	Status FIFO ISR Watermark Reg */
+	/* 0x0eae - 0x0eaf:	reserved */
+
+/* Level and ISR Timer Registers (Yukon-2 only) */
+#define STAT_LEV_TIMER_INI	0x0eb0	/* 32 bit	Level Timer Init. Value Reg */
+#define STAT_LEV_TIMER_CNT	0x0eb4	/* 32 bit	Level Timer Counter Reg */
+#define STAT_LEV_TIMER_CTRL	0x0eb8	/*  8 bit	Level Timer Control Reg */
+#define STAT_LEV_TIMER_TEST	0x0eb9	/*  8 bit	Level Timer Test Reg */
+	/* 0x0eba - 0x0ebf:	reserved */
+#define STAT_TX_TIMER_INI	0x0ec0	/* 32 bit	Tx Timer Init. Value Reg */
+#define STAT_TX_TIMER_CNT	0x0ec4	/* 32 bit	Tx Timer Counter Reg */
+#define STAT_TX_TIMER_CTRL	0x0ec8	/*  8 bit	Tx Timer Control Reg */
+#define STAT_TX_TIMER_TEST	0x0ec9	/*  8 bit	Tx Timer Test Reg */
+	/* 0x0eca - 0x0ecf:	reserved */
+#define STAT_ISR_TIMER_INI	0x0ed0	/* 32 bit	ISR Timer Init. Value Reg */
+#define STAT_ISR_TIMER_CNT	0x0ed4	/* 32 bit	ISR Timer Counter Reg */
+#define STAT_ISR_TIMER_CTRL	0x0ed8	/*  8 bit	ISR Timer Control Reg */
+#define STAT_ISR_TIMER_TEST	0x0ed9	/*  8 bit	ISR Timer Test Reg */
+	/* 0x0eda - 0x0eff:	reserved */
+
+#define ST_LAST_IDX_MASK	0x007f	/* Last Index Mask */
+#define ST_TXRP_IDX_MASK	0x0fff	/* Tx Report Index Mask */
+#define ST_TXTH_IDX_MASK	0x0fff	/* Tx Threshold Index Mask */
+#define ST_WM_IDX_MASK		0x3f	/* FIFO Watermark Index Mask */
+
+/*
+ *	Bank 30
+ */
+/* GMAC and GPHY Control Registers (YUKON only) */
+#define GMAC_CTRL		0x0f00	/* 32 bit	GMAC Control Reg */
+#define GPHY_CTRL		0x0f04	/* 32 bit	GPHY Control Reg */
+#define GMAC_IRQ_SRC	0x0f08	/*  8 bit	GMAC Interrupt Source Reg */
+	/* 0x0f09 - 0x0f0b:	reserved */
+#define GMAC_IRQ_MSK	0x0f0c	/*  8 bit	GMAC Interrupt Mask Reg */
+	/* 0x0f0d - 0x0f0f:	reserved */
+#define GMAC_LINK_CTRL	0x0f10	/* 16 bit	Link Control Reg */
+	/* 0x0f14 - 0x0f1f:	reserved */
+
+/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
+
+#define WOL_REG_OFFS	0x20	/* HW-Bug: Address is + 0x20 against spec. */
+
+#define WOL_CTRL_STAT	0x0f20	/* 16 bit	WOL Control/Status Reg */
+#define WOL_MATCH_CTL	0x0f22	/*  8 bit	WOL Match Control Reg */
+#define WOL_MATCH_RES	0x0f23	/*  8 bit	WOL Match Result Reg */
+#define WOL_MAC_ADDR_LO	0x0f24	/* 32 bit	WOL MAC Address Low */
+#define WOL_MAC_ADDR_HI	0x0f28	/* 16 bit	WOL MAC Address High */
+#define WOL_PATT_PME	0x0f2a	/*  8 bit	WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_ASFM	0x0f2b	/*  8 bit	WOL ASF Match Enable (Yukon-2) */
+#define WOL_PATT_RPTR	0x0f2c	/*  8 bit	WOL Pattern Read Pointer */
+
+/* WOL Pattern Length Registers (YUKON only) */
+
+#define WOL_PATT_LEN_LO	0x0f30		/* 32 bit	WOL Pattern Length 3..0 */
+#define WOL_PATT_LEN_HI	0x0f34		/* 24 bit	WOL Pattern Length 6..4 */
+
+/* WOL Pattern Counter Registers (YUKON only) */
+
+#define WOL_PATT_CNT_0	0x0f38		/* 32 bit	WOL Pattern Counter 3..0 */
+#define WOL_PATT_CNT_4	0x0f3c		/* 24 bit	WOL Pattern Counter 6..4 */
+	/* 0x0f40 - 0x0f7f:	reserved */
+
+/*
+ *	Bank 31
+ */
+/* 0x0f80 - 0x0fff:	reserved */
+
+/* WOL registers link 2 */
+
+/* use this macro to access WOL registers */
+#define WOL_REG(Port, Reg)		((Reg) + (Port) * 0x80 + pAC->GIni.GIWolOffs)
+
+/*
+ *	Bank 0x20 - 0x21
+ */
+#define WOL_PATT_RAM_1	0x1000	/* WOL Pattern RAM Link 1 */
+#define WOL_PATT_RAM_2	0x1400	/* WOL Pattern RAM Link 2 */
+
+/* use this macro to retrieve the pattern RAM base address */
+#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port) * 0x400)
+
+/* offset to configuration space on Yukon-2 */
+#define Y2_CFG_SPC		0x1c00
+/*
+ *	Bank 0x22 - 0x3f
+ */
+/* 0x1100 - 0x1fff:	reserved */
+
+/*
+ *	Bank 0x40 - 0x4f
+ */
+#define BASE_XMAC_1		0x2000	/* XMAC 1 registers */
+
+/*
+ *	Bank 0x50 - 0x5f
+ */
+#define BASE_GMAC_1		0x2800	/* GMAC 1 registers */
+
+/*
+ *	Bank 0x60 - 0x6f
+ */
+#define BASE_XMAC_2		0x3000	/* XMAC 2 registers */
+
+/*
+ *	Bank 0x70 - 0x7f
+ */
+#define BASE_GMAC_2		0x3800	/* GMAC 2 registers */
+
+/*
+ *	Control Register Bit Definitions:
+ */
+/*	B0_RAP		8 bit	Register Address Port */
+								/* Bit 7:	reserved */
+#define RAP_MSK			0x7f	/* Bit 6..0:	0 = block 0,..,6f = block 6f */
+
+/*	B0_CTST			24 bit	Control/Status register */
+								/* Bit 23..18:	reserved */
+#define Y2_VMAIN_AVAIL	BIT_17		/* VMAIN available (YUKON-2 only) */
+#define Y2_VAUX_AVAIL	BIT_16		/* VAUX available (YUKON-2 only) */
+#define Y2_HW_WOL_ON	BIT_15S		/* HW WOL On  (Yukon-EC Ultra A1 only) */
+#define Y2_HW_WOL_OFF	BIT_14S		/* HW WOL Off (Yukon-EC Ultra A1 only) */
+#define Y2_ASF_ENABLE	BIT_13S		/* ASF Unit Enable (YUKON-2 only) */
+#define Y2_ASF_DISABLE	BIT_12S		/* ASF Unit Disable (YUKON-2 only) */
+#define Y2_CLK_RUN_ENA	BIT_11S		/* CLK_RUN Enable  (YUKON-2 only) */
+#define Y2_CLK_RUN_DIS	BIT_10S		/* CLK_RUN Disable (YUKON-2 only) */
+#define Y2_LED_STAT_ON	BIT_9S		/* Status LED On  (YUKON-2 only) */
+#define Y2_LED_STAT_OFF	BIT_8S		/* Status LED Off (YUKON-2 only) */
+								/* Bit  7.. 0:	same as below */
+
+/*	B0_CTST			16 bit	Control/Status register */
+								/* Bit 15..14:	reserved */
+#define CS_CLK_RUN_HOT	BIT_13S		/* CLK_RUN Hot m. (YUKON-Lite only) */
+#define CS_CLK_RUN_RST	BIT_12S		/* CLK_RUN Reset  (YUKON-Lite only) */
+#define CS_CLK_RUN_ENA	BIT_11S		/* CLK_RUN Enable (YUKON-Lite only) */
+#define CS_VAUX_AVAIL	BIT_10S		/* VAUX available (YUKON only) */
+#define CS_BUS_CLOCK	BIT_9S		/* Bus Clock 0/1 = 33/66 MHz */
+#define CS_BUS_SLOT_SZ	BIT_8S		/* Slot Size 0/1 = 32/64 bit slot */
+#define CS_ST_SW_IRQ	BIT_7S		/* Set IRQ SW Request */
+#define CS_CL_SW_IRQ	BIT_6S		/* Clear IRQ SW Request */
+#define CS_STOP_DONE	BIT_5S		/* Stop Master is finished */
+#define CS_STOP_MAST	BIT_4S		/* Command Bit to stop the master */
+#define CS_MRST_CLR		BIT_3S		/* Clear Master Reset */
+#define CS_MRST_SET		BIT_2S		/* Set   Master Reset */
+#define CS_RST_CLR		BIT_1S		/* Clear Software Reset */
+#define CS_RST_SET		BIT_0S		/* Set   Software Reset */
+
+/*	B0_LED			 8 Bit	LED register (GENESIS only) */
+								/* Bit  7.. 2:	reserved */
+#define LED_STAT_ON		BIT_1S		/* Status LED On */
+#define LED_STAT_OFF	BIT_0S		/* Status LED Off */
+
+/*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
+#define PC_VAUX_ENA		BIT_7		/* Switch VAUX Enable  */
+#define PC_VAUX_DIS		BIT_6		/* Switch VAUX Disable */
+#define PC_VCC_ENA		BIT_5		/* Switch VCC Enable  */
+#define PC_VCC_DIS		BIT_4		/* Switch VCC Disable */
+#define PC_VAUX_ON		BIT_3		/* Switch VAUX On  */
+#define PC_VAUX_OFF		BIT_2		/* Switch VAUX Off */
+#define PC_VCC_ON		BIT_1		/* Switch VCC On  */
+#define PC_VCC_OFF		BIT_0		/* Switch VCC Off */
+
+/* Yukon and Genesis */
+/*	B0_ISRC			32 bit	Interrupt Source Register */
+/*	B0_IMSK			32 bit	Interrupt Mask Register */
+/*	B0_SP_ISRC		32 bit	Special Interrupt Source Reg */
+/*	B2_IRQM_MSK		32 bit	IRQ Moderation Mask */
+#define IS_ALL_MSK		0xbfffffffUL	/* All Interrupt bits */
+#define IS_HW_ERR		BIT_31		/* Interrupt HW Error */
+								/* Bit 30:	reserved */
+#define IS_PA_TO_RX1	BIT_29		/* Packet Arb Timeout Rx1 */
+#define IS_PA_TO_RX2	BIT_28		/* Packet Arb Timeout Rx2 */
+#define IS_PA_TO_TX1	BIT_27		/* Packet Arb Timeout Tx1 */
+#define IS_PA_TO_TX2	BIT_26		/* Packet Arb Timeout Tx2 */
+#define IS_I2C_READY	BIT_25		/* IRQ on end of I2C Tx */
+#define IS_IRQ_SW		BIT_24		/* SW forced IRQ */
+#define IS_EXT_REG		BIT_23		/* IRQ from LM80 or PHY (GENESIS only) */
+									/* IRQ from PHY (YUKON only) */
+#define IS_TIMINT		BIT_22		/* IRQ from Timer */
+#define IS_MAC1			BIT_21		/* IRQ from MAC 1 */
+#define IS_LNK_SYNC_M1	BIT_20		/* Link Sync Cnt wrap MAC 1 */
+#define IS_MAC2			BIT_19		/* IRQ from MAC 2 */
+#define IS_LNK_SYNC_M2	BIT_18		/* Link Sync Cnt wrap MAC 2 */
+/* Receive Queue 1 */
+#define IS_R1_B			BIT_17		/* Q_R1 End of Buffer */
+#define IS_R1_F			BIT_16		/* Q_R1 End of Frame */
+#define IS_R1_C			BIT_15		/* Q_R1 Encoding Error */
+/* Receive Queue 2 */
+#define IS_R2_B			BIT_14		/* Q_R2 End of Buffer */
+#define IS_R2_F			BIT_13		/* Q_R2 End of Frame */
+#define IS_R2_C			BIT_12		/* Q_R2 Encoding Error */
+/* Synchronous Transmit Queue 1 */
+#define IS_XS1_B		BIT_11		/* Q_XS1 End of Buffer */
+#define IS_XS1_F		BIT_10		/* Q_XS1 End of Frame */
+#define IS_XS1_C		BIT_9		/* Q_XS1 Encoding Error */
+/* Asynchronous Transmit Queue 1 */
+#define IS_XA1_B		BIT_8		/* Q_XA1 End of Buffer */
+#define IS_XA1_F		BIT_7		/* Q_XA1 End of Frame */
+#define IS_XA1_C		BIT_6		/* Q_XA1 Encoding Error */
+/* Synchronous Transmit Queue 2 */
+#define IS_XS2_B		BIT_5		/* Q_XS2 End of Buffer */
+#define IS_XS2_F		BIT_4		/* Q_XS2 End of Frame */
+#define IS_XS2_C		BIT_3		/* Q_XS2 Encoding Error */
+/* Asynchronous Transmit Queue 2 */
+#define IS_XA2_B		BIT_2		/* Q_XA2 End of Buffer */
+#define IS_XA2_F		BIT_1		/* Q_XA2 End of Frame */
+#define IS_XA2_C		BIT_0		/* Q_XA2 Encoding Error */
+
+/* Yukon-2 */
+/*	B0_ISRC			32 bit	Interrupt Source Register */
+/*	B0_IMSK			32 bit	Interrupt Mask Register */
+/*	B0_SP_ISRC		32 bit	Special Interrupt Source Reg */
+/*	B2_IRQM_MSK		32 bit	IRQ Moderation Mask */
+/*	B0_Y2_SP_ISRC2	32 bit	Special Interrupt Source Reg 2 */
+/*	B0_Y2_SP_ISRC3	32 bit	Special Interrupt Source Reg 3 */
+/*	B0_Y2_SP_EISR	32 bit	Enter ISR Reg */
+/*	B0_Y2_SP_LISR	32 bit	Leave ISR Reg */
+#define Y2_IS_PORT_MASK(Port, Mask)	((Mask) << (Port*8))
+#define Y2_IS_HW_ERR	BIT_31		/* Interrupt HW Error */
+#define Y2_IS_STAT_BMU	BIT_30		/* Status BMU Interrupt */
+#define Y2_IS_ASF		BIT_29		/* ASF subsystem Interrupt */
+#define Y2_IS_CPU_TO	BIT_28		/* CPU Timeout */
+#define Y2_IS_POLL_CHK	BIT_27		/* Check IRQ from polling unit */
+#define Y2_IS_TWSI_RDY	BIT_26		/* IRQ on end of TWSI Tx */
+#define Y2_IS_IRQ_SW	BIT_25		/* SW forced IRQ */
+#define Y2_IS_TIMINT	BIT_24		/* IRQ from Timer */
+							/* Bit 23..16 reserved */
+						/* Link 2 Interrupts */
+#define Y2_IS_IRQ_PHY2	BIT_12		/* Interrupt from PHY 2 */
+#define Y2_IS_IRQ_MAC2	BIT_11		/* Interrupt from MAC 2 */
+#define Y2_IS_CHK_RX2	BIT_10		/* Descriptor error Rx 2 */
+#define Y2_IS_CHK_TXS2	BIT_9		/* Descriptor error TXS 2 */
+#define Y2_IS_CHK_TXA2	BIT_8		/* Descriptor error TXA 2 */
+#define Y2_IS_PSM_ACK	BIT_7		/* PSM Acknowledge (Yukon-Optima only) */
+#define Y2_IS_PTP_TIST	BIT_6		/* PTP Time Stamp (Yukon-Optima only) */
+#define Y2_IS_PHY_QLNK	BIT_5		/* PHY Quick Link (Yukon-Optima only) */
+						/* Link 1 interrupts */
+#define Y2_IS_IRQ_PHY1	BIT_4		/* Interrupt from PHY 1 */
+#define Y2_IS_IRQ_MAC1	BIT_3		/* Interrupt from MAC 1 */
+#define Y2_IS_CHK_RX1	BIT_2		/* Descriptor error Rx 1 */
+#define Y2_IS_CHK_TXS1	BIT_1		/* Descriptor error TXS 1 */
+#define Y2_IS_CHK_TXA1	BIT_0		/* Descriptor error TXA 1 */
+
+						/* IRQ Mask for port 1 */
+#define Y2_IS_L1_MASK	(Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_RX1 |\
+						 Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)
+
+						/* IRQ Mask for port 2 */
+#define Y2_IS_L2_MASK	(Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_RX2 |\
+						 Y2_IS_CHK_TXS2 | Y2_IS_CHK_TXA2)
+
+						/* All Interrupt bits for port 1 */
+#define Y2_IS_ALL_MSK	(Y2_IS_HW_ERR | Y2_IS_STAT_BMU | Y2_IS_ASF |\
+						 Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY | Y2_IS_IRQ_SW |\
+						 Y2_IS_TIMINT | Y2_IS_L1_MASK)
+
+/*	B0_Y2_SP_ICR	32 bit	Interrupt Control Register */
+							/* Bit 31.. 4:	reserved */
+#define Y2_IC_ISR_MASK	BIT_3		/* ISR mask flag */
+#define Y2_IC_ISR_STAT	BIT_2		/* ISR status flag */
+#define Y2_IC_LEAVE_ISR	BIT_1		/* Leave ISR */
+#define Y2_IC_ENTER_ISR	BIT_0		/* Enter ISR */
+
+/* Yukon and Genesis */
+/*	B0_HWE_ISRC		32 bit	HW Error Interrupt Source Reg */
+/*	B0_HWE_IMSK		32 bit	HW Error Interrupt Mask Reg */
+/*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
+#define IS_ERR_MSK		0x00000fffL	/*		All Error bits */
+							/* Bit 31..14:	reserved */
+#define IS_IRQ_TIST_OV	BIT_13	/* Time Stamp Timer Overflow (YUKON only) */
+#define IS_IRQ_SENSOR	BIT_12	/* IRQ from Sensor (YUKON only) */
+#define IS_IRQ_MST_ERR	BIT_11	/* IRQ master error detected */
+#define IS_IRQ_STAT		BIT_10	/* IRQ status exception */
+#define IS_NO_STAT_M1	BIT_9	/* No Rx Status from MAC 1 */
+#define IS_NO_STAT_M2	BIT_8	/* No Rx Status from MAC 2 */
+#define IS_NO_TIST_M1	BIT_7	/* No Time Stamp from MAC 1 */
+#define IS_NO_TIST_M2	BIT_6	/* No Time Stamp from MAC 2 */
+#define IS_RAM_RD_PAR	BIT_5	/* RAM Read  Parity Error */
+#define IS_RAM_WR_PAR	BIT_4	/* RAM Write Parity Error */
+#define IS_M1_PAR_ERR	BIT_3	/* MAC 1 Parity Error */
+#define IS_M2_PAR_ERR	BIT_2	/* MAC 2 Parity Error */
+#define IS_R1_PAR_ERR	BIT_1	/* Queue R1 Parity Error */
+#define IS_R2_PAR_ERR	BIT_0	/* Queue R2 Parity Error */
+
+/* Yukon-2 */
+/*	B0_HWE_ISRC		32 bit	HW Error Interrupt Source Reg */
+/*	B0_HWE_IMSK		32 bit	HW Error Interrupt Mask Reg */
+/*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
+						/* Bit: 31..30 reserved */
+#define Y2_IS_TIST_OV	BIT_29	/* Time Stamp Timer overflow interrupt */
+#define Y2_IS_SENSOR	BIT_28	/* Sensor interrupt */
+#define Y2_IS_MST_ERR	BIT_27	/* Master error interrupt */
+#define Y2_IS_IRQ_STAT	BIT_26	/* Status exception interrupt */
+#define Y2_IS_PCI_EXP	BIT_25	/* PCI-Express interrupt */
+#define Y2_IS_PCI_NEXP	BIT_24	/* Bus Abort detected */
+						/* Bit: 23..14 reserved */
+						/* Link 2 */
+#define Y2_IS_PAR_RD2	BIT_13	/* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR2	BIT_12	/* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC2	BIT_11	/* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX2	BIT_10	/* Parity Error Rx Queue 2 */
+#define Y2_IS_TCP_TXS2	BIT_9	/* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA2	BIT_8	/* TCP length mismatch async Tx queue IRQ */
+						/* Bit:  9.. 6 reserved */
+						/* Link 1 */
+#define Y2_IS_PAR_RD1	BIT_5	/* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR1	BIT_4	/* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC1	BIT_3	/* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX1	BIT_2	/* Parity Error Rx Queue 1 */
+#define Y2_IS_TCP_TXS1	BIT_1	/* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA1	BIT_0	/* TCP length mismatch async Tx queue IRQ */
+
+#define Y2_HWE_L1_MASK	(Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
+						 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
+#define Y2_HWE_L2_MASK	(Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
+						 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
+
+#define Y2_HWE_ALL_MSK	(Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
+						 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
+						 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
+
+/*	B2_CONN_TYP		 8 bit	Connector type */
+/*	B2_PMD_TYP		 8 bit	PMD type */
+/*	Values of connector and PMD type comply to SysKonnect internal std */
+
+/*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
+#define CFG_CHIP_R_MSK	(0xf<<4)	/* Bit 7.. 4: Chip Revision */
+									/* Bit 3.. 2:	reserved */
+#define CFG_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */
+#define CFG_SNG_MAC		BIT_0S		/* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
+
+/*	B2_CHIP_ID		 8 bit	Chip Identification Number */
+#define CHIP_ID_GENESIS		0x0a	/* Chip ID for GENESIS */
+#define CHIP_ID_YUKON		0xb0	/* Chip ID for YUKON */
+#define CHIP_ID_YUKON_LITE	0xb1	/* Chip ID for YUKON-Lite (Rev. A1-A3) */
+#define CHIP_ID_YUKON_LP	0xb2	/* Chip ID for YUKON-LP */
+#define CHIP_ID_YUKON_XL	0xb3	/* Chip ID for YUKON-2 XL */
+#define CHIP_ID_YUKON_EC_U	0xb4	/* Chip ID for YUKON-2 EC Ultra */
+#define CHIP_ID_YUKON_EX	0xb5	/* Chip ID for YUKON-2 Extreme */
+#define CHIP_ID_YUKON_EC	0xb6	/* Chip ID for YUKON-2 EC */
+#define CHIP_ID_YUKON_FE	0xb7	/* Chip ID for YUKON-2 FE */
+#define CHIP_ID_YUKON_FE_P	0xb8	/* Chip ID for YUKON-2 FE+ */
+#define CHIP_ID_YUKON_SUPR	0xb9	/* Chip ID for YUKON-2 Supreme */
+#define CHIP_ID_YUKON_UL_2	0xba	/* Chip ID for YUKON-2 Ultra 2 */
+#define CHIP_ID_YUKON_OPT	0xbc	/* Chip ID for YUKON-2 Optima */
+#define CHIP_ID_YUKON_PRM	0xbd	/* Chip ID for YUKON-2 Optima Prime */
+#define CHIP_ID_YUKON_OP_2	0xbe	/* Chip ID for YUKON-2 Optima 2 */
+
+#define CHIP_REV_YU_LITE_A1	3		/* Chip Rev. for YUKON-Lite A1,A2 */
+#define CHIP_REV_YU_LITE_A3	7		/* Chip Rev. for YUKON-Lite A3 */
+#define CHIP_REV_YU_LITE_A4	9		/* Chip Rev. for YUKON-Lite A4 */
+
+#define CHIP_REV_YU_XL_A0	0		/* Chip Rev. for Yukon-2 A0 */
+#define CHIP_REV_YU_XL_A1	1		/* Chip Rev. for Yukon-2 A1 */
+#define CHIP_REV_YU_XL_A2	2		/* Chip Rev. for Yukon-2 A2 */
+#define CHIP_REV_YU_XL_A3	3		/* Chip Rev. for Yukon-2 A3 */
+
+#define CHIP_REV_YU_EC_A1	0		/* Chip Rev. for Yukon-EC A0,A1 */
+#define CHIP_REV_YU_EC_A2	1		/* Chip Rev. for Yukon-EC A2 */
+#define CHIP_REV_YU_EC_A3	2		/* Chip Rev. for Yukon-EC A3 */
+
+#define CHIP_REV_YU_EC_U_A0	1		/* Chip Rev. for Yukon-EC Ultra A0 */
+#define CHIP_REV_YU_EC_U_A1	2		/* Chip Rev. for Yukon-EC Ultra A1 */
+#define CHIP_REV_YU_EC_U_B0	3		/* Chip Rev. for Yukon-EC Ultra B0 */
+#define CHIP_REV_YU_EC_U_B1	5		/* Chip Rev. for Yukon-EC Ultra B1 */
+
+#define CHIP_REV_YU_FE_A1	1		/* Chip Rev. for Yukon-FE A1 */
+#define CHIP_REV_YU_FE_A2	3		/* Chip Rev. for Yukon-FE A2 */
+
+#define CHIP_REV_YU_FE2_A0	0		/* Chip Rev. for Yukon-FE+ A0 */
+
+#define CHIP_REV_YU_EX_A0	1		/* Chip Rev. for Yukon-Extreme A0 */
+#define CHIP_REV_YU_EX_B0	2		/* Chip Rev. for Yukon-Extreme B0 */
+
+#define CHIP_REV_YU_SU_A0	0		/* Chip Rev. for Yukon-Supreme A0 */
+#define CHIP_REV_YU_SU_B0	1		/* Chip Rev. for Yukon-Supreme B0 */
+#define CHIP_REV_YU_SU_B1	3		/* Chip Rev. for Yukon-Supreme B1 */
+
+#define CHIP_CAP_MSK_EX_B1	2		/* B1: bit 1 is cleared in chip cap. */
+
+/*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
+#define Y2_STATUS_LNK2_INAC	BIT_7S	/* Status Link 2 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK2_DIS	BIT_6S	/* Disable PHY clock for Link 2 */
+#define Y2_COR_CLK_LNK2_DIS	BIT_5S	/* Disable Core clock Link 2 */
+#define Y2_PCI_CLK_LNK2_DIS	BIT_4S	/* Disable PCI clock Link 2 */
+#define Y2_STATUS_LNK1_INAC	BIT_3S	/* Status Link 1 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK1_DIS	BIT_2S	/* Disable PHY clock for Link 1 */
+#define Y2_COR_CLK_LNK1_DIS	BIT_1S	/* Disable Core clock Link 1 */
+#define Y2_PCI_CLK_LNK1_DIS	BIT_0S	/* Disable PCI clock Link 1 */
+
+/*	B2_Y2_HW_RES	8 bit	HW Resources (Yukon-2 only) */
+								/* Bit 7.. 6:	reserved */
+#define CFG_PEX_PME_NATIVE	BIT_5S	/* PCI-E PME native mode select */
+#define CFG_LED_MODE_MSK	(7<<2)	/* Bit  4.. 2:	LED Mode Mask */
+#define CFG_LINK_2_AVAIL	BIT_1S	/* Link 2 available */
+#define CFG_LINK_1_AVAIL	BIT_0S	/* Link 1 available */
+
+#define CFG_LED_MODE(x)		(((x) & CFG_LED_MODE_MSK) >> 2)
+#define CFG_DUAL_MAC_MSK	(CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
+
+#define CFG_LED_DUAL_ACT_LNK	1	/* Dual LED ACT/LNK mode */
+#define CFG_LED_LINK_MUX_P60	2	/* Link LED on pin 60 (Yukon-EC Ultra) */
+#define CFG_LED_ACT_OFF_NOTR	4	/* Activity LED off (no traffic) */
+#define CFG_LED_COMB_ACT_LNK	5	/* Combined ACT/LNK mode */
+#define CFG_LED_HP_SPC_4_LED	6	/* HP special 4 LED mode */
+
+/*	B2_E_3			 8 bit	lower 4 bits used for HW self test result */
+#define B2_E3_RES_MASK	0x0f
+
+/*	B2_FAR			32 bit	Flash-Prom Addr Reg/Cnt */
+#define FAR_ADDR		0x1ffffL	/* Bit 16.. 0:	FPROM Address Mask */
+
+/*	B2_Y2_CLK_CTRL	32 bit	Core Clock Frequency Control Register (Yukon-2/EC) */
+								/* Bit 31..24:	reserved */
+/* Yukon-EC/FE */
+#define Y2_CLK_DIV_VAL_MSK	(0xffL<<16)	/* Bit 23..16:	Clock Divisor Value */
+#define Y2_CLK_DIV_VAL(x)	(SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
+/* Yukon-2 */
+#define Y2_CLK_DIV_VAL2_MSK	(7L<<21)	/* Bit 23..21:	Clock Divisor Value */
+#define Y2_CLK_SELECT2_MSK	(0x1fL<<16)	/* Bit 20..16:	Clock Select */
+#define Y2_CLK_DIV_VAL_2(x)	(SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
+#define Y2_CLK_SEL_VAL_2(x)	(SHIFT16(x) & Y2_CLK_SELECT2_MSK)
+								/* Bit 15.. 2:	reserved */
+#define Y2_CLK_DIV_ENA		BIT_1S	/* Enable  Core Clock Division */
+#define Y2_CLK_DIV_DIS		BIT_0S	/* Disable Core Clock Division */
+
+/*	B2_LD_CTRL		 8 bit	EPROM loader control register */
+/*	Bits are currently reserved */
+
+/*	B2_LD_TEST		 8 bit	EPROM loader test register */
+								/* Bit 7.. 4:	reserved */
+#define LD_T_ON			BIT_3S	/* Loader Test mode on */
+#define LD_T_OFF		BIT_2S	/* Loader Test mode off */
+#define LD_T_STEP		BIT_1S	/* Decrement FPROM addr. Counter */
+#define LD_START		BIT_0S	/* Start loading FPROM */
+
+/*
+ *	Timer Section
+ */
+/*	B2_TI_CTRL		 8 bit	Timer control */
+/*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
+								/* Bit 7.. 3:	reserved */
+#define TIM_START		BIT_2S	/* Start Timer */
+#define TIM_STOP		BIT_1S	/* Stop  Timer */
+#define TIM_CLR_IRQ		BIT_0S	/* Clear Timer IRQ (!IRQM) */
+
+/*	B2_TI_TEST		 8 Bit	Timer Test */
+/*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
+/*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
+								/* Bit 7.. 3:	reserved */
+#define TIM_T_ON		BIT_2S	/* Test mode on */
+#define TIM_T_OFF		BIT_1S	/* Test mode off */
+#define TIM_T_STEP		BIT_0S	/* Test step */
+
+/*	B28_DPT_INI	32 bit	Descriptor Poll Timer Init Val */
+/*	B28_DPT_VAL	32 bit	Descriptor Poll Timer Curr Val */
+								/* Bit 31..24:	reserved */
+#define DPT_MSK		0x00ffffffL	/* Bit 23.. 0:	Desc Poll Timer Bits */
+
+/*	B28_DPT_CTRL	 8 bit	Descriptor Poll Timer Ctrl Reg */
+								/* Bit  7.. 2:	reserved */
+#define DPT_START		BIT_1S	/* Start Descriptor Poll Timer */
+#define DPT_STOP		BIT_0S	/* Stop  Descriptor Poll Timer */
+
+/*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
+#define TST_FRC_DPERR_MR	BIT_7S	/* force DATAPERR on MST RD */
+#define TST_FRC_DPERR_MW	BIT_6S	/* force DATAPERR on MST WR */
+#define TST_FRC_DPERR_TR	BIT_5S	/* force DATAPERR on TRG RD */
+#define TST_FRC_DPERR_TW	BIT_4S	/* force DATAPERR on TRG WR */
+#define TST_FRC_APERR_M		BIT_3S	/* force ADDRPERR on MST */
+#define TST_FRC_APERR_T		BIT_2S	/* force ADDRPERR on TRG */
+#define TST_CFG_WRITE_ON	BIT_1S	/* Enable  Config Reg WR */
+#define TST_CFG_WRITE_OFF	BIT_0S	/* Disable Config Reg WR */
+
+/*	B2_TST_CTRL2	 8 bit	Test Control Register 2 */
+									/* Bit 7.. 4:	reserved */
+			/* force the following error on the next master read/write */
+#define TST_FRC_DPERR_MR64	BIT_3S	/* Data PERR RD 64 */
+#define TST_FRC_DPERR_MW64	BIT_2S	/* Data PERR WR 64 */
+#define TST_FRC_APERR_1M64	BIT_1S	/* Addr PERR on 1. phase */
+#define TST_FRC_APERR_2M64	BIT_0S	/* Addr PERR on 2. phase */
+
+/*	B2_GP_IO		32 bit	General Purpose I/O Register */
+						/* Bit 31..26:	reserved */
+#define GP_DIR_9	BIT_25	/* IO_9 direct, 0=In/1=Out */
+#define GP_DIR_8	BIT_24	/* IO_8 direct, 0=In/1=Out */
+#define GP_DIR_7	BIT_23	/* IO_7 direct, 0=In/1=Out */
+#define GP_DIR_6	BIT_22	/* IO_6 direct, 0=In/1=Out */
+#define GP_DIR_5	BIT_21	/* IO_5 direct, 0=In/1=Out */
+#define GP_DIR_4	BIT_20	/* IO_4 direct, 0=In/1=Out */
+#define GP_DIR_3	BIT_19	/* IO_3 direct, 0=In/1=Out */
+#define GP_DIR_2	BIT_18	/* IO_2 direct, 0=In/1=Out */
+#define GP_DIR_1	BIT_17	/* IO_1 direct, 0=In/1=Out */
+#define GP_DIR_0	BIT_16	/* IO_0 direct, 0=In/1=Out */
+						/* Bit 15..10:	reserved */
+#define GP_IO_9		BIT_9	/* IO_9 pin */
+#define GP_IO_8		BIT_8	/* IO_8 pin */
+#define GP_IO_7		BIT_7	/* IO_7 pin */
+#define GP_IO_6		BIT_6	/* IO_6 pin */
+#define GP_IO_5		BIT_5	/* IO_5 pin */
+#define GP_IO_4		BIT_4	/* IO_4 pin */
+#define GP_IO_3		BIT_3	/* IO_3 pin */
+#define GP_IO_2		BIT_2	/* IO_2 pin */
+#define GP_IO_1		BIT_1	/* IO_1 pin */
+#define GP_IO_0		BIT_0	/* IO_0 pin */
+
+/*	B2_I2C_CTRL		32 bit	I2C HW Control Register */
+#define I2C_FLAG		BIT_31		/* Start read/write if WR */
+#define I2C_ADDR		(0x7fffL<<16)	/* Bit 30..16:	Addr to be RD/WR */
+#define I2C_DEV_SEL		(0x7fL<<9)		/* Bit 15.. 9:	I2C Device Select */
+								/* Bit	8.. 5:	reserved */
+#define I2C_BURST_LEN	BIT_4		/* Burst Len, 1/4 bytes */
+#define I2C_DEV_SIZE	(7<<1)		/* Bit	3.. 1:	I2C Device Size */
+#define I2C_025K_DEV	(0<<1)		/*		0:   256 Bytes or smaller */
+#define I2C_05K_DEV		(1<<1)		/*		1:   512 Bytes */
+#define I2C_1K_DEV		(2<<1)		/*		2:  1024 Bytes */
+#define I2C_2K_DEV		(3<<1)		/*		3:  2048 Bytes */
+#define I2C_4K_DEV		(4<<1)		/*		4:  4096 Bytes */
+#define I2C_8K_DEV		(5<<1)		/*		5:  8192 Bytes */
+#define I2C_16K_DEV		(6<<1)		/*		6: 16384 Bytes */
+#define I2C_32K_DEV		(7<<1)		/*		7: 32768 Bytes */
+#define I2C_STOP		BIT_0		/* Interrupt I2C transfer */
+
+/*	B2_I2C_IRQ		32 bit	I2C HW IRQ Register */
+								/* Bit 31.. 1	reserved */
+#define I2C_CLR_IRQ		BIT_0	/* Clear I2C IRQ */
+
+/*	B2_I2C_SW		32 bit (8 bit access)	I2C SW Port Register */
+								/* Bit  7.. 3:	reserved */
+#define I2C_DATA_DIR	BIT_2S		/* direction of I2C_DATA */
+#define I2C_DATA		BIT_1S		/* I2C Data Port */
+#define I2C_CLK			BIT_0S		/* I2C Clock Port */
+
+/* I2C Address */
+#define I2C_SENS_ADDR	LM80_ADDR	/* I2C Sensor Address (Volt and Temp) */
+
+
+/*	B2_BSC_CTRL		 8 bit	Blink Source Counter Control */
+							/* Bit  7.. 2:	reserved */
+#define BSC_START	BIT_1S		/* Start Blink Source Counter */
+#define BSC_STOP	BIT_0S		/* Stop  Blink Source Counter */
+
+/*	B2_BSC_STAT		 8 bit	Blink Source Counter Status */
+							/* Bit  7.. 1:	reserved */
+#define BSC_SRC		BIT_0S		/* Blink Source, 0=Off / 1=On */
+
+/*	B2_BSC_TST		16 bit	Blink Source Counter Test Reg */
+#define BSC_T_ON	BIT_2S		/* Test mode on */
+#define BSC_T_OFF	BIT_1S		/* Test mode off */
+#define BSC_T_STEP	BIT_0S		/* Test step */
+
+/*	Y2_PEX_PHY_ADDR/DATA		PEX PHY address and data reg  (Yukon-2 only) */
+#define PEX_RD_ACCESS	BIT_31	/* Access Mode Read = 1, Write = 0 */
+#define PEX_DB_ACCESS	BIT_30	/* Access to debug register */
+
+
+/*	B3_RAM_ADDR		32 bit	RAM Address, to read or write */
+					/* Bit 31..19:	reserved */
+#define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */
+
+/* RAM Interface Registers */
+/*	B3_RI_CTRL		16 bit	RAM Interface Control Register */
+								/* Bit 15..10:	reserved */
+#define RI_CLR_RD_PERR	BIT_9S	/* Clear IRQ RAM Read  Parity Err */
+#define RI_CLR_WR_PERR	BIT_8S	/* Clear IRQ RAM Write Parity Err */
+								/* Bit	7.. 2:	reserved */
+#define RI_RST_CLR		BIT_1S	/* Clear RAM Interface Reset */
+#define RI_RST_SET		BIT_0S	/* Set   RAM Interface Reset */
+
+/*	B3_RI_TEST		 8 bit	RAM Iface Test Register */
+								/* Bit 15.. 4:	reserved */
+#define RI_T_EV			BIT_3S	/* Timeout Event occurred */
+#define RI_T_ON			BIT_2S	/* Timeout Timer Test On */
+#define RI_T_OFF		BIT_1S	/* Timeout Timer Test Off */
+#define RI_T_STEP		BIT_0S	/* Timeout Timer Step */
+
+/* MAC Arbiter Registers */
+/*	B3_MA_TO_CTRL	16 bit	MAC Arbiter Timeout Ctrl Reg */
+								/* Bit 15.. 4:	reserved */
+#define MA_FOE_ON		BIT_3S	/* XMAC Fast Output Enable ON */
+#define MA_FOE_OFF		BIT_2S	/* XMAC Fast Output Enable OFF */
+#define MA_RST_CLR		BIT_1S	/* Clear MAC Arbiter Reset */
+#define MA_RST_SET		BIT_0S	/* Set   MAC Arbiter Reset */
+
+/*	B3_MA_RC_CTRL	16 bit	MAC Arbiter Recovery Ctrl Reg */
+								/* Bit 15.. 8:	reserved */
+#define MA_ENA_REC_TX2	BIT_7S	/* Enable  Recovery Timer TX2 */
+#define MA_DIS_REC_TX2	BIT_6S	/* Disable Recovery Timer TX2 */
+#define MA_ENA_REC_TX1	BIT_5S	/* Enable  Recovery Timer TX1 */
+#define MA_DIS_REC_TX1	BIT_4S	/* Disable Recovery Timer TX1 */
+#define MA_ENA_REC_RX2	BIT_3S	/* Enable  Recovery Timer RX2 */
+#define MA_DIS_REC_RX2	BIT_2S	/* Disable Recovery Timer RX2 */
+#define MA_ENA_REC_RX1	BIT_1S	/* Enable  Recovery Timer RX1 */
+#define MA_DIS_REC_RX1	BIT_0S	/* Disable Recovery Timer RX1 */
+
+/* Packet Arbiter Registers */
+/*	B3_PA_CTRL		16 bit	Packet Arbiter Ctrl Register */
+								/* Bit 15..14:	reserved */
+#define PA_CLR_TO_TX2	BIT_13S	/* Clear IRQ Packet Timeout TX2 */
+#define PA_CLR_TO_TX1	BIT_12S	/* Clear IRQ Packet Timeout TX1 */
+#define PA_CLR_TO_RX2	BIT_11S	/* Clear IRQ Packet Timeout RX2 */
+#define PA_CLR_TO_RX1	BIT_10S	/* Clear IRQ Packet Timeout RX1 */
+#define PA_ENA_TO_TX2	BIT_9S	/* Enable  Timeout Timer TX2 */
+#define PA_DIS_TO_TX2	BIT_8S	/* Disable Timeout Timer TX2 */
+#define PA_ENA_TO_TX1	BIT_7S	/* Enable  Timeout Timer TX1 */
+#define PA_DIS_TO_TX1	BIT_6S	/* Disable Timeout Timer TX1 */
+#define PA_ENA_TO_RX2	BIT_5S	/* Enable  Timeout Timer RX2 */
+#define PA_DIS_TO_RX2	BIT_4S	/* Disable Timeout Timer RX2 */
+#define PA_ENA_TO_RX1	BIT_3S	/* Enable  Timeout Timer RX1 */
+#define PA_DIS_TO_RX1	BIT_2S	/* Disable Timeout Timer RX1 */
+#define PA_RST_CLR		BIT_1S	/* Clear MAC Arbiter Reset */
+#define PA_RST_SET		BIT_0S	/* Set   MAC Arbiter Reset */
+
+#define PA_ENA_TO_ALL	(PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
+						 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
+
+/* Rx/Tx Path related Arbiter Test Registers */
+/*	B3_MA_TO_TEST	16 bit	MAC Arbiter Timeout Test Reg */
+/*	B3_MA_RC_TEST	16 bit	MAC Arbiter Recovery Test Reg */
+/*	B3_PA_TEST		16 bit	Packet Arbiter Test Register */
+/*			Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
+#define TX2_T_EV	BIT_15S		/* TX2 Timeout/Recv Event occurred */
+#define TX2_T_ON	BIT_14S		/* TX2 Timeout/Recv Timer Test On */
+#define TX2_T_OFF	BIT_13S		/* TX2 Timeout/Recv Timer Tst Off */
+#define TX2_T_STEP	BIT_12S		/* TX2 Timeout/Recv Timer Step */
+#define TX1_T_EV	BIT_11S		/* TX1 Timeout/Recv Event occurred */
+#define TX1_T_ON	BIT_10S		/* TX1 Timeout/Recv Timer Test On */
+#define TX1_T_OFF	BIT_9S		/* TX1 Timeout/Recv Timer Tst Off */
+#define TX1_T_STEP	BIT_8S		/* TX1 Timeout/Recv Timer Step */
+#define RX2_T_EV	BIT_7S		/* RX2 Timeout/Recv Event occurred */
+#define RX2_T_ON	BIT_6S		/* RX2 Timeout/Recv Timer Test On */
+#define RX2_T_OFF	BIT_5S		/* RX2 Timeout/Recv Timer Tst Off */
+#define RX2_T_STEP	BIT_4S		/* RX2 Timeout/Recv Timer Step */
+#define RX1_T_EV	BIT_3S		/* RX1 Timeout/Recv Event occurred */
+#define RX1_T_ON	BIT_2S		/* RX1 Timeout/Recv Timer Test On */
+#define RX1_T_OFF	BIT_1S		/* RX1 Timeout/Recv Timer Tst Off */
+#define RX1_T_STEP	BIT_0S		/* RX1 Timeout/Recv Timer Step */
+
+
+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+/*	TXA_ITI_INI		32 bit	Tx Arb Interval Timer Init Val */
+/*	TXA_ITI_VAL		32 bit	Tx Arb Interval Timer Value */
+/*	TXA_LIM_INI		32 bit	Tx Arb Limit Counter Init Val */
+/*	TXA_LIM_VAL		32 bit	Tx Arb Limit Counter Value */
+								/* Bit 31..24:	reserved */
+#define TXA_MAX_VAL	0x00ffffffUL/* Bit 23.. 0:	Max TXA Timer/Cnt Val */
+
+/*	TXA_CTRL		 8 bit	Tx Arbiter Control Register */
+#define TXA_ENA_FSYNC	BIT_7S	/* Enable  force of sync Tx queue */
+#define TXA_DIS_FSYNC	BIT_6S	/* Disable force of sync Tx queue */
+#define TXA_ENA_ALLOC	BIT_5S	/* Enable  alloc of free bandwidth */
+#define TXA_DIS_ALLOC	BIT_4S	/* Disable alloc of free bandwidth */
+#define TXA_START_RC	BIT_3S	/* Start sync Rate Control */
+#define TXA_STOP_RC		BIT_2S	/* Stop  sync Rate Control */
+#define TXA_ENA_ARB		BIT_1S	/* Enable  Tx Arbiter */
+#define TXA_DIS_ARB		BIT_0S	/* Disable Tx Arbiter */
+
+/*	TXA_TEST		 8 bit	Tx Arbiter Test Register */
+								/* Bit 7.. 6:	reserved */
+#define TXA_INT_T_ON	BIT_5S	/* Tx Arb Interval Timer Test On */
+#define TXA_INT_T_OFF	BIT_4S	/* Tx Arb Interval Timer Test Off */
+#define TXA_INT_T_STEP	BIT_3S	/* Tx Arb Interval Timer Step */
+#define TXA_LIM_T_ON	BIT_2S	/* Tx Arb Limit Timer Test On */
+#define TXA_LIM_T_OFF	BIT_1S	/* Tx Arb Limit Timer Test Off */
+#define TXA_LIM_T_STEP	BIT_0S	/* Tx Arb Limit Timer Step */
+
+/*	TXA_STAT		 8 bit	Tx Arbiter Status Register */
+								/* Bit 7.. 1:	reserved */
+#define TXA_PRIO_XS		BIT_0S	/* sync queue has prio to send */
+
+/*	Q_BC			32 bit	Current Byte Counter */
+								/* Bit 31..16:	reserved */
+#define BC_MAX			0xffff	/* Bit 15.. 0:	Byte counter */
+
+/* BMU Control / Status Registers (Yukon and Genesis) */
+/*	B0_R1_CSR		32 bit	BMU Ctrl/Stat Rx Queue 1 */
+/*	B0_R2_CSR		32 bit	BMU Ctrl/Stat Rx Queue 2 */
+/*	B0_XA1_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
+/*	B0_XS1_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
+/*	B0_XA2_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
+/*	B0_XS2_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
+/*	Q_CSR			32 bit	BMU Control/Status Register */
+								/* Bit 31..25:	reserved */
+#define CSR_SV_IDLE		BIT_24		/* BMU SM Idle */
+								/* Bit 23..22:	reserved */
+#define CSR_DESC_CLR	BIT_21		/* Clear Reset for Descr */
+#define CSR_DESC_SET	BIT_20		/* Set   Reset for Descr */
+#define CSR_FIFO_CLR	BIT_19		/* Clear Reset for FIFO */
+#define CSR_FIFO_SET	BIT_18		/* Set   Reset for FIFO */
+#define CSR_HPI_RUN		BIT_17		/* Release HPI SM */
+#define CSR_HPI_RST		BIT_16		/* Reset   HPI SM to Idle */
+#define CSR_SV_RUN		BIT_15		/* Release Supervisor SM */
+#define CSR_SV_RST		BIT_14		/* Reset   Supervisor SM */
+#define CSR_DREAD_RUN	BIT_13		/* Release Descr Read SM */
+#define CSR_DREAD_RST	BIT_12		/* Reset   Descr Read SM */
+#define CSR_DWRITE_RUN	BIT_11		/* Release Descr Write SM */
+#define CSR_DWRITE_RST	BIT_10		/* Reset   Descr Write SM */
+#define CSR_TRANS_RUN	BIT_9		/* Release Transfer SM */
+#define CSR_TRANS_RST	BIT_8		/* Reset   Transfer SM */
+#define CSR_ENA_POL		BIT_7		/* Enable  Descr Polling */
+#define CSR_DIS_POL		BIT_6		/* Disable Descr Polling */
+#define CSR_STOP		BIT_5		/* Stop  Rx/Tx Queue */
+#define CSR_START		BIT_4		/* Start Rx/Tx Queue */
+#define CSR_IRQ_CL_P	BIT_3		/* (Rx)	Clear Parity IRQ */
+#define CSR_IRQ_CL_B	BIT_2		/* Clear EOB IRQ */
+#define CSR_IRQ_CL_F	BIT_1		/* Clear EOF IRQ */
+#define CSR_IRQ_CL_C	BIT_0		/* Clear ERR IRQ */
+
+#define CSR_SET_RESET	(CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
+						 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
+						 CSR_TRANS_RST)
+#define CSR_CLR_RESET	(CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
+						 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
+						 CSR_TRANS_RUN)
+
+/* Rx BMU Control / Status Registers (Yukon-2) */
+#define BMU_IDLE			BIT_31	/* BMU Idle State */
+#define BMU_RX_TCP_PKT		BIT_30	/* Rx TCP Packet (when RSS Hash enabled) */
+#define BMU_RX_IP_PKT		BIT_29	/* Rx IP  Packet (when RSS Hash enabled) */
+								/* Bit 28..16:	reserved */
+#define BMU_ENA_RX_RSS_HASH	BIT_15	/* Enable  Rx RSS Hash */
+#define BMU_DIS_RX_RSS_HASH	BIT_14	/* Disable Rx RSS Hash */
+#define BMU_ENA_RX_CHKSUM	BIT_13	/* Enable  Rx TCP/IP Checksum Check */
+#define BMU_DIS_RX_CHKSUM	BIT_12	/* Disable Rx TCP/IP Checksum Check */
+#define BMU_CLR_IRQ_PAR		BIT_11	/* Clear IRQ on Parity errors (Rx) */
+#define BMU_CLR_IRQ_TCP		BIT_11	/* Clear IRQ on TCP segmen. error (Tx) */
+#define BMU_CLR_IRQ_CHK		BIT_10	/* Clear IRQ Check */
+#define BMU_STOP			BIT_9	/* Stop  Rx/Tx Queue */
+#define BMU_START			BIT_8	/* Start Rx/Tx Queue */
+#define BMU_FIFO_OP_ON		BIT_7	/* FIFO Operational On */
+#define BMU_FIFO_OP_OFF		BIT_6	/* FIFO Operational Off */
+#define BMU_FIFO_ENA		BIT_5	/* Enable FIFO */
+#define BMU_FIFO_RST		BIT_4	/* Reset  FIFO */
+#define BMU_OP_ON			BIT_3	/* BMU Operational On */
+#define BMU_OP_OFF			BIT_2	/* BMU Operational Off */
+#define BMU_RST_CLR			BIT_1	/* Clear BMU Reset (Enable) */
+#define BMU_RST_SET			BIT_0	/* Set   BMU Reset */
+
+#define BMU_CLR_RESET		(BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
+#define BMU_OPER_INIT		(BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
+							BMU_FIFO_ENA | BMU_OP_ON)
+
+/* Tx BMU Control / Status Registers (Yukon-2) */
+								/* Bit 31: same as for Rx */
+								/* Bit 30..14:	reserved */
+#define BMU_TX_IPIDINCR_ON	BIT_13	/* Enable  IP ID Increment */
+#define BMU_TX_IPIDINCR_OFF	BIT_12	/* Disable IP ID Increment */
+#define BMU_TX_CLR_IRQ_TCP	BIT_11	/* Clear IRQ on TCP segm. length mism. */
+								/* Bit 10..0: same as for Rx */
+
+/*	Q_F				32 bit	Flag Register */
+									/* Bit 31..28:	reserved */
+#define F_ALM_FULL		BIT_27		/* Rx FIFO: almost full */
+#define F_EMPTY			BIT_27		/* Tx FIFO: empty flag */
+#define F_FIFO_EOF		BIT_26		/* Tag (EOF Flag) bit in FIFO */
+#define F_WM_REACHED	BIT_25		/* Watermark reached */
+#define F_M_RX_RAM_DIS	BIT_24		/* MAC Rx RAM Read Port disable */
+#define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
+									/* Bit 15..11:	reserved */
+#define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */
+
+/*	Q_T1			32 bit	Test Register 1 */
+/*		Holds four State Machine control Bytes */
+#define SM_CTRL_SV_MSK	(0xffL<<24)	/* Bit 31..24:	Control Supervisor SM */
+#define SM_CTRL_RD_MSK	(0xffL<<16)	/* Bit 23..16:	Control Read Desc SM */
+#define SM_CTRL_WR_MSK	(0xffL<<8)	/* Bit 15.. 8:	Control Write Desc SM */
+#define SM_CTRL_TR_MSK	0xffL		/* Bit	7.. 0:	Control Transfer SM */
+
+/*	Q_T1_TR			 8 bit	Test Register 1 Transfer SM */
+/*	Q_T1_WR			 8 bit	Test Register 1 Write Descriptor SM */
+/*	Q_T1_RD			 8 bit	Test Register 1 Read Descriptor SM */
+/*	Q_T1_SV			 8 bit	Test Register 1 Supervisor SM */
+
+/* The control status byte of each machine looks like ... */
+#define SM_STATE		0xf0	/* Bit 7.. 4:	State which shall be loaded */
+#define SM_LOAD			BIT_3S	/* Load the SM with SM_STATE */
+#define SM_TEST_ON		BIT_2S	/* Switch on SM Test Mode */
+#define SM_TEST_OFF		BIT_1S	/* Go off the Test Mode */
+#define SM_STEP			BIT_0S	/* Step the State Machine */
+/* The encoding of the states is not supported by the Diagnostics Tool */
+
+/*	Q_T2			32 bit	Test Register 2 */
+								/* Bit 31.. 8:	reserved */
+#define T2_AC_T_ON		BIT_7	/* Address Counter Test Mode on */
+#define T2_AC_T_OFF		BIT_6	/* Address Counter Test Mode off */
+#define T2_BC_T_ON		BIT_5	/* Byte Counter Test Mode on */
+#define T2_BC_T_OFF		BIT_4	/* Byte Counter Test Mode off */
+#define T2_STEP04		BIT_3	/* Inc AC/Dec BC by 4 */
+#define T2_STEP03		BIT_2	/* Inc AC/Dec BC by 3 */
+#define T2_STEP02		BIT_1	/* Inc AC/Dec BC by 2 */
+#define T2_STEP01		BIT_0	/* Inc AC/Dec BC by 1 */
+
+/*	Q_T3			32 bit	Test Register 3 */
+								/* Bit 31.. 7:	reserved */
+#define T3_MUX_MSK		(7<<4)	/* Bit  6.. 4:	Mux Position */
+								/* Bit  3:	reserved */
+#define T3_VRAM_MSK		7		/* Bit  2.. 0:	Virtual RAM Buffer Address */
+
+/* PREF_UNIT_CTRL_REG	32 bit	Prefetch Control register */
+#define PREF_UNIT_OP_ON		BIT_3	/* prefetch unit operational */
+#define PREF_UNIT_OP_OFF	BIT_2	/* prefetch unit not operational */
+#define PREF_UNIT_RST_CLR	BIT_1	/* Clear Prefetch Unit Reset */
+#define PREF_UNIT_RST_SET	BIT_0	/* Set   Prefetch Unit Reset */
+
+/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
+/*	RB_START		32 bit	RAM Buffer Start Address */
+/*	RB_END			32 bit	RAM Buffer End Address */
+/*	RB_WP			32 bit	RAM Buffer Write Pointer */
+/*	RB_RP			32 bit	RAM Buffer Read Pointer */
+/*	RB_RX_UTPP		32 bit	Rx Upper Threshold, Pause Pack */
+/*	RB_RX_LTPP		32 bit	Rx Lower Threshold, Pause Pack */
+/*	RB_RX_UTHP		32 bit	Rx Upper Threshold, High Prio */
+/*	RB_RX_LTHP		32 bit	Rx Lower Threshold, High Prio */
+/*	RB_PC			32 bit	RAM Buffer Packet Counter */
+/*	RB_LEV			32 bit	RAM Buffer Level Register */
+				/* Bit 31..19:	reserved */
+#define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */
+
+/*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
+							/* Bit 7.. 4:	reserved */
+#define RB_PC_DEC		BIT_3S	/* Packet Counter Decrement */
+#define RB_PC_T_ON		BIT_2S	/* Packet Counter Test On */
+#define RB_PC_T_OFF		BIT_1S	/* Packet Counter Test Off */
+#define RB_PC_INC		BIT_0S	/* Packet Counter Increment */
+
+/*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
+							/* Bit 7:	reserved */
+#define RB_WP_T_ON		BIT_6S	/* Write Pointer Test On */
+#define RB_WP_T_OFF		BIT_5S	/* Write Pointer Test Off */
+#define RB_WP_INC		BIT_4S	/* Write Pointer Increment */
+								/* Bit 3:	reserved */
+#define RB_RP_T_ON		BIT_2S	/* Read Pointer Test On */
+#define RB_RP_T_OFF		BIT_1S	/* Read Pointer Test Off */
+#define RB_RP_INC		BIT_0S	/* Read Pointer Increment */
+
+/*	RB_CTRL			 8 bit	RAM Buffer Control Register */
+							/* Bit 7.. 6:	reserved */
+#define RB_ENA_STFWD	BIT_5S	/* Enable  Store & Forward */
+#define RB_DIS_STFWD	BIT_4S	/* Disable Store & Forward */
+#define RB_ENA_OP_MD	BIT_3S	/* Enable  Operation Mode */
+#define RB_DIS_OP_MD	BIT_2S	/* Disable Operation Mode */
+#define RB_RST_CLR		BIT_1S	/* Clear RAM Buf STM Reset */
+#define RB_RST_SET		BIT_0S	/* Set   RAM Buf STM Reset */
+
+/* Yukon-2 */
+							/* Bit 31..20:	reserved */
+#define RB_CNT_DOWN		BIT_19	/* Packet Counter Decrement */
+#define RB_CNT_TST_ON	BIT_18	/* Packet Counter Test On */
+#define RB_CNT_TST_OFF	BIT_17	/* Packet Counter Test Off */
+#define RB_CNT_UP		BIT_16	/* Packet Counter Increment */
+							/* Bit 15:	reserved */
+#define RB_WP_TST_ON	BIT_14	/* Write Pointer Test On */
+#define RB_WP_TST_OFF	BIT_13	/* Write Pointer Test Off */
+#define RB_WP_UP		BIT_12	/* Write Pointer Increment  */
+							/* Bit 11:	reserved */
+#define RB_RP_TST_ON	BIT_10	/* Read Pointer Test On */
+#define RB_RP_TST_OFF	BIT_9	/* Read Pointer Test Off */
+#define RB_RP_UP		BIT_8	/* Read Pointer Increment */
+
+
+/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
+
+/*	RX_MFF_EA		32 bit	Receive MAC FIFO End Address */
+/*	RX_MFF_WP		32 bit	Receive MAC FIFO Write Pointer */
+/*	RX_MFF_RP		32 bit	Receive MAC FIFO Read Pointer */
+/*	RX_MFF_PC		32 bit	Receive MAC FIFO Packet Counter */
+/*	RX_MFF_LEV		32 bit	Receive MAC FIFO Level */
+/*	TX_MFF_EA		32 bit	Transmit MAC FIFO End Address */
+/*	TX_MFF_WP		32 bit	Transmit MAC FIFO Write Pointer */
+/*	TX_MFF_WSP		32 bit	Transmit MAC FIFO WR Shadow Pointer */
+/*	TX_MFF_RP		32 bit	Transmit MAC FIFO Read Pointer */
+/*	TX_MFF_PC		32 bit	Transmit MAC FIFO Packet Cnt */
+/*	TX_MFF_LEV		32 bit	Transmit MAC FIFO Level */
+								/* Bit 31.. 6:	reserved */
+#define MFF_MSK			0x007fL	/* Bit	5.. 0:	MAC FIFO Address/Ptr Bits */
+
+/*	RX_MFF_CTRL1	16 bit	Receive MAC FIFO Control Reg 1 */
+								/* Bit 15..14:	reserved */
+#define MFF_ENA_RDY_PAT	BIT_13S		/* Enable  Ready Patch */
+#define MFF_DIS_RDY_PAT	BIT_12S		/* Disable Ready Patch */
+#define MFF_ENA_TIM_PAT	BIT_11S		/* Enable  Timing Patch */
+#define MFF_DIS_TIM_PAT	BIT_10S		/* Disable Timing Patch */
+#define MFF_ENA_ALM_FUL	BIT_9S		/* Enable  AlmostFull Sign */
+#define MFF_DIS_ALM_FUL	BIT_8S		/* Disable AlmostFull Sign */
+#define MFF_ENA_PAUSE	BIT_7S		/* Enable  Pause Signaling */
+#define MFF_DIS_PAUSE	BIT_6S		/* Disable Pause Signaling */
+#define MFF_ENA_FLUSH	BIT_5S		/* Enable  Frame Flushing */
+#define MFF_DIS_FLUSH	BIT_4S		/* Disable Frame Flushing */
+#define MFF_ENA_TIST	BIT_3S		/* Enable  Time Stamp Gener */
+#define MFF_DIS_TIST	BIT_2S		/* Disable Time Stamp Gener */
+#define MFF_CLR_INTIST	BIT_1S		/* Clear IRQ No Time Stamp */
+#define MFF_CLR_INSTAT	BIT_0S		/* Clear IRQ No Status */
+
+#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
+
+/*	TX_MFF_CTRL1	16 bit	Transmit MAC FIFO Control Reg 1 */
+#define MFF_CLR_PERR	BIT_15S		/* Clear Parity Error IRQ */
+								/* Bit 14:	reserved */
+#define MFF_ENA_PKT_REC	BIT_13S		/* Enable  Packet Recovery */
+#define MFF_DIS_PKT_REC BIT_12S		/* Disable Packet Recovery */
+/*	MFF_ENA_TIM_PAT	 (see RX_MFF_CTRL1) Bit 11:	Enable  Timing Patch */
+/*	MFF_DIS_TIM_PAT	 (see RX_MFF_CTRL1) Bit 10:	Disable Timing Patch */
+/*	MFF_ENA_ALM_FUL	 (see RX_MFF_CTRL1) Bit	 9:	Enable  Almost Full Sign */
+/*	MFF_DIS_ALM_FUL	 (see RX_MFF_CTRL1) Bit	 8:	Disable Almost Full Sign */
+#define MFF_ENA_W4E		BIT_7S		/* Enable  Wait for Empty */
+#define MFF_DIS_W4E		BIT_6S		/* Disable Wait for Empty */
+/*	MFF_ENA_FLUSH	 (see RX_MFF_CTRL1) Bit	 5:	Enable  Frame Flushing */
+/*	MFF_DIS_FLUSH	 (see RX_MFF_CTRL1) Bit	 4:	Disable Frame Flushing */
+#define MFF_ENA_LOOPB	BIT_3S		/* Enable  Loopback */
+#define MFF_DIS_LOOPB	BIT_2S		/* Disable Loopback */
+#define MFF_CLR_MAC_RST	BIT_1S		/* Clear XMAC Reset */
+#define MFF_SET_MAC_RST	BIT_0S		/* Set   XMAC Reset */
+
+#define MFF_TX_CTRL_DEF	(MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
+
+/*	RX_MFF_TST2		 8 bit	Receive MAC FIFO Test Register 2 */
+/*	TX_MFF_TST2		 8 bit	Transmit MAC FIFO Test Register 2 */
+								/* Bit 7:	reserved */
+#define MFF_WSP_T_ON	BIT_6S	/* Tx: Write Shadow Pointer Test On */
+#define MFF_WSP_T_OFF	BIT_5S	/* Tx: Write Shadow Pointer Test Off */
+#define MFF_WSP_INC		BIT_4S	/* Tx: Write Shadow Pointer Increment */
+#define MFF_PC_DEC		BIT_3S	/* Packet Counter Decrement */
+#define MFF_PC_T_ON		BIT_2S	/* Packet Counter Test On */
+#define MFF_PC_T_OFF	BIT_1S	/* Packet Counter Test Off */
+#define MFF_PC_INC		BIT_0S	/* Packet Counter Increment */
+
+/*	RX_MFF_TST1		 8 bit	Receive MAC FIFO Test Register 1 */
+/*	TX_MFF_TST1		 8 bit	Transmit MAC FIFO Test Register 1 */
+					/* Bit 7:	reserved */
+#define MFF_WP_T_ON		BIT_6S	/* Write Pointer Test On */
+#define MFF_WP_T_OFF	BIT_5S	/* Write Pointer Test Off */
+#define MFF_WP_INC		BIT_4S	/* Write Pointer Increment */
+							/* Bit 3:	reserved */
+#define MFF_RP_T_ON		BIT_2S	/* Read Pointer Test On */
+#define MFF_RP_T_OFF	BIT_1S	/* Read Pointer Test Off */
+#define MFF_RP_DEC		BIT_0S	/* Read Pointer Decrement */
+
+/*	RX_MFF_CTRL2	 8 bit	Receive MAC FIFO Control Reg 2 */
+/*	TX_MFF_CTRL2	 8 bit	Transmit MAC FIFO Control Reg 2 */
+								/* Bit 7..4:	reserved */
+#define MFF_ENA_OP_MD	BIT_3S	/* Enable  Operation Mode */
+#define MFF_DIS_OP_MD	BIT_2S	/* Disable Operation Mode */
+#define MFF_RST_CLR		BIT_1S	/* Clear MAC FIFO Reset */
+#define MFF_RST_SET		BIT_0S	/* Set   MAC FIFO Reset */
+
+
+/*	Link LED Counter Registers (GENESIS only) */
+
+/*	RX_LED_CTRL		 8 bit	Receive LED Cnt Control Reg */
+/*	TX_LED_CTRL		 8 bit	Transmit LED Cnt Control Reg */
+							/* Bit 7.. 3:	reserved */
+#define LED_START		BIT_2S	/* Start Counter */
+#define LED_STOP		BIT_1S	/* Stop Counter */
+#define LED_STATE		BIT_0S	/* Rx/Tx: LED State, 1=LED On */
+
+/*	LNK_SYNC_CTRL	 8 bit	Link Sync Cnt Control Register */
+							/* Bit 7.. 3:	reserved */
+#define LNK_START		BIT_2S	/* Start Counter */
+#define LNK_STOP		BIT_1S	/* Stop Counter */
+#define LNK_CLR_IRQ		BIT_0S	/* Clear Link IRQ */
+
+/*	RX_LED_TST		 8 bit	Receive LED Cnt Test Register */
+/*	TX_LED_TST		 8 bit	Transmit LED Cnt Test Register */
+/*	LNK_SYNC_TST	 8 bit	Link Sync Cnt Test Register */
+							/* Bit 7.. 3:	reserved */
+#define LED_T_ON		BIT_2S	/* LED Counter Test mode On */
+#define LED_T_OFF		BIT_1S	/* LED Counter Test mode Off */
+#define LED_T_STEP		BIT_0S	/* LED Counter Step */
+
+/*	LNK_LED_REG		 8 bit	Link LED Register */
+							/* Bit 7.. 6:	reserved */
+#define LED_BLK_ON		BIT_5S	/* Link LED Blinking On */
+#define LED_BLK_OFF		BIT_4S	/* Link LED Blinking Off */
+#define LED_SYNC_ON		BIT_3S	/* Use Sync Wire to switch LED */
+#define LED_SYNC_OFF	BIT_2S	/* Disable Sync Wire Input */
+#define LED_ON			BIT_1S	/* Switch LED On */
+#define LED_OFF			BIT_0S	/* Switch LED Off */
+
+/*	Receive and Transmit GMAC FIFO Registers (YUKON only) */
+
+/*	TX_GMF_EA		32 bit	Rx GMAC FIFO End Address */
+/*	Yukon-FE+ specific */
+#define TX_DYN_WM_ENA	(BIT_0S | BIT_1S)
+
+/*	RX_GMF_AF_THR	32 bit	Rx GMAC FIFO Almost Full Thresh. */
+/*	RX_GMF_WP		32 bit	Rx GMAC FIFO Write Pointer */
+/*	RX_GMF_WLEV		32 bit	Rx GMAC FIFO Write Level */
+/*	RX_GMF_RP		32 bit	Rx GMAC FIFO Read Pointer */
+/*	RX_GMF_RLEV		32 bit	Rx GMAC FIFO Read Level */
+/*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
+/*	TX_GMF_AE_THR	32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
+/*	TX_GMF_WP		32 bit	Tx GMAC FIFO Write Pointer */
+/*	TX_GMF_WSP		32 bit	Tx GMAC FIFO Write Shadow Pointer */
+/*	TX_GMF_WLEV		32 bit	Tx GMAC FIFO Write Level */
+/*	TX_GMF_RP		32 bit	Tx GMAC FIFO Read Pointer */
+/*	TX_GMF_RSTP		32 bit	Tx GMAC FIFO Restart Pointer */
+/*	TX_GMF_RLEV		32 bit	Tx GMAC FIFO Read Level */
+
+/*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
+						/* Bit 31..28 reserved */
+#define RX_TRUNC_ON		BIT_27	/* Enable  Packet Truncation */
+#define RX_TRUNC_OFF	BIT_26	/* Disable Packet Truncation */
+#define RX_VLAN_STRIP_ON	BIT_25	/* Enable  VLAN Stripping */
+#define RX_VLAN_STRIP_OFF	BIT_24	/* Disable VLAN Stripping */
+						/* Bit 23..15 reserved */
+#define GMF_WP_TST_ON	BIT_14	/* Write Pointer Test On */
+#define GMF_WP_TST_OFF	BIT_13	/* Write Pointer Test Off */
+#define GMF_WP_STEP		BIT_12	/* Write Pointer Step/Increment */
+						/* Bit 11:	reserved */
+#define GMF_RP_TST_ON	BIT_10	/* Read Pointer Test On */
+#define GMF_RP_TST_OFF	BIT_9	/* Read Pointer Test Off */
+#define GMF_RP_STEP		BIT_8	/* Read Pointer Step/Increment */
+#define GMF_RX_F_FL_ON	BIT_7	/* Rx FIFO Flush Mode On */
+#define GMF_RX_F_FL_OFF	BIT_6	/* Rx FIFO Flush Mode Off */
+#define GMF_CLI_RX_FO	BIT_5	/* Clear IRQ Rx FIFO Overrun */
+#define GMF_CLI_RX_FC	BIT_4	/* Clear IRQ Rx Frame Complete */
+#define GMF_OPER_ON		BIT_3	/* Operational Mode On */
+#define GMF_OPER_OFF	BIT_2	/* Operational Mode Off */
+#define GMF_RST_CLR		BIT_1	/* Clear GMAC FIFO Reset */
+#define GMF_RST_SET		BIT_0	/* Set   GMAC FIFO Reset */
+
+/*	RX_GMF_FL_CTRL	16 bit	Rx GMAC FIFO Flush Control (Yukon-Supreme) */
+							/* Bit 15.. 10 reserved */
+#define RX_IPV6_SA_MOB_ENA	BIT_9S	/* IPv6 SA Mobility Support Enable */
+#define RX_IPV6_SA_MOB_DIS	BIT_8S	/* IPv6 SA Mobility Support Disable */
+#define RX_IPV6_DA_MOB_ENA	BIT_7S	/* IPv6 DA Mobility Support Enable */
+#define RX_IPV6_DA_MOB_DIS	BIT_6S	/* IPv6 DA Mobility Support Disable */
+#define RX_PTR_SYNCDLY_ENA	BIT_5S	/* Pointers Delay Synch Enable */
+#define RX_PTR_SYNCDLY_DIS	BIT_4S	/* Pointers Delay Synch Disable */
+#define RX_ASF_NEWFLAG_ENA	BIT_3S	/* RX ASF Flag New Logic Enable */
+#define RX_ASF_NEWFLAG_DIS	BIT_2S	/* RX ASF Flag New Logic Disable */
+#define RX_FLSH_MISSPKT_ENA	BIT_1S	/* RX Flush Miss-Packet Enable */
+#define RX_FLSH_MISSPKT_DIS	BIT_0S	/* RX Flush Miss-Packet Disable */
+
+/*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
+#define TX_STFW_DIS		BIT_31	/* Disable Store & Forward (Yukon-EC Ultra) */
+#define TX_STFW_ENA		BIT_30	/* Enable  Store & Forward (Yukon-EC Ultra) */
+						/* Bits 29..26: reserved */
+#define TX_VLAN_TAG_ON	BIT_25	/* Enable  VLAN tagging */
+#define TX_VLAN_TAG_OFF	BIT_24	/* Disable VLAN tagging */
+#define TX_PCI_JUM_ENA	BIT_23	/* Enable  PCI Jumbo Mode (Yukon-EC Ultra) */
+#define TX_PCI_JUM_DIS	BIT_22	/* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
+						/* Bits 21..19: reserved */
+#define GMF_WSP_TST_ON	BIT_18	/* Write Shadow Pointer Test On */
+#define GMF_WSP_TST_OFF	BIT_17	/* Write Shadow Pointer Test Off */
+#define GMF_WSP_STEP	BIT_16	/* Write Shadow Pointer Step/Increment */
+						/* Bits 15.. 8: same as for RX_GMF_CTRL_T */
+						/* Bit 7:	reserved */
+#define GMF_CLI_TX_FU	BIT_6	/* Clear IRQ Tx FIFO Underrun */
+#define GMF_CLI_TX_FC	BIT_5	/* Clear IRQ Tx Frame Complete */
+#define GMF_CLI_TX_PE	BIT_4	/* Clear IRQ Tx Parity Error */
+						/* Bits  3.. 0: same as for RX_GMF_CTRL_T */
+
+#define GMF_RX_CTRL_DEF		(GMF_OPER_ON | GMF_RX_F_FL_ON)
+#define GMF_TX_CTRL_DEF		GMF_OPER_ON
+
+#define RX_GMF_AF_THR_MIN	0x0c	/* Rx GMAC FIFO Almost Full Thresh. min. */
+#define RX_GMF_FL_THR_DEF	0x0a	/* Rx GMAC FIFO Flush Threshold default */
+
+/*	GMAC_TI_ST_CTRL	 8 bit	Time Stamp Timer Ctrl Reg (YUKON only) */
+							/* Bit 7.. 5:	reserved */
+#define GMT_ST_LE_ENA	BIT_4S	/* Enable  List Element Generation */
+#define GMT_ST_LE_DIS	BIT_3S	/* Disable List Element Generation */
+#define GMT_ST_START	BIT_2S	/* Start Time Stamp Timer */
+#define GMT_ST_STOP		BIT_1S	/* Stop  Time Stamp Timer */
+#define GMT_ST_CLR_IRQ	BIT_0S	/* Clear Time Stamp Timer IRQ */
+
+/*	POLL_CTRL		32 bit	Polling Unit control register (Yukon-2 only) */
+							/* Bit 31.. 6:	reserved */
+#define PC_CLR_IRQ_CHK	BIT_5	/* Clear IRQ Check */
+#define PC_POLL_RQ		BIT_4	/* Poll Request Start */
+#define PC_POLL_OP_ON	BIT_3	/* Operational Mode On */
+#define PC_POLL_OP_OFF	BIT_2	/* Operational Mode Off */
+#define PC_POLL_RST_CLR	BIT_1	/* Clear Polling Unit Reset (Enable) */
+#define PC_POLL_RST_SET	BIT_0	/* Set   Polling Unit Reset */
+
+
+/* The bit definition of the following registers is still missing! */
+/* B28_Y2_SMB_CONFIG		32 bit	ASF SMBus Config Register */
+/* B28_Y2_SMB_CSD_REG		32 bit	ASF SMB Control/Status/Data */
+/* B28_Y2_ASF_IRQ_V_BASE	32 bit	ASF IRQ Vector Base */
+
+/* B28_Y2_ASF_STAT_CMD		32 bit	ASF Status and Command Reg */
+/* This register is used by the host driver software */
+							/* Bit 31.. 5	reserved */
+#define Y2_ASF_OS_PRES	BIT_4S	/* ASF operation system present */
+#define Y2_ASF_RESET	BIT_3S	/* ASF system in reset state */
+#define Y2_ASF_RUNNING	BIT_2S	/* ASF system operational */
+#define Y2_ASF_CLR_HSTI	BIT_1S	/* Clear ASF IRQ */
+#define Y2_ASF_IRQ		BIT_0S	/* Issue an IRQ to ASF system */
+
+#define Y2_ASF_UC_STATE	(3<<2)	/* ASF uC State */
+#define Y2_ASF_CLK_HALT	0		/* ASF system clock stopped */
+
+/* B28_Y2_ASF_HOST_COM	32 bit	ASF Host Communication Reg */
+/* This register is used by the ASF firmware */
+							/* Bit 31.. 2	reserved */
+#define Y2_ASF_CLR_ASFI	BIT_1	/* Clear host IRQ */
+#define Y2_ASF_HOST_IRQ	BIT_0	/* Issue an IRQ to HOST system */
+
+
+/*	STAT_CTRL		32 bit	Status BMU control register (Yukon-2 only) */
+							/* Bit  7.. 5:	reserved */
+#define SC_STAT_CLR_IRQ	BIT_4	/* Status Burst IRQ clear */
+#define SC_STAT_OP_ON	BIT_3	/* Operational Mode On */
+#define SC_STAT_OP_OFF	BIT_2	/* Operational Mode Off */
+#define SC_STAT_RST_CLR	BIT_1	/* Clear Status Unit Reset (Enable) */
+#define SC_STAT_RST_SET	BIT_0	/* Set   Status Unit Reset */
+
+/*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
+						/* Bits 31.. 8:	reserved */
+#define GMC_H_BURST_ON	BIT_7	/* Half Duplex Burst Mode On */
+#define GMC_H_BURST_OFF	BIT_6	/* Half Duplex Burst Mode Off */
+#define GMC_F_LOOPB_ON	BIT_5	/* FIFO Loopback On */
+#define GMC_F_LOOPB_OFF	BIT_4	/* FIFO Loopback Off */
+#define GMC_PAUSE_ON	BIT_3	/* Pause On */
+#define GMC_PAUSE_OFF	BIT_2	/* Pause Off */
+#define GMC_RST_CLR		BIT_1	/* Clear GMAC Reset */
+#define GMC_RST_SET		BIT_0	/* Set   GMAC Reset */
+
+/*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */
+						/* Bits 31..29:	reserved */
+#define GPC_SEL_BDT		BIT_28	/* Select Bi-Dir. Transfer for MDC/MDIO */
+#define GPC_INT_POL		BIT_27	/* IRQ Polarity is Active Low */
+#define GPC_75_OHM		BIT_26	/* Use 75 Ohm Termination instead of 50 */
+#define GPC_DIS_FC		BIT_25	/* Disable Automatic Fiber/Copper Detection */
+#define GPC_DIS_SLEEP	BIT_24	/* Disable Energy Detect */
+#define GPC_HWCFG_M_3	BIT_23	/* HWCFG_MODE[3] */
+#define GPC_HWCFG_M_2	BIT_22	/* HWCFG_MODE[2] */
+#define GPC_HWCFG_M_1	BIT_21	/* HWCFG_MODE[1] */
+#define GPC_HWCFG_M_0	BIT_20	/* HWCFG_MODE[0] */
+#define GPC_ANEG_0		BIT_19	/* ANEG[0] */
+#define GPC_ENA_XC		BIT_18	/* Enable MDI crossover */
+#define GPC_DIS_125		BIT_17	/* Disable 125 MHz clock */
+#define GPC_ANEG_3		BIT_16	/* ANEG[3] */
+#define GPC_ANEG_2		BIT_15	/* ANEG[2] */
+#define GPC_ANEG_1		BIT_14	/* ANEG[1] */
+#define GPC_ENA_PAUSE	BIT_13	/* Enable Pause (SYM_OR_REM) */
+#define GPC_PHYADDR_4	BIT_12	/* Bit 4 of PHY Addr */
+#define GPC_PHYADDR_3	BIT_11	/* Bit 3 of PHY Addr */
+#define GPC_PHYADDR_2	BIT_10	/* Bit 2 of PHY Addr */
+#define GPC_PHYADDR_1	BIT_9	/* Bit 1 of PHY Addr */
+#define GPC_PHYADDR_0	BIT_8	/* Bit 0 of PHY Addr */
+						/* Bits  7..2:	reserved */
+#define GPC_RST_CLR		BIT_1	/* Clear GPHY Reset */
+#define GPC_RST_SET		BIT_0	/* Set   GPHY Reset */
+
+/* Yukon-EC Ultra and newer chips */
+#define GPC_PHY_ENER_DET	BIT_31	/* PHY Stat Energy Detect */
+#define GPC_PHY_TX_P_ENA	BIT_30	/* PHY Stat Tx Pause enabled */
+#define GPC_PHY_RX_P_ENA	BIT_29	/* PHY Stat Rx Pause enabled */
+#define GPC_PHY_SPEED_1000	BIT_28	/* PHY Stat Speed 1000M */
+#define GPC_PHY_SPEED_100	BIT_27	/* PHY Stat Speed 100M */
+#define GPC_PHY_SPEED_MSK	(3L<<27)	/* Bit 28..27: PHY Stat Speed Mask */
+#define GPC_PHY_LINK_UP		BIT_26	/* PHY Stat Link Up */
+#define GPC_PHY_FULL_DUP	BIT_25	/* PHY Stat Full Duplex */
+#define GPC_PHY_125MHZ_ST	BIT_24	/* PHY Stat 125 MHz stable */
+
+#define GPC_LED_CONF_MSK	(7<<6)	/* Bit 8.. 6:	GPHY LED Config */
+#define GPC_PD_125M_CLK_OFF	BIT_5	/* Disable Power Down Clock 125 MHz */
+#define GPC_PD_125M_CLK_ON	BIT_4	/* Enable  Power Down Clock 125 MHz */
+#define GPC_DPLL_RST_SET	BIT_3	/* Set   GPHY's DPLL Reset */
+#define GPC_DPLL_RST_CLR	BIT_2	/* Clear GPHY's DPLL Reset */
+									/* (DPLL = Digital Phase Lock Loop) */
+#define GPC_LED_CONF_VAL(x)	(SHIFT6(x) & GPC_LED_CONF_MSK)
+
+#define GPC_HWCFG_GMII_COP	(GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
+							 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
+
+#define GPC_HWCFG_GMII_FIB	(				 GPC_HWCFG_M_2 | \
+							 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
+
+#define GPC_ANEG_ADV_ALL_M	(GPC_ANEG_3 | GPC_ANEG_2 | \
+							 GPC_ANEG_1 | GPC_ANEG_0)
+
+/* forced speed and duplex mode (don't mix with other ANEG bits) */
+#define GPC_FRC10MBIT_HALF	0
+#define GPC_FRC10MBIT_FULL	GPC_ANEG_0
+#define GPC_FRC100MBIT_HALF	GPC_ANEG_1
+#define GPC_FRC100MBIT_FULL	(GPC_ANEG_0 | GPC_ANEG_1)
+
+/* auto-negotiation with limited advertised speeds */
+/* mix only with master/slave settings (for copper) */
+#define GPC_ADV_1000_HALF	GPC_ANEG_2
+#define GPC_ADV_1000_FULL	GPC_ANEG_3
+#define GPC_ADV_ALL			(GPC_ANEG_2 | GPC_ANEG_3)
+
+/* master/slave settings */
+/* only for copper with 1000 Mbps */
+#define GPC_FORCE_MASTER	0
+#define GPC_FORCE_SLAVE		GPC_ANEG_0
+#define GPC_PREF_MASTER		GPC_ANEG_1
+#define GPC_PREF_SLAVE		(GPC_ANEG_1 | GPC_ANEG_0)
+
+/*	GMAC_IRQ_SRC	 8 bit	GMAC Interrupt Source Reg (YUKON only) */
+/*	GMAC_IRQ_MSK	 8 bit	GMAC Interrupt Mask   Reg (YUKON only) */
+#define GM_IS_RX_CO_OV	BIT_5S		/* Receive Counter Overflow IRQ */
+#define GM_IS_TX_CO_OV	BIT_4S		/* Transmit Counter Overflow IRQ */
+#define GM_IS_TX_FF_UR	BIT_3S		/* Transmit FIFO Underrun */
+#define GM_IS_TX_COMPL	BIT_2S		/* Frame Transmission Complete */
+#define GM_IS_RX_FF_OR	BIT_1S		/* Receive FIFO Overrun */
+#define GM_IS_RX_COMPL	BIT_0S		/* Frame Reception Complete */
+
+#define GMAC_DEF_MSK	(GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
+						GM_IS_TX_FF_UR)
+
+/*	GMAC_LINK_CTRL	16 bit	Link Control Reg (YUKON only) */
+						/* Bits 15.. 2:	reserved */
+#define GMLC_RST_CLR	BIT_1S		/* Clear Link Reset */
+#define GMLC_RST_SET	BIT_0S		/* Set   Link Reset */
+
+
+/*	WOL_CTRL_STAT	16 bit	WOL Control/Status Reg */
+#define WOL_CTL_LINK_CHG_OCC			BIT_15S
+#define WOL_CTL_MAGIC_PKT_OCC			BIT_14S
+#define WOL_CTL_PATTERN_OCC				BIT_13S
+
+#define WOL_CTL_CLEAR_RESULT			BIT_12S
+
+#define WOL_CTL_ENA_PME_ON_LINK_CHG		BIT_11S
+#define WOL_CTL_DIS_PME_ON_LINK_CHG		BIT_10S
+#define WOL_CTL_ENA_PME_ON_MAGIC_PKT	BIT_9S
+#define WOL_CTL_DIS_PME_ON_MAGIC_PKT	BIT_8S
+#define WOL_CTL_ENA_PME_ON_PATTERN		BIT_7S
+#define WOL_CTL_DIS_PME_ON_PATTERN		BIT_6S
+
+#define WOL_CTL_ENA_LINK_CHG_UNIT		BIT_5S
+#define WOL_CTL_DIS_LINK_CHG_UNIT		BIT_4S
+#define WOL_CTL_ENA_MAGIC_PKT_UNIT		BIT_3S
+#define WOL_CTL_DIS_MAGIC_PKT_UNIT		BIT_2S
+#define WOL_CTL_ENA_PATTERN_UNIT		BIT_1S
+#define WOL_CTL_DIS_PATTERN_UNIT		BIT_0S
+
+#define WOL_CTL_DEFAULT				\
+	(WOL_CTL_DIS_PME_ON_LINK_CHG |	\
+	 WOL_CTL_DIS_PME_ON_PATTERN |	\
+	 WOL_CTL_DIS_PME_ON_MAGIC_PKT |	\
+	 WOL_CTL_DIS_LINK_CHG_UNIT |	\
+	 WOL_CTL_DIS_PATTERN_UNIT |		\
+	 WOL_CTL_DIS_MAGIC_PKT_UNIT)
+
+/*	WOL_MATCH_CTL	 8/16 bit	WOL Match Control Reg */
+#define WOL_CTL_PATT_ENA(x)				(BIT_0 << (x))
+
+/*	WOL_PATT_PME	8 bit	WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_FORCE_PME				BIT_7	/* Generates a PME */
+#define WOL_PATT_MATCH_PME_ALL			0x7f
+
+#define SK_NUM_WOL_PATTERN		7
+#define SK_NUM_WOL_PATTERN_EX	9
+#define SK_NUM_WOL_PATTERN_FEP	6
+#define SK_PATTERN_PER_WORD		4
+#define SK_BITMASK_PATTERN		7
+#define SK_POW_PATTERN_LENGTH	128
+
+#define SK_WOL_PATT_LO_MSK_EX	0x0000ffffUL
+#define SK_WOL_PATT_HI_MSK_EX	0x03000000UL
+
+#define SK_WOL_PATT_LO_MSK_SU	0xffffffffUL
+#define SK_WOL_PATT_HI_MSK_SU	0x7fffffffUL
+
+#define SK_WOL_PATT_LO_MSK_OP	0x000000ffUL
+#define SK_WOL_PATT_HI_MSK_OP	0x01000000UL
+
+#define WOL_LENGTH_MSK		0x7f
+#define WOL_LENGTH_SHIFT	8
+
+
+/* typedefs ******************************************************************/
+
+/* Receive and Transmit Descriptors ******************************************/
+
+/* Transmit Descriptor struct */
+typedef	struct s_HwTxd {
+	SK_U32 volatile	TxCtrl;	/* Transmit Buffer Control Field */
+	SK_U32	TxNext;			/* Physical Address Pointer to the next TxD */
+	SK_U32	TxAdrLo;		/* Physical Tx Buffer Address lower DWord */
+	SK_U32	TxAdrHi;		/* Physical Tx Buffer Address upper DWord */
+	SK_U32	TxStat;			/* Transmit Frame Status Word */
+#ifndef SK_USE_REV_DESC
+	SK_U16	TxTcpOffs;		/* TCP Checksum Calculation Start Value */
+	SK_U16	TxRes1;			/* 16 bit reserved field */
+	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
+	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	TxRes1;			/* 16 bit reserved field */
+	SK_U16	TxTcpOffs;		/* TCP Checksum Calculation Start Value */
+	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
+	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
+#endif /* SK_USE_REV_DESC */
+	SK_U32  TxRes2;			/* 32 bit reserved field */
+} SK_HWTXD;
+
+/* Receive Descriptor struct */
+typedef	struct s_HwRxd {
+	SK_U32 volatile RxCtrl;	/* Receive Buffer Control Field */
+	SK_U32	RxNext;			/* Physical Address Pointer to the next RxD */
+	SK_U32	RxAdrLo;		/* Physical Rx Buffer Address lower DWord */
+	SK_U32	RxAdrHi;		/* Physical Rx Buffer Address upper DWord */
+	SK_U32	RxStat;			/* Receive Frame Status Word */
+	SK_U32	RxTiSt;			/* Receive Time Stamp (from XMAC on GENESIS) */
+#ifndef SK_USE_REV_DESC
+	SK_U16	RxTcpSum1;		/* Rx TCP Checksum 1 */
+	SK_U16	RxTcpSum2;		/* Rx TCP Checksum 2 */
+	SK_U16	RxTcpSp1;		/* TCP Checksum Calculation Start Position 1 */
+	SK_U16	RxTcpSp2;		/* TCP Checksum Calculation Start Position 2 */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	RxTcpSum2;		/* Rx TCP Checksum 2 */
+	SK_U16	RxTcpSum1;		/* Rx TCP Checksum 1 */
+	SK_U16	RxTcpSp2;		/* TCP Checksum Calculation Start Position 2 */
+	SK_U16	RxTcpSp1;		/* TCP Checksum Calculation Start Position 1 */
+#endif /* SK_USE_REV_DESC */
+} SK_HWRXD;
+
+/*
+ * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
+ * should set the define SK_USE_REV_DESC.
+ * Structures are 'normally' not endianess dependent. But in this case
+ * the SK_U16 fields are bound to bit positions inside the descriptor.
+ * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
+ * The bit positions inside a DWord are of course endianess dependent and
+ * swap if the DWord is swapped by the hardware.
+ */
+
+/* YUKON-2 descriptors ******************************************************/
+
+typedef struct _TxMss {		/* Yukon-Extreme only */
+#ifndef SK_USE_REV_DESC
+	SK_U16	TxMssVal;		/* MSS value */
+	SK_U16	reserved;		/* reserved */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	reserved;		/* TCP Checksum Calculation Start Position */
+	SK_U16	TxMssVal;		/* MSS value */
+#endif /* SK_USE_REV_DESC */
+} SK_HWTXMSS;
+
+typedef struct _TxChksum {
+#ifndef SK_USE_REV_DESC
+	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
+	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	TxTcpSp;		/* TCP Checksum Calculation Start Position */
+	SK_U16	TxTcpWp;		/* TCP Checksum Write Position */
+#endif /* SK_USE_REV_DESC */
+} SK_HWTXCS;
+
+typedef struct _LargeSend {
+#ifndef SK_USE_REV_DESC
+	SK_U16 Length;		/* Large Send Segment Length */
+	SK_U16 Reserved;	/* reserved */
+#else  /* SK_USE_REV_DESC */
+	SK_U16 Reserved;	/* reserved */
+	SK_U16 Length;		/* Large Send Segment Length */
+#endif /* SK_USE_REV_DESC */
+} SK_HWTXLS;
+
+typedef union u_HwTxBuf {
+	SK_U16	BufLen;		/* Tx Buffer Length */
+	SK_U16	VlanTag;	/* VLAN Tag */
+	SK_U16	InitCsum;	/* Init. Checksum */
+#ifdef SK_LITTLE_ENDIAN
+	struct {
+		SK_U16 BufLen:12;
+		SK_U16 LenRange:4;
+#else
+	struct {
+		SK_U16 LenRange:4;
+		SK_U16 BufLen:12;
+#endif
+	} AvbLen;
+} SK_HWTXBUF;
+
+/* Tx List Element structure */
+typedef struct s_HwLeTx {
+	union {
+		SK_U32	BufAddr;	/* Tx LE Buffer Address high/low */
+		SK_U32	LsoV2Len;	/* Total lenght of LSOv2 packet */
+		SK_HWTXCS	ChkSum;	/* Tx LE TCP Checksum parameters */
+		SK_HWTXLS	LargeSend;/* Large Send length */
+		SK_HWTXMSS	Mss;	/* MSS value; Yukon-Extreme only */
+	} TxUn;
+#ifndef SK_USE_REV_DESC
+	SK_HWTXBUF	Send;
+	SK_U8	ControlFlags;	/* Tx LE Control field or Lock Number */
+	SK_U8	Opcode;			/* Tx LE Opcode field */
+#else  /* SK_USE_REV_DESC */
+	SK_U8	Opcode;			/* Tx LE Opcode field */
+	SK_U8	ControlFlags;	/* Tx LE Control field or Lock Number */
+	SK_HWTXBUF	Send;
+#endif /* SK_USE_REV_DESC */
+} SK_HWLETX;
+
+typedef struct _RxChkSum{
+#ifndef SK_USE_REV_DESC
+	SK_U16	RxTcpSp1;		/* TCP Checksum Calculation Start Position 1 */
+	SK_U16	RxTcpSp2;		/* TCP Checksum Calculation Start Position 2 */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	RxTcpSp2;		/* TCP Checksum Calculation Start Position 2 */
+	SK_U16	RxTcpSp1;		/* TCP Checksum Calculation Start Position 1 */
+#endif /* SK_USE_REV_DESC */
+} SK_HWRXCS;
+
+/* Rx List Element structure */
+typedef struct s_HwLeRx {
+	union {
+		SK_U32	BufAddr;	/* Rx LE Buffer Address high/low */
+		SK_HWRXCS ChkSum;	/* Rx LE TCP Checksum parameters */
+	} RxUn;
+#ifndef SK_USE_REV_DESC
+	SK_U16	BufferLength;	/* Rx LE Buffer Length field */
+	SK_U8	ControlFlags;	/* Rx LE Control field */
+	SK_U8	Opcode;			/* Rx LE Opcode field */
+#else  /* SK_USE_REV_DESC */
+	SK_U8	Opcode;			/* Rx LE Opcode field */
+	SK_U8	ControlFlags;	/* Rx LE Control field */
+	SK_U16	BufferLength;	/* Rx LE Buffer Length field */
+#endif /* SK_USE_REV_DESC */
+} SK_HWLERX;
+
+typedef struct s_StRxTCPChkSum {
+#ifndef SK_USE_REV_DESC
+	SK_U16	RxTCPSum1;		/* Rx TCP Checksum 1 */
+	SK_U16	RxTCPSum2;		/* Rx TCP Checksum 2 */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	RxTCPSum2;		/* Rx TCP Checksum 2 */
+	SK_U16	RxTCPSum1;		/* Rx TCP Checksum 1 */
+#endif /* SK_USE_REV_DESC */
+} SK_HWSTCS;
+
+typedef struct s_StRxRssFlags {
+#ifndef SK_USE_REV_DESC
+	SK_U8	FlagField;		/* contains TCP and IP flags */
+	SK_U8	reserved;		/* reserved */
+#else  /* SK_USE_REV_DESC */
+	SK_U8	reserved;		/* reserved */
+	SK_U8	FlagField;		/* contains TCP and IP flags */
+#endif /* SK_USE_REV_DESC */
+} SK_HWSTRSS;
+
+/* bit definition of MAC Sec Rx Status	(SK_HWLEST.StMacSecWord)	*/
+/*										(Yukon-Ext only)			*/
+									/* bit 31..10 reserved */
+#define MS_AUTH_RES_MSK	(0xf<<6)	/* MAC Sec, encoded auth. result info */
+									/* see figure 10-5 in 802.1AE spec */
+#define MS_ENCRYPT_ENA	BIT_5		/* MAC Sec, encryption enabled */
+#define MS_AUTHENT_ENA	BIT_4		/* MAC Sec, authentication enabled */
+#define MS_LKUP_NUM_MSK	(3<<1)		/* MAC Sec, lookup entry number mask */
+									/* Info needed 0 = Bypass etc... TBD XXX */
+#define MS_LKUP_TAB_HIT	BIT_0		/* MAC Sec, lookup table hit */
+
+/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
+								/* bit 7..3 reserved */
+#define RSS_CALC_HASH_TCP_IPV6_EX_FLAG	BIT_8S	/* Yukon-Extreme B0 */
+#define RSS_CALC_HASH_IPV6_EX_FLAG		BIT_7S	/* Yukon-Extreme B0 */
+#define RSS_CALC_HASH_TCP_IPV6_FLAG		BIT_6S	/* Yukon-Extreme B0 */
+#define RSS_CALC_HASH_IPV6_FLAG			BIT_5S	/* Yukon-Extreme B0 */
+#define RSS_CALC_HASH_TCP_IPV4_FLAG		BIT_4S	/* Yukon-Extreme B0 */
+#define RSS_CALC_HASH_IPV4_FLAG			BIT_3S	/* Yukon-Extreme B0 */
+#define RSS_IPV6_FLAG	BIT_2S	/* RSS value related to IP V6 (Yukon-Ext only)*/
+#define RSS_TCP_FLAG	BIT_1S	/* RSS value related to TCP area */
+#define RSS_IP_FLAG		BIT_0S	/* RSS value related to IP area */
+/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
+/* For protocol errors or other protocols an empty RSS LE is generated */
+
+typedef union u_HwStBuf {
+	SK_U16	TxDone3;	/* AVB TX done report 3rd queue */
+	SK_U16	BufLen;		/* Rx Buffer Length */
+	SK_U16	VlanTag;	/* VLAN Tag */
+	SK_U16	StTxStatHi;	/* Tx Queue Status (high) */
+	SK_HWSTRSS	Rss;	/* Flag Field for TCP and IP protocol */
+} SK_HWSTBUF;
+
+typedef struct s_StTxDoneIndeces {
+#ifndef SK_USE_REV_DESC
+	SK_U16	TxDone1;		/* Rx TCP Checksum 1 */
+	SK_U16	TxDone2;		/* Rx TCP Checksum 2 */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	TxDone2;		/* Rx TCP Checksum 2 */
+	SK_U16	TxDone1;		/* Rx TCP Checksum 1 */
+#endif /* SK_USE_REV_DESC */
+} SK_HWSTTXDONE;
+
+/* Status List Element structure */
+typedef struct s_HwLeSt {
+	union {
+		SK_U32	StRxStatWord;	/* Rx Status Dword */
+		SK_U32	StRxTimeStamp;	/* Rx Timestamp */
+		SK_HWSTCS StRxTCPCSum;	/* Rx TCP Checksum */
+		SK_HWSTTXDONE TxDone;	/* Tx Done indeces */
+		SK_U32	StTxStatLow;	/* Tx Queue Status (low) */
+		SK_U32	StRxRssValue;	/* Rx RSS value */
+		SK_U32	StMacSecWord;	/* Rx MAC Sec Satus Word (Yukon-Ext only) */
+	} StUn;
+#ifndef SK_USE_REV_DESC
+	SK_HWSTBUF	Stat;
+	SK_U8	Link;			/* Status LE Link field (& Csum Stat for Yukon-Ext)*/
+	SK_U8	Opcode;			/* Status LE Opcode field */
+#else  /* SK_USE_REV_DESC */
+	SK_U8	Opcode;			/* Status LE Opcode field */
+	SK_U8	Link;			/* Status LE Link field (& Csum Stat for Yukon-Ext)*/
+	SK_HWSTBUF	Stat;
+#endif /* SK_USE_REV_DESC */
+} SK_HWLEST;
+
+/* Special Action List Element */
+typedef struct s_HwLeSa {
+#ifndef SK_USE_REV_DESC
+	SK_U16	TxAIdxVld;		/* Special Action LE TxA Put Index field */
+	SK_U16	TxSIdxVld;		/* Special Action LE TxS Put Index field */
+	SK_U16	RxIdxVld;		/* Special Action LE Rx Put Index field */
+	SK_U8	Link;			/* Special Action LE Link field */
+	SK_U8	Opcode;			/* Special Action LE Opcode field */
+#else  /* SK_USE_REV_DESC */
+	SK_U16	TxSIdxVld;		/* Special Action LE TxS Put Index field */
+	SK_U16	TxAIdxVld;		/* Special Action LE TxA Put Index field */
+	SK_U8	Opcode;			/* Special Action LE Opcode field */
+	SK_U8	Link;			/* Special Action LE Link field */
+	SK_U16	RxIdxVld;		/* Special Action LE Rx Put Index field */
+#endif /* SK_USE_REV_DESC */
+} SK_HWLESA;
+
+/* Common List Element union */
+typedef union u_HwLeTxRxSt {
+	/* Transmit List Element Structure */
+	SK_HWLETX Tx;
+	/* Receive List Element Structure */
+	SK_HWLERX Rx;
+	/* Status List Element Structure */
+	SK_HWLEST St;
+	/* Special Action List Element Structure */
+	SK_HWLESA Sa;
+	/* Full List Element */
+	SK_U64 Full;
+} SK_HWLE;
+
+#define MAX_LARGE_SEND_LEN	0xffff
+
+/* mask and shift value to get Tx async queue status for port 1 */
+#define STLE_TXA1_MSKL		0x00000fff
+#define STLE_TXA1_SHIFTL	0
+
+/* mask and shift value to get Tx sync queue status for port 1 */
+#define STLE_TXS1_MSKL		0x00fff000
+#define STLE_TXS1_SHIFTL	12
+
+/* mask and shift value to get Tx async queue status for port 2 */
+#define STLE_TXA2_MSKL		0xff000000
+#define STLE_TXA2_SHIFTL	24
+#define STLE_TXA2_MSKH		0x000f
+/* this one shifts up */
+#define STLE_TXA2_SHIFTH	8
+
+/* mask and shift value to get Tx sync queue status for port 2 */
+#define STLE_TXS2_MSKL		0x00000000
+#define STLE_TXS2_SHIFTL	0
+#define STLE_TXS2_MSKH		0xfff0
+#define STLE_TXS2_SHIFTH	4
+
+/* YUKON-2 bit values */
+#define HW_OWNER		BIT_7
+#define SW_OWNER		0
+
+#define PU_PUTIDX_VALID		BIT_12
+
+/* YUKON-2 Control flags */
+#define UDPTCP			BIT_0S
+#define CALSUM			BIT_1S
+#define WR_SUM			BIT_2S
+#define INIT_SUM		BIT_3S
+#define LOCK_SUM		BIT_4S
+#define INS_VLAN		BIT_5S
+#define FRC_STAT		BIT_6S
+#define	MACSEC			BIT_6S	/* Yukon-Ext only */
+#define EOP				BIT_7S
+
+#define TX_LOCK			BIT_8S
+#define BUF_SEND		BIT_9S
+#define PACKET_SEND		BIT_10S
+
+#define NO_WARNING		BIT_14S
+#define NO_UPDATE		BIT_15S
+
+#define CALSUM_TL		BIT_1S	/* Yukon-Ext only */
+#define CALSUM_IP		BIT_0S	/* Yukon-Ext only */
+
+/* Yukon-Ext CSum Status defines (Rx Status, Link field) */
+#define CSS_TCPUDPCSOK	BIT_7S	/* TCP / UDP checksum is ok */
+#define CSS_ISUDP		BIT_6S	/* packet is a UDP packet */
+#define CSS_ISTCP		BIT_5S	/* packet is a TCP packet */
+#define CSS_ISIPFRAG	BIT_4S	/* packet is a TCP/UDP frag, CS calc not done */
+#define CSS_ISIPV6		BIT_3S	/* packet is a IPv6 packet */
+#define CSS_IPV4CSUMOK	BIT_2S	/* IP v4: TCP header checksum is ok */
+#define CSS_ISIPV4		BIT_1S	/* packet is a IPv4 packet */
+#define CSS_LINK_BIT	BIT_0S	/* port number (legacy) */
+
+
+/* YUKON-2 Rx/Tx opcodes defines */
+#define OP_TCPWRITE		0x11
+#define OP_TCPSTART		0x12
+#define OP_TCPINIT		0x14
+#define OP_TCPLCK		0x18
+#define OP_TCPCHKSUM	OP_TCPSTART
+#define OP_TCPIS		(OP_TCPINIT | OP_TCPSTART)
+#define OP_TCPLW		(OP_TCPLCK | OP_TCPWRITE)
+#define OP_TCPLSW		(OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
+#define OP_TCPLISW		(OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
+#define OP_ADDR64		0x21
+#define OP_VLAN			0x22
+#define OP_ADDR64VLAN	(OP_ADDR64 | OP_VLAN)
+#define OP_LRGLEN		0x24							/* not Yukon-Ext */
+#define OP_LRGLENVLAN	(OP_LRGLEN | OP_VLAN)			/* not Yukon-Ext */
+#define OP_MSS			0x28							/* Yukon-Ext only */
+#define OP_MSSVLAN		(OP_MSS | OP_VLAN)				/* Yukon-Ext only */
+#define OP_BUFFER		0x40
+#define OP_PACKET		0x41
+#define OP_LARGESEND	0x43
+#define OP_LSOV2		0x45							/* Yukon-Ext only */
+
+
+/* YUKON-2 STATUS opcodes defines */
+#define OP_RXSTAT		0x60
+#define OP_RXTIMESTAMP	0x61
+#define OP_RXVLAN		0x62
+#define OP_RXCHKS		0x64
+#define OP_RXCHKSVLAN	(OP_RXCHKS | OP_RXVLAN)
+#define OP_RXTIMEVLAN	(OP_RXTIMESTAMP | OP_RXVLAN)
+#define OP_RSS_HASH		0x65
+#define OP_TXINDEXLE	0x68
+#define OP_TXDONE2		0x69
+#define OP_TXDONE3		0x6a
+#define OP_MACSEC		0x6c							/* Yukon-Ext only */
+#define OP_MACSECVLAN	(OP_MACSEC | OP_RXVLAN)			/* Yukon-Ext only */
+
+/* YUKON-2 SPECIAL opcodes defines */
+#define OP_PUTIDX	0x70
+
+/* Descriptor Bit Definition */
+/*	TxCtrl		Transmit Buffer Control Field */
+/*	RxCtrl		Receive  Buffer Control Field */
+#define BMU_OWN			BIT_31	/* OWN bit: 0=host/1=BMU */
+#define BMU_STF			BIT_30	/* Start of Frame */
+#define BMU_EOF			BIT_29	/* End of Frame */
+#define BMU_IRQ_EOB		BIT_28	/* Req "End of Buffer" IRQ */
+#define BMU_IRQ_EOF		BIT_27	/* Req "End of Frame" IRQ */
+/* TxCtrl specific bits */
+#define BMU_STFWD		BIT_26	/* (Tx)	Store & Forward Frame */
+#define BMU_NO_FCS		BIT_25	/* (Tx) Disable MAC FCS (CRC) generation */
+#define BMU_SW			BIT_24	/* (Tx)	1 bit res. for SW use */
+/* RxCtrl specific bits */
+#define BMU_DEV_0		BIT_26	/* (Rx)	Transfer data to Dev0 */
+#define BMU_STAT_VAL	BIT_25	/* (Rx)	Rx Status Valid */
+#define BMU_TIST_VAL	BIT_24	/* (Rx)	Rx TimeStamp Valid */
+								/* Bit 23..16:	BMU Check Opcodes */
+#define BMU_CHECK		(0x55L<<16)	/* Default BMU check */
+#define BMU_TCP_CHECK	(0x56L<<16)	/* Descr with TCP ext */
+#define BMU_UDP_CHECK	(0x57L<<16)	/* Descr with UDP ext (YUKON only) */
+#define BMU_BBC			0xffffL	/* Bit 15.. 0:	Buffer Byte Counter */
+
+/*	TxStat		Transmit Frame Status Word */
+/*	RxStat		Receive Frame Status Word */
+/*
+ *Note: TxStat is reserved for ASIC loopback mode only
+ *
+ *	The Bits of the Status words are defined in xmac_ii.h
+ *	(see XMR_FS bits)
+ */
+
+/* macros ********************************************************************/
+
+/* Macro for accessing the key registers */
+#define RSS_KEY_ADDR(Port, KeyIndex)	\
+		((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
+
+/* Receive and Transmit Queues */
+#define Q_R1	0x0000		/* Receive Queue 1 */
+#define Q_R2	0x0080		/* Receive Queue 2 */
+#define Q_XS1	0x0200		/* Synchronous Transmit Queue 1 */
+#define Q_XA1	0x0280		/* Asynchronous Transmit Queue 1 */
+#define Q_XS2	0x0300		/* Synchronous Transmit Queue 2 */
+#define Q_XA2	0x0380		/* Asynchronous Transmit Queue 2 */
+
+/* Yukon-Optima AVB Tx Queues */
+#define Q_AVB_TX_1	0x280	/* Transmit Prefetch Unit Q1 Registers */
+#define Q_AVB_TX_2	0x200	/* Transmit Prefetch Unit Q2 Registers */
+#define Q_AVB_TX_3	0x380	/* Transmit Prefetch Unit Q3 Registers */
+#define Q_AVB_TX_4	0x300	/* Transmit Prefetch Unit Q4 Registers */
+#define Q_AVB_TX_5	0x0c0	/* Transmit Prefetch Unit Q5 Registers */
+#define Q_AVB_TX_6	0x100	/* Transmit Prefetch Unit Q6 Registers */
+#define Q_AVB_TX_7	0x140	/* Transmit Prefetch Unit Q7 Registers */
+#define Q_AVB_TX_8	0x180	/* Transmit Prefetch Unit Q8 Registers */
+
+/* Yukon-Optima LE Registers */
+#define TPLE_BASE			TPLE1_REQ_CTRL	/* Transmit LE register base */
+#define TPLE_AVB_REG_1		0x00			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_2		0x10			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_3		0x20			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_4		0x30			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_5		0x80			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_6		0x90			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_7		0xa0			/* Transmit LE registers Q1 */
+#define TPLE_AVB_REG_8		0xb0			/* Transmit LE registers Q1 */
+
+/* Offsets */
+#define REQ_CTRL			0x00	/* Control register offset */
+#define REQ_TH				0x04	/* Threshold register offset */
+#define	LEPKT_COUNTER		0x08	/* Packet counter register offset */
+
+#define Q_ASF_R1	0x100	/* ASF Rx Queue 1 */
+#define Q_ASF_R2	0x180	/* ASF Rx Queue 2 */
+#define Q_ASF_T1	0x140	/* ASF Tx Queue 1 */
+#define Q_ASF_T2	0x1c0	/* ASF Tx Queue 2 */
+/*
+ *	Macro Q_ADDR()
+ *
+ *	Use this macro to access the Receive and Transmit Queue Registers.
+ *
+ * para:
+ *	Queue	Queue to access.
+ *				Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
+ *	Offs	Queue register offset.
+ *				Values: Q_D, Q_DA_L ... Q_T2, Q_T3
+ *
+ * usage	SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
+ */
+#define Q_ADDR(Queue, Offs)	(B8_Q_REGS + (Queue) + (Offs))
+
+/*
+ *	Macro Y2_PREF_Q_ADDR()
+ *
+ *	Use this macro to access the Prefetch Units of the receive and
+ *	transmit queues of Yukon-2.
+ *
+ * para:
+ *	Queue	Queue to access.
+ *				Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
+ *	Offs	Queue register offset.
+ *				Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
+ *
+ * usage	SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
+ */
+#define Y2_PREF_Q_ADDR(Queue, Offs)	(Y2_B8_PREF_REGS + (Queue) + (Offs))
+
+/*
+ *	Macro Y2_AVB_MAC_Q_ADDR()
+ *
+ *	Use this macro to access the MAC FIFO transmit queues of Yukon-2.
+ *
+ * para:
+ *	Queue	Offset of TCTL register for this queue.
+ *				Values: TXMF_TCTL, TXMF_TCTL2, TXMF_TCTL3, TXMF_TCTL4, TXMF_TCTL5
+ *	Offs	Queue register offset.
+ *				Values: TXMF_TCTL ... TXMF_STAT
+ *
+ * usage	SK_IN8(IoC, Y2_AVB_MAC_Q_ADDR(TXMF_TCTL2, TXMF_TCTL), pVal)
+ */
+#define Y2_AVB_MAC_Q_ADDR(Queue, Offs) ((Queue) + (Offs) - TXMF_TCTL)
+
+/*
+ *	Macro Y2_AVB_CLS_ADDR()
+ *
+ *	Use this macro to access the Transmit Classification registers of Yukon-2.
+ *
+ * para:
+ *	Class	Offset of CLASS_x_RATE_INT register for this queue.
+ *				Values: CLASS_A_RATE_INT, CLASS_B_RATE_INT
+ *	Offs	Queue register offset.
+ *				Values: CLASS_A_RATE_INT ... CLASS_A_ST
+ *
+ * usage	SK_IN8(IoC, Y2_AVB_CLS_ADDR(CLASS_B_RATE_INT, CLASS_A_ST), pVal)
+ */
+#define Y2_AVB_CLS_ADDR(Class, Offs) ((Class) + (Offs) - CLASS_A_RATE_INT)
+
+/*
+ *	Macro RB_ADDR()
+ *
+ *	Use this macro to access the RAM Buffer Registers.
+ *
+ * para:
+ *	Queue	Queue to access.
+ *				Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
+ *	Offs	Queue register offset.
+ *				Values: RB_START, RB_END ... RB_LEV, RB_CTRL
+ *
+ * usage	SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
+ */
+#define RB_ADDR(Queue, Offs)	(B16_RAM_REGS + (Queue) + (Offs))
+
+/*
+ *	Macro TPLE_ADDR()
+ *
+ *	Use this macro to access the TPLE AVB Registers
+ *
+ * para:
+ *	Queue	Queue to access.
+ *				Values: 1 -8
+ *	Offs	Queue register offset.
+ *				Values: REQ_CTRL, REQ_TH, LEPKT_COUNTER
+ *
+ * usage	SK_IN32(IoC, TPLE_ADDR(TPLE_AVB_REG_1, REQ_CTRL), pVal)
+ */
+#define TPLE_ADDR(Queue, Offs)	(((Queue == 1) ? TPLE1_REQ_CTRL :		\
+								  (Queue == 2) ? TPLE2_REQ_CTRL :		\
+								  (Queue == 3) ? TPLE3_REQ_CTRL :		\
+								  (Queue == 4) ? TPLE4_REQ_CTRL :		\
+								  (Queue == 5) ? TPLE5_REQ_CTRL :		\
+								  (Queue == 6) ? TPLE6_REQ_CTRL :		\
+								  (Queue == 7) ? TPLE7_REQ_CTRL :		\
+								  TPLE8_REQ_CTRL) + Offs)
+
+
+/* MAC Related Registers */
+#define MAC_1		0	/* 1st port */
+#define MAC_2		1	/* 2nd port */
+
+/*
+ *	Macro MR_ADDR()
+ *
+ *	Use this macro to access a MAC Related Registers inside the ASIC.
+ *
+ * para:
+ *	Mac		MAC to access.
+ *				Values: MAC_1, MAC_2
+ *	Offs	MAC register offset.
+ *				Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
+ *						TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
+ *
+ * usage	SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
+ */
+#define MR_ADDR(Mac, Offs)	(((Mac) << 7) + (Offs))
+
+/*
+ * macros to access the XMAC (GENESIS only)
+ *
+ * XM_IN16(),		to read a 16 bit register (e.g. XM_MMU_CMD)
+ * XM_OUT16(),		to write a 16 bit register (e.g. XM_MMU_CMD)
+ * XM_IN32(),		to read a 32 bit register (e.g. XM_TX_EV_CNT)
+ * XM_OUT32(),		to write a 32 bit register (e.g. XM_TX_EV_CNT)
+ * XM_INADDR(),		to read a network address register (e.g. XM_SRC_CHK)
+ * XM_OUTADDR(),	to write a network address register (e.g. XM_SRC_CHK)
+ * XM_INHASH(),		to read the XM_HSM_CHK register
+ * XM_OUTHASH()		to write the XM_HSM_CHK register
+ *
+ * para:
+ *	Mac		XMAC to access		values: MAC_1 or MAC_2
+ *	IoC		I/O context needed for SK I/O macros
+ *	Reg		XMAC Register to read or write
+ *	(p)Val	Value or pointer to the value which should be read or written
+ *
+ * usage:	XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value);
+ */
+
+#define XMA(Mac, Reg)									\
+	((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
+
+#define XM_IN16(IoC, Mac, Reg, pVal)	\
+	SK_IN16(IoC, XMA(Mac, Reg), pVal)
+
+#define XM_OUT16(IoC, Mac, Reg, Val)	\
+	SK_OUT16(IoC, XMA(Mac, Reg), Val)
+
+#ifdef SK_LITTLE_ENDIAN
+
+#define XM_IN32(IoC, Mac, Reg, pVal) {								\
+	SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal));			\
+	SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1);	\
+}
+
+#else  /* !SK_LITTLE_ENDIAN */
+
+#define XM_IN32(IoC, Mac, Reg, pVal) {							\
+	SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1);	\
+	SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal));	\
+}
+
+#endif /* !SK_LITTLE_ENDIAN */
+
+#define XM_OUT32(IoC, Mac, Reg, Val) {										\
+	SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL));				\
+	SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL));	\
+}
+
+/* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
+
+#define XM_INADDR(IoC, Mac, Reg, pVal) {				\
+	SK_U16	Word;										\
+	SK_U8	*pByte;										\
+	pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];				\
+	SK_IN16((IoC), XMA((Mac), (Reg)), &Word);			\
+	pByte[0] = (SK_U8)(Word & 0x00ff);					\
+	pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);			\
+	SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word);		\
+	pByte[2] = (SK_U8)(Word & 0x00ff);					\
+	pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);			\
+	SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word);		\
+	pByte[4] = (SK_U8)(Word & 0x00ff);					\
+	pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);			\
+}
+
+#define XM_OUTADDR(IoC, Mac, Reg, pVal) {				\
+	SK_U8	SK_FAR *pByte;								\
+	pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0];	\
+	SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)			\
+		(((SK_U16)(pByte[0]) & 0x00ff) |				\
+		(((SK_U16)(pByte[1]) << 8) & 0xff00)));			\
+	SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16)		\
+		(((SK_U16)(pByte[2]) & 0x00ff) |				\
+		(((SK_U16)(pByte[3]) << 8) & 0xff00)));			\
+	SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16)		\
+		(((SK_U16)(pByte[4]) & 0x00ff) |				\
+		(((SK_U16)(pByte[5]) << 8) & 0xff00)));			\
+}
+
+#define XM_INHASH(IoC, Mac, Reg, pVal) {				\
+	SK_U16	Word;										\
+	SK_U8	SK_FAR *pByte;								\
+	pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0];	\
+	SK_IN16((IoC), XMA((Mac), (Reg)), &Word);			\
+	pByte[0] = (SK_U8)(Word & 0x00ff);					\
+	pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);			\
+	SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word);		\
+	pByte[2] = (SK_U8)(Word & 0x00ff);					\
+	pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);			\
+	SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word);		\
+	pByte[4] = (SK_U8)(Word & 0x00ff);					\
+	pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);			\
+	SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word);		\
+	pByte[6] = (SK_U8)(Word & 0x00ff);					\
+	pByte[7] = (SK_U8)((Word >> 8) & 0x00ff);			\
+}
+
+#define XM_OUTHASH(IoC, Mac, Reg, pVal) {				\
+	SK_U8	SK_FAR *pByte;								\
+	pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0];	\
+	SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)			\
+		(((SK_U16)(pByte[0]) & 0x00ff)|					\
+		(((SK_U16)(pByte[1]) << 8) & 0xff00)));			\
+	SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16)		\
+		(((SK_U16)(pByte[2]) & 0x00ff)|					\
+		(((SK_U16)(pByte[3]) << 8) & 0xff00)));			\
+	SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16)		\
+		(((SK_U16)(pByte[4]) & 0x00ff)|					\
+		(((SK_U16)(pByte[5]) << 8) & 0xff00)));			\
+	SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16)		\
+		(((SK_U16)(pByte[6]) & 0x00ff)|					\
+		(((SK_U16)(pByte[7]) << 8) & 0xff00)));			\
+}
+
+/*
+ * macros to access the GMAC (YUKON only)
+ *
+ * GM_IN16(),		to read  a 16 bit register (e.g. GM_GP_STAT)
+ * GM_OUT16(),		to write a 16 bit register (e.g. GM_GP_CTRL)
+ * GM_IN32(),		to read  a 32 bit register (e.g. GM_RXF_UC_OK)
+ * GM_OUT32(),		to write a 32 bit register
+ * GM_INADDR(),		to read  a network address register (e.g. GM_SRC_ADDR_1L)
+ * GM_OUTADDR(),	to write a network address register (e.g. GM_SRC_ADDR_2L)
+ * GM_INHASH(),		to read  the hash registers (e.g. GM_MC_ADDR_H1..4)
+ * GM_OUTHASH()		to write the hash registers (e.g. GM_MC_ADDR_H1..4)
+ *
+ * para:
+ *	Mac		GMAC to access		values: MAC_1 or MAC_2
+ *	IoC		I/O context needed for SK I/O macros
+ *	Reg		GMAC Register to read or write
+ *	(p)Val	Value or pointer to the value which should be read or written
+ *
+ * usage:	GM_OUT16(IoC, MAC_1, GM_GP_CTRL, Value);
+ */
+
+#define GMA(Mac, Reg)									\
+	((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
+
+#ifdef NO_DEV_424
+
+#define GM_IN16(IoC, Mac, Reg, pVal)	\
+	SK_IN16(IoC, GMA(Mac, Reg), pVal)
+
+#else /* DEV_424 */
+
+#define GM_IN16(IoC, Mac, Reg, pVal) {	\
+	SK_U8	Dummy;						\
+	SK_ACQ_SPIN_LOCK(IoC);				\
+	SK_IN16(IoC, GMA(Mac, Reg), pVal);	\
+	SK_IN8(IoC, B0_RAP, &Dummy);		\
+	SK_REL_SPIN_LOCK(IoC);				\
+}
+#endif /* DEV_424 */
+
+#define GM_OUT16(IoC, Mac, Reg, Val)	\
+	SK_OUT16(IoC, GMA(Mac, Reg), Val)
+
+#ifdef SK_LITTLE_ENDIAN
+
+#ifdef NO_DEV_424
+
+#define GM_IN32(IoC, Mac, Reg, pVal) {								\
+	SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal));			\
+	SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1);	\
+}
+
+#else /* DEV_424 */
+
+#define GM_IN32(IoC, Mac, Reg, pVal) {								\
+	SK_U8	Dummy;													\
+	SK_ACQ_SPIN_LOCK(IoC);											\
+	SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal));			\
+	SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1);	\
+	SK_IN8(IoC, B0_RAP, &Dummy);									\
+	SK_REL_SPIN_LOCK(IoC);											\
+}
+#endif /* DEV_424 */
+
+#else  /* !SK_LITTLE_ENDIAN */
+
+#ifdef NO_DEV_424
+
+#define GM_IN32(IoC, Mac, Reg, pVal) {							\
+	SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1);	\
+	SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal));	\
+}
+
+#else /* DEV_424 */
+
+#define GM_IN32(IoC, Mac, Reg, pVal) {							\
+	SK_U8	Dummy;												\
+	SK_ACQ_SPIN_LOCK(IoC);										\
+	SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1);	\
+	SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal));	\
+	SK_IN8(IoC, B0_RAP, &Dummy);								\
+	SK_REL_SPIN_LOCK(IoC);										\
+}
+#endif /* DEV_424 */
+
+#endif /* !SK_LITTLE_ENDIAN */
+
+#define GM_OUT32(IoC, Mac, Reg, Val) {										\
+	SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL));				\
+	SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL));	\
+}
+
+#define GM_INADDR(IoC, Mac, Reg, pVal) {		\
+	SK_U16	Word;								\
+	SK_U8	Dummy;								\
+	SK_U8	*pByte;								\
+	pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];		\
+	SK_ACQ_SPIN_LOCK(IoC);						\
+	SK_IN16(IoC, GMA((Mac), (Reg)), &Word);		\
+	pByte[0] = (SK_U8)(Word & 0x00ff);			\
+	pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);	\
+	SK_IN16(IoC, GMA((Mac), (Reg) + 4), &Word);	\
+	pByte[2] = (SK_U8)(Word & 0x00ff);			\
+	pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);	\
+	SK_IN16(IoC, GMA((Mac), (Reg) + 8), &Word);	\
+	pByte[4] = (SK_U8)(Word & 0x00ff);			\
+	pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);	\
+	SK_IN8(IoC, B0_RAP, &Dummy);				\
+	SK_REL_SPIN_LOCK(IoC);						\
+}
+
+#define GM_OUTADDR(IoC, Mac, Reg, pVal) {					\
+	SK_U8	SK_FAR *pByte;									\
+	pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0];	\
+	SK_OUT16(IoC, GMA((Mac), (Reg)), (SK_U16)				\
+		(((SK_U16)(pByte[0]) & 0x00ff) |					\
+		(((SK_U16)(pByte[1]) << 8) & 0xff00)));				\
+	SK_OUT16(IoC, GMA((Mac), (Reg) + 4), (SK_U16)			\
+		(((SK_U16)(pByte[2]) & 0x00ff) |					\
+		(((SK_U16)(pByte[3]) << 8) & 0xff00)));				\
+	SK_OUT16(IoC, GMA((Mac), (Reg) + 8), (SK_U16)			\
+		(((SK_U16)(pByte[4]) & 0x00ff) |					\
+		(((SK_U16)(pByte[5]) << 8) & 0xff00)));				\
+}
+
+#define GM_INHASH(IoC, Mac, Reg, pVal) {			\
+	SK_U16	Word;									\
+	SK_U8	Dummy;									\
+	SK_U8	*pByte;									\
+	pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];			\
+	SK_ACQ_SPIN_LOCK(IoC);							\
+	SK_IN16(IoC, GMA((Mac), (Reg)), &Word);			\
+	pByte[0] = (SK_U8)(Word & 0x00ff);				\
+	pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);		\
+	SK_IN16(IoC, GMA((Mac), (Reg) + 4), &Word);		\
+	pByte[2] = (SK_U8)(Word & 0x00ff);				\
+	pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);		\
+	SK_IN16(IoC, GMA((Mac), (Reg) + 8), &Word);		\
+	pByte[4] = (SK_U8)(Word & 0x00ff);				\
+	pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);		\
+	SK_IN16(IoC, GMA((Mac), (Reg) + 12), &Word);	\
+	pByte[6] = (SK_U8)(Word & 0x00ff);				\
+	pByte[7] = (SK_U8)((Word >> 8) & 0x00ff);		\
+	SK_IN8(IoC, B0_RAP, &Dummy);					\
+	SK_REL_SPIN_LOCK(IoC);							\
+}
+
+#define GM_OUTHASH(IoC, Mac, Reg, pVal) {			\
+	SK_U8	*pByte;									\
+	pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];			\
+	SK_OUT16(IoC, GMA((Mac), (Reg)), (SK_U16)		\
+		(((SK_U16)(pByte[0]) & 0x00ff) |			\
+		(((SK_U16)(pByte[1]) << 8) & 0xff00)));		\
+	SK_OUT16(IoC, GMA((Mac), (Reg) + 4), (SK_U16)	\
+		(((SK_U16)(pByte[2]) & 0x00ff) |			\
+		(((SK_U16)(pByte[3]) << 8) & 0xff00)));		\
+	SK_OUT16(IoC, GMA((Mac), (Reg) + 8), (SK_U16)	\
+		(((SK_U16)(pByte[4]) & 0x00ff) |			\
+		(((SK_U16)(pByte[5]) << 8) & 0xff00)));		\
+	SK_OUT16(IoC, GMA((Mac), (Reg) + 12), (SK_U16)	\
+		(((SK_U16)(pByte[6]) & 0x00ff)|				\
+		(((SK_U16)(pByte[7]) << 8) & 0xff00)));		\
+}
+
+/*
+ * Different MAC Types
+ */
+#define SK_MAC_XMAC		0	/* Xaqti XMAC II */
+#define SK_MAC_GMAC		1	/* Marvell GMAC */
+
+/*
+ * Different PHY Types
+ */
+#define SK_PHY_XMAC			0	/* integrated in XMAC II */
+#define SK_PHY_BCOM			1	/* Broadcom BCM5400 */
+#define SK_PHY_LONE			2	/* Level One LXT1000 */
+#define SK_PHY_NAT			3	/* National DP83891 */
+#define SK_PHY_MARV_COPPER	4	/* Marvell 88E1040S */
+#define SK_PHY_MARV_FIBER	5	/* Marvell 88E1040S working on fiber */
+
+/*
+ * PHY addresses (bits 12..8 of PHY address reg)
+ */
+#define PHY_ADDR_XMAC	(0<<8)
+#define PHY_ADDR_BCOM	(1<<8)
+#define PHY_ADDR_LONE	(3<<8)
+#define PHY_ADDR_NAT	(0<<8)
+
+/* GPHY address (bits 15..11 of SMI control reg) */
+#define PHY_ADDR_MARV	0
+
+/*
+ * macros to access the PHY
+ *
+ * PHY_READ()		read a 16 bit value from the PHY
+ * PHY_WRITE()		write a 16 bit value to the PHY
+ *
+ * para:
+ *	IoC		I/O context needed for SK I/O macros
+ *	pPort	Pointer to port struct for PhyAddr
+ *	Mac		XMAC to access		values: MAC_1 or MAC_2
+ *	PhyReg	PHY Register to read or write
+ *	(p)Val	Value or pointer to the value which should be read or
+ *			written.
+ *
+ * usage:	PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
+ * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
+ *	comes back. This is checked in DEBUG mode.
+ */
+#ifndef DEBUG
+#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
+	SK_U16 Mmu;															\
+																		\
+	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
+	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
+	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
+		do {															\
+			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
+		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
+		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
+	}																	\
+}
+#else
+#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
+	SK_U16 Mmu;															\
+	int __i = 0;														\
+																		\
+	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
+	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
+	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
+		do {															\
+			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
+			__i++;														\
+			if (__i > 100000) {											\
+				SK_DBG_PRINTF("*****************************\n");		\
+				SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n");		\
+				SK_DBG_PRINTF("*****************************\n");		\
+				break;													\
+			}															\
+		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
+		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
+	}																	\
+}
+#endif /* DEBUG */
+
+#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) {						\
+	SK_U16 Mmu;															\
+																		\
+	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
+		do {															\
+			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
+		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
+	}																	\
+	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
+	XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val));							\
+	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
+		do {															\
+			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
+		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
+	}																	\
+}
+
+/*
+ *	Macro PCI_C()
+ *
+ *	Use this macro to access PCI config register from the I/O space.
+ *
+ * para:
+ *	pAC		Pointer to adapter context
+ *	Addr	PCI configuration register to access.
+ *			Values:	PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
+ *
+ * usage	SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
+ * usage	SkPciReadCfgDWord(pAC, PCI_C1(pAC, PCI_VENDOR_ID), pVal);
+ * usage	SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_VENDOR_ID), pVal);
+ */
+#define PCI_C(p, Addr) \
+	(((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
+#ifdef YUK_USB		/* later for Yukon Optima 2 with USB */
+#define PCI_C1(pac, Addr)													\
+	(CHIP_ID_YUKON_OP_2 == (pac)->GIni.GIChipId ? (Addr) : ((Addr) % 0x300))
+#define PCI_C2(pac, ioc, Addr)												\
+	(CHIP_ID_YUKON_OP_2 == (pac)->GIni.GIChipId ?							\
+	(SK_OUT8(ioc, 6, (Addr) / 0x300 ^ 3), Y2_CFG_SPC + ((Addr) % 0x300)) :	\
+	(CHIP_ID_YUKON_2(pac) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr) % 0x300)
+#else	/* !YUK_USB */
+#define PCI_C1(pac, Addr)	(Addr)
+#define PCI_C2(pac, ioc, Addr) \
+	(((CHIP_ID_YUKON_2(pac)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
+#endif	/* !YUK_USB */
+
+/*
+ *	Macro SK_HW_ADDR(Base, Addr)
+ *
+ *	Calculates the effective HW address
+ *
+ * para:
+ *	Base	I/O or memory base address
+ *	Addr	Address offset
+ *
+ * usage:	May be used in SK_INxx and SK_OUTxx macros
+ *		#define SK_IN8(IoC, Addr, pVal) ...\
+ *			*pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
+ */
+#ifdef SK_MEM_MAPPED_IO
+#define SK_HW_ADDR(Base, Addr)	((Base) + (Addr))
+#else  /* SK_MEM_MAPPED_IO */
+#define SK_HW_ADDR(Base, Addr)	\
+			((Base) + (((Addr) & 0x7f) | (((Addr) >> 7 > 0) ? 0x80 : 0)))
+#endif /* SK_MEM_MAPPED_IO */
+
+#define SZ_LONG	(sizeof(SK_U32))
+
+/*
+ *	Macro SK_HWAC_LINK_LED()
+ *
+ *	Use this macro to set the link LED mode.
+ * para:
+ *	pAC		Pointer to adapter context struct
+ *	IoC		I/O context needed for SK I/O macros
+ *	Port	Port number
+ *	Mode	Mode to set for this LED
+ */
+#define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
+	SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
+
+#define SK_SET_GP_IO(IoC, Bit) {	\
+	SK_U32	DWord;					\
+	SK_IN32(IoC, B2_GP_IO, &DWord);	\
+	DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
+	SK_OUT32(IoC, B2_GP_IO, DWord);	\
+}
+
+#define SK_CLR_GP_IO(IoC, Bit) {	\
+	SK_U32	DWord;					\
+	SK_IN32(IoC, B2_GP_IO, &DWord);	\
+	DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
+	SK_OUT32(IoC, B2_GP_IO, DWord);	\
+}
+
+#define SK_TST_MODE_ON(IoC) {			\
+	SK_U8 TstCtl;						\
+	SK_IN8(IoC, B2_TST_CTRL1, &TstCtl);	\
+	TstCtl &= ~TST_CFG_WRITE_OFF;		\
+	TstCtl |= TST_CFG_WRITE_ON;			\
+	SK_OUT8(IoC, B2_TST_CTRL1, TstCtl);	\
+}
+
+#define SK_TST_MODE_OFF(IoC) {			\
+	SK_U8 TstCtl;						\
+	SK_IN8(IoC, B2_TST_CTRL1, &TstCtl);	\
+	TstCtl &= ~TST_CFG_WRITE_ON;		\
+	TstCtl |= TST_CFG_WRITE_OFF;		\
+	SK_OUT8(IoC, B2_TST_CTRL1, TstCtl);	\
+}
+
+/* enable timestamp LEs generation */
+#define SK_Y2_TIST_LE_ENA(IoC) \
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_LE_ENA)
+
+/* disable timestamp LEs generation */
+#define SK_Y2_TIST_LE_DIS(IoC) \
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_LE_DIS)
+
+#define SK_GE_PCI_FIFO_SIZE		1600	/* PCI FIFO Size */
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_SKGEHW_H */
+
diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h
--- linux/drivers/net/sk98lin/h/skgehwt.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgehwt.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,91 @@
+/******************************************************************************
+ *
+ * Name:	skhwt.h
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Defines for the hardware timer functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgehwt.h,v $
+ *	Revision 2.3  2007/07/31 12:58:09  rschmidt
+ *	Used SK_BOOL for HWT flag
+ *	Editorial changes
+ *	
+ *	Revision 2.2  2005/12/14 16:11:03  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.7  2003/09/16 12:55:08  rschmidt
+ *	Editorial changes
+ *
+ *	Revision 1.6  2003/05/13 17:57:48  mkarl
+ *	Editorial changes.
+ *
+ *	Revision 1.5  1999/11/22 13:54:24  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.4  1998/08/19 09:50:58  gklug
+ *	fix: remove struct keyword from C-code (see CCC) add typedefs
+ *
+ *	Revision 1.3  1998/08/14 07:09:29  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.2  1998/08/07 12:54:21  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.1  1998/08/07 09:32:58  gklug
+ *	first version
+ *
+ ******************************************************************************/
+
+/*
+ * SKGEHWT.H	contains all defines and types for the timer functions
+ */
+
+#ifndef _SKGEHWT_H_
+#define _SKGEHWT_H_
+
+/*
+ * SK Hardware Timer
+ * - needed wherever the HWT module is used
+ * - use in Adapters context name pAC->Hwt
+ */
+typedef	struct s_Hwt {
+	SK_U32		TStart;		/* HWT start */
+	SK_U32		TStop;		/* HWT stop */
+	SK_BOOL		TActive;	/* HWT: flag : active/inactive */
+} SK_HWT;
+
+extern void SkHwtInit(SK_AC *pAC, SK_IOC IoC);
+extern void SkHwtStart(SK_AC *pAC, SK_IOC IoC, SK_U32 Time);
+extern void SkHwtStop(SK_AC *pAC, SK_IOC IoC);
+extern SK_U32 SkHwtRead(SK_AC *pAC, SK_IOC IoC);
+extern void SkHwtIsr(SK_AC *pAC, SK_IOC IoC);
+#endif /* _SKGEHWT_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h
--- linux/drivers/net/sk98lin/h/skgeinit.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgeinit.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1342 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skgeinit.h#16 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #16 $, $Change: 6260 $
+ * Date:	$DateTime: 2011/05/11 11:40:08 $
+ * Purpose:	Structures and prototypes for the GE Init Module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKGEINIT_H_
+#define __INC_SKGEINIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ********************************************************************/
+
+#define SK_TEST_VAL		0x11335577UL
+
+/* modifying Link LED behaviour (used with SkGeLinkLED()) */
+#define SK_LNK_OFF		LED_OFF
+#define SK_LNK_ON		(LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
+#define SK_LNK_BLINK	(LED_ON | LED_BLK_ON  | LED_SYNC_ON)
+#define SK_LNK_PERM		(LED_ON | LED_BLK_OFF | LED_SYNC_ON)
+#define SK_LNK_TST		(LED_ON | LED_BLK_ON  | LED_SYNC_OFF)
+
+/* parameter 'Mode' when calling SK_HWAC_LINK_LED() */
+#define SK_LED_OFF		LED_OFF
+#define SK_LED_ACTIVE	(LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
+#define SK_LED_STANDBY	(LED_ON | LED_BLK_ON  | LED_SYNC_OFF)
+
+/* addressing LED Registers in SkGeXmitLED() */
+#define XMIT_LED_INI	0
+#define XMIT_LED_CNT	(RX_LED_VAL - RX_LED_INI)
+#define XMIT_LED_CTRL	(RX_LED_CTRL- RX_LED_INI)
+#define XMIT_LED_TST	(RX_LED_TST - RX_LED_INI)
+
+/* parameter 'Mode' when calling SkGeXmitLED() */
+#define SK_LED_DIS	0
+#define SK_LED_ENA	1
+#define SK_LED_TST	2
+
+/* Counter and Timer constants, for a host clock of 62.5 MHz */
+#define SK_XMIT_DUR		0x002faf08UL	/*  50 ms */
+#define SK_BLK_DUR		0x01dcd650UL	/* 500 ms */
+
+#define SK_DPOLL_DEF	0x00ee6b28UL	/* 250 ms at 62.5 MHz (Genesis) */
+#define SK_DPOLL_DEF_Y2	0x0000124fUL	/*  75 us (Yukon-2) */
+
+#define SK_DPOLL_MAX	0x00ffffffUL	/* 268 ms at 62.5 MHz */
+										/* 215 ms at 78.12 MHz (Yukon) */
+
+#define SK_FACT_62		100			/* default 62.5 MHz --> 100 % */
+#define SK_FACT_50		 80			/* on YUKON-FE+:  50 MHz */
+#define SK_FACT_53		 85			/* on GENESIS:	53.12 MHz */
+#define SK_FACT_78		125			/* on YUKON:	78.12 MHz */
+#define SK_FACT_100		160			/* on YUKON-FE:	 100 MHz */
+#define SK_FACT_125		200			/* on YUKON-EC:	 125 MHz */
+
+/* Timeout values */
+#define SK_MAC_TO_53	72			/* MAC arbiter timeout */
+#define SK_PKT_TO_53	0x2000		/* Packet arbiter timeout */
+#define SK_PKT_TO_MAX	0xffff		/* Maximum value */
+#define SK_RI_TO_53		36			/* RAM interface timeout */
+
+#define SK_PHY_ACC_TO	600000		/* PHY access timeout */
+
+/* RAM Buffer High Pause Threshold values */
+#define SK_RB_ULPP		( 8 * 1024)	/* Upper Level in kB/8 */
+#define SK_RB_LLPP_S	(10 * 1024)	/* Lower Level for small Queues */
+#define SK_RB_LLPP_B	(16 * 1024)	/* Lower Level for big Queues */
+
+/* Threshold values for Yukon-EC Ultra and Extreme */
+#define SK_ECU_ULPP		0x0080	/* Upper Pause Threshold (multiples of 8) */
+#define SK_DEV521_ULPP	0x00c4	/* Upper Pause Threshold for Dev. 5.21 */
+#define SK_ECU_LLPP		0x0060	/* Lower Pause Threshold (multiples of 8) */
+#define SK_ECU_AE_THR	0x0070	/* Almost Empty Threshold */
+#define SK_ECU_TXFF_LEV	0x01a0	/* Tx BMU FIFO Level */
+#define SK_ECU_JUMBO_WM	0x0400	/* Jumbo Mode Watermark */
+
+#define SK_EXT_ULPP		0x05c0	/* Upper Pause Threshold (multiples of 8) */
+
+#ifndef SK_BMU_RX_WM
+#define SK_BMU_RX_WM		0x600	/* BMU Rx Watermark */
+#endif
+
+#ifndef SK_BMU_TX_WM
+#define SK_BMU_TX_WM		0x600	/* BMU Tx Watermark */
+#endif
+
+/* performance sensitive drivers should set this define to 0x80 */
+#ifndef SK_BMU_RX_WM_PEX
+#define SK_BMU_RX_WM_PEX	0x80	/* BMU Rx Watermark for PEX */
+#endif
+
+/* XMAC II Rx High Watermark */
+#define SK_XM_RX_HI_WM	0x05aa		/* 1450 */
+
+/* XMAC II Tx Threshold */
+#define SK_XM_THR_REDL	0x01fb		/* .. for redundant link usage */
+#define SK_XM_THR_SL	0x01fb		/* .. for single link adapters */
+#define SK_XM_THR_MULL	0x01fb		/* .. for multiple link usage */
+#define SK_XM_THR_JUMBO	0x03fc		/* .. for jumbo frame usage */
+
+/* values for PortUsage */
+#define SK_RED_LINK		1		/* redundant link usage */
+#define SK_MUL_LINK		2		/* multiple link usage */
+#define SK_JUMBO_LINK	3		/* driver uses jumbo frames */
+
+/* Minimum RAM Buffer Rx Queue Size */
+#define SK_MIN_RXQ_SIZE	(((pAC)->GIni.GIYukon2) ? 10 : 16)		/* 10/16 kB */
+
+/* Minimum RAM Buffer Tx Queue Size */
+#define SK_MIN_TXQ_SIZE	(((pAC)->GIni.GIYukon2) ? 10 : 16)		/* 10/16 kB */
+
+/* Queue Size units (Genesis/Yukon) */
+#define QZ_UNITS		7
+#define QZ_STEP			8
+
+/* Queue Size units (Yukon-2) */
+#define QZ_STEP_Y2		1
+
+/* Percentage of queue size from whole memory */
+/* 80 % for receive */
+#define RAM_QUOTA_RX	80
+/*  0 % for sync transfer */
+#define RAM_QUOTA_SYNC	0
+/* the rest (20%) is taken for async transfer */
+
+/* Types of RAM Buffer Queues */
+#define SK_RX_SRAM_Q	1	/* small receive queue */
+#define SK_RX_BRAM_Q	2	/* big receive queue */
+#define SK_TX_RAM_Q		3	/* small or big transmit queue */
+
+/* parameter 'Dir' when calling SkGeStopPort() */
+#define SK_STOP_TX	1	/* Stops the transmit path, resets the XMAC */
+#define SK_STOP_RX	2	/* Stops the receive path */
+#define SK_STOP_ALL	3	/* Stops Rx and Tx path, resets the XMAC */
+
+/* parameter 'RstMode' when calling SkGeStopPort() */
+#define SK_SOFT_RST	1	/* perform a software reset */
+#define SK_HARD_RST	2	/* perform a hardware reset */
+
+/* Init Levels */
+#define SK_INIT_DATA	0	/* Init level 0: init data structures */
+#define SK_INIT_IO		1	/* Init level 1: init with IOs */
+#define SK_INIT_RUN		2	/* Init level 2: init for run time */
+
+/* Link Mode Parameter */
+#define SK_LMODE_HALF		1	/* Half Duplex Mode */
+#define SK_LMODE_FULL		2	/* Full Duplex Mode */
+#define SK_LMODE_AUTOHALF	3	/* AutoHalf Duplex Mode */
+#define SK_LMODE_AUTOFULL	4	/* AutoFull Duplex Mode */
+#define SK_LMODE_AUTOBOTH	5	/* AutoBoth Duplex Mode */
+#define SK_LMODE_AUTOSENSE	6	/* configured mode auto sensing */
+#define SK_LMODE_INDETERMINATED	7	/* indeterminated */
+
+/* Auto-negotiation timeout in 100ms granularity */
+#define SK_AND_MAX_TO		6	/* Wait 600 msec before link comes up */
+
+/* Auto-negotiation error codes */
+#define SK_AND_OK			0	/* no error */
+#define SK_AND_OTHER		1	/* other error than below */
+#define SK_AND_DUP_CAP		2	/* Duplex capabilities error */
+
+/* Link Speed Capabilities */
+#define SK_LSPEED_CAP_AUTO			BIT_0S	/* Automatic resolution */
+#define SK_LSPEED_CAP_10MBPS		BIT_1S	/* 10 Mbps */
+#define SK_LSPEED_CAP_100MBPS		BIT_2S	/* 100 Mbps */
+#define SK_LSPEED_CAP_1000MBPS		BIT_3S	/* 1000 Mbps */
+#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
+
+/* Link Speed Parameter */
+#define SK_LSPEED_AUTO				1	/* Automatic resolution */
+#define SK_LSPEED_10MBPS			2	/* 10 Mbps */
+#define SK_LSPEED_100MBPS			3	/* 100 Mbps */
+#define SK_LSPEED_1000MBPS			4	/* 1000 Mbps */
+#define SK_LSPEED_INDETERMINATED	5	/* indeterminated */
+
+/* Link Speed Current State */
+#define SK_LSPEED_STAT_UNKNOWN		1
+#define SK_LSPEED_STAT_10MBPS		2
+#define SK_LSPEED_STAT_100MBPS		3
+#define SK_LSPEED_STAT_1000MBPS		4
+#define SK_LSPEED_STAT_INDETERMINATED 5
+
+/* Link Capability Parameter */
+#define SK_LMODE_CAP_HALF		BIT_0S	/* Half Duplex Mode */
+#define SK_LMODE_CAP_FULL		BIT_1S	/* Full Duplex Mode */
+#define SK_LMODE_CAP_AUTOHALF	BIT_2S	/* AutoHalf Duplex Mode */
+#define SK_LMODE_CAP_AUTOFULL	BIT_3S	/* AutoFull Duplex Mode */
+#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
+
+/* Link Mode Current State */
+#define SK_LMODE_STAT_UNKNOWN	1	/* Unknown Duplex Mode */
+#define SK_LMODE_STAT_HALF		2	/* Half Duplex Mode */
+#define SK_LMODE_STAT_FULL		3	/* Full Duplex Mode */
+#define SK_LMODE_STAT_AUTOHALF	4	/* Half Duplex Mode obtained by Auto-Neg */
+#define SK_LMODE_STAT_AUTOFULL	5	/* Full Duplex Mode obtained by Auto-Neg */
+#define SK_LMODE_STAT_INDETERMINATED 6	/* indeterminated */
+
+/* Flow Control Mode Parameter (and capabilities) */
+#define SK_FLOW_MODE_NONE		1	/* No Flow Control */
+#define SK_FLOW_MODE_LOC_SEND	2	/* Local station sends PAUSE */
+#define SK_FLOW_MODE_SYMMETRIC	3	/* Both stations may send PAUSE */
+#define SK_FLOW_MODE_SYM_OR_REM	4	/* Both stations may send PAUSE or
+					 * just the remote station may send PAUSE
+					 */
+#define SK_FLOW_MODE_INDETERMINATED 5	/* indeterminated */
+
+/* Flow Control Status Parameter */
+#define SK_FLOW_STAT_NONE		1	/* No Flow Control */
+#define SK_FLOW_STAT_REM_SEND	2	/* Remote Station sends PAUSE */
+#define SK_FLOW_STAT_LOC_SEND	3	/* Local station sends PAUSE */
+#define SK_FLOW_STAT_SYMMETRIC	4	/* Both station may send PAUSE */
+#define SK_FLOW_STAT_INDETERMINATED 5	/* indeterminated */
+
+/* Master/Slave Mode Capabilities */
+#define SK_MS_CAP_AUTO		BIT_0S	/* Automatic resolution */
+#define SK_MS_CAP_MASTER	BIT_1S	/* This station is master */
+#define SK_MS_CAP_SLAVE		BIT_2S	/* This station is slave */
+#define SK_MS_CAP_INDETERMINATED BIT_3S	/* indeterminated */
+
+/* Set Master/Slave Mode Parameter (and capabilities) */
+#define SK_MS_MODE_AUTO		1	/* Automatic resolution */
+#define SK_MS_MODE_MASTER	2	/* This station is master */
+#define SK_MS_MODE_SLAVE	3	/* This station is slave */
+#define SK_MS_MODE_INDETERMINATED 4	/* indeterminated */
+
+/* Master/Slave Status Parameter */
+#define SK_MS_STAT_UNSET	1	/* The M/S status is not set */
+#define SK_MS_STAT_MASTER	2	/* This station is master */
+#define SK_MS_STAT_SLAVE	3	/* This station is slave */
+#define SK_MS_STAT_FAULT	4	/* M/S resolution failed */
+#define SK_MS_STAT_INDETERMINATED 5	/* indeterminated */
+
+/* parameter 'Mode' when calling SkMacSetRxCmd() */
+#define SK_STRIP_FCS_ON		BIT_0S	/* Enable  FCS stripping of Rx frames */
+#define SK_STRIP_FCS_OFF	BIT_1S	/* Disable FCS stripping of Rx frames */
+#define SK_STRIP_PAD_ON		BIT_2S	/* Enable  pad byte stripping of Rx fr */
+#define SK_STRIP_PAD_OFF	BIT_3S	/* Disable pad byte stripping of Rx fr */
+#define SK_LENERR_OK_ON		BIT_4S	/* Don't chk fr for in range len error */
+#define SK_LENERR_OK_OFF	BIT_5S	/* Check frames for in range len error */
+#define SK_BIG_PK_OK_ON		BIT_6S	/* Don't set Rx Error bit for big frames */
+#define SK_BIG_PK_OK_OFF	BIT_7S	/* Set Rx Error bit for big frames */
+#define SK_SELF_RX_ON		BIT_8S	/* Enable  Rx of own packets */
+#define SK_SELF_RX_OFF		BIT_9S	/* Disable Rx of own packets */
+
+/* parameter 'Para' when calling SkMacSetRxTxEn() */
+#define SK_MAC_LOOPB_ON		BIT_0S	/* Enable  MAC Loopback Mode */
+#define SK_MAC_LOOPB_OFF	BIT_1S	/* Disable MAC Loopback Mode */
+#define SK_PHY_LOOPB_ON		BIT_2S	/* Enable  PHY Loopback Mode */
+#define SK_PHY_LOOPB_OFF	BIT_3S	/* Disable PHY Loopback Mode */
+#define SK_PHY_FULLD_ON		BIT_4S	/* Enable  GMII Full Duplex */
+#define SK_PHY_FULLD_OFF	BIT_5S	/* Disable GMII Full Duplex */
+
+/* States of PState */
+#define SK_PRT_RESET	0	/* the port is reset */
+#define SK_PRT_STOP		1	/* the port is stopped (similar to SW reset) */
+#define SK_PRT_INIT		2	/* the port is initialized */
+#define SK_PRT_RUN		3	/* the port has an active link */
+
+/* PHY power down modes */
+#define PHY_PM_OPERATIONAL_MODE		0	/* PHY operational mode */
+#define PHY_PM_DEEP_SLEEP			1	/* Coma mode --> minimal power */
+#define PHY_PM_IEEE_POWER_DOWN		2	/* IEEE 22.2.4.1.5 compl. power down */
+#define PHY_PM_ENERGY_DETECT		3	/* Energy detect */
+#define PHY_PM_ENERGY_DETECT_PLUS	4	/* Energy detect plus */
+#define PHY_PM_POWER_STATE_MANAGER	5	/* Power State Manager (PSM) */
+
+/* PCI Bus Types */
+#define SK_PCI_BUS		BIT_0S		/* normal PCI bus */
+#define SK_PCIX_BUS		BIT_1S		/* PCI-X bus */
+#define SK_PEX_BUS		BIT_2S		/* PCI-Express bus */
+
+/* values for GILedBlinkCtrl (LED Blink Control) */
+#define SK_ACT_LED_BLINK	BIT_0S	/* Activity LED blinking */
+#define SK_DUP_LED_NORMAL	BIT_1S	/* Duplex LED normal */
+#define SK_LED_LINK100_ON	BIT_2S	/* Link 100M LED on */
+#define SK_DUAL_LED_ACT_LNK	BIT_3S	/* Dual LED ACT/LNK configuration */
+#define SK_LED_LINK_MUX_P60	BIT_4S	/* Link LED muxed to pin 60 */
+#define SK_LED_COMB_ACT_LNK	BIT_5S	/* Combined ACT/LNK LED mode */
+#define SK_ACT_LED_NOTR_OFF	BIT_6S	/* Activity LED off (no traffic) */
+
+/* Link Partner Status */
+#define SK_LIPA_UNKNOWN	0	/* Link partner is in unknown state */
+#define SK_LIPA_MANUAL	1	/* Link partner is in detected manual state */
+#define SK_LIPA_AUTO	2	/* Link partner is in auto-negotiation state */
+
+/* Maximum Restarts before restart is ignored (3Com WA) */
+#define SK_MAX_LRESTART	3	/* Max. 3 times the link is restarted */
+
+/* Max. Auto-neg. timeouts before link detection in sense mode is reset */
+#define SK_MAX_ANEG_TO	10	/* Max. 10 times the sense mode is reset */
+
+
+/******************************************************************************
+ *
+ * HW_FEATURE() macro
+ */
+
+/* DWORD 0: Features */
+#define HWF_ENA_POW_SAV_W_WOL	0x08000000UL /* Power saving with WOL ena. */
+#define HWF_FORCE_AUTO_NEG		0x04000000UL /* Force Auto-Negotiation */
+#define HWF_CLK_GATING_ENABLE	0x02000000UL /* Enable Clock Gating */
+#define HWF_RED_CORE_CLK_SUP	0x01000000UL /* Reduced Core Clock supp. */
+#define HWF_RESTORE_LOST_BARS	0x00800000UL /* Save and restore PCI BARs */
+#define HWF_ASPM_SWITCHING		0x00400000UL /* Activate ASPM feature */
+#define HWF_TX_IP_ID_INCR_ON	0x00200000UL /* Enable Tx IP ID Increment */
+#define HWF_ADV_CSUM_SUPPORT	0x00100000UL /* Sel Csum of IP and TCP/UDP */
+#define HWF_PSM_SUPPORTED		0x00080000UL /* Power State Manager support*/
+#define HWF_NEW_FLOW_CONTROL	0x00040000UL /* New Flow-Control support */
+#define HWF_HW_WOL_ENABLE		0x00020000UL /* Enable HW WOL */
+#define HWF_D0_CLK_GAT_ENABLE	0x00010000UL /* Enable D0 Clock Gating */
+#define HWF_TRAFO_LESS_ENABLE	0x00008000UL /* Enable PHY Transformer-less */
+#define HWF_PHY_CLASS_A_100BT	0x00004000UL /* Enable PHY Class A 100Base-T */
+#define HWF_DO_EEE_ENABLE		0x00002000UL /* Enable EEE support(default on)*/
+#define HWF_PHY_SET_SLAVE_MDIX	0x00001000UL /* Force PHY slave & MDIX */
+
+
+/*-RMV- DWORD 1: Deviations (all in use) */
+#define HWF_WA_DEV_4222			0x18000000UL /*-RMV- 4.222 (Done Idx rep.) */
+#define HWF_WA_DEV_56			0x14000000UL /*-RMV- 5.6 (Rx Chksum 0xffff)*/
+#define HWF_WA_DEV_54			0x12000000UL /*-RMV- 5.4 (Missing Status LE)*/
+#define HWF_WA_DEV_53			0x11000000UL /*-RMV- 5.3 (Tx Done LSOv2 rep)*/
+#define HWF_WA_DEV_LIM_IPV6_RSS	0x10800000UL /*-RMV- IPV6 RSS limitted */
+#define HWF_WA_DEV_4217			0x10400000UL /*-RMV- 4.217 (PCI-E blockage) */
+#define HWF_WA_DEV_4200			0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/
+#define HWF_WA_DEV_4185CS		0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/
+#define HWF_WA_DEV_4185			0x10080000UL /*-RMV- 4.185 (ECU Tx hang) */
+#define HWF_WA_DEV_4167			0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/
+#define HWF_WA_DEV_4152			0x10020000UL /*-RMV- 4.152 (RSS issue) */
+#define HWF_WA_DEV_4115			0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */
+#define HWF_WA_DEV_4109			0x10008000UL /*-RMV- 4.109 (BIU hang) */
+#define HWF_WA_DEV_483			0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */
+#define HWF_WA_DEV_479			0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */
+#define HWF_WA_DEV_472			0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */
+#define HWF_WA_DEV_463			0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */
+#define HWF_WA_DEV_427			0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */
+#define HWF_WA_DEV_42			0x10000200UL /*-RMV- 4.2 (pref unit burst) */
+#define HWF_WA_DEV_46			0x10000100UL /*-RMV- 4.6 (CPU crash II) */
+#define HWF_WA_DEV_43_418		0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */
+											 /*-RMV- compl&Stat BMU deadl) */
+#define HWF_WA_DEV_420			0x10000040UL /*-RMV- 4.20 (Status BMU ov) */
+#define HWF_WA_DEV_423			0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */
+#define HWF_WA_DEV_424			0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */
+#define HWF_WA_DEV_425			0x10000008UL /*-RMV- 4.25 (Magic packet */
+											 /*-RMV- with odd offset) */
+#define HWF_WA_DEV_428			0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi) */
+#define HWF_WA_FIFO_FLUSH_YLA0	0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush */
+											 /*-RMV- for Yu-L Rev. A0 only */
+#define HWF_WA_COMA_MODE		0x10000001UL /*-RMV- Coma Mode WA req */
+
+/*-RMV- DWORD 2: Deviations */
+#define HWF_WA_DEV_563			0x20002000UL /*-RMV- 5.63 (L4 CSUM IPV6 TX) */
+#define HWF_WA_DEV_547			0x20001000UL /*-RMV- 5.47 (IRQ + clk gating) */
+#define HWF_WA_DEV_548			0x20000800UL /*-RMV- 5.48 (IPv4 Header CS) */
+#define HWF_WA_DEV_4216			0x20000400UL /*-RMV- 4.216 (fragm. IPV4+RSS) */
+#define HWF_WA_DEV_519			0x20000200UL /*-RMV- 5.19 (MACsec: unexp. LE) */
+#define HWF_WA_DEV_517			0x20000100UL /*-RMV- 5.17 (MACsec+FlowThrough)*/
+#define HWF_WA_DEV_515			0x20000080UL /*-RMV- 5.15 (MACsec TX underr) */
+#define HWF_WA_DEV_542			0x20000040UL /*-RMV- 5.42 (CPU CLK + Flash) */
+#define HWF_WA_DEV_4229			0x20000020UL /*-RMV- 4.229 (RSS + VLAN) */
+#define HWF_WA_DEV_521			0x20000010UL /*-RMV- 5.21 (wrong RFSW) */
+#define HWF_WA_DEV_520			0x20000008UL /*-RMV- 5.20 (Tx lost of data) */
+#define HWF_WA_DEV_511			0x20000004UL /*-RMV- 5.11 (Tx Underrun) */
+#define HWF_WA_DEV_510			0x20000002UL /*-RMV- 5.10 (Tx Checksum) */
+#define HWF_WA_DEV_51			0x20000001UL /*-RMV- 5.1 (MACSec sync) */
+
+#if 0
+#define HWF_SYNC_TX_SUP			0x20800000UL /* Synch. Tx Queue available */
+#define HWF_SINGLE_PORT_DEVICE	0x20400000UL /* Device has only one LAN IF */
+#define HWF_JUMBO_FRAMES_SUP	0x20200000UL /* Jumbo Frames supported */
+#define HWF_TX_TCP_CSUM_SUP		0x20100000UL /* TCP Tx checksum supported */
+#define HWF_TX_UDP_CSUM_SUP		0x20080000UL /* UDP Tx checksum supported */
+#define HWF_RX_CSUM_SUP			0x20040000UL /* RX checksum supported */
+#define HWF_TCP_SEGM_SUP		0x20020000UL /* TCP segmentation supported */
+#define HWF_RSS_HASH_SUP		0x20010000UL /* RSS Hash supported */
+#define HWF_PORT_VLAN_SUP		0x20008000UL /* VLAN can be config per port*/
+#define HWF_ROLE_PARAM_SUP		0x20004000UL /* Role parameter supported */
+#define HWF_LOW_PMODE_SUP		0x20002000UL /* Low Power Mode supported */
+#define HWF_ENERGIE_DEMO_SUP	0x20001000UL /* Energy Detect mode supp. */
+#define HWF_SPEED1000_SUP		0x20000800UL /* Line Speed 1000 supported */
+#define HWF_SPEED100_SUP		0x20000400UL /* Line Speed 100 supported */
+#define HWF_SPEED10_SUP			0x20000200UL /* Line Speed 10 supported */
+#define HWF_AUTONEGSENSE_SUP	0x20000100UL /* Autoneg Sense supported */
+#define HWF_PHY_LOOPB_MD_SUP	0x20000080UL /* PHY loopback mode supp. */
+#define HWF_ASF_SUP				0x20000040UL /* ASF support possible */
+#define HWF_QS_STEPS_1KB		0x20000020UL /* The Rx/Tx queues can be */
+											 /* configured with 1 kB res. */
+#define HWF_OWN_RAM_PER_PORT	0x20000010UL /* Each port has a separate */
+											 /* RAM buffer */
+#define HWF_MIN_LED_IF			0x20000008UL /* Minimal LED interface */
+											 /* (e.g. for Yukon-EC) */
+#define HWF_LIST_ELEMENTS_USED	0x20000004UL /* HW uses list elements */
+											 /* (otherwise desc. are used) */
+#define HWF_GMAC_INSIDE			0x20000002UL /* Device contains GMAC */
+#define HWF_TWSI_PRESENT		0x20000001UL /* TWSI sensor bus present */
+#endif
+
+/* DWORD 3: still unused */
+
+
+/*
+ * HW_FEATURE()	-	returns whether the feature is serviced or not
+ */
+#define HW_FEATURE(pAC, ReqFeature) \
+	(((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
+	 ((ReqFeature) & 0x0fffffffUL)) != 0)
+
+#define HW_FEAT_LIST	0
+#define HW_DEV_LIST		1
+#define HW_DEV_LIST_2	2
+
+#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) {	\
+	if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) {			\
+		(pAC)->GIni.HwF.OffMask[List] = (OffMaskValue);				\
+		(pAC)->GIni.HwF.OnMask[List] = (OnMaskValue);				\
+	}																\
+}
+
+/* driver access macros for GIni structure ***********************************/
+
+#define CHIP_ID_YUKON_2(pAC)		((pAC)->GIni.GIYukon2)
+
+#define HW_SYNC_TX_SUPPORTED(pAC)					\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON		||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL)
+
+#define HW_HAS_NEWER_PHY(pAC)						\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX	||	\
+	 (pAC)->GIni.GIChipId >= CHIP_ID_YUKON_SUPR)
+
+#define HW_MS_TO_TICKS(pAC, MsTime) \
+	((MsTime) * (1000UL * (pAC)->GIni.GIHstClkFact * SK_FACT_62) / SK_FACT_100)
+
+#define HW_TICKS_TO_USEC(pAC, HwTicks) \
+	((HwTicks) / ((((pAC)->GIni.GIHstClkFact) * SK_FACT_62) / SK_FACT_100))
+
+#define HW_IS_EXT_LE_FORMAT(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_IS_NEW_ASF_FORMAT(pAC)	((pAC)->GIni.GIExtLeFormat)
+
+/* Is RAM buffer available? */
+#define HW_IS_RAM_IF_AVAIL(pAC)						\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON		||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC	||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_FE)
+
+#define HW_NUM_OF_PATTERN(pAC)	((pAC)->GIni.GINumOfPattern)
+
+#define HW_OTP_SUPPORTED(pAC)						\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_FE_P ||	\
+	 (pAC)->GIni.GIChipId >= CHIP_ID_YUKON_UL_2)
+
+/* general CSUM */
+/* flag to distinguish between old style and new style csum offload */
+#define HW_SUP_FULL_OFFLOAD(pAC)		((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_NEW_LSOV1(pAC)			((pAC)->GIni.GIExtLeFormat)
+
+/* Rx CSUM IPv4 */
+#define HW_SUP_RX_CSUM_IPV4(pAC)		SK_TRUE
+#define HW_SUP_RX_CSUM_OPT_IPV4(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_RX_CSUM_TCPIPV4(pAC)		SK_TRUE
+#define HW_SUP_RX_CSUM_OPT_TCPIPV4(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_RX_CSUM_UDPIPV4(pAC)		SK_TRUE
+
+/* Rx CSUM IPv6 */
+#define HW_SUP_RX_CSUM_IPV6_EXT_HDR(pAC)((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_RX_CSUM_TCPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_RX_CSUM_OPT_TCPIPV6(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_RX_CSUM_UDPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)
+
+/* Tx CSUM IPv4 */
+#define HW_SUP_TX_CSUM_IPV4(pAC)		((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_OPT_IPV4(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_TCPIPV4(pAC)		(!HW_FEATURE(pAC, HWF_WA_DEV_4185CS))
+#define HW_SUP_TX_CSUM_OPT_TCPIPV4(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_UDPIPV4(pAC)		(!HW_FEATURE(pAC, HWF_WA_DEV_4185CS))
+/* Tx CSUM IPv6 */
+#define HW_SUP_TX_CSUM_IPV6_EXT_HDR(pAC)((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_TCPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_OPT_TCPIPV6(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_TX_CSUM_UDPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)
+
+/* Tx CSUM special flag for FIFO size */
+#define HW_SUP_TX_CSUM_FOR_JUMBO(pAC)			\
+	((pAC)->GIni.GIJumTcpSegSup ||				\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON ||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE)
+
+/* LSO */
+#define HW_SUP_LSOV1(pAC)				((pAC)->GIni.GIYukon2)
+#define HW_SUP_OPT_IPV4_LSOV1(pAC)		((pAC)->GIni.GIYukon2)
+#define HW_SUP_OPT_TCPIPV4_LSOV1(pAC)	((pAC)->GIni.GIYukon2)
+#define HW_SUP_LSOV2(pAC)				((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_IPV6_EXT_HDR_LSOV2(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_OPT_TCPIPV6_LSOV2(pAC)	((pAC)->GIni.GIExtLeFormat)
+#define HW_SUP_LSO_FOR_JUMBO(pAC)		((pAC)->GIni.GIJumTcpSegSup)
+
+/* RSS */
+#define HW_SUP_IPV4_RSS(pAC)									\
+	((pAC)->GIni.GIYukon2 && !HW_FEATURE(pAC, HWF_WA_DEV_4152))
+
+/*
+ * IPV6_RSS is supported since Yukon-Extreme B0
+ * To avoid that IPV6 RSS is executed on Extreme A0 (which is obsolete already)
+ * the HW_SUM_IPV6_RSS condition needs to be combined with the term
+ * "&& !HW_FEATURE(pAC, HWF_WA_DEV_LIM_IPV6_RSS)"
+ */
+#define HW_SUP_IPV6_RSS(pAC)			((pAC)->GIni.GIExtLeFormat)
+
+/* MACSec */
+#define HW_SUP_MACSEC(pAC)							\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX ||	\
+	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_SUPR)
+
+/* AVB */
+#define HW_SUP_AVB(pAC)								\
+	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_OPT &&	\
+	 (pAC)->GIni.GIChipId <= CHIP_ID_YUKON_OP_2)
+
+/* PTP */
+#define HW_SUP_PTP(pAC)								\
+	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_OPT &&	\
+	 (pAC)->GIni.GIChipId <= CHIP_ID_YUKON_OP_2)
+
+/* Network Presence */
+#define HW_SUP_NETWORK_PRESENCE(pAC)				\
+	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_PRM &&	\
+	 (pAC)->GIni.GIChipId <= CHIP_ID_YUKON_OP_2)
+
+/* EEE */
+#define HW_SUP_EEE(pAC)				\
+	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_PRM &&	\
+	 (pAC)->GIni.GIChipId <= CHIP_ID_YUKON_OP_2)
+
+#define AVB_LE_Q_CNT	8	/* Number of available AVB LE queues */
+#define AVB_MAC_Q_CNT	5	/* Number of available AVB MAC FIFO queues */
+#define AVB_CLS_CNT		2	/* Number of available AVB classes */
+
+/* VPD Support */
+#define HW_SUP_VPD(pAC)							\
+	((pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE_P)
+
+/* SPI PROM Support */
+#define HW_SUP_SPI_PROM(pAC)						\
+	((pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE_P &&	\
+	 (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE)
+
+/* Battery Power Management */
+#define HW_NO_BAT_POW_MANAGEMENT(pAC)				\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&	\
+	 (pAC)->GIni.GIChipRev > CHIP_REV_YU_EC_U_A0 &&	\
+	 (pAC)->GIni.GIChipCap == 2 &&					\
+	 !HW_FEATURE(pAC, HWF_WA_DEV_4200))
+
+/* maximal supported link speed; returns 100 or 1000 */
+#define HW_MAX_LINE_SPEED(pAC)							\
+	((pAC)->GIni.GP[MAC_1].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS ? 1000 : 100)
+
+/* Hardware has free usable Timestamp Timer */
+#define HW_SUP_FREE_TS_TIMER(pAC)						\
+	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_FE_P ||		\
+	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX &&		\
+	((pAC)->GIni.GIChipCap & CHIP_CAP_MSK_EX_B1) == 0))
+
+/* structures *****************************************************************/
+
+/*
+ * HW Feature structure
+ */
+typedef struct s_HwFeatures {
+	SK_U32	Features[4];	/* Feature list */
+	SK_U32	OffMask[4];		/* Off Mask */
+	SK_U32	OnMask[4];		/* On Mask */
+} SK_HW_FEATURES;
+
+/*
+ * MAC specific functions
+ */
+typedef struct s_GeMacFunc {
+	int	(*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
+	int	(*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
+	int	(*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
+	int	(*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
+	void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
+#ifdef SK_DIAG
+	int	(*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
+	int	(*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
+#endif /* SK_DIAG */
+} SK_GEMACFUNC;
+
+/*
+ * Port Structure
+ */
+typedef struct s_GePort {
+#ifndef SK_DIAG
+	SK_TIMER	PWaTimer;	/* Workaround Timer */
+	SK_TIMER	PPauseTimer;/* Pause Packet Timer */
+	SK_U32		PPauseTxCnt;/* Pause Packet Counter (Tx) */
+	SK_BOOL		PPauseFlag;	/* Pause Packet Flag */
+#endif /* !SK_DIAG */
+	int		PRxQSize;		/* Port Rx Queue Size in kB */
+	int		PXSQSize;		/* Port Synchronous  Transmit Queue Size in kB */
+	int		PXAQSize;		/* Port Asynchronous Transmit Queue Size in kB */
+	SK_U32	PRxQRamStart;	/* Receive Queue RAM Buffer Start Address */
+	SK_U32	PRxQRamEnd;		/* Receive Queue RAM Buffer End Address */
+	SK_U32	PXsQRamStart;	/* Sync Tx Queue RAM Buffer Start Address */
+	SK_U32	PXsQRamEnd;		/* Sync Tx Queue RAM Buffer End Address */
+	SK_U32	PXaQRamStart;	/* Async Tx Queue RAM Buffer Start Address */
+	SK_U32	PXaQRamEnd;		/* Async Tx Queue RAM Buffer End Address */
+#ifndef SK_SLIM
+	SK_U32	PRxOverCnt;		/* Receive Overflow Counter */
+#endif
+	int		PRxQOff;		/* Rx Queue Address Offset */
+	int		PXsQOff;		/* Synchronous Tx Queue Address Offset */
+	int		PXaQOff;		/* Asynchronous Tx Queue Address Offset */
+	int		PAvbQOffs[AVB_LE_Q_CNT];			/* AVB Tx queues Offsets          */
+	int		PAvbMacQOffs[AVB_MAC_Q_CNT];		/* AVB MAC FIFO Tx queues Offsets */
+	int		PAvbClsQOffs[AVB_CLS_CNT];			/* AVB Classes offsets            */
+	int		PhyType;		/* PHY used on this port */
+	int		PState;			/* Port status (reset, stop, init, run) */
+	int		PPortUsage;		/* Driver Port Usage */
+	SK_U16	PhyId1;			/* PHY Id1 on this port */
+	SK_U16	PhyAddr;		/* MDIO/MDC PHY address */
+	SK_BOOL	PHWLinkUp;		/* The hardware Link is up (wiring) */
+	SK_BOOL	PPhyQLink;		/* PHY Quick Link detected */
+	SK_BOOL	PRevAutoNeg;	/* PHY Reverse Auto-negotiation */
+	SK_BOOL	PCheckPar;		/* Do we check for parity errors ? */
+	SK_U8	PLinkModeConf;	/* Link Mode configured */
+	SK_U8	PLinkMode;		/* Link Mode currently used */
+	SK_U8	PLinkModeStatus;/* Link Mode Status */
+	SK_U8	PLinkSpeedCap;	/* Link Speed Capabilities (10/100/1000 Mbps) */
+	SK_U8	PLinkSpeed;		/* configured Link Speed (10/100/1000 Mbps) */
+	SK_U8	PLinkSpeedUsed;	/* current Link Speed (10/100/1000 Mbps) */
+	SK_U8	PFlowCtrlMode;	/* Flow Control Mode */
+	SK_U8	PFlowCtrlStatus;/* Flow Control Status */
+#ifndef SK_SLIM
+	SK_U8	PLinkCap;		/* Link Capabilities */
+	SK_U8	PFlowCtrlCap;	/* Flow Control Capabilities */
+	SK_U8	PMSCap;			/* Master/Slave Capabilities */
+	SK_U16	PLipaAbil;		/* Link Partner Ability */
+#endif
+	SK_U8	PMSMode;		/* Master/Slave Mode */
+	SK_U8	PMSStatus;		/* Master/Slave Status */
+	SK_BOOL	PEnDetMode;		/* Energy Detect Mode */
+	SK_BOOL	PAutoNegFail;	/* Auto-negotiation fail flag */
+	SK_U8	PLipaAutoNeg;	/* Auto-negotiation possible with Link Partner */
+	SK_U8	PPhyPowerState;	/* PHY current power state */
+	SK_U16	PMacAddr[3];	/* MAC address */
+#ifndef SK_SLIM
+	SK_U8	PCableLen;		/* Cable Length */
+	SK_U8	PMdiPairLen[4];	/* MDI[0..3] Pair Length */
+	SK_U8	PMdiPairSts[4];	/* MDI[0..3] Pair Diagnostic Status */
+	int		PMacColThres;	/* MAC Collision Threshold */
+	int		PMacBackOffLim;	/* MAC Back-off Limit */
+	int		PMacJamIpgData;	/* MAC IPG Jam to Data */
+	int		PMacJamIpgVal;	/* MAC Jam IPG */
+	int		PMacJamLen;		/* MAC Jam length */
+	int		PMacDataBlind;	/* MAC Data Blinder */
+	int		PMacIpgData_1G;	/* MAC Data IPG for 1000 Mbps */
+	int		PMacIpgData_FE;	/* MAC Data IPG for 10/100 Mbps */
+	SK_BOOL PMacLimit4;		/* reset collision counter and backoff algorithm */
+#endif
+} SK_GEPORT;
+
+/*
+ * Configuration Data Structure
+ */
+typedef union s_Cfg{
+	struct {
+		SK_U32 ValidConfig:1;
+		SK_U32 MemoryType:1;
+		SK_U32 reserved_1:2;
+		SK_U32 LED_Scheme:4;
+		SK_U32 WakeFromS5:1;
+		SK_U32 HW_WoLAN:1;
+		SK_U32 reserved_2:2;
+		SK_U32 EnergyScheme:4;
+		SK_U32 reserved_3:4;
+		SK_U32 AutoNegScheme:2;
+		SK_U32 MonSpeedStep:1;
+		SK_U32 SmartSpeed:1;
+		SK_U32 WakeUpSpeed:2;
+		SK_U32 DynClockGating:1;
+		SK_U32 reserved_4:5;
+	} fields;
+
+	struct {
+		SK_U32 D00:1;
+		SK_U32 D01:1;
+		SK_U32 D02:1;
+		SK_U32 D03:1;
+		SK_U32 D04:1;
+		SK_U32 D05:1;
+		SK_U32 D06:1;
+		SK_U32 D07:1;
+		SK_U32 D08:1;
+		SK_U32 D09:1;
+		SK_U32 D10:1;
+		SK_U32 D11:1;
+		SK_U32 D12:1;
+		SK_U32 D13:1;
+		SK_U32 D14:1;
+		SK_U32 D15:1;
+		SK_U32 D16:1;
+		SK_U32 D17:1;
+		SK_U32 D18:1;
+		SK_U32 D19:1;
+		SK_U32 D20:1;
+		SK_U32 D21:1;
+		SK_U32 D22:1;
+		SK_U32 D23:1;
+		SK_U32 D24:1;
+		SK_U32 D25:1;
+		SK_U32 D26:1;
+		SK_U32 D27:1;
+		SK_U32 D28:1;
+		SK_U32 D29:1;
+		SK_U32 D30:1;
+		SK_U32 D31:1;
+	} bits;
+
+	SK_U32 ApplicConfigVal;
+} SK_APP_CONF;
+
+typedef struct s_AppConfData {
+	int		WakeUpSpeedSel;		/* WakeUp Speed Sel. (10M / 100M / Rev. AN) */
+	int		EnergySaveScheme;	/* Energy Saving Scheme (0..4) */
+	int		LED_SchemeSel;		/* LED Scheme Selection (0..5) */
+	int		AutoNegSchemeSel;	/* Auto-Negotiation Scheme (normal/forced) */
+	SK_BOOL	DynClockGatingEn;	/* Dynamic Clock Gating Enable */
+	SK_BOOL	SmartSpeedDownEn;	/* Smart Speed Down Enable */
+	SK_BOOL	MonitorSpeedStepEn;	/* Monitor Speed Step Enable */
+	SK_BOOL	HW_WakeOnLAN_En;	/* HW Wake-on-LAN Enable */
+	SK_BOOL	WakeFromShutdownEn;	/* Wake From Shutdown (S5) Enable */
+	SK_BOOL	MemoryTypeInternal;	/* Memory Type (internal/external) */
+	SK_BOOL	ValidConfiguration;	/* Valid Configuration Flag */
+} SK_APP_CONFIG;
+
+/*
+ * Gigabit Ethernet Initialization Struct
+ * (has to be included in the adapter context)
+ */
+typedef struct s_GeInit {
+	int			GIChipId;		/* Chip Identification Number */
+	int			GIChipRev;		/* Chip Revision Number */
+	SK_U8		GIPciHwRev;		/* PCI HW Revision Number */
+	SK_U8		GIPciBus;		/* PCI Bus Type (PCI / PCI-X / PCI-Express) */
+	SK_U8		GIPciMode;		/* PCI / PCI-X Mode @ Clock */
+	SK_U8		GIPexWidth;		/* PCI-Express Negotiated Link Width */
+	SK_BOOL		GIYukonLite;	/* YUKON-Lite chip */
+	SK_BOOL		GIYukon2;		/* YUKON-2 chip (-XL, -EC or -FE) */
+	SK_U8		GIConTyp;		/* Connector Type */
+	SK_U8		GIPmdTyp;		/* PMD Type */
+	SK_BOOL		GICopperType;	/* Copper Type adapter ? */
+	SK_BOOL		GIPciSlot64;	/* 64-bit PCI Slot */
+	SK_BOOL		GIPciClock66;	/* 66 MHz PCI Clock */
+	SK_BOOL		GIVauxAvail;	/* VAUX available (YUKON) */
+	SK_BOOL		GIVMainAvail;	/* VMAIN available */
+	SK_BOOL		GIYukon32Bit;	/* 32-Bit YUKON adapter */
+	SK_BOOL		GIAsfEnabled;	/* ASF subsystem enabled */
+	SK_BOOL		GIAsfRunning;	/* ASF subsystem running */
+	SK_BOOL		GIExtLeFormat;	/* Extended LE format (Yukon-Ext) */
+	SK_BOOL		GIDontInitPhy;	/* Don't Initialize PHY */
+	SK_BOOL		GIVlanPkt;
+	SK_BOOL		GIVlanIns;
+	SK_BOOL		GIVlanStrp;
+#ifndef SK_SLIM
+	SK_BOOL		GIJumTcpSegSup;	/* TCP Segmentation of Jumbo frames supp. ? */
+#endif
+#ifdef SK_PHY_LP_MODE
+	SK_BOOL		GIGotoD3Cold;	/* System set to D3cold */
+#endif
+	SK_U16		GILedBlinkCtrl;	/* LED Blink Control */
+	SK_U16		GIPexLinkCtrl;	/* PCI-Express Link Control */
+	int			GIMacsFound;	/* Number of MACs found on this adapter */
+	int			GIMacType;		/* MAC Type used on this adapter */
+	int			GIChipCap;		/* Adapter's Capabilities */
+	int			GIHwResInfo;	/* HW Resources / Application Information */
+	int			GIHstClkFact;	/* Host Clock Factor (HstClk / 62.5 * 100) */
+	int			GILevel;		/* Initialization Level completed */
+	int			GIRamSize;		/* The RAM size of the adapter in kB */
+	int			GIPexCapOffs;	/* PCI-E Capability Reg Off (moved in Y-Ex B0)*/
+#ifndef SK_SLIM
+	int			GIWolOffs;		/* WOL Register Offset (HW-Bug in Rev. A) */
+	int			GINumOfPattern;	/* Number of Pattern supported by HW */
+	int			GINumOfRssKeys;	/* Number of supported RSS keys */
+	int			GITxIdxRepThres;/* Tx Index reporting threshold */
+#endif
+	SK_U32		GIRamOffs;		/* RAM Address Offset for addr calculation */
+	SK_U32		GIPollTimerVal;	/* Descr. Poll Timer Init Val (HstClk ticks) */
+	SK_U32		GIValIrqMask;	/* Value for Interrupt Mask */
+	SK_U32		GIValHwIrqMask;	/* Value for HWE Interrupt Mask */
+#ifndef SK_SLIM
+	SK_U32		GITimeStampCnt;	/* Time Stamp High Counter (YUKON only) */
+	SK_U32		GIPhyInitTime;	/* Time Stamp on PHY Init */
+#endif
+	SK_GEPORT	GP[SK_MAX_MACS];/* Port Dependent Information */
+	SK_HW_FEATURES	HwF;		/* HW Features struct */
+	SK_APP_CONF		CfgVal;		/* Application Configuration Value */
+	SK_APP_CONFIG	CfgData;	/* Application Configuration Structure */
+	SK_GEMACFUNC	GIFunc;		/* MAC depedent functions */
+} SK_GEINIT;
+
+/*
+ * Error numbers and messages for skxmac2.c and skgeinit.c
+ */
+#define SKERR_HWI_E001		(SK_ERRBASE_HWINIT+1)
+#define SKERR_HWI_E001MSG	"SkXmClrExactAddr() has got illegal parameters"
+#define SKERR_HWI_E002		(SKERR_HWI_E001+1)
+#define SKERR_HWI_E002MSG	"SkGeInit(): Level 1 call missing"
+#define SKERR_HWI_E003		(SKERR_HWI_E002+1)
+#define SKERR_HWI_E003MSG	"SkGeInit() called with illegal init Level"
+#define SKERR_HWI_E004		(SKERR_HWI_E003+1)
+#define SKERR_HWI_E004MSG	"SkGeInitPort(): Queue Size illegal configured"
+#define SKERR_HWI_E005		(SKERR_HWI_E004+1)
+#define SKERR_HWI_E005MSG	"SkGeInitPort(): cannot init running ports"
+#define SKERR_HWI_E006		(SKERR_HWI_E005+1)
+#define SKERR_HWI_E006MSG	"SkGeInit() called with illegal Chip Id"
+#define SKERR_HWI_E007		(SKERR_HWI_E006+1)
+#define SKERR_HWI_E007MSG	"SkXmInitDupMd() called with invalid Dup Mode"
+#define SKERR_HWI_E008		(SKERR_HWI_E007+1)
+#define SKERR_HWI_E008MSG	"SkXmSetRxCmd() called with invalid Mode"
+#define SKERR_HWI_E009		(SKERR_HWI_E008+1)
+#define SKERR_HWI_E009MSG	"SkGeCfgSync() called although PXSQSize zero"
+#define SKERR_HWI_E010		(SKERR_HWI_E009+1)
+#define SKERR_HWI_E010MSG	"SkGeCfgSync() called with invalid parameters"
+#define SKERR_HWI_E011		(SKERR_HWI_E010+1)
+#define SKERR_HWI_E011MSG	"SkGeInitPort(): Receive Queue Size too small"
+#define SKERR_HWI_E012		(SKERR_HWI_E011+1)
+#define SKERR_HWI_E012MSG	"SkGeInitPort(): invalid Queue Size specified"
+#define SKERR_HWI_E013		(SKERR_HWI_E012+1)
+#define SKERR_HWI_E013MSG	"SkGeInitPort(): cfg changed for running queue"
+#define SKERR_HWI_E014		(SKERR_HWI_E013+1)
+#define SKERR_HWI_E014MSG	"SkGeInitPort(): unknown PortUsage specified"
+#define SKERR_HWI_E015		(SKERR_HWI_E014+1)
+#define SKERR_HWI_E015MSG	"Illegal Link Mode parameter"
+#define SKERR_HWI_E016		(SKERR_HWI_E015+1)
+#define SKERR_HWI_E016MSG	"Illegal Flow Control Mode parameter"
+#define SKERR_HWI_E017		(SKERR_HWI_E016+1)
+#define SKERR_HWI_E017MSG	"Illegal value specified for GIPollTimerVal"
+#define SKERR_HWI_E018		(SKERR_HWI_E017+1)
+#define SKERR_HWI_E018MSG	"FATAL: SkGeStopPort() does not terminate (Tx)"
+#define SKERR_HWI_E019		(SKERR_HWI_E018+1)
+#define SKERR_HWI_E019MSG	"Illegal Speed parameter"
+#define SKERR_HWI_E020		(SKERR_HWI_E019+1)
+#define SKERR_HWI_E020MSG	"Illegal Master/Slave parameter"
+#define SKERR_HWI_E021		(SKERR_HWI_E020+1)
+#define SKERR_HWI_E021MSG	"MacUpdateStats(): cannot update statistic counter"
+#define SKERR_HWI_E022		(SKERR_HWI_E021+1)
+#define SKERR_HWI_E022MSG	"MacStatistic(): illegal statistic base address"
+#define SKERR_HWI_E023		(SKERR_HWI_E022+1)
+#define SKERR_HWI_E023MSG	"SkGeInitPort(): Transmit Queue Size too small"
+#define SKERR_HWI_E024		(SKERR_HWI_E023+1)
+#define SKERR_HWI_E024MSG	"FATAL: SkGeStopPort() does not terminate (Rx)"
+#define SKERR_HWI_E025		(SKERR_HWI_E024+1)
+#define SKERR_HWI_E025MSG	"Link Partner not Auto-Neg. able"
+#define SKERR_HWI_E026		(SKERR_HWI_E025+1)
+#define SKERR_HWI_E026MSG	"PEX negotiated Link width not max."
+#define SKERR_HWI_E027		(SKERR_HWI_E026+1)
+#define SKERR_HWI_E027MSG	""
+
+/* function prototypes *******************************************************/
+
+#ifndef	SK_KR_PROTO
+
+/*
+ * public functions in skgeinit.c
+ */
+extern void SkGePortVlan(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL Enable);
+
+extern void SkGeMacSecLE(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+
+extern void SkGeRxRss(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+
+extern void SkGeRxCsum(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL Enable);
+
+#ifndef DISABLE_YUKON_I
+extern void	SkGePollRxD(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	PollRxD);
+
+extern void	SkGePollTxD(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL PollTxD);
+#endif /* !DISABLE_YUKON_I */
+
+extern void	SkGeYellowLED(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		State);
+
+extern void	SkGeStopPort(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Dir,
+	int		RstMode);
+
+extern int	SkGeInit(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Level);
+
+extern void	SkGeDeInit(
+	SK_AC	*pAC,
+	SK_IOC	IoC);
+
+extern int	SkGeInitPort(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkGeInitRamIface(
+	SK_AC	*pAC,
+	SK_IOC	IoC);
+
+extern int	SkGeInitAssignRamToQueues(
+	SK_AC	*pAC,
+	int		Port,
+	SK_BOOL	DualNet);
+
+extern void	DoInitRamQueue(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		QuIoOffs,
+	SK_U32	QuStartAddr,
+	SK_U32	QuEndAddr,
+	int		QuType);
+
+extern int	SkYuk2RestartRxBmu(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void SkYuk2StopTx(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+extern void SkYuk2StartTx(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern SK_U32 SkHwGetTimeDelta(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	Start);
+
+#if defined(SK_POWER_MGMT) || defined(SK_DIAG)
+extern void SkGeRamRead(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	Addr,
+	SK_U32	*pLowDword,
+	SK_U32	*pHighDword,
+	int		RamSelect);
+
+extern void SkGeRamWrite(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U32	Addr,
+	SK_U32	LowDword,
+	SK_U32	HighDword,
+	int		RamSelect);
+#endif	/* SK_POWER_MGMT || SK_DIAG */
+
+/*
+ * public functions in skxmac2.c
+ */
+extern void SkMacRxTxDisable(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacSoftRst(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacHardRst(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacClearRst(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkGmInitMac(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void SkMacInitPhy(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	DoLoop);
+
+extern void SkMacIrqDisable(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacIrq(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern int	SkMacAutoNegDone(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacAutoNegLipaPhy(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_U16	IStatus);
+
+extern void	SkMacSetRxTxEn(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Para);
+
+extern int	SkMacRxTxEnable(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+extern void	SkMacPromiscMode(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+
+extern void	SkMacHashing(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+
+extern void	SkMacTimeStamp(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+
+extern int	SkGmPhyRead(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	SK_FAR *pVal);
+
+extern int	SkGmPhyWrite(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	Val);
+
+extern int SkGmMacStatistic(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int Port,
+	SK_U16	StatAddr,
+	SK_U32	SK_FAR *pVal);
+
+extern int SkGmResetCounter(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int Port);
+
+extern int SkGmOverflowStatus(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int Port,
+	SK_U16	MacStatus,
+	SK_U64	SK_FAR *pStatus);
+
+#ifndef SK_SLIM
+extern int	SkGmPtpRead(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	*pVal);
+
+extern int	SkGmPtpReadDbl(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U32	*pVal);
+
+extern int	SkGmPtpWrite(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	Val);
+
+extern int SkGmUpdateStats(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int Port);
+
+extern int SkGmCableDiagStatus(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	StartTest);
+#endif /* !SK_SLIM */
+
+#ifdef SK_PHY_LP_MODE
+extern int SkGmEnterLowPowerMode(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_U8	Mode);
+
+extern int SkGmLeaveLowPowerMode(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+#endif /* SK_PHY_LP_MODE */
+
+#ifdef SK_DIAG
+extern void	SkGePhyRead(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	*pVal);
+
+extern void	SkGePhyWrite(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Addr,
+	SK_U16	Val);
+
+extern void	SkMacSetRxCmd(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		Mode);
+extern void	SkMacCrcGener(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+extern void	SkGmSendCont(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	SK_BOOL	Enable);
+extern int	SkGmReadPhyTempSensor(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port,
+	int		*pVal);
+#endif /* SK_DIAG */
+
+extern SK_BOOL SkYuk2AVBModeEnabled(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port);
+extern void SkYuk2AVBControl(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	SK_BOOL Enable);
+void SkYuk2SetQueueDataRate(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	int Queue,
+	SK_U32 DataRate);
+
+void SkYuk2SetClassDataRates(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	int		Port);
+
+void SkYuk2AvbSetQueueClass(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	int Queue,
+	SK_U32 Class);
+void SkYuk2AvbSetQueuePriority(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	int Queue,
+	SK_U32 Priority);
+void SkYuk2AvbSetLeQueue(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	int Pfu,
+	int Queue);
+void SkYuk2AvbSetLePriority(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	int Port,
+	int Pfu,
+	int Queue);
+void RegisterSelectiveSetReset(
+	SK_AC *pAC,
+	SK_IOC IoC,
+	SK_U32 Register,
+	SK_U32 BitsToSet,
+	SK_U32 BitsToClear);
+#else	/* SK_KR_PROTO */
+
+/*
+ * public functions in skgeinit.c
+ */
+#ifndef DISABLE_YUKON_I
+extern void	SkGePollRxD();
+extern void	SkGePollTxD();
+#endif /* !DISABLE_YUKON_I */
+extern void	SkGeYellowLED();
+extern void	SkGeStopPort();
+extern int	SkGeInit();
+extern void	SkGeDeInit();
+extern int	SkGeInitPort();
+extern void	SkGeInitRamIface();
+extern int	SkGeInitAssignRamToQueues();
+extern void	SkGePortVlan();
+extern void	SkGeRxCsum();
+extern void	SkGeMacSecLE();
+extern void	SkGeRxRss();
+extern void	DoInitRamQueue();
+extern int	SkYuk2RestartRxBmu();
+extern void SkYuk2StopTx();
+extern void SkYuk2StartTx();
+extern SK_U32 SkHwGetTimeDelta();
+
+/*
+ * public functions in skxmac2.c
+ */
+extern void	SkMacRxTxDisable();
+extern void	SkMacSoftRst();
+extern void	SkMacHardRst();
+extern void	SkMacClearRst();
+extern void	SkMacInitPhy();
+extern int	SkMacRxTxEnable();
+extern void	SkMacPromiscMode();
+extern void	SkMacHashing();
+extern void	SkMacIrqDisable();
+extern void	SkMacIrq();
+extern int	SkMacAutoNegDone();
+extern void	SkMacAutoNegLipaPhy();
+extern void	SkMacSetRxTxEn();
+extern void	SkMacTimeStamp();
+extern void	SkGmInitMac();
+extern int	SkGmPhyRead();
+extern int	SkGmPhyWrite();
+extern int	SkGmMacStatistic();
+extern int	SkGmResetCounter();
+extern int	SkGmOverflowStatus();
+
+#ifndef SK_SLIM
+extern int	SkGmPtpRead();
+extern int	SkGmPtpReadDbl();
+extern int	SkGmPtpWrite();
+extern int	SkGmUpdateStats();
+extern int	SkGmCableDiagStatus();
+#endif /* !SK_SLIM */
+
+#ifdef SK_PHY_LP_MODE
+extern int	SkGmEnterLowPowerMode();
+extern int	SkGmLeaveLowPowerMode();
+#endif /* SK_PHY_LP_MODE */
+
+#ifdef SK_DIAG
+extern void	SkGePhyRead();
+extern void	SkGePhyWrite();
+extern void	SkMacSetRxCmd();
+extern void	SkMacCrcGener();
+extern void	SkGmSendCont();
+extern int	SkGmReadPhyTempSensor();
+#endif /* SK_DIAG */
+
+#endif /* SK_KR_PROTO */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_SKGEINIT_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h
--- linux/drivers/net/sk98lin/h/skgepnm2.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgepnm2.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,515 @@
+/*****************************************************************************
+ *
+ * Name:	skgepnm2.h
+ * Project:	Gigabit Ethernet Adapters, PNMI-Module
+ * Version:	$Revision: #7 $
+ * Date:	$Date: 2010/11/10 $
+ * Purpose:	Defines for Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgepnm2.h,v $
+ *	Revision 2.8  2010/03/23 16:22:33  tschilli
+ *	Added missing PNMI chipset defines used for pAC->Pnmi.Chipset in SkPnmiInit().
+ *	
+ *	Revision 2.7  2009/10/27 08:24:08  tschilli
+ *	Added changes to support compilation without RMLT (SK_NO_RLMT)
+ *	
+ *	Revision 2.6  2007/01/17 15:15:23  rschmidt
+ *	Editorial changes
+ *	
+ *	Revision 2.5  2005/12/14 16:11:19  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.4  2005/05/03 06:42:43  tschilli
+ *	Added missing defines for OID_SKGE_CHIPSET.
+ *
+ *	Revision 2.3  2004/03/19 16:19:59  tschilli
+ *	Merged the changes of revision 1.37.
+ *
+ *	Revision 2.2  2003/11/24 13:27:37  mkarl
+ *	Semicolon added after SK_DBG_MSG.
+ *
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.37  2004/01/02 12:01:22  rschmidt
+ *	Editorial changes.
+ *
+ *	Revision 1.36  2003/05/23 12:45:13  tschilli
+ *	#ifndef SK_PNMI_HUNDREDS_SEC added to SK_PNMI_HUNDREDS_SEC definition
+ *	to allow own time macro defines.
+ *
+ *	Revision 1.35  2003/03/27 11:27:48  tschilli
+ *	Copyright messages changed.
+ *
+ *	Revision 1.34  2002/12/16 09:05:18  tschilli
+ *	Code for VCT handling added.
+ *
+ *	Revision 1.33  2002/09/10 09:00:03  rwahl
+ *	Adapted boolean definitions according sktypes.
+ *
+ *	Revision 1.32  2002/08/09 09:47:01  rwahl
+ *	Added write-only flag to oid access defines.
+ *	Editorial changes.
+ *
+ *	Revision 1.31  2002/07/17 19:23:18  rwahl
+ *	- Replaced MAC counter definitions by enumeration.
+ *	- Added definition SK_PNMI_MAC_TYPES.
+ *	- Added chipset defnition for Yukon.
+ *
+ *	Revision 1.30  2001/02/06 10:03:41  mkunz
+ *	- Pnmi V4 dual net support added. Interface functions and macros extended
+ *	- Vpd bug fixed
+ *	- OID_SKGE_MTU added
+ *
+ *	Revision 1.29  2001/01/22 13:41:37  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *
+ *	Revision 1.28  2000/08/03 15:12:48  rwahl
+ *	- Additional comment for MAC statistic data structure.
+ *
+ *	Revision 1.27  2000/08/01 16:10:18  rwahl
+ *	- Added mac statistic data structure for StatRxLongFrame counter.
+ *
+ *	Revision 1.26  2000/03/31 13:51:34  rwahl
+ *	Added SK_UPTR cast to offset calculation for PNMI struct fields;
+ *	missing cast caused compiler warnings by Win64 compiler.
+ *
+ *	Revision 1.25  1999/11/22 13:57:41  cgoos
+ *	Changed license header to GPL.
+ *	Allowing overwrite for SK_PNMI_STORE/_READ defines.
+ *
+ *	Revision 1.24  1999/04/13 15:11:11  mhaveman
+ *	Changed copyright.
+ *
+ *	Revision 1.23  1999/01/28 15:07:12  mhaveman
+ *	Changed default threshold for port switches per hour from 10
+ *	to 240 which means 4 switches per minute. This fits better
+ *	the granularity of 32 for the port switch estimate counter.
+ *
+ *	Revision 1.22  1999/01/05 12:52:30  mhaveman
+ *	Removed macro SK_PNMI_MICRO_SEC.
+ *
+ *	Revision 1.21  1999/01/05 12:50:34  mhaveman
+ *	Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit
+ *	arithmetic is necessary if SK_TICKS_PER_SEC is 100.
+ *
+ *	Revision 1.20  1998/12/09 14:02:53  mhaveman
+ *	Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch threshold.
+ *
+ *	Revision 1.19  1998/12/03 11:28:41  mhaveman
+ *	Removed SK_PNMI_CHECKPTR macro.
+ *
+ *	Revision 1.18  1998/12/03 11:21:00  mhaveman
+ *	-Added pointer check macro SK_PNMI_CHECKPTR
+ *	-Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for
+ *	 VPD key evaluation.
+ *
+ *	Revision 1.17  1998/11/20 13:20:33  mhaveman
+ *	Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set.
+ *
+ *	Revision 1.16  1998/11/20 08:08:49  mhaveman
+ *	Macro SK_PNMI_CHECKFLAGS has got a if clause.
+ *
+ *	Revision 1.15  1998/11/03 13:53:40  mhaveman
+ *	Fixed alignment problem in SK_PNMI_SET_STAT macro.
+ *
+ *	Revision 1.14  1998/10/30 15:50:13  mhaveman
+ *	Added macro SK_PNMI_MICRO_SEC()
+ *
+ *	Revision 1.13  1998/10/30 12:32:20  mhaveman
+ *	Added forgotten cast in SK_PNMI_READ_U32 macro.
+ *
+ *	Revision 1.12  1998/10/29 15:40:26  mhaveman
+ *	-Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now
+ *	 variable string length.
+ *	-Defined SK_PNMI_CHECKFLAGS macro
+ *
+ *	Revision 1.11  1998/10/29 08:53:34  mhaveman
+ *	Removed SK_PNMI_RLM_XXX table indexed because these counters need
+ *	not been saved over XMAC resets.
+ *
+ *	Revision 1.10  1998/10/28 08:48:20  mhaveman
+ *	-Added macros for storage according to alignment
+ *	-Changed type of Instance to SK_U32 because of VPD
+ *	-Removed trap structures. Not needed because of alignment problem
+ *	-Changed type of Action form SK_U8 to int
+ *
+ *	Revision 1.9  1998/10/21 13:34:45  mhaveman
+ *	Fixed mismatched calculation of SK_PNMI_HUNDREDS_SEC.
+ *
+ *	Revision 1.8  1998/10/21 13:24:58  mhaveman
+ *	Changed calculation of hundreds of seconds.
+ *
+ *	Revision 1.7  1998/10/20 07:31:41  mhaveman
+ *	Made type changes to unsigned int where possible.
+ *
+ *	Revision 1.6  1998/09/04 17:04:05  mhaveman
+ *	Added Sync counters to offset storage to provided settled values on
+ *	port switch.
+ *
+ *	Revision 1.5  1998/09/04 12:45:35  mhaveman
+ *	Removed dummies for SK_DRIVER_ macros. They should be added by driver
+ *	writer in skdrv2nd.h.
+ *
+ *	Revision 1.4  1998/09/04 11:59:50  mhaveman
+ *	Everything compiles now. Driver Macros for counting still missing.
+ *
+ *	Revision 1.3  1998/08/24 12:01:35  mhaveman
+ *	Intermediate state.
+ *
+ *	Revision 1.2  1998/08/17 07:51:40  mhaveman
+ *	Intermediate state.
+ *
+ *	Revision 1.1  1998/08/11 09:08:40  mhaveman
+ *	Intermediate state.
+ *
+ *****************************************************************************/
+
+#ifndef _SKGEPNM2_H_
+#define _SKGEPNM2_H_
+
+/*
+ * General definitions
+ */
+#define SK_PNMI_CHIPSET_XMAC		1	/* XMAC11800FP */
+#define SK_PNMI_CHIPSET_YUKON		2	/* YUKON */
+#define SK_PNMI_CHIPSET_YUKON_LITE	3	/* YUKON-Lite (Rev. A1-A3) */
+#define SK_PNMI_CHIPSET_YUKON_LP	4	/* YUKON-LP */
+#define SK_PNMI_CHIPSET_YUKON_XL	5	/* YUKON-2 XL */
+#define SK_PNMI_CHIPSET_YUKON_EC	6	/* YUKON-2 EC */
+#define SK_PNMI_CHIPSET_YUKON_FE	7	/* YUKON-2 FE */
+#define SK_PNMI_CHIPSET_YUKON_FE_P	8	/* YUKON-2 FE+ */
+#define SK_PNMI_CHIPSET_YUKON_EC_U	9	/* YUKON-2 EC Ultra */
+#define SK_PNMI_CHIPSET_YUKON_EX	10	/* YUKON-2 Extreme */
+#define SK_PNMI_CHIPSET_YUKON_SUPR	11	/* YUKON-2 Supreme */
+#define SK_PNMI_CHIPSET_YUKON_UL_2	12	/* YUKON-2 Ultra 2 */
+#define SK_PNMI_CHIPSET_YUKON_OPT	13	/* YUKON-2 Optima */
+#define SK_PNMI_CHIPSET_YUKON_PRM	14	/* YUKON-2 Optima Prime */
+
+#define SK_PNMI_BUS_PCI		1	/* PCI bus*/
+
+/*
+ * Actions
+ */
+#define SK_PNMI_ACT_IDLE		1
+#define SK_PNMI_ACT_RESET		2
+#define SK_PNMI_ACT_SELFTEST	3
+#define SK_PNMI_ACT_RESETCNT	4
+
+/*
+ * VPD releated defines
+ */
+
+#define SK_PNMI_VPD_RW		1
+#define SK_PNMI_VPD_RO		2
+
+#define SK_PNMI_VPD_OK			0
+#define SK_PNMI_VPD_NOTFOUND	1
+#define SK_PNMI_VPD_CUT			2
+#define SK_PNMI_VPD_TIMEOUT		3
+#define SK_PNMI_VPD_FULL		4
+#define SK_PNMI_VPD_NOWRITE		5
+#define SK_PNMI_VPD_FATAL		6
+
+#define SK_PNMI_VPD_IGNORE	0
+#define SK_PNMI_VPD_CREATE	1
+#define SK_PNMI_VPD_DELETE	2
+
+
+/*
+ * RLMT related defines
+ */
+#define SK_PNMI_DEF_RLMT_CHG_THRES	240	/* 4 changes per minute */
+
+
+/*
+ * VCT internal status values
+ */
+#define SK_PNMI_VCT_PENDING		0x20
+#define SK_PNMI_VCT_TEST_DONE	0x40
+#define SK_PNMI_VCT_LINK		0x80
+
+/*
+ * Internal table definitions
+ */
+#define SK_PNMI_GET		0
+#define SK_PNMI_PRESET	1
+#define SK_PNMI_SET		2
+
+#define SK_PNMI_RO		0
+#define SK_PNMI_RW		1
+#define SK_PNMI_WO		2
+
+typedef struct s_OidTabEntry {
+	SK_U32			Id;
+	SK_U32			InstanceNo;
+	unsigned int	StructSize;
+	unsigned int	Offset;
+	int				Access;
+	int				(* Func)(SK_AC *pAc, SK_IOC pIo, int action,
+							 SK_U32 Id, char* pBuf, unsigned int* pLen,
+							 SK_U32 Instance, unsigned int TableIndex,
+							 SK_U32 NetNumber);
+	SK_U16			Param;
+} SK_PNMI_TAB_ENTRY;
+
+
+/*
+ * Trap lengths
+ */
+#define SK_PNMI_TRAP_SIMPLE_LEN			17
+#define SK_PNMI_TRAP_SENSOR_LEN_BASE	46
+#define SK_PNMI_TRAP_RLMT_CHANGE_LEN	23
+#define SK_PNMI_TRAP_RLMT_PORT_LEN		23
+
+/*
+ * Number of MAC types supported
+ */
+#define SK_PNMI_MAC_TYPES	(SK_MAC_GMAC + 1)
+
+/*
+ * MAC statistic data list (overall set for MAC types used)
+ */
+enum SK_MACSTATS {
+	SK_PNMI_HTX				= 0,
+	SK_PNMI_HTX_OCTET,
+	SK_PNMI_HTX_OCTETHIGH 	= SK_PNMI_HTX_OCTET,
+	SK_PNMI_HTX_OCTETLOW,
+	SK_PNMI_HTX_BROADCAST,
+	SK_PNMI_HTX_MULTICAST,
+	SK_PNMI_HTX_UNICAST,
+	SK_PNMI_HTX_BURST,
+	SK_PNMI_HTX_PMACC,
+	SK_PNMI_HTX_MACC,
+	SK_PNMI_HTX_COL,
+	SK_PNMI_HTX_SINGLE_COL,
+	SK_PNMI_HTX_MULTI_COL,
+	SK_PNMI_HTX_EXCESS_COL,
+	SK_PNMI_HTX_LATE_COL,
+	SK_PNMI_HTX_DEFFERAL,
+	SK_PNMI_HTX_EXCESS_DEF,
+	SK_PNMI_HTX_UNDERRUN,
+	SK_PNMI_HTX_CARRIER,
+	SK_PNMI_HTX_UTILUNDER,
+	SK_PNMI_HTX_UTILOVER,
+	SK_PNMI_HTX_64,
+	SK_PNMI_HTX_127,
+	SK_PNMI_HTX_255,
+	SK_PNMI_HTX_511,
+	SK_PNMI_HTX_1023,
+	SK_PNMI_HTX_MAX,
+	SK_PNMI_HTX_LONGFRAMES,
+	SK_PNMI_HTX_SYNC,
+	SK_PNMI_HTX_SYNC_OCTET,
+	SK_PNMI_HTX_RESERVED,
+
+	SK_PNMI_HRX,
+	SK_PNMI_HRX_OCTET,
+	SK_PNMI_HRX_OCTETHIGH	= SK_PNMI_HRX_OCTET,
+	SK_PNMI_HRX_OCTETLOW,
+	SK_PNMI_HRX_BADOCTET,
+	SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET,
+	SK_PNMI_HRX_BADOCTETLOW,
+	SK_PNMI_HRX_BROADCAST,
+	SK_PNMI_HRX_MULTICAST,
+	SK_PNMI_HRX_UNICAST,
+	SK_PNMI_HRX_PMACC,
+	SK_PNMI_HRX_MACC,
+	SK_PNMI_HRX_PMACC_ERR,
+	SK_PNMI_HRX_MACC_UNKWN,
+	SK_PNMI_HRX_BURST,
+	SK_PNMI_HRX_MISSED,
+	SK_PNMI_HRX_FRAMING,
+	SK_PNMI_HRX_UNDERSIZE,
+	SK_PNMI_HRX_OVERFLOW,
+	SK_PNMI_HRX_JABBER,
+	SK_PNMI_HRX_CARRIER,
+	SK_PNMI_HRX_IRLENGTH,
+	SK_PNMI_HRX_SYMBOL,
+	SK_PNMI_HRX_SHORTS,
+	SK_PNMI_HRX_RUNT,
+	SK_PNMI_HRX_TOO_LONG,
+	SK_PNMI_HRX_FCS,
+	SK_PNMI_HRX_CEXT,
+	SK_PNMI_HRX_UTILUNDER,
+	SK_PNMI_HRX_UTILOVER,
+	SK_PNMI_HRX_64,
+	SK_PNMI_HRX_127,
+	SK_PNMI_HRX_255,
+	SK_PNMI_HRX_511,
+	SK_PNMI_HRX_1023,
+	SK_PNMI_HRX_MAX,
+	SK_PNMI_HRX_LONGFRAMES,
+
+	SK_PNMI_HRX_RESERVED,
+
+	SK_PNMI_MAX_IDX		/* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */
+};
+
+/*
+ * MAC specific data
+ */
+typedef struct s_PnmiStatAddr {
+	SK_U16		Reg;		/* MAC register containing the value */
+	SK_BOOL		GetOffset;	/* TRUE: Offset managed by PNMI (GetStatVal()) */
+} SK_PNMI_STATADDR;
+
+
+/*
+ * SK_PNMI_STRUCT_DATA copy offset evaluation macros
+ */
+#define SK_PNMI_OFF(e)		((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
+#define SK_PNMI_MAI_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
+#define SK_PNMI_VPD_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e))
+#define SK_PNMI_SEN_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e))
+#define SK_PNMI_CHK_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e))
+#define SK_PNMI_STA_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e))
+#define SK_PNMI_CNF_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e))
+#ifndef SK_NO_RLMT
+#define SK_PNMI_RLM_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e))
+#define SK_PNMI_MON_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e))
+#endif
+#define SK_PNMI_TRP_OFF(e)	((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e))
+
+#define SK_PNMI_SET_STAT(b,s,o)	{SK_U32	Val32; char *pVal; \
+					Val32 = (s); \
+					pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
+						&(((SK_PNMI_STRUCT_DATA *)0)-> \
+						ReturnStatus.ErrorStatus)); \
+					SK_PNMI_STORE_U32(pVal, Val32); \
+					Val32 = (o); \
+					pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
+						&(((SK_PNMI_STRUCT_DATA *)0)-> \
+						ReturnStatus.ErrorOffset)); \
+					SK_PNMI_STORE_U32(pVal, Val32);}
+
+/*
+ * Time macros
+ */
+#ifndef SK_PNMI_HUNDREDS_SEC
+#if SK_TICKS_PER_SEC == 100
+#define SK_PNMI_HUNDREDS_SEC(t)	(t)
+#else
+#define SK_PNMI_HUNDREDS_SEC(t)	(((t) * 100) / (SK_TICKS_PER_SEC))
+#endif /* !SK_TICKS_PER_SEC */
+#endif /* !SK_PNMI_HUNDREDS_SEC */
+
+/*
+ * Macros to work around alignment problems
+ */
+#ifndef SK_PNMI_STORE_U16
+#define SK_PNMI_STORE_U16(p,v)	{*(char *)(p) = *((char *)&(v)); \
+					*((char *)(p) + 1) = \
+						*(((char *)&(v)) + 1);}
+#endif
+
+#ifndef SK_PNMI_STORE_U32
+#define SK_PNMI_STORE_U32(p,v)	{*(char *)(p) = *((char *)&(v)); \
+					*((char *)(p) + 1) = \
+						*(((char *)&(v)) + 1); \
+					*((char *)(p) + 2) = \
+						*(((char *)&(v)) + 2); \
+					*((char *)(p) + 3) = \
+						*(((char *)&(v)) + 3);}
+#endif
+
+#ifndef SK_PNMI_STORE_U64
+#define SK_PNMI_STORE_U64(p,v)	{*(char *)(p) = *((char *)&(v)); \
+					*((char *)(p) + 1) = \
+						*(((char *)&(v)) + 1); \
+					*((char *)(p) + 2) = \
+						*(((char *)&(v)) + 2); \
+					*((char *)(p) + 3) = \
+						*(((char *)&(v)) + 3); \
+					*((char *)(p) + 4) = \
+						*(((char *)&(v)) + 4); \
+					*((char *)(p) + 5) = \
+						*(((char *)&(v)) + 5); \
+					*((char *)(p) + 6) = \
+						*(((char *)&(v)) + 6); \
+					*((char *)(p) + 7) = \
+						*(((char *)&(v)) + 7);}
+#endif
+
+#ifndef SK_PNMI_READ_U16
+#define SK_PNMI_READ_U16(p,v)	{*((char *)&(v)) = *(char *)(p); \
+					*(((char *)&(v)) + 1) = \
+						*((char *)(p) + 1);}
+#endif
+
+#ifndef SK_PNMI_READ_U32
+#define SK_PNMI_READ_U32(p,v)	{*((char *)&(v)) = *(char *)(p); \
+					*(((char *)&(v)) + 1) = \
+						*((char *)(p) + 1); \
+					*(((char *)&(v)) + 2) = \
+						*((char *)(p) + 2); \
+					*(((char *)&(v)) + 3) = \
+						*((char *)(p) + 3);}
+#endif
+
+#ifndef SK_PNMI_READ_U64
+#define SK_PNMI_READ_U64(p,v)	{*((char *)&(v)) = *(char *)(p); \
+					*(((char *)&(v)) + 1) = \
+						*((char *)(p) + 1); \
+					*(((char *)&(v)) + 2) = \
+						*((char *)(p) + 2); \
+					*(((char *)&(v)) + 3) = \
+						*((char *)(p) + 3); \
+					*(((char *)&(v)) + 4) = \
+						*((char *)(p) + 4); \
+					*(((char *)&(v)) + 5) = \
+						*((char *)(p) + 5); \
+					*(((char *)&(v)) + 6) = \
+						*((char *)(p) + 6); \
+					*(((char *)&(v)) + 7) = \
+						*((char *)(p) + 7);}
+#endif
+
+/*
+ * Macros for Debug
+ */
+#ifdef DEBUG
+
+#define SK_PNMI_CHECKFLAGS(vSt)	{if (pAC->Pnmi.MacUpdatedFlag > 0 || \
+					pAC->Pnmi.RlmtUpdatedFlag > 0 || \
+					pAC->Pnmi.SirqUpdatedFlag > 0) { \
+						SK_DBG_MSG(pAC, \
+						SK_DBGMOD_PNMI, \
+						SK_DBGCAT_CTRL,	\
+						("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \
+						vSt, \
+						pAC->Pnmi.MacUpdatedFlag, \
+						pAC->Pnmi.RlmtUpdatedFlag, \
+						pAC->Pnmi.SirqUpdatedFlag));}}
+
+#else	/* !DEBUG */
+
+#define SK_PNMI_CHECKFLAGS(vSt)	/* Nothing */
+
+#endif	/* !DEBUG */
+
+#endif	/* _SKGEPNM2_H_ */
diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h
--- linux/drivers/net/sk98lin/h/skgepnmi.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgepnmi.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1400 @@
+/*****************************************************************************
+ *
+ * Name:	skgepnmi.h
+ * Project:	Gigabit Ethernet Adapters, PNMI-Module
+ * Version:	$Revision: #9 $
+ * Date:	$Date: 2011/02/03 $
+ * Purpose:	Defines for Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgepnmi.h,v $
+ *	Revision 2.26  2010/04/29 14:26:52  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_OS_VERSION_INFO_SET.
+ *
+ *	Revision 2.25  2010/03/23 16:23:51  tschilli
+ *	Added define Sk_NO_RLMT in struct SK_PNMI_STRUCT_DATA to fix offset mismatch.
+ *
+ *	Revision 2.24  2009/10/27 08:23:53  tschilli
+ *	Added changes to support compilation without RMLT (SK_NO_RLMT)
+ *
+ *	Revision 2.23  2009/02/19 14:38:32  omater
+ *	add OID_SKGE_MACSEC_CONFIGURATION
+ *
+ *	Revision 2.22  2008/09/12 13:45:11  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_IP_INFO_EXT and OID_SKGE_ASF_DASH_SPECIAL_ACTION.
+ *
+ *	Revision 2.21  2008/08/07 12:50:36  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_IP_INFO.
+ *
+ *	Revision 2.20  2008/03/06 14:16:17  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_MAX_USER.
+ *
+ *	Revision 2.19  2008/02/27 16:07:28  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_USER_DAT and OID_SKGE_ASF_DASH_BUSY.
+ *
+ *	Revision 2.18  2008/01/15 13:09:15  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_CAP and OID_SKGE_ASF_DASH_ENA.
+ *
+ *	Revision 2.17  2007/09/03 14:45:02  tschilli
+ *	Fixed C++ comments.
+ *
+ *	Revision 2.16  2007/09/03 14:17:32  mkunz
+ *	Changes required for VCT handling.
+ *
+ *	Revision 2.15  2007/03/28 13:45:25  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_FW_REMOVE
+ *	- OID_SKGE_ASF_CHECK_SPI
+ *
+ *	Revision 2.14  2007/01/12 10:28:32  rschmidt
+ *	Renamed and incremented SK_PNMI_VCT_SUPPORTED
+ *	Editorial changes.
+ *
+ *	Revision 2.13  2006/11/21 09:55:25  pweber
+ *	Added defines SK_PNMI_OID_PSET and SK_PNMI_OID_SET needed for the SET OID path
+ *	(via IOCTL) under Vista
+ *
+ *	Revision 2.12  2005/12/14 16:11:19  ibrueder
+ *	added copyright header flags
+ *
+ *	Revision 2.11  2005/08/09 09:02:12  tschilli
+ *	Added VpdKeyReadError to struct SK_PNMI.
+ *
+ *	Revision 2.10  2005/07/12 09:07:14  mkunz
+ *	Added OIDs for Intermediate drivers in Windows.
+ *
+ *	Revision 2.9  2004/10/26 12:42:39  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_FWVER_OID
+ *	- OID_SKGE_ASF_ACPI_OID
+ *	- OID_SKGE_ASF_SMBUS_OID
+ *
+ *	Revision 2.8  2004/06/14 06:55:26  tschilli
+ *	VCT OID added:
+ *	- OID_SKGE_VCT_CAPABILITIES
+ *	New defines for OID_SKGE_VCT_CAPABILITIES added:
+ *	- SK_PNMI_VCT_SUPPORTED
+ *	- SK_PNMI_VCT_NOT_SUPPORTED
+ *	New define for VCT cable status added:
+ *	- SK_PNMI_VCT_NOT_PRESENT
+ *
+ *	Revision 2.7  2004/05/13 13:48:56  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_KEY_OP
+ *	- OID_SKGE_ASF_KEY_ADM
+ *	- OID_SKGE_ASF_KEY_GEN
+ *	- OID_SKGE_ASF_CAP
+ *	ASF OIDs removed:
+ *	- OID_SKGE_ASF_PAR_2
+ *	- OID_SKGE_ASF_PAR_3
+ *	- OID_SKGE_ASF_PAR_4
+ *	- OID_SKGE_ASF_PAR_5
+ *	ASF OID changed:
+ *	- OID_SKGE_ASF_PAR_1
+ *
+ *	Revision 2.6  2004/03/19 16:25:06  tschilli
+ *	Merged the changes of revision 1.63.
+ *	Editorial changes.
+ *
+ *	Revision 2.5  2004/03/08 14:27:11  mkunz
+ *	Changes of ASF OID
+ *
+ *	Revision 2.4  2004/02/26 16:01:27  mkunz
+ *	Changes for ASF
+ *
+ *	Revision 2.3  2004/02/02 15:58:19  mkunz
+ *	Added ASF support
+ *
+ *	Revision 2.2  2004/01/19 08:42:51  mkarl
+ *	TWSI include file name is now sktwsi.h.
+ *
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.63  2004/01/02 11:58:09  rschmidt
+ *	Changed names of entries in struct s_PnmiVct.
+ *	Added defines for RLMT and VCT timer checks:
+ *	SK_PNMI_EVT_TIMER_CHECK and SK_PNMI_VCT_TIMER_CHECK.
+ *	Removed struct s_VctTimer.
+ *	Editorial changes.
+ *
+ *	Revision 1.62  2003/08/15 12:31:52  tschilli
+ *	Added new OIDs:
+ *	OID_SKGE_DRIVER_RELDATE
+ *	OID_SKGE_DRIVER_FILENAME
+ *	OID_SKGE_CHIPID
+ *	OID_SKGE_RAMSIZE
+ *	OID_SKGE_VAUXAVAIL
+ *	OID_SKGE_PHY_TYPE
+ *	OID_SKGE_PHY_LP_MODE
+ *
+ *	Added new define SK_DIAG_ATTACHED for OID_SKGE_DIAG_MODE handling.
+ *
+ *	Revision 1.61  2003/05/23 12:53:52  tschilli
+ *	Generic PNMI IOCTL subcommands added.
+ *	Function prototype SkPnmiGenIoctl() added.
+ *	OID_SKGE_BOARDLEVEL added.
+ *	Return value SK_PNMI_ERR_NOT_SUPPORTED added.
+ *	Editorial changes.
+ *
+ *	Revision 1.60  2003/03/27 11:27:26  tschilli
+ *	Copyright messages changed.
+ *
+ *	Revision 1.59  2002/12/16 14:03:50  tschilli
+ *	New defines for VCT added.
+ *
+ *	Revision 1.58  2002/12/16 09:04:59  tschilli
+ *	Code for VCT handling added.
+ *
+ *	Revision 1.57  2002/09/26 12:41:05  tschilli
+ *	SK_PNMI_PORT BufPort entry in struct SK_PNMI added.
+ *
+ *	Revision 1.56  2002/08/16 11:10:41  rwahl
+ *	- Replaced c++ comment.
+ *
+ *	Revision 1.55  2002/08/09 15:40:21  rwahl
+ *	Editorial change (renamed ConfSpeedCap).
+ *
+ *	Revision 1.54  2002/08/09 11:06:07  rwahl
+ *	Added OID_SKGE_SPEED_CAP.
+ *
+ *	Revision 1.53  2002/08/09 09:45:28  rwahl
+ *	Added support for NDIS OID_PNP_xxx.
+ *	Editorial changes.
+ *
+ *	Revision 1.52  2002/08/06 17:54:07  rwahl
+ *	- Added speed cap to PNMI config struct.
+ *
+ *	Revision 1.51  2002/07/17 19:19:26  rwahl
+ *	- Added OID_SKGE_SPEED_MODE and OID_SKGE_SPEED_STATUS.
+ *	- Added SK_PNMI_CNT_RX_PMACC_ERR() & SK_PNMI_CNT_RX_LONGFRAMES().
+ *	- Added speed mode & status to PNMI config struct.
+ *	- Editorial changes.
+ *
+ *	Revision 1.50  2002/05/22 08:59:37  rwahl
+ *	Added string definitions for error msgs.
+ *
+ *	Revision 1.49  2001/11/20 09:23:50  rwahl
+ *	- pnmi struct: reordered and aligned to 32bit.
+ *
+ *	Revision 1.48  2001/02/23 14:34:24  mkunz
+ *	Changed macro PHYS2INST. Added pAC to Interface
+ *
+ *	Revision 1.47  2001/02/07 08:28:23  mkunz
+ *	- Added Oids: 	OID_SKGE_DIAG_ACTION
+ *					OID_SKGE_DIAG_RESULT
+ *					OID_SKGE_MULTICAST_LIST
+ *					OID_SKGE_CURRENT_PACKET_FILTER
+ *					OID_SKGE_INTERMEDIATE_SUPPORT
+ *	- Changed value of OID_SKGE_MTU
+ *
+ *	Revision 1.46  2001/02/06 10:01:41  mkunz
+ *	- Pnmi V4 dual net support added. Interface functions and macros extended
+ *	- Vpd bug fixed
+ *	- OID_SKGE_MTU added
+ *
+ *	Revision 1.45  2001/01/22 13:41:37  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *
+ *	Revision 1.44  2000/09/07 07:35:27  rwahl
+ *	- removed NDIS counter specific data type.
+ *	- fixed spelling for OID_SKGE_RLMT_PORT_PREFERRED.
+ *
+ *	Revision 1.43  2000/08/04 11:41:08  rwahl
+ *	- Fixed compiler warning (port is always >= 0) for macros
+ *	  SK_PNMI_CNT_RX_LONGFRAMES & SK_PNMI_CNT_SYNC_OCTETS
+ *
+ *	Revision 1.42  2000/08/03 15:14:07  rwahl
+ *	- Corrected error in driver macros addressing a physical port.
+ *
+ *	Revision 1.41  2000/08/01 16:22:29  rwahl
+ *	- Changed MDB version to 3.1.
+ *	- Added definitions for StatRxLongFrames counter.
+ *	- Added macro to be used by driver to count long frames received.
+ *	- Added directive to control width (default = 32bit) of NDIS statistic
+ *	  counters (SK_NDIS_64BIT_CTR).
+ *
+ *	Revision 1.40  2000/03/31 13:51:34  rwahl
+ *	Added SK_UPTR cast to offset calculation for PNMI struct fields;
+ *	missing cast caused compiler warnings by Win64 compiler.
+ *
+ *	Revision 1.39  1999/12/06 10:09:47  rwahl
+ *	Added new error log message.
+ *
+ *	Revision 1.38  1999/11/22 13:57:55  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.37  1999/09/14 14:25:32  rwahl
+ *	Set MDB version for 1000Base-T (sensors, Master/Slave) changes.
+ *
+ *	Revision 1.36  1999/05/20 09:24:56  cgoos
+ *	Changes for 1000Base-T (sensors, Master/Slave).
+ *
+ *	Revision 1.35  1999/04/13 15:10:51  mhaveman
+ *	Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to
+ *	grant unified interface. But PNMI macros will store the same
+ *	value as RLMT macros.
+ *
+ *	Revision 1.34  1999/04/13 15:03:49  mhaveman
+ *	-Changed copyright
+ *	-Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be
+ *	 used.
+ *
+ *	Revision 1.33  1999/03/23 10:41:02  mhaveman
+ *	Changed comments.
+ *
+ *	Revision 1.32  1999/01/25 15:01:33  mhaveman
+ *	Added support for multiple simultaniously active ports.
+ *
+ *	Revision 1.31  1999/01/19 10:06:26  mhaveman
+ *	Added new error log message.
+ *
+ *	Revision 1.30  1999/01/05 10:34:49  mhaveman
+ *	Fixed little error in RlmtChangeEstimate calculation.
+ *
+ *	Revision 1.29  1999/01/05 09:59:41  mhaveman
+ *	Redesigned port switch average calculation to avoid 64bit arithmetic.
+ *
+ *	Revision 1.28  1998/12/08 10:05:48  mhaveman
+ *	Defined macro SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ *	Revision 1.27  1998/12/03 14:39:35  mhaveman
+ *	Fixed problem that LSTAT was enumerated wrong.
+ *
+ *	Revision 1.26  1998/12/03 11:19:51  mhaveman
+ *	Changed contents of errlog message SK_PNMI_ERR016MSG
+ *
+ *	Revision 1.25  1998/12/01 10:40:04  mhaveman
+ *	Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in
+ *	SK_PNMI_STRUCT_DATA to be conform with OID definition.
+ *
+ *	Revision 1.24  1998/11/20 08:09:27  mhaveman
+ *	Added macros to convert between logical, physical port indexes and
+ *	instances.
+ *
+ *	Revision 1.23  1998/11/10 13:41:13  mhaveman
+ *	Needed to change interface, because NT driver needs a return value
+ *	of needed buffer space on TOO_SHORT errors. Therefore all
+ *	SkPnmiGet/Preset/Set functions now have a pointer to the length
+ *	parameter, where the needed space on error is returned.
+ *
+ *	Revision 1.22  1998/11/03 12:05:51  mhaveman
+ *	Added pAC parameter to counter macors.
+ *
+ *	Revision 1.21  1998/11/02 10:47:36  mhaveman
+ *	Added syslog messages for internal errors.
+ *
+ *	Revision 1.20  1998/10/30 15:49:36  mhaveman
+ *	-Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt.
+ *	-Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds.
+ *
+ *	Revision 1.19  1998/10/29 15:38:44  mhaveman
+ *	Changed string lengths of PNMI_STRUCT_DATA structure because
+ *	string OIDs are now encoded with leading length ocetet.
+ *
+ *	Revision 1.18  1998/10/29 08:52:27  mhaveman
+ *	-Added byte to strings in PNMI_STRUCT_DATA structure.
+ *	-Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements.
+ *
+ *	Revision 1.17  1998/10/28 08:49:50  mhaveman
+ *	-Changed type of Instance back to SK_U32 because of VPD
+ *	-Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD,
+ *	 and Connector.
+ *
+ *	Revision 1.16  1998/10/22 10:42:31  mhaveman
+ *	-Removed (SK_U32) casts for OIDs
+ *	-excluded NDIS OIDs when they are already defined with ifndef _NDIS_
+ *
+ *	Revision 1.15  1998/10/20 13:56:28  mhaveman
+ *	Headerfile includes now directly other header files to comile correctly.
+ *
+ *	Revision 1.14  1998/10/20 07:31:09  mhaveman
+ *	Made type changes to unsigned int where possible.
+ *
+ *	Revision 1.13  1998/10/19 10:53:13  mhaveman
+ *	-Casted OID definitions to SK_U32
+ *	-Renamed RlmtMAC... to RlmtPort...
+ *	-Changed wrong type of VpdEntriesList from SK_U32 to char *
+ *
+ *	Revision 1.12  1998/10/13 07:42:27  mhaveman
+ *	-Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA
+ *	-Removed old cvs history entries
+ *	-Renamed MacNumber to PortNumber
+ *
+ *	Revision 1.11  1998/10/07 10:55:24  mhaveman
+ *	-Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs
+ *	 necessary.
+ *	-Added OID_GEN_ Ids to support the Windows driver.
+ *
+ *	Revision 1.10  1998/09/30 13:41:10  mhaveman
+ *	Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'.
+ *
+ *	Revision 1.9  1998/09/04 17:06:17  mhaveman
+ *	-Added SyncCounter as macro.
+ *	-Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS.
+ *	-Added macros for driver description and version strings.
+ *
+ *	Revision 1.8  1998/09/04 14:36:52  mhaveman
+ *	Added OIDs and Structure to access value of macro counters which are
+ *	counted by the driver.
+ *
+ *	Revision 1.7  1998/09/04 11:59:36  mhaveman
+ *	Everything compiles now. Driver Macros for counting still missing.
+ *
+ *****************************************************************************/
+
+#ifndef _SKGEPNMI_H_
+#define _SKGEPNMI_H_
+
+/*
+ * Include dependencies
+ */
+#include "h/sktypes.h"
+#include "h/skerror.h"
+#include "h/sktimer.h"
+#include "h/sktwsi.h"
+#include "h/skaddr.h"
+#ifndef SK_NO_RLMT
+#include "h/skrlmt.h"
+#endif
+#include "h/skvpd.h"
+
+/*
+ * Management Database Version
+ */
+#define SK_PNMI_MDB_VERSION		0x00030001	/* 3.1 */
+
+/*
+ * Event definitions
+ */
+#define SK_PNMI_EVT_SIRQ_OVERFLOW		1	/* Counter overflow */
+#define SK_PNMI_EVT_SEN_WAR_LOW			2	/* Lower war thres exceeded */
+#define SK_PNMI_EVT_SEN_WAR_UPP			3	/* Upper war thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_LOW			4	/* Lower err thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_UPP			5	/* Upper err thres exceeded */
+#define SK_PNMI_EVT_CHG_EST_TIMER		6	/* Timer event for RLMT Chg */
+#define SK_PNMI_EVT_UTILIZATION_TIMER	7	/* Timer event for Utiliza. */
+#define SK_PNMI_EVT_CLEAR_COUNTER		8	/* Clear statistic counters */
+#define SK_PNMI_EVT_XMAC_RESET			9	/* XMAC will be reset */
+#define SK_PNMI_EVT_RLMT_PORT_UP		10	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_PORT_DOWN		11	/* Port went logically down */
+#define SK_PNMI_EVT_RLMT_SEGMENTATION	13	/* Two SP root bridges found */
+#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN	14	/* Port went logically down */
+#define SK_PNMI_EVT_RLMT_ACTIVE_UP		15	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_SET_NETS		16	/* Number of nets (1 or 2). */
+#define SK_PNMI_EVT_VCT_RESET			17	/* VCT port reset timer event started with SET. */
+
+/*
+ * Return values
+ */
+#define SK_PNMI_ERR_OK				0
+#define SK_PNMI_ERR_GENERAL			1
+#define SK_PNMI_ERR_TOO_SHORT		2
+#define SK_PNMI_ERR_BAD_VALUE		3
+#define SK_PNMI_ERR_READ_ONLY		4
+#define SK_PNMI_ERR_UNKNOWN_OID		5
+#define SK_PNMI_ERR_UNKNOWN_INST	6
+#define SK_PNMI_ERR_UNKNOWN_NET 	7
+#define SK_PNMI_ERR_NOT_SUPPORTED	10
+
+/*
+ * Return values of driver reset function SK_DRIVER_RESET() and
+ * driver event function SK_DRIVER_EVENT()
+ */
+#define SK_PNMI_ERR_OK			0
+#define SK_PNMI_ERR_FAIL		1
+
+/*
+ * Return values of driver test function SK_DRIVER_SELFTEST()
+ */
+#define SK_PNMI_TST_UNKNOWN		(1 << 0)
+#define SK_PNMI_TST_TRANCEIVER	(1 << 1)
+#define SK_PNMI_TST_ASIC		(1 << 2)
+#define SK_PNMI_TST_SENSOR		(1 << 3)
+#define SK_PNMI_TST_POWERMGMT	(1 << 4)
+#define SK_PNMI_TST_PCI			(1 << 5)
+#define SK_PNMI_TST_MAC			(1 << 6)
+
+/*
+ * RLMT specific definitions
+ */
+#define SK_PNMI_RLMT_STATUS_STANDBY	1
+#define SK_PNMI_RLMT_STATUS_ACTIVE	2
+#define SK_PNMI_RLMT_STATUS_ERROR	3
+
+#define SK_PNMI_RLMT_LSTAT_PHY_DOWN	1
+#define SK_PNMI_RLMT_LSTAT_AUTONEG	2
+#define SK_PNMI_RLMT_LSTAT_LOG_DOWN	3
+#define SK_PNMI_RLMT_LSTAT_LOG_UP	4
+#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5
+
+#define SK_PNMI_RLMT_MODE_CHK_LINK	(SK_RLMT_CHECK_LINK)
+#define SK_PNMI_RLMT_MODE_CHK_RX	(SK_RLMT_CHECK_LOC_LINK)
+#define SK_PNMI_RLMT_MODE_CHK_SPT	(SK_RLMT_CHECK_SEG)
+/* #define SK_PNMI_RLMT_MODE_CHK_EX */
+
+/*
+ * OID definition
+ */
+
+#define SK_PNMI_OID_PSET				0x00400000
+#define SK_PNMI_OID_SET					0x00800000
+
+#ifndef _NDIS_	/* Check, whether NDIS already included OIDs */
+
+#define OID_GEN_XMIT_OK					0x00020101
+#define OID_GEN_RCV_OK					0x00020102
+#define OID_GEN_XMIT_ERROR				0x00020103
+#define OID_GEN_RCV_ERROR				0x00020104
+#define OID_GEN_RCV_NO_BUFFER			0x00020105
+
+/* #define OID_GEN_DIRECTED_BYTES_XMIT	0x00020201 */
+#define OID_GEN_DIRECTED_FRAMES_XMIT	0x00020202
+/* #define OID_GEN_MULTICAST_BYTES_XMIT	0x00020203 */
+#define OID_GEN_MULTICAST_FRAMES_XMIT	0x00020204
+/* #define OID_GEN_BROADCAST_BYTES_XMIT	0x00020205 */
+#define OID_GEN_BROADCAST_FRAMES_XMIT	0x00020206
+/* #define OID_GEN_DIRECTED_BYTES_RCV	0x00020207 */
+#define OID_GEN_DIRECTED_FRAMES_RCV		0x00020208
+/* #define OID_GEN_MULTICAST_BYTES_RCV	0x00020209 */
+#define OID_GEN_MULTICAST_FRAMES_RCV	0x0002020A
+/* #define OID_GEN_BROADCAST_BYTES_RCV	0x0002020B */
+#define OID_GEN_BROADCAST_FRAMES_RCV	0x0002020C
+#define OID_GEN_RCV_CRC_ERROR			0x0002020D
+#define OID_GEN_TRANSMIT_QUEUE_LENGTH	0x0002020E
+
+#define OID_802_3_PERMANENT_ADDRESS		0x01010101
+#define OID_802_3_CURRENT_ADDRESS		0x01010102
+/* #define OID_802_3_MULTICAST_LIST		0x01010103 */
+/* #define OID_802_3_MAXIMUM_LIST_SIZE	0x01010104 */
+/* #define OID_802_3_MAC_OPTIONS		0x01010105 */
+
+#define OID_802_3_RCV_ERROR_ALIGNMENT	0x01020101
+#define OID_802_3_XMIT_ONE_COLLISION	0x01020102
+#define OID_802_3_XMIT_MORE_COLLISIONS	0x01020103
+#define OID_802_3_XMIT_DEFERRED			0x01020201
+#define OID_802_3_XMIT_MAX_COLLISIONS	0x01020202
+#define OID_802_3_RCV_OVERRUN			0x01020203
+#define OID_802_3_XMIT_UNDERRUN			0x01020204
+#define OID_802_3_XMIT_TIMES_CRS_LOST	0x01020206
+#define OID_802_3_XMIT_LATE_COLLISIONS	0x01020207
+
+/*
+ * PnP and PM OIDs
+ */
+#ifdef SK_POWER_MGMT
+#define OID_PNP_CAPABILITIES			0xFD010100
+#define OID_PNP_SET_POWER				0xFD010101
+#define OID_PNP_QUERY_POWER				0xFD010102
+#define OID_PNP_ADD_WAKE_UP_PATTERN		0xFD010103
+#define OID_PNP_REMOVE_WAKE_UP_PATTERN	0xFD010104
+#define OID_PNP_ENABLE_WAKE_UP			0xFD010106
+#define OID_PM_ADD_PROTOCOL_OFFLOAD		0xFD01010D
+#define OID_PM_REMOVE_PROTOCOL_OFFLOAD	0xFD01010F
+#endif /* SK_POWER_MGMT */
+
+#endif /* _NDIS_ */
+
+#define OID_SKGE_MDB_VERSION			0xFF010100
+#define OID_SKGE_SUPPORTED_LIST			0xFF010101
+#define OID_SKGE_VPD_FREE_BYTES			0xFF010102
+#define OID_SKGE_VPD_ENTRIES_LIST		0xFF010103
+#define OID_SKGE_VPD_ENTRIES_NUMBER		0xFF010104
+#define OID_SKGE_VPD_KEY				0xFF010105
+#define OID_SKGE_VPD_VALUE				0xFF010106
+#define OID_SKGE_VPD_ACCESS				0xFF010107
+#define OID_SKGE_VPD_ACTION				0xFF010108
+
+#define OID_SKGE_PORT_NUMBER			0xFF010110
+#define OID_SKGE_DEVICE_TYPE			0xFF010111
+#define OID_SKGE_DRIVER_DESCR			0xFF010112
+#define OID_SKGE_DRIVER_VERSION			0xFF010113
+#define OID_SKGE_HW_DESCR				0xFF010114
+#define OID_SKGE_HW_VERSION				0xFF010115
+#define OID_SKGE_CHIPSET				0xFF010116
+#define OID_SKGE_ACTION					0xFF010117
+#define OID_SKGE_RESULT					0xFF010118
+#define OID_SKGE_BUS_TYPE				0xFF010119
+#define OID_SKGE_BUS_SPEED				0xFF01011A
+#define OID_SKGE_BUS_WIDTH				0xFF01011B
+/* 0xFF01011C unused */
+#define OID_SKGE_DIAG_ACTION			0xFF01011D
+#define OID_SKGE_DIAG_RESULT			0xFF01011E
+#define OID_SKGE_MTU					0xFF01011F
+#define OID_SKGE_PHYS_CUR_ADDR			0xFF010120
+#define OID_SKGE_PHYS_FAC_ADDR			0xFF010121
+#define OID_SKGE_PMD					0xFF010122
+#define OID_SKGE_CONNECTOR				0xFF010123
+#define OID_SKGE_LINK_CAP				0xFF010124
+#define OID_SKGE_LINK_MODE				0xFF010125
+#define OID_SKGE_LINK_MODE_STATUS		0xFF010126
+#define OID_SKGE_LINK_STATUS			0xFF010127
+#define OID_SKGE_FLOWCTRL_CAP			0xFF010128
+#define OID_SKGE_FLOWCTRL_MODE			0xFF010129
+#define OID_SKGE_FLOWCTRL_STATUS		0xFF01012A
+#define OID_SKGE_PHY_OPERATION_CAP		0xFF01012B
+#define OID_SKGE_PHY_OPERATION_MODE		0xFF01012C
+#define OID_SKGE_PHY_OPERATION_STATUS	0xFF01012D
+#define OID_SKGE_MULTICAST_LIST			0xFF01012E
+#define OID_SKGE_CURRENT_PACKET_FILTER	0xFF01012F
+
+#define OID_SKGE_TRAP					0xFF010130
+#define OID_SKGE_TRAP_NUMBER			0xFF010131
+
+#define OID_SKGE_RLMT_MODE				0xFF010140
+#define OID_SKGE_RLMT_PORT_NUMBER		0xFF010141
+#define OID_SKGE_RLMT_PORT_ACTIVE		0xFF010142
+#define OID_SKGE_RLMT_PORT_PREFERRED	0xFF010143
+
+#define OID_SKGE_RLMT_MONITOR_NUMBER	0xFF010150
+#define OID_SKGE_RLMT_MONITOR_INDEX		0xFF010151
+#define OID_SKGE_RLMT_MONITOR_ADDR		0xFF010152
+#define OID_SKGE_RLMT_MONITOR_ERRS		0xFF010153
+#define OID_SKGE_RLMT_MONITOR_TIMESTAMP	0xFF010154
+#define OID_SKGE_RLMT_MONITOR_ADMIN		0xFF010155
+
+#define OID_SKGE_INTERMEDIATE_SUPPORT		0xFF010160
+#define OID_SKGE_SET_TEAM_MAC_ADDRESS		0xFF010161
+#define OID_SKGE_DEVICE_INFORMATION 		0xFF010162
+#define OID_SKGE_MACSEC_CONFIGURATION 		0xFF010163
+
+#define OID_SKGE_SPEED_CAP				0xFF010170
+#define OID_SKGE_SPEED_MODE				0xFF010171
+#define OID_SKGE_SPEED_STATUS			0xFF010172
+
+#define OID_SKGE_BOARDLEVEL				0xFF010180
+
+#define OID_SKGE_SENSOR_NUMBER			0xFF020100
+#define OID_SKGE_SENSOR_INDEX			0xFF020101
+#define OID_SKGE_SENSOR_DESCR			0xFF020102
+#define OID_SKGE_SENSOR_TYPE			0xFF020103
+#define OID_SKGE_SENSOR_VALUE			0xFF020104
+#define OID_SKGE_SENSOR_WAR_THRES_LOW	0xFF020105
+#define OID_SKGE_SENSOR_WAR_THRES_UPP	0xFF020106
+#define OID_SKGE_SENSOR_ERR_THRES_LOW	0xFF020107
+#define OID_SKGE_SENSOR_ERR_THRES_UPP	0xFF020108
+#define OID_SKGE_SENSOR_STATUS			0xFF020109
+#define OID_SKGE_SENSOR_WAR_CTS			0xFF02010A
+#define OID_SKGE_SENSOR_ERR_CTS			0xFF02010B
+#define OID_SKGE_SENSOR_WAR_TIME		0xFF02010C
+#define OID_SKGE_SENSOR_ERR_TIME		0xFF02010D
+
+#define OID_SKGE_CHKSM_NUMBER			0xFF020110
+#define OID_SKGE_CHKSM_RX_OK_CTS		0xFF020111
+#define OID_SKGE_CHKSM_RX_UNABLE_CTS	0xFF020112
+#define OID_SKGE_CHKSM_RX_ERR_CTS		0xFF020113
+#define OID_SKGE_CHKSM_TX_OK_CTS		0xFF020114
+#define OID_SKGE_CHKSM_TX_UNABLE_CTS	0xFF020115
+
+#define OID_SKGE_STAT_TX				0xFF020120
+#define OID_SKGE_STAT_TX_OCTETS			0xFF020121
+#define OID_SKGE_STAT_TX_BROADCAST		0xFF020122
+#define OID_SKGE_STAT_TX_MULTICAST		0xFF020123
+#define OID_SKGE_STAT_TX_UNICAST		0xFF020124
+#define OID_SKGE_STAT_TX_LONGFRAMES		0xFF020125
+#define OID_SKGE_STAT_TX_BURST			0xFF020126
+#define OID_SKGE_STAT_TX_PFLOWC			0xFF020127
+#define OID_SKGE_STAT_TX_FLOWC			0xFF020128
+#define OID_SKGE_STAT_TX_SINGLE_COL		0xFF020129
+#define OID_SKGE_STAT_TX_MULTI_COL		0xFF02012A
+#define OID_SKGE_STAT_TX_EXCESS_COL		0xFF02012B
+#define OID_SKGE_STAT_TX_LATE_COL		0xFF02012C
+#define OID_SKGE_STAT_TX_DEFFERAL		0xFF02012D
+#define OID_SKGE_STAT_TX_EXCESS_DEF		0xFF02012E
+#define OID_SKGE_STAT_TX_UNDERRUN		0xFF02012F
+#define OID_SKGE_STAT_TX_CARRIER		0xFF020130
+/* #define OID_SKGE_STAT_TX_UTIL		0xFF020131 */
+#define OID_SKGE_STAT_TX_64				0xFF020132
+#define OID_SKGE_STAT_TX_127			0xFF020133
+#define OID_SKGE_STAT_TX_255			0xFF020134
+#define OID_SKGE_STAT_TX_511			0xFF020135
+#define OID_SKGE_STAT_TX_1023			0xFF020136
+#define OID_SKGE_STAT_TX_MAX			0xFF020137
+#define OID_SKGE_STAT_TX_SYNC			0xFF020138
+#define OID_SKGE_STAT_TX_SYNC_OCTETS	0xFF020139
+#define OID_SKGE_STAT_RX				0xFF02013A
+#define OID_SKGE_STAT_RX_OCTETS			0xFF02013B
+#define OID_SKGE_STAT_RX_BROADCAST		0xFF02013C
+#define OID_SKGE_STAT_RX_MULTICAST		0xFF02013D
+#define OID_SKGE_STAT_RX_UNICAST		0xFF02013E
+#define OID_SKGE_STAT_RX_PFLOWC			0xFF02013F
+#define OID_SKGE_STAT_RX_FLOWC			0xFF020140
+#define OID_SKGE_STAT_RX_PFLOWC_ERR		0xFF020141
+#define OID_SKGE_STAT_RX_FLOWC_UNKWN	0xFF020142
+#define OID_SKGE_STAT_RX_BURST			0xFF020143
+#define OID_SKGE_STAT_RX_MISSED			0xFF020144
+#define OID_SKGE_STAT_RX_FRAMING		0xFF020145
+#define OID_SKGE_STAT_RX_OVERFLOW		0xFF020146
+#define OID_SKGE_STAT_RX_JABBER			0xFF020147
+#define OID_SKGE_STAT_RX_CARRIER		0xFF020148
+#define OID_SKGE_STAT_RX_IR_LENGTH		0xFF020149
+#define OID_SKGE_STAT_RX_SYMBOL			0xFF02014A
+#define OID_SKGE_STAT_RX_SHORTS			0xFF02014B
+#define OID_SKGE_STAT_RX_RUNT			0xFF02014C
+#define OID_SKGE_STAT_RX_CEXT			0xFF02014D
+#define OID_SKGE_STAT_RX_TOO_LONG		0xFF02014E
+#define OID_SKGE_STAT_RX_FCS			0xFF02014F
+/* #define OID_SKGE_STAT_RX_UTIL		0xFF020150 */
+#define OID_SKGE_STAT_RX_64				0xFF020151
+#define OID_SKGE_STAT_RX_127			0xFF020152
+#define OID_SKGE_STAT_RX_255			0xFF020153
+#define OID_SKGE_STAT_RX_511			0xFF020154
+#define OID_SKGE_STAT_RX_1023			0xFF020155
+#define OID_SKGE_STAT_RX_MAX			0xFF020156
+#define OID_SKGE_STAT_RX_LONGFRAMES		0xFF020157
+
+#define OID_SKGE_RLMT_CHANGE_CTS		0xFF020160
+#define OID_SKGE_RLMT_CHANGE_TIME		0xFF020161
+#define OID_SKGE_RLMT_CHANGE_ESTIM		0xFF020162
+#define OID_SKGE_RLMT_CHANGE_THRES		0xFF020163
+
+#define OID_SKGE_RLMT_PORT_INDEX		0xFF020164
+#define OID_SKGE_RLMT_STATUS			0xFF020165
+#define OID_SKGE_RLMT_TX_HELLO_CTS		0xFF020166
+#define OID_SKGE_RLMT_RX_HELLO_CTS		0xFF020167
+#define OID_SKGE_RLMT_TX_SP_REQ_CTS		0xFF020168
+#define OID_SKGE_RLMT_RX_SP_CTS			0xFF020169
+
+#define OID_SKGE_TX_SW_QUEUE_LEN		0xFF020170
+#define OID_SKGE_TX_SW_QUEUE_MAX		0xFF020171
+#define OID_SKGE_TX_RETRY				0xFF020172
+#define OID_SKGE_RX_INTR_CTS			0xFF020173
+#define OID_SKGE_TX_INTR_CTS			0xFF020174
+#define OID_SKGE_RX_NO_BUF_CTS			0xFF020175
+#define OID_SKGE_TX_NO_BUF_CTS			0xFF020176
+#define OID_SKGE_TX_USED_DESCR_NO		0xFF020177
+#define OID_SKGE_RX_DELIVERED_CTS		0xFF020178
+#define OID_SKGE_RX_OCTETS_DELIV_CTS	0xFF020179
+#define OID_SKGE_RX_HW_ERROR_CTS		0xFF02017A
+#define OID_SKGE_TX_HW_ERROR_CTS		0xFF02017B
+#define OID_SKGE_IN_ERRORS_CTS			0xFF02017C
+#define OID_SKGE_OUT_ERROR_CTS			0xFF02017D
+#define OID_SKGE_ERR_RECOVERY_CTS		0xFF02017E
+#define OID_SKGE_SYSUPTIME				0xFF02017F
+
+#define OID_SKGE_ALL_DATA				0xFF020190
+
+/* Defines for VCT. */
+#define OID_SKGE_VCT_GET				0xFF020200
+#define OID_SKGE_VCT_SET				0xFF020201
+#define OID_SKGE_VCT_STATUS				0xFF020202
+#define OID_SKGE_VCT_CAPABILITIES		0xFF020203
+
+#ifdef SK_DIAG_SUPPORT
+/* Defines for driver DIAG mode. */
+#define OID_SKGE_DIAG_MODE				0xFF020204
+#endif /* SK_DIAG_SUPPORT */
+
+/* New OIDs */
+#define OID_SKGE_DRIVER_RELDATE			0xFF020210
+#define OID_SKGE_DRIVER_FILENAME		0xFF020211
+#define OID_SKGE_CHIPID					0xFF020212
+#define OID_SKGE_RAMSIZE				0xFF020213
+#define OID_SKGE_VAUXAVAIL				0xFF020214
+#define OID_SKGE_PHY_TYPE				0xFF020215
+#define OID_SKGE_PHY_LP_MODE			0xFF020216
+
+/*
+ * Added for new DualNet IM driver V2
+ */
+#define OID_SKGE_MAC_COUNT				0xFF020217
+#define OID_SKGE_DUALNET_MODE			0xFF020218
+#define OID_SKGE_SET_TAGHEADER			0xFF020219
+
+#ifdef SK_ASF
+/* Defines for ASF */
+#define OID_SKGE_ASF					0xFF02021a
+#define OID_SKGE_ASF_STORE_CONFIG		0xFF02021b
+#define OID_SKGE_ASF_ENA				0xFF02021c
+#define OID_SKGE_ASF_RETRANS			0xFF02021d
+#define OID_SKGE_ASF_RETRANS_INT		0xFF02021e
+#define OID_SKGE_ASF_HB_ENA				0xFF02021f
+#define OID_SKGE_ASF_HB_INT				0xFF020220
+#define OID_SKGE_ASF_WD_ENA				0xFF020221
+#define OID_SKGE_ASF_WD_TIME			0xFF020222
+#define OID_SKGE_ASF_IP_SOURCE			0xFF020223
+#define OID_SKGE_ASF_MAC_SOURCE			0xFF020224
+#define OID_SKGE_ASF_IP_DEST			0xFF020225
+#define OID_SKGE_ASF_MAC_DEST			0xFF020226
+#define OID_SKGE_ASF_COMMUNITY_NAME		0xFF020227
+#define OID_SKGE_ASF_RSP_ENA			0xFF020228
+#define OID_SKGE_ASF_RETRANS_COUNT_MIN	0xFF020229
+#define OID_SKGE_ASF_RETRANS_COUNT_MAX	0xFF02022a
+#define OID_SKGE_ASF_RETRANS_INT_MIN	0xFF02022b
+#define OID_SKGE_ASF_RETRANS_INT_MAX	0xFF02022c
+#define OID_SKGE_ASF_HB_INT_MIN			0xFF02022d
+#define OID_SKGE_ASF_HB_INT_MAX			0xFF02022e
+#define OID_SKGE_ASF_WD_TIME_MIN		0xFF02022f
+#define OID_SKGE_ASF_WD_TIME_MAX		0xFF020230
+#define OID_SKGE_ASF_HB_CAP				0xFF020231
+#define OID_SKGE_ASF_WD_TIMER_RES		0xFF020232
+#define OID_SKGE_ASF_GUID				0xFF020233
+#define OID_SKGE_ASF_KEY_OP				0xFF020234
+#define OID_SKGE_ASF_KEY_ADM			0xFF020235
+#define OID_SKGE_ASF_KEY_GEN			0xFF020236
+#define OID_SKGE_ASF_CAP				0xFF020237
+#define OID_SKGE_ASF_PAR_1				0xFF020238
+#define OID_SKGE_ASF_OVERALL_OID		0xFF020239
+#define OID_SKGE_ASF_FW_REMOVE			0xFF02023a
+#define OID_SKGE_ASF_CHECK_SPI			0xFF02023b
+#endif /* SK_ASF */
+
+
+/* Defined for Yukon-2 path only */
+#define OID_SKGE_UPPER_MINIPORT			0xFF02023D
+
+
+#ifdef SK_ASF
+/* Defines for ASF */
+#define OID_SKGE_ASF_FWVER_OID			0xFF020240
+#define OID_SKGE_ASF_ACPI_OID			0xFF020241
+#define OID_SKGE_ASF_SMBUS_OID			0xFF020242
+#define OID_SKGE_ASF_DASH_CAP			0xFF020243
+#define OID_SKGE_ASF_DASH_ENA			0xFF020244
+#define OID_SKGE_ASF_DASH_USER_DAT		0xFF020245
+#define OID_SKGE_ASF_DASH_BUSY			0xFF020246
+#define OID_SKGE_ASF_DASH_MAX_USER		0xFF020247
+#define OID_SKGE_ASF_DASH_IP_INFO		0xFF020300
+#define OID_SKGE_ASF_DASH_IP_INFO_EXT		0xFF020301
+#define OID_SKGE_ASF_DASH_SPECIAL_ACTION	0xFF020302
+#define OID_SKGE_ASF_DASH_OS_VERSION_INFO_SET	0xFF020303
+#define OID_SKGE_ASF_DASH_FW_GET_FLASH_RESULT	0xFF020304
+#define OID_SKGE_ASF_DASH_FW_GET_VERSIONS		0xFF020305
+
+#endif /* SK_ASF */
+
+/* VCT struct to store a backup copy of VCT data after a port reset. */
+typedef struct s_PnmiVct {
+	SK_U8			VctStatus;
+	SK_U8			CableLen;
+	SK_U32			MdiPairLen[4];
+	SK_U8			MdiPairSts[4];
+} SK_PNMI_VCT;
+
+
+/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
+#define SK_PNMI_VCT_NONE			0x00
+#define SK_PNMI_VCT_OLD_VCT_DATA	0x01
+#define SK_PNMI_VCT_NEW_VCT_DATA	0x02
+#define SK_PNMI_VCT_OLD_DSP_DATA	0x04
+#define SK_PNMI_VCT_NEW_DSP_DATA	0x08
+#define SK_PNMI_VCT_RUNNING			0x10
+
+
+/* VCT cable test status. */
+#define SK_PNMI_VCT_NORMAL_CABLE		0
+#define SK_PNMI_VCT_SHORT_CABLE			1
+#define SK_PNMI_VCT_OPEN_CABLE			2
+#define SK_PNMI_VCT_TEST_FAIL			3
+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH	4
+#define SK_PNMI_VCT_NOT_PRESENT			5
+
+/* DSP cable ranges. */
+#define DSP_CABLE_RANGE_UNDER_50		0	/* under 50m */
+#define DSP_CABLE_RANGE_50_TO_80		1	/* 50m - 80m */
+#define DSP_CABLE_RANGE_80_TO_150		2	/* 80m - 150m*/
+#define DSP_CABLE_RANGE_110_TO_140		3	/* 110m - 140m */
+#define DSP_CABLE_RANGE_ABOVE_140		4	/* above 140m */
+#define DSP_CABLE_RANGE_NOT_SUPPORTED	((SK_U8)-1)	/* not supported */
+
+#define DSP_CABLE_RANGE_UNDER_50_END	50	/* under 50m */
+#define DSP_CABLE_RANGE_50_TO_80_END	80	/* 50m - 80m */
+#define DSP_CABLE_RANGE_80_TO_140_END	140	/* 80m - 140m */
+
+/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */
+#define SK_PNMI_VCT_SUPPORTED_VERSION	1
+#define SK_PNMI_VCT_NOT_SUPPORTED		0
+
+#define OID_SKGE_TRAP_SEN_WAR_LOW		500
+#define OID_SKGE_TRAP_SEN_WAR_UPP		501
+#define OID_SKGE_TRAP_SEN_ERR_LOW		502
+#define OID_SKGE_TRAP_SEN_ERR_UPP		503
+#define OID_SKGE_TRAP_RLMT_CHANGE_THRES	520
+#define OID_SKGE_TRAP_RLMT_CHANGE_PORT	521
+#define OID_SKGE_TRAP_RLMT_PORT_DOWN	522
+#define OID_SKGE_TRAP_RLMT_PORT_UP		523
+#define OID_SKGE_TRAP_RLMT_SEGMENTATION	524
+
+#ifdef SK_DIAG_SUPPORT
+/* Defines for driver DIAG mode. */
+#define SK_DIAG_ATTACHED	2
+#define SK_DIAG_RUNNING		1
+#define SK_DIAG_IDLE		0
+#endif /* SK_DIAG_SUPPORT */
+
+/*
+ * Generic PNMI IOCTL subcommand definitions.
+ */
+#define SK_GET_SINGLE_VAR		1
+#define SK_SET_SINGLE_VAR		2
+#define SK_PRESET_SINGLE_VAR	3
+#define SK_GET_FULL_MIB			4
+#define SK_SET_FULL_MIB			5
+#define SK_PRESET_FULL_MIB		6
+
+/*
+ * Define error numbers and messages for syslog
+ */
+#define SK_PNMI_ERR001		(SK_ERRBASE_PNMI + 1)
+#define SK_PNMI_ERR001MSG	"SkPnmiGetStruct: Unknown OID"
+#define SK_PNMI_ERR002		(SK_ERRBASE_PNMI + 2)
+#define SK_PNMI_ERR002MSG	"SkPnmiGetStruct: Cannot read VPD keys"
+#define SK_PNMI_ERR003		(SK_ERRBASE_PNMI + 3)
+#define SK_PNMI_ERR003MSG	"OidStruct: Called with wrong OID"
+#define SK_PNMI_ERR004		(SK_ERRBASE_PNMI + 4)
+#define SK_PNMI_ERR004MSG	"OidStruct: Called with wrong action"
+#define SK_PNMI_ERR005		(SK_ERRBASE_PNMI + 5)
+#define SK_PNMI_ERR005MSG	"Perform: Cannot reset driver"
+#define SK_PNMI_ERR006		(SK_ERRBASE_PNMI + 6)
+#define SK_PNMI_ERR006MSG	"Perform: Unknown OID action command"
+#define SK_PNMI_ERR007		(SK_ERRBASE_PNMI + 7)
+#define SK_PNMI_ERR007MSG	"General: Driver description not initialized"
+#define SK_PNMI_ERR008		(SK_ERRBASE_PNMI + 8)
+#define SK_PNMI_ERR008MSG	"Addr: Tried to get unknown OID"
+#define SK_PNMI_ERR009		(SK_ERRBASE_PNMI + 9)
+#define SK_PNMI_ERR009MSG	"Addr: Unknown OID"
+#define SK_PNMI_ERR010		(SK_ERRBASE_PNMI + 10)
+#define SK_PNMI_ERR010MSG	"CsumStat: Unknown OID"
+#define SK_PNMI_ERR011		(SK_ERRBASE_PNMI + 11)
+#define SK_PNMI_ERR011MSG	"SensorStat: Sensor descr string too long"
+#define SK_PNMI_ERR012		(SK_ERRBASE_PNMI + 12)
+#define SK_PNMI_ERR012MSG	"SensorStat: Unknown OID"
+#define SK_PNMI_ERR013		(SK_ERRBASE_PNMI + 13)
+#define SK_PNMI_ERR013MSG	""
+#define SK_PNMI_ERR014		(SK_ERRBASE_PNMI + 14)
+#define SK_PNMI_ERR014MSG	"Vpd: Cannot read VPD keys"
+#define SK_PNMI_ERR015		(SK_ERRBASE_PNMI + 15)
+#define SK_PNMI_ERR015MSG	"Vpd: Internal array for VPD keys too small"
+#define SK_PNMI_ERR016		(SK_ERRBASE_PNMI + 16)
+#define SK_PNMI_ERR016MSG	"Vpd: Key string too long"
+#define SK_PNMI_ERR017		(SK_ERRBASE_PNMI + 17)
+#define SK_PNMI_ERR017MSG	"Vpd: Invalid VPD status pointer"
+#define SK_PNMI_ERR018		(SK_ERRBASE_PNMI + 18)
+#define SK_PNMI_ERR018MSG	"Vpd: VPD data not valid"
+#define SK_PNMI_ERR019		(SK_ERRBASE_PNMI + 19)
+#define SK_PNMI_ERR019MSG	"Vpd: VPD entries list string too long"
+#define SK_PNMI_ERR021		(SK_ERRBASE_PNMI + 21)
+#define SK_PNMI_ERR021MSG	"Vpd: VPD data string too long"
+#define SK_PNMI_ERR022		(SK_ERRBASE_PNMI + 22)
+#define SK_PNMI_ERR022MSG	"Vpd: VPD data string too long should be errored before"
+#define SK_PNMI_ERR023		(SK_ERRBASE_PNMI + 23)
+#define SK_PNMI_ERR023MSG	"Vpd: Unknown OID in get action"
+#define SK_PNMI_ERR024		(SK_ERRBASE_PNMI + 24)
+#define SK_PNMI_ERR024MSG	"Vpd: Unknown OID in preset/set action"
+#define SK_PNMI_ERR025		(SK_ERRBASE_PNMI + 25)
+#define SK_PNMI_ERR025MSG	"Vpd: Cannot write VPD after modify entry"
+#define SK_PNMI_ERR026		(SK_ERRBASE_PNMI + 26)
+#define SK_PNMI_ERR026MSG	"Vpd: Cannot update VPD"
+#define SK_PNMI_ERR027		(SK_ERRBASE_PNMI + 27)
+#define SK_PNMI_ERR027MSG	"Vpd: Cannot delete VPD entry"
+#define SK_PNMI_ERR028		(SK_ERRBASE_PNMI + 28)
+#define SK_PNMI_ERR028MSG	"Vpd: Cannot update VPD after delete entry"
+#define SK_PNMI_ERR029		(SK_ERRBASE_PNMI + 29)
+#define SK_PNMI_ERR029MSG	"General: Driver description string too long"
+#define SK_PNMI_ERR030		(SK_ERRBASE_PNMI + 30)
+#define SK_PNMI_ERR030MSG	"General: Driver version not initialized"
+#define SK_PNMI_ERR031		(SK_ERRBASE_PNMI + 31)
+#define SK_PNMI_ERR031MSG	"General: Driver version string too long"
+#define SK_PNMI_ERR032		(SK_ERRBASE_PNMI + 32)
+#define SK_PNMI_ERR032MSG	"General: Cannot read VPD Name for HW descr"
+#define SK_PNMI_ERR033		(SK_ERRBASE_PNMI + 33)
+#define SK_PNMI_ERR033MSG	"General: HW description string too long"
+#define SK_PNMI_ERR034		(SK_ERRBASE_PNMI + 34)
+#define SK_PNMI_ERR034MSG	"General: Unknown OID"
+#define SK_PNMI_ERR035		(SK_ERRBASE_PNMI + 35)
+#define SK_PNMI_ERR035MSG	"Rlmt: Unknown OID"
+#define SK_PNMI_ERR036		(SK_ERRBASE_PNMI + 36)
+#define SK_PNMI_ERR036MSG	""
+#define SK_PNMI_ERR037		(SK_ERRBASE_PNMI + 37)
+#define SK_PNMI_ERR037MSG	"Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"
+#define SK_PNMI_ERR038		(SK_ERRBASE_PNMI + 38)
+#define SK_PNMI_ERR038MSG	"Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"
+#define SK_PNMI_ERR039		(SK_ERRBASE_PNMI + 39)
+#define SK_PNMI_ERR039MSG	"RlmtStat: Unknown OID"
+#define SK_PNMI_ERR040		(SK_ERRBASE_PNMI + 40)
+#define SK_PNMI_ERR040MSG	"PowerManagement: Unknown OID"
+#define SK_PNMI_ERR041		(SK_ERRBASE_PNMI + 41)
+#define SK_PNMI_ERR041MSG	"MacPrivateConf: Unknown OID"
+#define SK_PNMI_ERR042		(SK_ERRBASE_PNMI + 42)
+#define SK_PNMI_ERR042MSG	"MacPrivateConf: SK_HWEV_SET_ROLE returned not 0"
+#define SK_PNMI_ERR043		(SK_ERRBASE_PNMI + 43)
+#define SK_PNMI_ERR043MSG	"MacPrivateConf: SK_HWEV_SET_LMODE returned not 0"
+#define SK_PNMI_ERR044		(SK_ERRBASE_PNMI + 44)
+#define SK_PNMI_ERR044MSG	"MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0"
+#define SK_PNMI_ERR045		(SK_ERRBASE_PNMI + 45)
+#define SK_PNMI_ERR045MSG	"MacPrivateConf: SK_HWEV_SET_SPEED returned not 0"
+#define SK_PNMI_ERR046		(SK_ERRBASE_PNMI + 46)
+#define SK_PNMI_ERR046MSG	"Monitor: Unknown OID"
+#define SK_PNMI_ERR047		(SK_ERRBASE_PNMI + 47)
+#define SK_PNMI_ERR047MSG	"SirqUpdate: Event function returned not 0"
+#define SK_PNMI_ERR048		(SK_ERRBASE_PNMI + 48)
+#define SK_PNMI_ERR048MSG	"RlmtUpdate: Event function returned not 0"
+#define SK_PNMI_ERR049		(SK_ERRBASE_PNMI + 49)
+#define SK_PNMI_ERR049MSG	"SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
+#define SK_PNMI_ERR050		(SK_ERRBASE_PNMI + 50)
+#define SK_PNMI_ERR050MSG	"SkPnmiInit: Invalid size of 'StatAddr' table!!"
+#define SK_PNMI_ERR051		(SK_ERRBASE_PNMI + 51)
+#define SK_PNMI_ERR051MSG	"SkPnmiEvent: Port switch suspicious"
+#define SK_PNMI_ERR052		(SK_ERRBASE_PNMI + 52)
+#define SK_PNMI_ERR052MSG	""
+#define SK_PNMI_ERR053		(SK_ERRBASE_PNMI + 53)
+#define SK_PNMI_ERR053MSG	"General: Driver release date not initialized"
+#define SK_PNMI_ERR054		(SK_ERRBASE_PNMI + 54)
+#define SK_PNMI_ERR054MSG	"General: Driver release date string too long"
+#define SK_PNMI_ERR055		(SK_ERRBASE_PNMI + 55)
+#define SK_PNMI_ERR055MSG	"General: Driver file name not initialized"
+#define SK_PNMI_ERR056		(SK_ERRBASE_PNMI + 56)
+#define SK_PNMI_ERR056MSG	"General: Driver file name string too long"
+
+/*
+ * Management counter macros called by the driver
+ */
+#define SK_PNMI_SET_DRIVER_DESCR(pAC,v)	((pAC)->Pnmi.pDriverDescription = \
+	(char *)(v))
+
+#define SK_PNMI_SET_DRIVER_VER(pAC,v)	((pAC)->Pnmi.pDriverVersion = \
+	(char *)(v))
+
+#define SK_PNMI_SET_DRIVER_RELDATE(pAC,v)	((pAC)->Pnmi.pDriverReleaseDate = \
+	(char *)(v))
+
+#define SK_PNMI_SET_DRIVER_FILENAME(pAC,v)	((pAC)->Pnmi.pDriverFileName = \
+	(char *)(v))
+
+#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \
+	{ \
+		(pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \
+		if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \
+			(pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \
+		} \
+	}
+#define SK_PNMI_CNT_TX_RETRY(pAC,p)	(((pAC)->Pnmi.Port[p].TxRetryCts)++)
+#define SK_PNMI_CNT_RX_INTR(pAC,p)	(((pAC)->Pnmi.Port[p].RxIntrCts)++)
+#define SK_PNMI_CNT_TX_INTR(pAC,p)	(((pAC)->Pnmi.Port[p].TxIntrCts)++)
+#define SK_PNMI_CNT_NO_RX_BUF(pAC,p)	(((pAC)->Pnmi.Port[p].RxNoBufCts)++)
+#define SK_PNMI_CNT_NO_TX_BUF(pAC,p)	(((pAC)->Pnmi.Port[p].TxNoBufCts)++)
+#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \
+	((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v));
+#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \
+	{ \
+		((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \
+		(pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \
+	}
+#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p)	(((pAC)->Pnmi.Port[p].ErrRecoveryCts)++);
+
+#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \
+	{ \
+		if ((p) < SK_MAX_MACS) { \
+			((pAC)->Pnmi.Port[p].StatSyncCts)++; \
+			(pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \
+		} \
+	}
+
+#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \
+	{ \
+		if ((p) < SK_MAX_MACS) { \
+			((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \
+		} \
+	}
+
+#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \
+	{ \
+		if ((p) < SK_MAX_MACS) { \
+			((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \
+		} \
+	}
+
+#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \
+	{ \
+		if ((p) < SK_MAX_MACS) { \
+			((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \
+		} \
+	}
+
+/*
+ * Conversion Macros
+ */
+#define SK_PNMI_PORT_INST2LOG(i)	((unsigned int)(i) - 1)
+#define SK_PNMI_PORT_LOG2INST(l)	((unsigned int)(l) + 1)
+#define SK_PNMI_PORT_PHYS2LOG(p)	((unsigned int)(p) + 1)
+#define SK_PNMI_PORT_LOG2PHYS(pAC,l)	((unsigned int)(l) - 1)
+#define SK_PNMI_PORT_PHYS2INST(pAC,p)	\
+	(pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2))
+#define SK_PNMI_PORT_INST2PHYS(pAC,i)	((unsigned int)(i) - 2)
+
+/*
+ * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
+ */
+#define SK_PNMI_VPD_KEY_SIZE	5
+#define SK_PNMI_VPD_BUFSIZE		(VPD_SIZE)
+#define SK_PNMI_VPD_ENTRIES		(VPD_SIZE / 4)
+#define SK_PNMI_VPD_DATALEN		128 /*  Number of data bytes */
+
+#define SK_PNMI_MULTICAST_LISTLEN	64
+#define SK_PNMI_SENSOR_ENTRIES		(SK_MAX_SENSORS)
+#define SK_PNMI_CHECKSUM_ENTRIES	3
+#define SK_PNMI_MAC_ENTRIES			(SK_MAX_MACS + 1)
+#define SK_PNMI_MONITOR_ENTRIES		20
+#define SK_PNMI_TRAP_ENTRIES		10
+#define SK_PNMI_TRAPLEN				128
+#define SK_PNMI_STRINGLEN1			80
+#define SK_PNMI_STRINGLEN2			25
+#define SK_PNMI_TRAP_QUEUE_LEN		512
+
+typedef struct s_PnmiVpd {
+	char			VpdKey[SK_PNMI_VPD_KEY_SIZE];
+	char			VpdValue[SK_PNMI_VPD_DATALEN];
+	SK_U8			VpdAccess;
+	SK_U8			VpdAction;
+} SK_PNMI_VPD;
+
+typedef struct s_PnmiSensor {
+	SK_U8			SensorIndex;
+	char			SensorDescr[SK_PNMI_STRINGLEN2];
+	SK_U8			SensorType;
+	SK_U32			SensorValue;
+	SK_U32			SensorWarningThresholdLow;
+	SK_U32			SensorWarningThresholdHigh;
+	SK_U32			SensorErrorThresholdLow;
+	SK_U32			SensorErrorThresholdHigh;
+	SK_U8			SensorStatus;
+	SK_U64			SensorWarningCts;
+	SK_U64			SensorErrorCts;
+	SK_U64			SensorWarningTimestamp;
+	SK_U64			SensorErrorTimestamp;
+} SK_PNMI_SENSOR;
+
+typedef struct s_PnmiChecksum {
+	SK_U64			ChecksumRxOkCts;
+	SK_U64			ChecksumRxUnableCts;
+	SK_U64			ChecksumRxErrCts;
+	SK_U64			ChecksumTxOkCts;
+	SK_U64			ChecksumTxUnableCts;
+} SK_PNMI_CHECKSUM;
+
+typedef struct s_PnmiStat {
+	SK_U64			StatTxOkCts;
+	SK_U64			StatTxOctetsOkCts;
+	SK_U64			StatTxBroadcastOkCts;
+	SK_U64			StatTxMulticastOkCts;
+	SK_U64			StatTxUnicastOkCts;
+	SK_U64			StatTxLongFramesCts;
+	SK_U64			StatTxBurstCts;
+	SK_U64			StatTxPauseMacCtrlCts;
+	SK_U64			StatTxMacCtrlCts;
+	SK_U64			StatTxSingleCollisionCts;
+	SK_U64			StatTxMultipleCollisionCts;
+	SK_U64			StatTxExcessiveCollisionCts;
+	SK_U64			StatTxLateCollisionCts;
+	SK_U64			StatTxDeferralCts;
+	SK_U64			StatTxExcessiveDeferralCts;
+	SK_U64			StatTxFifoUnderrunCts;
+	SK_U64			StatTxCarrierCts;
+	SK_U64			Dummy1; /* StatTxUtilization */
+	SK_U64			StatTx64Cts;
+	SK_U64			StatTx127Cts;
+	SK_U64			StatTx255Cts;
+	SK_U64			StatTx511Cts;
+	SK_U64			StatTx1023Cts;
+	SK_U64			StatTxMaxCts;
+	SK_U64			StatTxSyncCts;
+	SK_U64			StatTxSyncOctetsCts;
+	SK_U64			StatRxOkCts;
+	SK_U64			StatRxOctetsOkCts;
+	SK_U64			StatRxBroadcastOkCts;
+	SK_U64			StatRxMulticastOkCts;
+	SK_U64			StatRxUnicastOkCts;
+	SK_U64			StatRxLongFramesCts;
+	SK_U64			StatRxPauseMacCtrlCts;
+	SK_U64			StatRxMacCtrlCts;
+	SK_U64			StatRxPauseMacCtrlErrorCts;
+	SK_U64			StatRxMacCtrlUnknownCts;
+	SK_U64			StatRxBurstCts;
+	SK_U64			StatRxMissedCts;
+	SK_U64			StatRxFramingCts;
+	SK_U64			StatRxFifoOverflowCts;
+	SK_U64			StatRxJabberCts;
+	SK_U64			StatRxCarrierCts;
+	SK_U64			StatRxIRLengthCts;
+	SK_U64			StatRxSymbolCts;
+	SK_U64			StatRxShortsCts;
+	SK_U64			StatRxRuntCts;
+	SK_U64			StatRxCextCts;
+	SK_U64			StatRxTooLongCts;
+	SK_U64			StatRxFcsCts;
+	SK_U64			Dummy2; /* StatRxUtilization */
+	SK_U64			StatRx64Cts;
+	SK_U64			StatRx127Cts;
+	SK_U64			StatRx255Cts;
+	SK_U64			StatRx511Cts;
+	SK_U64			StatRx1023Cts;
+	SK_U64			StatRxMaxCts;
+} SK_PNMI_STAT;
+
+typedef struct s_PnmiConf {
+	char			ConfMacCurrentAddr[6];
+	char			ConfMacFactoryAddr[6];
+	SK_U8			ConfPMD;
+	SK_U8			ConfConnector;
+	SK_U32			ConfPhyType;
+	SK_U32			ConfPhyMode;
+	SK_U8			ConfLinkCapability;
+	SK_U8			ConfLinkMode;
+	SK_U8			ConfLinkModeStatus;
+	SK_U8			ConfLinkStatus;
+	SK_U8			ConfFlowCtrlCapability;
+	SK_U8			ConfFlowCtrlMode;
+	SK_U8			ConfFlowCtrlStatus;
+	SK_U8			ConfPhyOperationCapability;
+	SK_U8			ConfPhyOperationMode;
+	SK_U8			ConfPhyOperationStatus;
+	SK_U8			ConfSpeedCapability;
+	SK_U8			ConfSpeedMode;
+	SK_U8			ConfSpeedStatus;
+} SK_PNMI_CONF;
+
+#ifndef SK_NO_RLMT
+typedef struct s_PnmiRlmt {
+	SK_U32			RlmtIndex;
+	SK_U32			RlmtStatus;
+	SK_U64			RlmtTxHelloCts;
+	SK_U64			RlmtRxHelloCts;
+	SK_U64			RlmtTxSpHelloReqCts;
+	SK_U64			RlmtRxSpHelloCts;
+} SK_PNMI_RLMT;
+
+typedef struct s_PnmiRlmtMonitor {
+	SK_U32			RlmtMonitorIndex;
+	char			RlmtMonitorAddr[6];
+	SK_U64			RlmtMonitorErrorCts;
+	SK_U64			RlmtMonitorTimestamp;
+	SK_U8			RlmtMonitorAdmin;
+} SK_PNMI_RLMT_MONITOR;
+#endif
+
+typedef struct s_PnmiRequestStatus {
+	SK_U32			ErrorStatus;
+	SK_U32			ErrorOffset;
+} SK_PNMI_REQUEST_STATUS;
+
+typedef struct s_PnmiStrucData {
+	SK_U32			MgmtDBVersion;
+	SK_PNMI_REQUEST_STATUS	ReturnStatus;
+	SK_U32			VpdFreeBytes;
+	char			VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE];
+	SK_U32			VpdEntriesNumber;
+	SK_PNMI_VPD		Vpd[SK_PNMI_VPD_ENTRIES];
+	SK_U32			PortNumber;
+	SK_U32			DeviceType;
+	char			DriverDescr[SK_PNMI_STRINGLEN1];
+	char			DriverVersion[SK_PNMI_STRINGLEN2];
+	char			DriverReleaseDate[SK_PNMI_STRINGLEN1];
+	char			DriverFileName[SK_PNMI_STRINGLEN1];
+	char			HwDescr[SK_PNMI_STRINGLEN1];
+	char			HwVersion[SK_PNMI_STRINGLEN2];
+	SK_U16			Chipset;
+	SK_U32			ChipId;
+	SK_U8			VauxAvail;
+	SK_U32			RamSize;
+	SK_U32			MtuSize;
+	SK_U32			Action;
+	SK_U32			TestResult;
+	SK_U8			BusType;
+	SK_U8			BusSpeed;
+	SK_U8			BusWidth;
+	SK_U8			SensorNumber;
+	SK_PNMI_SENSOR	Sensor[SK_PNMI_SENSOR_ENTRIES];
+	SK_U8			ChecksumNumber;
+	SK_PNMI_CHECKSUM	Checksum[SK_PNMI_CHECKSUM_ENTRIES];
+	SK_PNMI_STAT	Stat[SK_PNMI_MAC_ENTRIES];
+	SK_PNMI_CONF	Conf[SK_PNMI_MAC_ENTRIES];
+#ifndef SK_NO_RLMT
+	SK_U8			RlmtMode;
+	SK_U32			RlmtPortNumber;
+	SK_U8			RlmtPortActive;
+	SK_U8			RlmtPortPreferred;
+	SK_U64			RlmtChangeCts;
+	SK_U64			RlmtChangeTime;
+	SK_U64			RlmtChangeEstimate;
+	SK_U64			RlmtChangeThreshold;
+	SK_PNMI_RLMT	Rlmt[SK_MAX_MACS];
+	SK_U32			RlmtMonitorNumber;
+	SK_PNMI_RLMT_MONITOR	RlmtMonitor[SK_PNMI_MONITOR_ENTRIES];
+#endif
+	SK_U32			TrapNumber;
+	SK_U8			Trap[SK_PNMI_TRAP_QUEUE_LEN];
+	SK_U64			TxSwQueueLen;
+	SK_U64			TxSwQueueMax;
+	SK_U64			TxRetryCts;
+	SK_U64			RxIntrCts;
+	SK_U64			TxIntrCts;
+	SK_U64			RxNoBufCts;
+	SK_U64			TxNoBufCts;
+	SK_U64			TxUsedDescrNo;
+	SK_U64			RxDeliveredCts;
+	SK_U64			RxOctetsDeliveredCts;
+	SK_U64			RxHwErrorsCts;
+	SK_U64			TxHwErrorsCts;
+	SK_U64			InErrorsCts;
+	SK_U64			OutErrorsCts;
+	SK_U64			ErrRecoveryCts;
+	SK_U64			SysUpTime;
+} SK_PNMI_STRUCT_DATA;
+
+#define SK_PNMI_STRUCT_SIZE	(sizeof(SK_PNMI_STRUCT_DATA))
+
+/* The ReturnStatus field must be located before VpdFreeBytes! */
+#define SK_PNMI_MIN_STRUCT_SIZE	((unsigned int)(SK_UPTR)\
+				 &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
+
+/*
+ * Various definitions
+ */
+#define SK_PNMI_EVT_TIMER_CHECK		28125000L	/* 28125 ms */
+
+#define SK_PNMI_VCT_TIMER_CHECK		 4000000L	/* 4 sec. */
+
+#define SK_PNMI_MAX_PROTOS		3
+
+/*
+ * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.
+ * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.
+ */
+#define SK_PNMI_CNT_NO			66
+
+/*
+ * Estimate data structure
+ */
+typedef struct s_PnmiEstimate {
+	unsigned int	EstValueIndex;
+	SK_U64			EstValue[7];
+	SK_U64			Estimate;
+	SK_TIMER		EstTimer;
+} SK_PNMI_ESTIMATE;
+
+
+/*
+ * PNMI specific adapter context structure
+ */
+typedef struct s_PnmiPort {
+	SK_U64			StatSyncCts;
+	SK_U64			StatSyncOctetsCts;
+	SK_U64			StatRxLongFrameCts;
+	SK_U64			StatRxFrameTooLongCts;
+	SK_U64			StatRxPMaccErr;
+	SK_U64			TxSwQueueLen;
+	SK_U64			TxSwQueueMax;
+	SK_U64			TxRetryCts;
+	SK_U64			RxIntrCts;
+	SK_U64			TxIntrCts;
+	SK_U64			RxNoBufCts;
+	SK_U64			TxNoBufCts;
+	SK_U64			TxUsedDescrNo;
+	SK_U64			RxDeliveredCts;
+	SK_U64			RxOctetsDeliveredCts;
+	SK_U64			RxHwErrorsCts;
+	SK_U64			TxHwErrorsCts;
+	SK_U64			InErrorsCts;
+	SK_U64			OutErrorsCts;
+	SK_U64			ErrRecoveryCts;
+	SK_U64			RxShortZeroMark;
+	SK_U64			CounterOffset[SK_PNMI_CNT_NO];
+	SK_U32			CounterHigh[SK_PNMI_CNT_NO];
+	SK_BOOL			ActiveFlag;
+	SK_U8			Align[3];
+} SK_PNMI_PORT;
+
+
+typedef struct s_PnmiData {
+	SK_PNMI_PORT	Port	[SK_MAX_MACS];
+	SK_PNMI_PORT	BufPort	[SK_MAX_MACS]; /* 2002-09-13 pweber  */
+	SK_U64			VirtualCounterOffset[SK_PNMI_CNT_NO];
+	SK_U32			TestResult;
+	char			HwVersion[10];
+	SK_U16			Align01;
+
+	char			*pDriverDescription;
+	char			*pDriverVersion;
+	char			*pDriverReleaseDate;
+	char			*pDriverFileName;
+
+	int				MacUpdatedFlag;
+	int				RlmtUpdatedFlag;
+	int				SirqUpdatedFlag;
+
+	SK_U64			RlmtChangeCts;
+	SK_U64			RlmtChangeTime;
+	SK_PNMI_ESTIMATE	RlmtChangeEstimate;
+	SK_U64			RlmtChangeThreshold;
+
+	SK_U64			StartUpTime;
+	SK_U32			DeviceType;
+	char			PciBusSpeed;
+	char			PciBusWidth;
+	char			Chipset;
+	char			PMD;
+	char			Connector;
+	SK_BOOL			DualNetActiveFlag;
+	SK_U16			Align02;
+
+	char			TrapBuf[SK_PNMI_TRAP_QUEUE_LEN];
+	unsigned int	TrapBufFree;
+	unsigned int	TrapQueueBeg;
+	unsigned int	TrapQueueEnd;
+	unsigned int	TrapBufPad;
+	unsigned int	TrapUnique;
+	SK_U8			VctStatus[SK_MAX_MACS];
+	SK_PNMI_VCT		VctBackup[SK_MAX_MACS];
+	SK_TIMER		VctTimeout[SK_MAX_MACS];
+#ifdef SK_DIAG_SUPPORT
+	SK_U32			DiagAttached;
+#endif /* SK_DIAG_SUPPORT */
+	SK_BOOL         VpdKeyReadError;
+} SK_PNMI;
+
+
+/*
+ * Function prototypes
+ */
+extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
+extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
+	unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
+extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
+	void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
+extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
+	unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
+extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
+	unsigned int *pLen, SK_U32 NetIndex);
+extern int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
+	unsigned int *pLen, SK_U32 NetIndex);
+extern int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
+	unsigned int *pLen, SK_U32 NetIndex);
+extern int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event,
+	SK_EVPARA Param);
+extern int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
+	unsigned int * pLen, SK_U32 NetIndex);
+
+#endif
diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h
--- linux/drivers/net/sk98lin/h/skgesirq.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgesirq.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,144 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/skgesirq.h#6 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #6 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	Gigabit Ethernet special IRQ functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef _INC_SKGESIRQ_H_
+#define _INC_SKGESIRQ_H_
+
+/* Define return codes of SkGePortCheckUp and CheckShort */
+#define SK_HW_PS_NONE		0	/* No action needed */
+#define SK_HW_PS_RESTART	1	/* Restart needed */
+#define SK_HW_PS_LINK		2	/* Link Up actions needed */
+
+/*
+ * Define the Event the special IRQ/INI module can handle
+ */
+#define SK_HWEV_WATIM			1	/* Timeout for WA Errata #2 XMAC */
+#define SK_HWEV_PORT_START		2	/* Port Start Event by RLMT */
+#define SK_HWEV_PORT_STOP		3	/* Port Stop Event by RLMT */
+#define SK_HWEV_CLEAR_STAT		4	/* Clear Statistics by PNMI */
+#define SK_HWEV_UPDATE_STAT		5	/* Update Statistics by PNMI */
+#define SK_HWEV_SET_LMODE		6	/* Set Link Mode by PNMI */
+#define SK_HWEV_SET_FLOWMODE	7	/* Set Flow Control Mode by PNMI */
+#define SK_HWEV_SET_ROLE		8	/* Set Master/Slave (Role) by PNMI */
+#define SK_HWEV_SET_SPEED		9	/* Set Link Speed by PNMI */
+#define SK_HWEV_HALFDUP_CHK		10	/* Half Duplex Hangup Workaround */
+#define SK_HWEV_PAUSE_PACKET	11	/* Pause Packet Handling */
+
+#define SK_WA_ACT_TIME		1000000UL	/* 1000 msec (1 sec) */
+#define SK_WA_INA_TIME		 100000UL	/*  100 msec */
+
+#define SK_HALFDUP_CHK_TIME	  10000UL	/*   10 msec */
+
+#define SK_PAUSE_PKT_TIME	  30000UL	/*   30 msec */
+
+/*
+ * Define the error numbers and messages
+ */
+#define SKERR_SIRQ_E001		(SK_ERRBASE_SIRQ+1)
+#define SKERR_SIRQ_E001MSG	"Unknown event"
+#define SKERR_SIRQ_E002		(SKERR_SIRQ_E001+1)
+#define SKERR_SIRQ_E002MSG	"Packet timeout RX1"
+#define SKERR_SIRQ_E003		(SKERR_SIRQ_E002+1)
+#define SKERR_SIRQ_E003MSG	"Packet timeout RX2"
+#define SKERR_SIRQ_E004		(SKERR_SIRQ_E003+1)
+#define SKERR_SIRQ_E004MSG	"MAC 1 not correctly initialized"
+#define SKERR_SIRQ_E005		(SKERR_SIRQ_E004+1)
+#define SKERR_SIRQ_E005MSG	"MAC 2 not correctly initialized"
+#define SKERR_SIRQ_E006		(SKERR_SIRQ_E005+1)
+#define SKERR_SIRQ_E006MSG	"CHECK failure R1"
+#define SKERR_SIRQ_E007		(SKERR_SIRQ_E006+1)
+#define SKERR_SIRQ_E007MSG	"CHECK failure R2"
+#define SKERR_SIRQ_E008		(SKERR_SIRQ_E007+1)
+#define SKERR_SIRQ_E008MSG	"CHECK failure XS1"
+#define SKERR_SIRQ_E009		(SKERR_SIRQ_E008+1)
+#define SKERR_SIRQ_E009MSG	"CHECK failure XA1"
+#define SKERR_SIRQ_E010		(SKERR_SIRQ_E009+1)
+#define SKERR_SIRQ_E010MSG	"CHECK failure XS2"
+#define SKERR_SIRQ_E011		(SKERR_SIRQ_E010+1)
+#define SKERR_SIRQ_E011MSG	"CHECK failure XA2"
+#define SKERR_SIRQ_E012		(SKERR_SIRQ_E011+1)
+#define SKERR_SIRQ_E012MSG	"Unexpected IRQ Master error"
+#define SKERR_SIRQ_E013		(SKERR_SIRQ_E012+1)
+#define SKERR_SIRQ_E013MSG	"Unexpected IRQ Status error"
+#define SKERR_SIRQ_E014		(SKERR_SIRQ_E013+1)
+#define SKERR_SIRQ_E014MSG	"Parity error on RAM (read)"
+#define SKERR_SIRQ_E015		(SKERR_SIRQ_E014+1)
+#define SKERR_SIRQ_E015MSG	"Parity error on RAM (write)"
+#define SKERR_SIRQ_E016		(SKERR_SIRQ_E015+1)
+#define SKERR_SIRQ_E016MSG	"Parity error MAC 1"
+#define SKERR_SIRQ_E017		(SKERR_SIRQ_E016+1)
+#define SKERR_SIRQ_E017MSG	"Parity error MAC 2"
+#define SKERR_SIRQ_E018		(SKERR_SIRQ_E017+1)
+#define SKERR_SIRQ_E018MSG	"Parity error RX 1"
+#define SKERR_SIRQ_E019		(SKERR_SIRQ_E018+1)
+#define SKERR_SIRQ_E019MSG	"Parity error RX 2"
+#define SKERR_SIRQ_E020		(SKERR_SIRQ_E019+1)
+#define SKERR_SIRQ_E020MSG	"MAC transmit FIFO underrun"
+#define SKERR_SIRQ_E021		(SKERR_SIRQ_E020+1)
+#define SKERR_SIRQ_E021MSG	"Spurious TWSI interrupt"
+#define SKERR_SIRQ_E022		(SKERR_SIRQ_E021+1)
+#define SKERR_SIRQ_E022MSG	"Cable pair swap error"
+#define SKERR_SIRQ_E023		(SKERR_SIRQ_E022+1)
+#define SKERR_SIRQ_E023MSG	"Auto-negotiation error"
+#define SKERR_SIRQ_E024		(SKERR_SIRQ_E023+1)
+#define SKERR_SIRQ_E024MSG	"FIFO overflow error"
+#define SKERR_SIRQ_E025		(SKERR_SIRQ_E024+1)
+#define SKERR_SIRQ_E025MSG	"2 Pair Downshift detected"
+#define SKERR_SIRQ_E026		(SKERR_SIRQ_E025+1)
+#define SKERR_SIRQ_E026MSG	"Uncorrectable PCI Express error"
+#define SKERR_SIRQ_E027		(SKERR_SIRQ_E026+1)
+#define SKERR_SIRQ_E027MSG	"PCI Bus Abort detected"
+#define SKERR_SIRQ_E028		(SKERR_SIRQ_E027+1)
+#define SKERR_SIRQ_E028MSG	"Parity error on RAM 1 (read)"
+#define SKERR_SIRQ_E029		(SKERR_SIRQ_E028+1)
+#define SKERR_SIRQ_E029MSG	"Parity error on RAM 1 (write)"
+#define SKERR_SIRQ_E030		(SKERR_SIRQ_E029+1)
+#define SKERR_SIRQ_E030MSG	"Parity error on RAM 2 (read)"
+#define SKERR_SIRQ_E031		(SKERR_SIRQ_E030+1)
+#define SKERR_SIRQ_E031MSG	"Parity error on RAM 2 (write)"
+#define SKERR_SIRQ_E032		(SKERR_SIRQ_E031+1)
+#define SKERR_SIRQ_E032MSG	"TCP segmentation error async. queue 1"
+#define SKERR_SIRQ_E033		(SKERR_SIRQ_E032+1)
+#define SKERR_SIRQ_E033MSG	"TCP segmentation error sync. queue 1"
+#define SKERR_SIRQ_E034		(SKERR_SIRQ_E033+1)
+#define SKERR_SIRQ_E034MSG	"TCP segmentation error async. queue 2"
+#define SKERR_SIRQ_E035		(SKERR_SIRQ_E034+1)
+#define SKERR_SIRQ_E035MSG	"TCP segmentation error sync. queue 2"
+#define SKERR_SIRQ_E036		(SKERR_SIRQ_E035+1)
+#define SKERR_SIRQ_E036MSG	"CHECK failure polling unit"
+#define SKERR_SIRQ_E037		(SKERR_SIRQ_E036+1)
+#define SKERR_SIRQ_E037MSG	"Unexpected IRQ from 2nd port"
+
+extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
+extern int  SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
+extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
+extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
+#ifndef DISABLE_YUKON_I
+extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
+#endif /* !DISABLE_YUKON_I */
+extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
+
+#endif /* _INC_SKGESIRQ_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h
--- linux/drivers/net/sk98lin/h/skgetwsi.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skgetwsi.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,243 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/twsi/V4/h/skgetwsi.h#4 $
+ * Project:	Gigabit Ethernet Adapters, TWSI-Module
+ * Version:	$Revision: #4 $, $Change: 4277 $
+ * Date:	$DateTime: 2010/11/05 10:41:17 $
+ * Purpose:	Special defines for TWSI
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+ * SKGETWSI.H	contains all SK-98xx specific defines for the TWSI handling
+ */
+
+#ifndef _INC_SKGETWSI_H_
+#define _INC_SKGETWSI_H_
+
+/*
+ * Macros to access the B2_I2C_CTRL
+ */
+#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
+	SK_OUT32(IoC, B2_I2C_CTRL,\
+		((flag) ? 0x80000000UL : 0L) | \
+		(((SK_U32)(reg) << 16) & I2C_ADDR) | \
+		(((SK_U32)(dev) << 9) & I2C_DEV_SEL) | \
+		((dev_size) & I2C_DEV_SIZE) | \
+		((burst) ? I2C_BURST_LEN : 0))
+
+#define SK_I2C_STOP(IoC) {			\
+	SK_U32	I2c_Ctrl;				\
+	SK_IN32(IoC, B2_I2C_CTRL, &I2c_Ctrl);	\
+	SK_OUT32(IoC, B2_I2C_CTRL, I2c_Ctrl | I2C_STOP);	\
+}
+
+#define SK_I2C_GET_CTL(IoC, pI2cCtrl)	SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
+
+/*
+ * Macros to access the TWSI SW Registers
+ */
+#define SK_I2C_SET_BIT(IoC, SetBits) {			\
+	SK_U8	OrgBits;				\
+	SK_IN8(IoC, B2_I2C_SW, &OrgBits);		\
+	SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits));	\
+}
+
+#define SK_I2C_CLR_BIT(IoC, ClrBits) {			\
+	SK_U8	OrgBits;				\
+	SK_IN8(IoC, B2_I2C_SW, &OrgBits);		\
+	SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits)));	\
+}
+
+#define SK_I2C_GET_SW(IoC, pI2cSw)	SK_IN8(IoC, B2_I2C_SW, pI2cSw)
+
+/*
+ * define the possible sensor states
+ */
+#define SK_SEN_IDLE		0	/* Idle: sensor not read */
+#define SK_SEN_VALUE	1	/* Value Read cycle */
+#define SK_SEN_VALEXT	2	/* Extended Value Read cycle */
+
+/*
+ * Conversion factor to convert read Voltage sensor to milli Volt
+ * Conversion factor to convert read Temperature sensor to 10th degree Celsius
+ */
+#define SK_LM80_VT_LSB		22	/* 22mV LSB resolution */
+#define SK_LM80_TEMP_LSB	10	/* 1 degree LSB resolution */
+#define SK_LM80_TEMPEXT_LSB	 5	/* 0.5 degree LSB resolution for ext. val. */
+
+/*
+ * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
+ * assuming: 6500 rpm, 4 pulses, divisor 1
+ */
+#define SK_LM80_FAN_FAKTOR	((22500L*60)/(1*2))
+
+/*
+ * Define sensor management data
+ * Maximum is reached on Genesis copper dual port and Yukon-64
+ * Board specific maximum is in pAC->I2c.MaxSens
+ */
+#define SK_MAX_SENSORS	8	/* maximal no. of installed sensors */
+#define SK_MIN_SENSORS	5	/* minimal no. of installed sensors */
+
+/*
+ * To watch the state machine (SM) use the timer in two ways
+ * instead of one as hitherto
+ */
+#define SK_TIMER_WATCH_SM		0	/* Watch the SM to finish in a spec. time */
+#define SK_TIMER_NEW_GAUGING	1	/* Start a new gauging when timer expires */
+
+/*
+ * Defines for the individual thresholds
+ */
+
+#define C_PLUS_20		120 / 100
+#define C_PLUS_15		115 / 100
+#define C_PLUS_10		110 / 100
+#define C_PLUS_5		105 / 100
+#define C_MINUS_5		 95 / 100
+#define C_MINUS_10		 90 / 100
+#define C_MINUS_15		 85 / 100
+
+/* Temperature sensor */
+#define SK_SEN_TEMP_HIGH_ERR	800	/* Temperature High Err  Threshold */
+#define SK_SEN_TEMP_HIGH_WARN	700	/* Temperature High Warn Threshold */
+#define SK_SEN_TEMP_LOW_WARN	100	/* Temperature Low  Warn Threshold */
+#define SK_SEN_TEMP_LOW_ERR		  0	/* Temperature Low  Err  Threshold */
+
+/* VCC which should be 5 V */
+#define SK_SEN_PCI_5V_HIGH_ERR		5588	/* Voltage PCI High Err  Threshold */
+#define SK_SEN_PCI_5V_HIGH_WARN		5346	/* Voltage PCI High Warn Threshold */
+#define SK_SEN_PCI_5V_LOW_WARN		4664	/* Voltage PCI Low  Warn Threshold */
+#define SK_SEN_PCI_5V_LOW_ERR		4422	/* Voltage PCI Low  Err  Threshold */
+
+/*
+ * VIO may be 5 V or 3.3 V. Initialization takes two parts:
+ * 1. Initialize lowest lower limit and highest higher limit.
+ * 2. After the first value is read correct the upper or the lower limit to
+ *    the appropriate C constant.
+ *
+ * Warning limits are +-5% of the exepected voltage.
+ * Error limits are +-10% of the expected voltage.
+ */
+
+/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
+
+#define SK_SEN_PCI_IO_5V_HIGH_ERR	5566	/* + 10% V PCI-IO High Err Threshold */
+#define SK_SEN_PCI_IO_5V_HIGH_WARN	5324	/* +  5% V PCI-IO High Warn Threshold */
+					/*		5000	mVolt */
+#define SK_SEN_PCI_IO_5V_LOW_WARN	4686	/* -  5% V PCI-IO Low Warn Threshold */
+#define SK_SEN_PCI_IO_5V_LOW_ERR	4444	/* - 10% V PCI-IO Low Err Threshold */
+
+#define SK_SEN_PCI_IO_RANGE_LIMITER	4000	/* 4000 mV range delimiter */
+
+/* correction values for the second pass */
+#define SK_SEN_PCI_IO_3V3_HIGH_ERR	3850	/* + 15% V PCI-IO High Err Threshold */
+#define SK_SEN_PCI_IO_3V3_HIGH_WARN	3674	/* + 10% V PCI-IO High Warn Threshold */
+					/*		3300	mVolt */
+#define SK_SEN_PCI_IO_3V3_LOW_WARN	2926	/* - 10% V PCI-IO Low Warn Threshold */
+#define SK_SEN_PCI_IO_3V3_LOW_ERR	2772	/* - 15% V PCI-IO Low Err  Threshold */
+
+/*
+ * VDD voltage
+ */
+#define SK_SEN_VDD_HIGH_ERR		3630	/* Voltage ASIC High Err  Threshold */
+#define SK_SEN_VDD_HIGH_WARN	3476	/* Voltage ASIC High Warn Threshold */
+#define SK_SEN_VDD_LOW_WARN		3146	/* Voltage ASIC Low  Warn Threshold */
+#define SK_SEN_VDD_LOW_ERR		2970	/* Voltage ASIC Low  Err  Threshold */
+
+/*
+ * PHY PLL 3V3 voltage
+ */
+#define SK_SEN_PLL_3V3_HIGH_ERR		3630	/* Voltage PMA High Err  Threshold */
+#define SK_SEN_PLL_3V3_HIGH_WARN	3476	/* Voltage PMA High Warn Threshold */
+#define SK_SEN_PLL_3V3_LOW_WARN		3146	/* Voltage PMA Low  Warn Threshold */
+#define SK_SEN_PLL_3V3_LOW_ERR		2970	/* Voltage PMA Low  Err  Threshold */
+
+/*
+ * VAUX (YUKON only)
+ */
+#define SK_SEN_VAUX_3V3_VAL		3300	/* Voltage VAUX 3.3 Volt */
+
+#define SK_SEN_VAUX_3V3_HIGH_ERR	(SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
+#define SK_SEN_VAUX_3V3_HIGH_WARN	(SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
+#define SK_SEN_VAUX_3V3_LOW_WARN	(SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
+#define SK_SEN_VAUX_3V3_LOW_ERR		(SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
+
+#define SK_SEN_VAUX_RANGE_LIMITER	1000	/* 1000 mV range delimiter */
+
+/*
+ * PHY 2V5 voltage
+ */
+#define SK_SEN_PHY_2V5_VAL		2500	/* Voltage PHY 2.5 Volt */
+
+#define SK_SEN_PHY_2V5_HIGH_ERR		(SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
+#define SK_SEN_PHY_2V5_HIGH_WARN	(SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
+#define SK_SEN_PHY_2V5_LOW_WARN		(SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
+#define SK_SEN_PHY_2V5_LOW_ERR		(SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
+
+/*
+ * ASIC Core 1V5 voltage (YUKON only)
+ */
+#define SK_SEN_CORE_1V5_VAL		1500	/* Voltage ASIC Core 1.5 Volt */
+
+#define SK_SEN_CORE_1V5_HIGH_ERR	(SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
+#define SK_SEN_CORE_1V5_HIGH_WARN	(SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
+#define SK_SEN_CORE_1V5_LOW_WARN	(SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
+#define SK_SEN_CORE_1V5_LOW_ERR		(SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
+
+/*
+ * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
+ */
+#define SK_SEN_CORE_1V2_VAL		1200	/* Voltage ASIC Core 1.2 Volt */
+
+#define SK_SEN_CORE_1V2_HIGH_ERR	(SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
+#define SK_SEN_CORE_1V2_HIGH_WARN	(SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
+#define SK_SEN_CORE_1V2_LOW_WARN	(SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
+#define SK_SEN_CORE_1V2_LOW_ERR		(SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
+
+#define SK_SEN_CORE_1V3_VAL		1300	/* Voltage ASIC Core 1.3 Volt */
+
+#define SK_SEN_CORE_1V3_HIGH_ERR	(SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
+#define SK_SEN_CORE_1V3_HIGH_WARN	(SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
+#define SK_SEN_CORE_1V3_LOW_WARN	(SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
+#define SK_SEN_CORE_1V3_LOW_ERR		(SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
+
+/*
+ * FAN 1 speed
+ */
+/* assuming: 6500rpm +-15%, 4 pulses,
+ * warning at:	80 %
+ * error at:	70 %
+ * no upper limit
+ */
+#define SK_SEN_FAN_HIGH_ERR		20000	/* FAN Speed High Err Threshold */
+#define SK_SEN_FAN_HIGH_WARN	20000	/* FAN Speed High Warn Threshold */
+#define SK_SEN_FAN_LOW_WARN		 5200	/* FAN Speed Low Warn Threshold */
+#define SK_SEN_FAN_LOW_ERR		 4550	/* FAN Speed Low Err Threshold */
+
+/*
+ * Some Voltages need dynamic thresholds
+ */
+#define SK_SEN_DYN_INIT_NONE		 0  /* No dynamic init of thresholds */
+#define SK_SEN_DYN_INIT_PCI_IO		10  /* Init PCI-IO with new thresholds */
+#define SK_SEN_DYN_INIT_VAUX		11  /* Init VAUX with new thresholds */
+
+extern	int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
+#endif	/* n_INC_SKGETWSI_H */
+
diff -ruN linux/drivers/net/sk98lin/h/skpcidevid.h linux-new/drivers/net/sk98lin/h/skpcidevid.h
--- linux/drivers/net/sk98lin/h/skpcidevid.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skpcidevid.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,239 @@
+/******************************************************************************
+ *
+ * Name:        skpcidevid.h_
+ * Project:     GEnesis, PCI Gigabit Ethernet Adapter
+ * Purpose:     Hold structure with PCI Device IDs
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	(C)Copyright 1998-2002 SysKonnect GmbH.
+ *	(C)Copyright 2002-2007 Marvell.
+ *
+ *	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	Address all question to: gr-msgg-linux@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
+	/*    1 */
+	{ 0x10B7, 0x1700, /* Generic 3Com 3C940 Gigabit Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    2 */
+	{ 0x10B7, 0x80EB, /* Generic 3Com 3C940B Gigabit LOM Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    3 */
+	{ 0x1148, 0x4320, /* Generic SysKonnect SK-98xx V2.0 Gigabit Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    4 */
+	{ 0x1148, 0x9000, /* Generic SysKonnect SK-9Sxx 10/100/1000Base-T Server Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    5 */
+	{ 0x1148, 0x9E00, /* Generic SysKonnect SK-9Exx 10/100/1000Base-T Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    6 */
+	{ 0x1148, 0x9E01, /* SysKonnect SK-9E21M 10/100/1000Base-T Adapter for DASH 1.1 */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    7 */
+	{ 0x1186, 0x4001, /* D-Link DGE-550SX PCI-X Gigabit Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    8 */
+	{ 0x1186, 0x4B00, /* D-Link DGE-560T PCI Express Gigabit Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*    9 */
+	{ 0x1186, 0x4B01, /* D-Link DGE-530T Gigabit Ethernet Adapter (rev.B) */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   10 */
+	{ 0x1186, 0x4B02, /* D-Link DGE-560SX Single Fiber Gigabit Ethernet PCI-E Adapter (rev.A) */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   11 */
+	{ 0x1186, 0x4B03, /* D-Link DGE-550T Gigabit Ethernet Adapter V.B1 */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   12 */
+	{ 0x1186, 0x4C00, /* D-Link DGE-530T Gigabit Ethernet Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   13 */
+	{ 0x11AB, 0x4320, /* Generic Marvell Yukon 88E8001/8003/8010 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   14 */
+	{ 0x11AB, 0x4340, /* Generic Marvell Yukon 88E8021 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   15 */
+	{ 0x11AB, 0x4341, /* Generic Marvell Yukon 88E8022 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   16 */
+	{ 0x11AB, 0x4342, /* Generic Marvell Yukon 88E8061 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   17 */
+	{ 0x11AB, 0x4343, /* Generic Marvell Yukon 88E8062 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   18 */
+	{ 0x11AB, 0x4344, /* Generic Marvell Yukon 88E8021 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   19 */
+	{ 0x11AB, 0x4345, /* Generic Marvell Yukon 88E8022 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   20 */
+	{ 0x11AB, 0x4346, /* Generic Marvell Yukon 88E8061 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   21 */
+	{ 0x11AB, 0x4347, /* Generic Marvell Yukon 88E8062 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   22 */
+	{ 0x11AB, 0x4350, /* Generic Marvell Yukon 88E8035 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   23 */
+	{ 0x11AB, 0x4351, /* Generic Marvell Yukon 88E8036 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   24 */
+	{ 0x11AB, 0x4352, /* Generic Marvell Yukon 88E8038 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   25 */
+	{ 0x11AB, 0x4353, /* Generic Marvell Yukon 88E8039 PCI-E Fast Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   26 */
+	{ 0x11AB, 0x4354, /* Marvell Yukon 88E8040 Family PCI-E Fast Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   27 */
+	{ 0x11AB, 0x4355, /* Generic Marvell Yukon 88E8040T PCI-E Fast Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   28 */
+	{ 0x11AB, 0x4356, /* Generic Marvell Yukon 88EC033 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   29 */
+	{ 0x11AB, 0x4357, /* Generic Marvell Yukon 88E8042 PCI-E Fast Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   30 */
+	{ 0x11AB, 0x435A, /* Generic Marvell Yukon 88E8048 PCI-E Fast Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   31 */
+	{ 0x11AB, 0x4360, /* Generic Marvell Yukon 88E8052 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   32 */
+	{ 0x11AB, 0x4361, /* Generic Marvell Yukon 88E8050 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   33 */
+	{ 0x11AB, 0x4362, /* Generic Marvell Yukon 88E8053 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   34 */
+	{ 0x11AB, 0x4363, /* Generic Marvell Yukon 88E8055 PCI-E Gigabit Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   35 */
+	{ 0x11AB, 0x4364, /* Generic Marvell Yukon 88E8056 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   36 */
+	{ 0x11AB, 0x4365, /* Generic Marvell Yukon 88E8070 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   37 */
+	{ 0x11AB, 0x4366, /* Generic Marvell Yukon 88EC036 PCI-E Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   38 */
+	{ 0x11AB, 0x4367, /* Generic Marvell Yukon 88EC032 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   39 */
+	{ 0x11AB, 0x4368, /* Generic Marvell Yukon 88EC034 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   40 */
+	{ 0x11AB, 0x4369, /* Generic Marvell Yukon 88EC042 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   41 */
+	{ 0x11AB, 0x436A, /* Generic Marvell Yukon 88E8058 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   42 */
+	{ 0x11AB, 0x436B, /* Generic Marvell Yukon 88E8071 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   43 */
+	{ 0x11AB, 0x436C, /* Generic Marvell Yukon 88E8072 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   44 */
+	{ 0x11AB, 0x436D, /* Generic Marvell Yukon 88E8055 PCI-E Gigabit Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   45 */
+	{ 0x11AB, 0x4370, /* Generic Marvell Yukon 88E8075 based Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   46 */
+	{ 0x11AB, 0x4380, /* Marvell Yukon 88E8057 Family PCI-E Gigabit Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   47 */
+	{ 0x11AB, 0x4381, /* Marvell Yukon 88E8059 Family PCI-E Gigabit Ethernet Controller */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   48 */
+	{ 0x11AB, 0x5005, /* Belkin Gigabit Desktop Card10/100/1000Base-T Adapter, Copper RJ-45 */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   49 */
+	{ 0x1371, 0x434E, /* Generic CNet PowerG-2000 1000/100/10Mbps N-Way PCI-Bus Giga-Card */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   50 */
+	{ 0x1737, 0x1032, /* Linksys EG1032 v2 Instant Gigabit Network Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	/*   51 */
+	{ 0x1737, 0x1064, /* Linksys EG1064 v2 Instant Gigabit Network Adapter */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+
+	{ 0, }
+
+};
diff -ruN linux/drivers/net/sk98lin/h/skpflash.h linux-new/drivers/net/sk98lin/h/skpflash.h
--- linux/drivers/net/sk98lin/h/skpflash.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skpflash.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,160 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/h/skpflash.h#6 $
+ * Project:	Flash Programmer, Manufacturing, Diagnostic Tools, and Drivers
+ * Version:	$Revision: #6 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains SPI-Flash EEPROM specific definitions and constants
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef	__INC_SKPFLASH_H
+#define	__INC_SKPFLASH_H 
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ******************************************************************/
+
+/* PFL constants */
+
+#define SK_PFL_READ			1		/* Read action for SkPflManage*() */
+#define SK_PFL_VERIFY		2		/* Verify action for SkPflManage*() */
+#define SK_PFL_WRITE		3		/* Write action for SkPflManage*() */
+#define SK_PFL_ERASE		4		/* Erase action for SkPflManage*() */
+
+/* macros *******************************************************************/
+
+#define FL_SWAP16(x)	\
+			((((x) & 0xff00) >> 8) | \
+			 (((x) & 0x00ff) << 8))
+
+#define FL_SWAP32(x)	\
+			((((x) & 0xff000000) >> 24) | \
+			 (((x) & 0x00ff0000) >>  8) | \
+			 (((x) & 0x0000ff00) <<  8) | \
+			 (((x) & 0x000000ff) << 24))
+
+
+/* typedefs ******************************************************************/
+
+/*
+ * Yukon-II family parallel flash device structure
+ */
+typedef struct s_PflDevTable {
+	char	*pManName;
+	SK_U32	ManId;
+	char	*pDevName;
+	SK_U16	DevId;
+	SK_U32	SectorSize[2];
+	SK_U32	NumSectors[2];
+
+	struct {
+		SK_U8	OpReadStatus;
+		SK_U8	OpReadManDev;
+
+		SK_U8	OpProgram;
+		SK_U8	OpProgramCompare;
+		SK_U8	OpPageErase;
+
+		SK_U8	OpInfoProgram;
+		SK_U8	OpInfoProgramCompare;
+		SK_U8	OpInfoPageErase;
+	} opcodes;
+} SK_PFL_DEVICE;
+
+/*
+ *	Instruction/command code:
+ *	8'h02   Program
+ *	8'h07   Program and Compare
+ *	8'h82   Information memory Program
+ *	8'h87   Information memory Program and compare
+ *	8'h05   Read Status register from Flash memory
+ *	8'h15   Read manufacturer and device code
+ *	8'h52   Page erase (to 1)
+ *	8'hD2   Information memory erase (to 1)
+ *	8'h62   Main memory erase (to 1)
+ *	8'hE2   Both Information and Main memory erase (to 1)
+ *	8'hA4   Shut down the flash
+ *	8'hE5   Wake up the flash
+ *	8'hA5   Set Slew
+ *	8'hB0   Set config register1
+ *	8'hB1   Set config register2
+ *	8'hB2   Set config register3
+ *	8'hB3   Set config register4
+ *	8'hB4   Read config register1
+ *	8'hB5   Read config register2
+ *	8'hB6   Read config register3
+ *	8'hB7   Read config register4
+ */
+
+typedef	struct s_Pfl {
+	SK_PFL_DEVICE	*pPflDev;				/* Pointer to type of parallel flash */
+	SK_U8			YkChipId;
+
+/*	SK_U8			ModifiedPages[0x80];	Modified pages: 0x80000 / 0x1000 */
+} SK_PFL;
+
+/* function prototypes *******************************************************/
+
+/*
+ * Module usage:
+ * - Call SkPflCheck() before calling any other SkPfl*() functions.
+ * - Call SkPflManage() or SkPflManageInfo() to execute actions in the
+ *   main or info part of the integrated parallel flash, respectively.
+ *
+ * NOTE: Writing contiguous 64-byte blocks during a single call to SkPflManage*()
+ *		 minimizes the number of 'program' accesses to the parallel flash.
+ *
+ * skpflash needs spi_timer() as macro or function:
+ *	extern int spi_timer(SK_AC *pAC, unsigned int t);
+ * 't' is the time in seconds after that the timer should expire.
+ * If 't' is 0, then the expiration status is returned (1 for 'expired').
+ *
+ * It also needs SK_IN*() and SK_OUT*() macros (or functions) for
+ * hardware accesses.
+ */
+
+int SkPflCheck(
+	SK_AC	*pAC,
+	SK_IOC	IoC);
+
+int SkPflManage(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U8	*pData,
+	SK_U32	Offs,
+	SK_U32	Len,
+	int		Action);
+
+int SkPflManageInfo(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_U8	*pData,
+	SK_U32	Offs,
+	SK_U32	Len,
+	int		Action);
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_SKPFLASH_H */
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h
--- linux/drivers/net/sk98lin/h/skqueue.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skqueue.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,204 @@
+/******************************************************************************
+ *
+ * Name:	skqueue.h
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Defines for the Event queue
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skqueue.h,v $
+ *	Revision 2.6  2010/07/07 15:50:36  malthoff
+ *	Added macros to lock the scheduler functions.
+ *	
+ *	Revision 2.5  2007/07/31 13:06:54  rschmidt
+ *	Changed defines for error numbers and messages
+ *	Editorial changes
+ *	
+ *	Revision 2.4  2005/12/14 16:11:03  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.3  2004/05/14 13:39:15  malthoff
+ *	Added some debug messages
+ *
+ *	Revision 2.2  2004/02/26 16:03:04  mkunz
+ *	Changes for ASF
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.16  2003/09/16 12:50:32  rschmidt
+ *	Editorial changes
+ *
+ *	Revision 1.15  2003/05/13 17:54:57  mkarl
+ *	Editorial changes.
+ *
+ *	Revision 1.14  2002/03/15 10:52:13  mkunz
+ *	Added event classes for link aggregation
+ *
+ *	Revision 1.13  1999/11/22 13:59:05  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.12  1998/09/08 08:48:01  gklug
+ *	add: init level handling
+ *
+ *	Revision 1.11  1998/09/03 14:15:11  gklug
+ *	add: CSUM and HWAC Eventclass and function.
+ *	fix: pParaPtr according to CCC
+ *
+ *	Revision 1.10  1998/08/20 12:43:03  gklug
+ *	add: typedef SK_QUEUE
+ *
+ *	Revision 1.9  1998/08/19 09:50:59  gklug
+ *	fix: remove struct keyword from C-code (see CCC) add typedefs
+ *
+ *	Revision 1.8  1998/08/18 07:00:01  gklug
+ *	fix: SK_PTR not defined use void * instead.
+ *
+ *	Revision 1.7  1998/08/17 13:43:19  gklug
+ *	chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ *	Revision 1.6  1998/08/14 07:09:30  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.5  1998/08/11 14:26:44  gklug
+ *	chg: Event Dispatcher returns now int.
+ *
+ *	Revision 1.4  1998/08/11 12:15:21  gklug
+ *	add: Error numbers of skqueue module
+ *
+ *	Revision 1.3  1998/08/07 12:54:23  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.2  1998/08/07 09:34:00  gklug
+ *	adapt structure defs to CCC
+ *	add: prototypes for functions
+ *
+ *	Revision 1.1  1998/07/30 14:52:12  gklug
+ *	Initial version.
+ *	Defines Event Classes, Event structs and queue management variables.
+ *
+ ******************************************************************************/
+
+/*
+ * SKQUEUE.H	contains all defines and types for the event queue
+ */
+
+#ifndef _SKQUEUE_H_
+#define _SKQUEUE_H_
+
+/*
+ * define the event classes to be served
+ */
+#define SKGE_DRV	1	/* Driver Event Class */
+#define SKGE_RLMT	2	/* RLMT Event Class */
+#define SKGE_I2C	3	/* I2C Event Class */
+#define SKGE_PNMI	4	/* PNMI Event Class */
+#define SKGE_CSUM	5	/* Checksum Event Class */
+#define SKGE_HWAC	6	/* Hardware Access Event Class */
+
+#define SKGE_SWT	9	/* Software Timer Event Class */
+#define SKGE_LACP	10	/* LACP Aggregation Event Class */
+#define SKGE_RSF	11	/* RSF Aggregation Event Class */
+#define SKGE_MARKER	12	/* MARKER Aggregation Event Class */
+#define SKGE_FD		13	/* FD Distributor Event Class */
+#ifdef SK_ASF
+#define SKGE_ASF	14	/* ASF Event Class */
+#endif
+
+/*
+ * define event queue as circular buffer
+ */
+#define SK_MAX_EVENT	64
+
+/*
+ * Parameter union for the Para stuff
+ */
+typedef	union u_EvPara {
+	void	*pParaPtr;	/* Parameter Pointer */
+	SK_U64	Para64;		/* Parameter 64bit version */
+	SK_U32	Para32[2];	/* Parameter Array of 32bit parameters */
+} SK_EVPARA;
+
+/*
+ * Event Queue
+ *	skqueue.c
+ * events are class/value pairs
+ *	class	is addressee, e.g. RLMT, PNMI etc.
+ *	value	is command, e.g. line state change, ring op change etc.
+ */
+typedef	struct s_EventElem {
+	SK_U32		Class;			/* Event class */
+	SK_U32		Event;			/* Event value */
+	SK_EVPARA	Para;			/* Event parameter */
+} SK_EVENTELEM;
+
+typedef	struct s_Queue {
+	SK_EVENTELEM	EvQueue[SK_MAX_EVENT];
+	SK_EVENTELEM	*EvPut;
+	SK_EVENTELEM	*EvGet;
+} SK_QUEUE;
+
+extern void SkEventInit(SK_AC *, SK_IOC, int Level);
+extern void SkEventQueue(SK_AC *, SK_U32 Class, SK_U32 Event, SK_EVPARA Para);
+extern int  SkEventDispatcher(SK_AC *, SK_IOC);
+
+/* Define Error Numbers and messages */
+#define SKERR_Q_E001	(SK_ERRBASE_QUEUE+1)
+#define SKERR_Q_E001MSG	"Event queue overflow"
+#define SKERR_Q_E002	(SKERR_Q_E001+1)
+#define SKERR_Q_E002MSG	"Undefined event class"
+#define SKERR_Q_E003	(SKERR_Q_E002+1)
+#define SKERR_Q_E003MSG	"Event queued in init level 0"
+#define SKERR_Q_E004	(SKERR_Q_E003+1)
+#define SKERR_Q_E004MSG	"Error reported from event function (queue blocked)"
+#define SKERR_Q_E005	(SKERR_Q_E004+1)
+#define SKERR_Q_E005MSG	"Event scheduler called in init level 0 or 1"
+
+/* define dummies for event mutex and lock */
+#if !defined(SK_EVENT_MUTEX_INITIALZE)
+#define SK_EVENT_MUTEX_INITIALZE(x)
+#endif
+
+#if !defined(SK_EVENT_MUTEX_ACQUIRE)
+#define SK_EVENT_MUTEX_ACQUIRE(x) 		SK_TRUE
+#endif
+
+#if !defined(SK_EVENT_MUTEX_RELEASE)
+#define SK_EVENT_MUTEX_RELEASE(x)
+#endif
+
+#if !defined(SK_EVENT_LOCK_ACQUIRE)
+#define SK_EVENT_LOCK_ACQUIRE(x)
+#endif
+
+#if !defined(SK_EVENT_LOCK_RELEASE)
+#define SK_EVENT_LOCK_RELEASE(x)
+#endif
+
+
+#endif /* _SKQUEUE_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/skspi.h linux-new/drivers/net/sk98lin/h/skspi.h
--- linux/drivers/net/sk98lin/h/skspi.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skspi.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,358 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/h/skspi.h#6 $
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools
+ * Version:	$Revision: #6 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains SPI-Flash EEPROM specific definitions and constants
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef	__INC_SKSPI_H
+#define	__INC_SKSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ******************************************************************/
+
+#define SPI_ADR_REG1	B2_FAR		/* VPD low  addr, SPI loader start addr */
+#define SPI_ADR_REG2	B2_FDP		/* VPD high addr, PiG loader start addr */
+#define SPI_CTRL_REG	B2_LD_CTRL	/* SPI control & status register */
+
+#define B2_TST_REG1		B2_TST_CTRL1/* Test control register */
+
+/* SPI commands and constants */
+
+#define SPI_PATTERN		0xffffffffL	/* Write value for SPI identification */
+#define SPI_COMP_MASK	0xfffe0000L	/* Compare Mask for SPI identification */
+
+#define SPI_VPD_MIN		0x0001f800L	/* Min Eprom addr for access via VPD port */
+#define SPI_VPD_MAX		0xfffff000L /* Max Eprom addr for access via VPD port */
+
+#define SPI_LSECT_OFF	0x18000L	/* Offset of last sector in SPI eprom */
+#define SPI_CONF_OFF	0x1c000L	/* Offset of config space in SPI eprom */
+
+#define SPI_PIG_OFF		0x1f000L	/* Plug-In-Go (PiG) Config space */
+#define SPI_NOC_OFF		0x1f800L	/* Normal Oper. Config (NOC) space */
+#define SPI_VPD_OFF		0x1c000L	/* Vital Product Data (VPD) space */
+#define SPI_PET_OFF		0x1d000L	/* Pet Frames space */
+
+#define SPI_CHIP_SIZE	0x20000L	/* Size of whole SPI eprom */
+#define SPI_SECT_SIZE	0x8000L		/* Size of a sector in SPI eprom */
+
+#define SPI_CONF_SIZE	0x4000L		/* Size of config area in SPI eprom */
+#define SPI_PIG_SIZE	0x0800L		/* Size of PiG area in SPI eprom */
+#define SPI_NOC_SIZE	0x0800L		/* Size of NOC area in SPI eprom */
+#define SPI_VPD_SIZE	0x0100L		/* Size of VPD area in SPI eprom */
+#define SPI_PET_SIZE	0x2000L		/* Size of PET area in SPI eprom */
+
+#define SPI_SECT_ERASE	0x00008000L	/* Sector erase command */
+#define SPI_CHIP_ERASE	0x00001000L /* Chip erase command */
+#define SPI_VPD_MAP		0x00080000L /* VPD to Eprom mapping flag */
+#define SPI_TIMER_SET	4			/* SPI timeout value (sec.) */
+#define SPI_TIMEOUT		0			/* Timeout check flag */
+#define SPI_READ		1			/* Read flag for spi_flash_manage() */
+#define SPI_VERIFY		2			/* Verify flag for spi_flash_manage() */
+#define SPI_WRITE		3			/* Write flag for spi_flash_manage() */
+
+/* VPD regs from PCI config reg. file mapped to control reg. file */
+
+#define VPD_ADR_REG		(B7_CFG_SPC | PCI_VPD_ADR_REG)	/* VPD address register in config file */
+#define VPD_DATA_PORT	(B7_CFG_SPC | PCI_VPD_DAT_REG)	/* VPD data port in configuration file */
+
+#define VPD_FLAG_MASK	0x8000		/* VPD read-write flag */
+
+#define	FT_SPI_UNKNOWN	(-1)
+#define FT_SPI			3			/* Flash type */
+#define FT_SPI_Y2		4			/* Yukon 2/EC SPI flash */
+
+/********************************************************************************
+ * Yukon 2/EC definitions and macros
+ ********************************************************************************/
+
+/* SPI EPROM control register */
+#define SPI_Y2_CONTROL_REG			SPI_CTRL
+/* SPI EPROM address register */
+#define SPI_Y2_ADDRESS_REG			SPI_ADDR
+/* SPI EPROM data register */
+#define SPI_Y2_DATA_REG				SPI_DATA
+/* SPI EPROM vendor-/device-id register */
+#define SPI_Y2_VENDOR_DEVICE_ID_REG	SPI_ID
+/* SPI EPROM first opcode register */
+#define SPI_Y2_OPCODE_REG0			SPI_CFG
+/* SPI EPROM second opcode register */
+#define SPI_Y2_OPCODE_REG1			SPI_OPC1
+/* SPI EPROM third opcode register */
+#define SPI_Y2_OPCODE_REG2			SPI_OPC2
+
+/* SPI EPROM Fast_Read_CYC_EN bit */
+#define SPI_Y2_FAST_READ_EN			BIT_8
+
+/* SPI EPROM instruction extension bit */
+#define SPI_Y2_INST_EXT				BIT_9
+
+/* SPI EPROM command mask */
+#define SPI_Y2_CMD_MASK				(7L << 16 | SPI_Y2_INST_EXT)
+
+/* Reg0 */
+/* SPI EPROM write status instruction */
+#define SPI_Y2_WST					(BIT_19 | 2L << 16 | SPI_Y2_INST_EXT)
+/* SPI EPROM read sector protection instruction */
+#define SPI_Y2_RDSP					(BIT_19 | 3L << 16 | SPI_Y2_INST_EXT)
+
+/* Reg1 */
+/* SPI EPROM read instruction */
+#define SPI_Y2_RD					(BIT_19 | 1L << 16)
+/* SPI EPROM read ID instruction */
+#define SPI_Y2_RDID					(BIT_19 | 2L << 16)
+/* SPI EPROM read status register instruction */
+#define SPI_Y2_RDST					(BIT_19 | 3L << 16)
+
+/* Reg2 */
+/* SPI EPROM write enable instruction */
+#define SPI_Y2_WEN					(BIT_19 | 4L << 16)
+/* SPI EPROM write instruction */
+#define SPI_Y2_WR					(BIT_19 | 5L << 16)
+/* SPI EPROM sector erase instruction */
+#define SPI_Y2_SERS					(BIT_19 | 6L << 16)
+/* SPI EPROM chip erase instruction */
+#define SPI_Y2_CERS					(BIT_19 | 7L << 16)
+
+/* SPI EPROM ID byte count mask */
+#define SPI_Y2_ID_BYTE_COUNT_MASK	(7L << 20)
+
+/* SPI EPROM clock divisor mask */
+#define SPI_Y2_CLK_DIV_MASK			(3L << 26)
+
+#define SPI_Y2_CLK_DIV(x)			(SHIFT26(x) & SPI_Y2_CLK_DIV_MASK)
+
+/* SPI flash read ID protocol */
+#define SPI_Y2_RDID_PROT			(1L << 28)
+
+/* SPI flash VPD mapping enable */
+#define SPI_Y2_VPD_ENABLE			(1L << 29)
+
+/* SPI EPROM BUSY CHECK */
+#define SPI_Y2_IS_BUSY(w)			(((w) >> 30) & 1)
+#define SPI_Y2_IS_BUSY_WR(w)		((w) & 1)
+
+#define SPI_Y2_MAN_ID_MASK			0xff00
+#define SPI_Y2_DEV_ID_MASK			0x00ff
+
+/* SPI flash manufacturer ID's */
+#define SPI_MAN_ID_ATMEL			0x1f
+#define SPI_MAN_ID_SST				0xbf
+#define SPI_MAN_ID_NUM				0x13
+#define SPI_MAN_ID_NUMONYX			0x20
+#define SPI_MAN_ID_CHTEK			0x9d
+#define SPI_MAN_ID_WINBOND			0xef
+#define SPI_MAN_ID_INTEL			0x89
+#define SPI_MAN_ID_MXIC				0xc2
+
+/* wait loop for SPI EPROM to finish command (start spi_timer() before) */
+#define SPI_Y2_WAIT_LP_SE_FINISH_CMD(pAC, IoC, stat, timeout) {		\
+	do {															\
+		SK_IN32(IoC, SPI_Y2_CONTROL_REG, &(stat));					\
+		if (0 != spi_timer(pAC, SPI_TIMEOUT)) {						\
+			fl_print("\nSPI timeout: %d sec.\n", timeout);			\
+			break;													\
+		}															\
+	} while (SPI_Y2_IS_BUSY(stat));									\
+}
+
+/* wait for SPI EPROM to finish command */
+#define SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, timeout) {				\
+	unsigned long stat;												\
+	/* wait for command to finish */								\
+	spi_timer(pAC, timeout);										\
+	SPI_Y2_WAIT_LP_SE_FINISH_CMD(pAC, IoC, stat, timeout);			\
+}
+
+/* wait for SPI EPROM to finish write/erase operation */
+#define SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, timeout) {				\
+	unsigned long stat2;											\
+	/* wait for command to finish */								\
+	spi_timer(pAC, SPI_TIMER_SET);									\
+	SPI_Y2_WAIT_LP_SE_FINISH_CMD(pAC, IoC, stat2, SPI_TIMER_SET);	\
+	if (!SPI_Y2_IS_BUSY(stat2)) {									\
+		/* wait for write to finish or timeout */					\
+		spi_timer(pAC, timeout);									\
+		do {														\
+			SK_IN32(IoC, SPI_Y2_CONTROL_REG, &stat2);				\
+			stat2 &= ~SPI_Y2_CMD_MASK;								\
+			stat2 |= SPI_Y2_RDST;									\
+			SK_OUT32(IoC, SPI_Y2_CONTROL_REG, stat2);				\
+																	\
+			SPI_Y2_WAIT_LP_SE_FINISH_CMD(pAC, IoC, stat2, timeout);	\
+			if (SPI_Y2_IS_BUSY(stat2) ||							\
+				0 != spi_timer(pAC, SPI_TIMEOUT)) {					\
+				break;												\
+			}														\
+			SK_IN32(IoC, SPI_Y2_CONTROL_REG, &stat2);				\
+		} while (SPI_Y2_IS_BUSY_WR(stat2));							\
+	}																\
+}
+
+#if defined(Core) || defined(DJGPP) || !defined(MSDOS)
+#define huge
+#endif /* Core || DJGPP || !MSDOS */
+
+/* typedefs ******************************************************************/
+
+/*
+ * Yukon-II family SPI flash device structure
+ */
+typedef struct s_SpiDevTable {
+	char			*man_name;
+	unsigned char	man_id;
+	char			*dev_name;
+	unsigned char	dev_id;
+	unsigned long	sector_size;
+	unsigned long	sector_num;
+	unsigned char	set_protocol;
+	unsigned char	clk_rate_div;
+	unsigned char	id_byte_count;	/* For Yukon-Optima and later */
+	unsigned char	dev_id2;		/* For Yukon-Optima and later */
+	unsigned		chip_erase_timeout;
+
+	struct {
+		unsigned char	op_read;
+		unsigned char	op_write;
+		unsigned char	op_write_enable;
+		unsigned char	op_write_disable;	/* Unused? */
+		unsigned char	op_read_status;
+		unsigned char	op_read_id;
+		unsigned char	op_sector_erase;
+		unsigned char	op_chip_erase;
+
+		/* For SPI_OPC0 on Yukon-Optima and later */
+		unsigned char	op_write_status;
+		unsigned char	op_read_sect_protect;
+	} opcodes;
+} SK_SPI_DEVICE;
+
+typedef	struct s_GeSpi {
+#ifndef SK_SPI_NO_FLASHFUN
+/* Used in flashfun.c */
+#if defined(MSDOS) || defined(INTERN) || defined(MRVL_UEFI)
+	unsigned char	*fprom;				/* Address of ROM */
+#endif	/* MSDOS || INTERN || MRVL_UEFI */
+
+	/* Statistics */
+	long			prog_retries;
+	int				max_retries;
+	int				erase_cycles;
+	int				vpp;				/* Flag: Vpp is on/off */
+#endif	/* !SK_SPI_NO_FLASHFUN */
+
+/* Used in flashfun.c and skspi.c */
+	long			max_pages;			/* Number of pages in SPI eprom */
+	long			max_faddr;			/* Pagesize of SPI eprom */
+	int				fl_type;			/* Flash type */
+
+/* Used in skspi.c */
+	SK_SPI_DEVICE	*pSpiDev;				/* Pointer to type of SPI flash */
+	unsigned char	yk_chip_id;				/* Chip ID */
+	unsigned char	yk_chip_rev;			/* Chip Revision */
+	unsigned char	needs_unprotect;		/* Needs unprotect before write/erase. */
+	unsigned char	ModifiedPages[0x80];	/* Modified pages: 0x80000 / 0x1000 */
+} SK_SPI;
+
+/* function prototypes *******************************************************/
+
+/*
+ * After every call to flash_check_spi() (which is also called by
+ * init_flash()), the MT-Tools should correct pAC->spi.ModifiedPages[].
+ * For all other users, the values set in flash_check_spi() should be fine.
+ */
+int flash_check_spi(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned long	*FlashSize);
+
+int spi_flash_erase(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned long	off,
+	unsigned long	len);
+
+int spi_flash_manage(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	off,
+	unsigned long	len,
+	int				flag);
+
+int spi_vpd_transfer(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	char	*buf,
+	int		addr,
+	int		len,
+	int		dir);
+
+int spi_get_pig(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+int spi_get_noc(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+int spi_get_pet(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+#ifndef SK_SPI_NO_UPDATE
+
+int spi_update_pig(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+int spi_update_noc(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+int spi_update_pet(
+	SK_AC			*pAC,
+	SK_IOC			IoC,
+	unsigned char	*data,
+	unsigned long	len);
+
+#endif	/* !SK_SPI_NO_UPDATE */
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif /* __INC_SKSPI_H */
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h
--- linux/drivers/net/sk98lin/h/sktimer.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/sktimer.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,120 @@
+/******************************************************************************
+ *
+ * Name:	sktimer.h
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Defines for the timer functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: sktimer.h,v $
+ *	Revision 2.3  2007/07/31 13:11:58  rschmidt
+ *	Used SK_BOOL for Timer flag
+ *	Editorial changes
+ *	
+ *	Revision 2.2  2005/12/14 16:11:03  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.11  2003/09/16 12:58:18  rschmidt
+ *	Editorial changes
+ *
+ *	Revision 1.10  2003/05/13 17:56:44  mkarl
+ *	Editorial changes.
+ *
+ *	Revision 1.9  1999/11/22 14:00:29  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.8  1998/09/08 08:48:02  gklug
+ *	add: init level handling
+ *
+ *	Revision 1.7  1998/08/20 12:31:29  gklug
+ *	fix: SK_TIMCTRL needs to be defined
+ *
+ *	Revision 1.6  1998/08/19 09:51:00  gklug
+ *	fix: remove struct keyword from C-code (see CCC) add typedefs
+ *
+ *	Revision 1.5  1998/08/17 13:43:21  gklug
+ *	chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ *	Revision 1.4  1998/08/14 07:09:31  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.3  1998/08/07 12:54:24  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.2  1998/08/07 09:35:29  gklug
+ *	add: Timer control struct for Adapters context
+ *	add: function prototypes
+ *
+ *	Revision 1.1  1998/08/05 11:27:01  gklug
+ *	First version: adapted from SMT
+ *
+ ******************************************************************************/
+
+/*
+ * SKTIMER.H	contains all defines and types for the timer functions
+ */
+
+#ifndef _SKTIMER_H_
+#define _SKTIMER_H_
+
+#include "h/skqueue.h"
+
+/*
+ * SK timer
+ * - needed wherever a timer is used. Put this in your data structure
+ *   wherever you want.
+ */
+typedef struct s_Timer SK_TIMER;
+
+struct s_Timer {
+	SK_TIMER	*TmNext;	/* linked list */
+	SK_U32		TmClass;	/* Timer Event class */
+	SK_U32		TmEvent;	/* Timer Event value */
+	SK_EVPARA	TmPara;		/* Timer Event parameter */
+	SK_U32		TmDelta;	/* delta time */
+	SK_BOOL		TmActive;	/* flag: active/inactive */
+};
+
+/*
+ * Timer control struct.
+ * - use in Adapters context name pAC->Tim
+ */
+typedef struct s_TimCtrl {
+	SK_TIMER	*StQueue;	/* Head of Timer queue */
+} SK_TIMCTRL;
+
+extern void SkTimerInit(SK_AC *pAC, SK_IOC IoC, int Level);
+extern void SkTimerStop(SK_AC *pAC, SK_IOC IoC, SK_TIMER *pTimer);
+extern void SkTimerStart(SK_AC *pAC, SK_IOC IoC, SK_TIMER *pTimer,
+	SK_U32 Time, SK_U32 Class, SK_U32 Event, SK_EVPARA Para);
+extern void SkTimerDone(SK_AC *pAC, SK_IOC IoC);
+
+#endif /* _SKTIMER_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h
--- linux/drivers/net/sk98lin/h/sktwsi.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/sktwsi.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,180 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/twsi/V4/h/sktwsi.h#4 $
+ * Project:	Gigabit Ethernet Adapters, TWSI-Module
+ * Version:	$Revision: #4 $, $Change: 4277 $
+ * Date:	$DateTime: 2010/11/05 10:41:17 $
+ * Purpose:	Defines to access Voltage and Temperature Sensor
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+ * SKTWSI.H	contains all TWSI specific defines
+ */
+
+#ifndef _SKTWSI_H_
+#define _SKTWSI_H_
+
+typedef struct  s_Sensor SK_SENSOR;
+
+#include "h/skgetwsi.h"
+
+/*
+ * Define the TWSI events.
+ */
+#define SK_I2CEV_IRQ	1	/* IRQ happened Event */
+#define SK_I2CEV_TIM	2	/* Timeout event */
+#define SK_I2CEV_CLEAR	3	/* Clear MIB Values */
+
+/*
+ * Define READ and WRITE Constants.
+ */
+#define I2C_READ	0
+#define I2C_WRITE	1
+#define I2C_BURST	1
+#define I2C_SINGLE	0
+
+#define SKERR_I2C_E001		(SK_ERRBASE_I2C+1)
+#define SKERR_I2C_E001MSG	"Sensor index unknown"
+#define SKERR_I2C_E002		(SKERR_I2C_E001+1)
+#define SKERR_I2C_E002MSG	"TWSI: transfer does not complete"
+#define SKERR_I2C_E003		(SKERR_I2C_E002+1)
+#define SKERR_I2C_E003MSG	"LM80: NAK on device send"
+#define SKERR_I2C_E004		(SKERR_I2C_E003+1)
+#define SKERR_I2C_E004MSG	"LM80: NAK on register send"
+#define SKERR_I2C_E005		(SKERR_I2C_E004+1)
+#define SKERR_I2C_E005MSG	"LM80: NAK on device (2) send"
+#define SKERR_I2C_E006		(SKERR_I2C_E005+1)
+#define SKERR_I2C_E006MSG	"Unknown event"
+#define SKERR_I2C_E007		(SKERR_I2C_E006+1)
+#define SKERR_I2C_E007MSG	"LM80 read out of state"
+#define SKERR_I2C_E008		(SKERR_I2C_E007+1)
+#define SKERR_I2C_E008MSG	"Unexpected sensor read completed"
+#define SKERR_I2C_E009		(SKERR_I2C_E008+1)
+#define SKERR_I2C_E009MSG	"WARNING: temperature sensor out of range"
+#define SKERR_I2C_E010		(SKERR_I2C_E009+1)
+#define SKERR_I2C_E010MSG	"WARNING: voltage sensor out of range"
+#define SKERR_I2C_E011		(SKERR_I2C_E010+1)
+#define SKERR_I2C_E011MSG	"ERROR: temperature sensor out of range"
+#define SKERR_I2C_E012		(SKERR_I2C_E011+1)
+#define SKERR_I2C_E012MSG	"ERROR: voltage sensor out of range"
+#define SKERR_I2C_E013		(SKERR_I2C_E012+1)
+#define SKERR_I2C_E013MSG	"ERROR: couldn't init sensor"
+#define SKERR_I2C_E014		(SKERR_I2C_E013+1)
+#define SKERR_I2C_E014MSG	"WARNING: fan sensor out of range"
+#define SKERR_I2C_E015		(SKERR_I2C_E014+1)
+#define SKERR_I2C_E015MSG	"ERROR: fan sensor out of range"
+#define SKERR_I2C_E016		(SKERR_I2C_E015+1)
+#define SKERR_I2C_E016MSG	"TWSI: active transfer does not complete"
+
+/*
+ * Define Timeout values
+ */
+#define SK_I2C_TIM_LONG		2000000L	/* 2 seconds */
+#define SK_I2C_TIM_SHORT	 100000L	/* 100 milliseconds */
+#define SK_I2C_TIM_WATCH	1000000L	/* 1 second */
+
+/*
+ * Define trap and error log hold times
+ */
+#ifndef SK_SEN_ERR_TR_HOLD
+#define SK_SEN_ERR_TR_HOLD		( 4*SK_TICKS_PER_SEC)
+#endif
+#ifndef SK_SEN_ERR_LOG_HOLD
+#define SK_SEN_ERR_LOG_HOLD		(60*SK_TICKS_PER_SEC)
+#endif
+#ifndef SK_SEN_WARN_TR_HOLD
+#define SK_SEN_WARN_TR_HOLD		(15*SK_TICKS_PER_SEC)
+#endif
+#ifndef	SK_SEN_WARN_LOG_HOLD
+#define SK_SEN_WARN_LOG_HOLD	(15*60*SK_TICKS_PER_SEC)
+#endif
+
+/*
+ * Defines for SenType
+ */
+#define SK_SEN_UNKNOWN	0
+#define SK_SEN_TEMP		1
+#define SK_SEN_VOLT		2
+#define SK_SEN_FAN		3
+
+/*
+ * Define for the SenErrorFlag
+ */
+#define SK_SEN_ERR_NOT_PRESENT	0	/* Error Flag: Sensor not present */
+#define SK_SEN_ERR_OK			1	/* Error Flag: O.K. */
+#define SK_SEN_ERR_WARN			2	/* Error Flag: Warning */
+#define SK_SEN_ERR_ERR			3	/* Error Flag: Error */
+#define SK_SEN_ERR_FAULTY		4	/* Error Flag: Faulty */
+
+/*
+ * Define the Sensor struct
+ */
+struct s_Sensor {
+	char	*SenDesc;			/* Description */
+	int		SenType;			/* Voltage or Temperature */
+	SK_I32	SenValue;			/* Current value of the sensor */
+	SK_I32	SenThreErrHigh;		/* High error Threshhold of this sensor */
+	SK_I32	SenThreWarnHigh;	/* High warning Threshhold of this sensor */
+	SK_I32	SenThreErrLow;		/* Lower error Threshold of the sensor */
+	SK_I32	SenThreWarnLow;		/* Lower warning Threshold of the sensor */
+	int		SenErrFlag;			/* Sensor indicated an error */
+	SK_BOOL	SenInit;			/* Is sensor initialized ? */
+	SK_U64	SenErrCts;			/* Error trap counter */
+	SK_U64	SenWarnCts;			/* Warning trap counter */
+	SK_U64	SenBegErrTS;		/* Begin error timestamp */
+	SK_U64	SenBegWarnTS;		/* Begin warning timestamp */
+	SK_U64	SenLastErrTrapTS;	/* Last error trap timestamp */
+	SK_U64	SenLastErrLogTS;	/* Last error log timestamp */
+	SK_U64	SenLastWarnTrapTS;	/* Last warning trap timestamp */
+	SK_U64	SenLastWarnLogTS;	/* Last warning log timestamp */
+	int		SenState;			/* Sensor State (see HW specific include) */
+	int		(*SenRead)(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
+								/* Sensors read function */
+	SK_U16	SenReg;				/* Register Address for this sensor */
+	SK_U8	SenDev;				/* Device Selection for this sensor */
+};
+
+typedef struct s_I2c {
+	SK_SENSOR	SenTable[SK_MAX_SENSORS];	/* Sensor Table */
+	int			CurrSens;	/* Which sensor is currently queried */
+	int			MaxSens;	/* Max. number of sensors */
+	int			TimerMode;	/* Use the timer also to watch the state machine */
+	int			InitLevel;	/* Initialized Level */
+#ifndef SK_DIAG
+	int			DummyReads;	/* Number of non-checked dummy reads */
+	SK_TIMER	SenTimer;	/* Sensors timer */
+#endif /* !SK_DIAG */
+} SK_I2C;
+
+extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
+extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
+					  int Reg, int Burst);
+extern int SkI2cWait(SK_AC *pAC, SK_IOC IoC, int Event);
+
+extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
+#ifdef SK_DIAG
+extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
+						int Burst);
+#else  /* !SK_DIAG */
+extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
+extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
+extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
+#endif /* !SK_DIAG */
+#endif /* n_SKTWSI_H */
+
diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h
--- linux/drivers/net/sk98lin/h/sktypes.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/sktypes.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,48 @@
+/******************************************************************************
+ *
+ * Name:	sktypes.h
+ * Project:	GEnesis, PCI Gigabit Ethernet Adapter
+ * Purpose:	Define data types for Linux
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKTYPES_H
+#define __INC_SKTYPES_H
+
+#define SK_I8    s8    /* 8 bits (1 byte) signed       */
+#define SK_U8    u8    /* 8 bits (1 byte) unsigned     */
+#define SK_I16  s16    /* 16 bits (2 bytes) signed     */
+#define SK_U16  u16    /* 16 bits (2 bytes) unsigned   */
+#define SK_I32  s32    /* 32 bits (4 bytes) signed     */
+#define SK_U32  u32    /* 32 bits (4 bytes) unsigned   */
+#define SK_I64  s64    /* 64 bits (8 bytes) signed     */
+#define SK_U64  u64    /* 64 bits (8 bytes) unsigned   */
+
+#define SK_UPTR	ulong  /* casting pointer <-> integral */
+
+#define SK_BOOL   SK_U8
+#define SK_FALSE  0
+#define SK_TRUE   (!SK_FALSE)
+
+#endif	/* __INC_SKTYPES_H */
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h
--- linux/drivers/net/sk98lin/h/skversion.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skversion.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Name:	skversion.h
+ * Project:	GEnesis, PCI Gigabit Ethernet Adapter
+ * Purpose:	specific version strings and numbers
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	(C)Copyright 1998-2002 SysKonnect GmbH.
+ *	(C)Copyright 2002-2005 Marvell.
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ ******************************************************************************/
+
+#define BOOT_STRING  "sk98lin: Network Device Driver v10.88.3.3\n" \
+                     "(C)Copyright 1999-2011 Marvell(R)."
+#define VER_STRING   "10.88.3.3"
+#define PATCHLEVEL   "03"
+#define DRIVER_FILE_NAME   "sk98lin"
+#define DRIVER_REL_DATE    "May-16-2011"
+#define DRV_NAME   "sk98lin"
+#define DRV_VERSION   "10.88.3.3"
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#define FW_FILE_PATHNAME    "/lib/firmware/___FWIMGNAME__"
+#define FW_FILE_NAME        "___FWIMGNAME__"
+#endif
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h
--- linux/drivers/net/sk98lin/h/skvpd.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/skvpd.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,284 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/vpd/V4/h/skvpd.h#4 $
+ * Project:	Gigabit Ethernet Adapters, VPD-Module
+ * Version:	$Revision: #4 $, $Change: 4281 $
+ * Date:	$DateTime: 2010/11/05 11:58:07 $
+ * Purpose:	Defines and Macros for VPD handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+ * skvpd.h	contains Diagnostic specific defines for VPD handling
+ */
+
+#ifndef __INC_SKVPD_H_
+#define __INC_SKVPD_H_
+
+/*
+ * Define Resource Type Identifiers and VPD keywords
+ */
+#define RES_ID		0x82	/* Resource Type ID String (Product Name) */
+#define RES_VPD_R	0x90	/* start of VPD read only area */
+#define RES_VPD_W	0x91	/* start of VPD read/write area */
+#define RES_END		0x78	/* Resource Type End Tag */
+
+#ifndef VPD_NAME
+#define VPD_NAME	"Name"	/* Product Name, VPD name of RES_ID */
+#endif	/* VPD_NAME */
+#define VPD_PN		"PN"	/* Adapter Part Number */
+#define VPD_EC		"EC"	/* Engineering Change Level */
+#define VPD_MN		"MN"	/* Manufacture ID */
+#define VPD_SN		"SN"	/* Serial Number */
+#define VPD_CP		"CP"	/* Extended Capability */
+#define VPD_RV		"RV"	/* Checksum and Reserved */
+#define VPD_YA		"YA"	/* Asset Tag Identifier */
+#define VPD_VL		"VL"	/* First Error Log Message (SK specific) */
+#define VPD_VF		"VF"	/* Second Error Log Message (SK specific) */
+#define VPD_VB		"VB"	/* Boot Agent ROM Configuration (SK specific) */
+#define VPD_VE		"VE"	/* EFI UNDI Configuration (SK specific) */
+#define VPD_RW		"RW"	/* Remaining Read / Write Area */
+
+/* 'type' values for vpd_setup_para() */
+#define VPD_RO_KEY	1	/* RO keys are "PN", "EC", "MN", "SN", "RV" */
+#define VPD_RW_KEY	2	/* RW keys are "Yx", "Vx", and "RW" */
+
+/* 'op' values for vpd_setup_para() */
+#define ADD_KEY		1	/* add the key at the pos "RV" or "RW" */
+#define OWR_KEY		2	/* overwrite key if already exists */
+
+/*
+ * Define READ and WRITE Constants.
+ */
+
+#define VPD_DEV_ID_GENESIS	0x4300
+
+#define VPD_SIZE_YUKON		256
+#define VPD_SIZE_GENESIS	512
+#define VPD_SIZE			512
+#define VPD_READ	0x0000
+#define VPD_WRITE	0x8000
+
+#define VPD_STOP(pAC,IoC)	VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
+
+#define VPD_GET_RES_LEN(p)	((unsigned int)\
+					(*(SK_U8 *)&(p)[1]) |\
+					((*(SK_U8 *)&(p)[2]) << 8))
+#define VPD_GET_VPD_LEN(p)	((unsigned int)(*(SK_U8 *)&(p)[2]))
+#define VPD_GET_VAL(p)		((char *)&(p)[3])
+
+#define VPD_MAX_LEN	50
+
+#define VPD_SPI_ADDR	0x1f700UL
+
+/* VPD status */
+	/* bit 7..2 reserved */
+#ifndef SK_SLIM
+#define VPD_NO_RW	(1<<1)	/* No buffer available for VPD R/W data */
+#endif	/* SK_SLIM */
+#define VPD_VALID	(1<<0)	/* VPD buffer, vpd_free_ro, and vpd_free_rw valid */
+
+/*
+ * VPD structs
+ */
+typedef	struct s_vpd_status {
+	unsigned short	Align01;			/* Alignment */
+	unsigned short	vpd_status;			/* VPD status, description see above */
+	int				vpd_free_ro;		/* unused bytes in read only area */
+	int				vpd_free_rw;		/* bytes available in read/write area */
+} SK_VPD_STATUS;
+
+typedef	struct s_vpd {
+	SK_VPD_STATUS	v;					/* VPD status structure */
+	char			vpd_buf[VPD_SIZE];	/* VPD buffer */
+	int				rom_size;			/* VPD ROM size from PCI_OUR_REG_2 */
+	int				vpd_size;			/* saved VPD-size */
+	SK_BOOL			CfgInSpi;			/* config data is stored in SPI flash */
+} SK_VPD;
+
+typedef	struct s_vpd_para {
+	unsigned int	p_len;	/* parameter length */
+	char			*p_val;	/* points to the value */
+} SK_VPD_PARA;
+
+/*
+ * structure of Large Resource Type Identifiers
+ */
+
+/* was removed because of alignment problems */
+
+/*
+ * structure of VPD keywords
+ */
+typedef	struct s_vpd_key {
+	char			p_key[2];	/* 2 bytes ID string */
+	unsigned char	p_len;		/* 1 byte length */
+	char			p_val;		/* start of the value string */
+} SK_VPD_KEY;
+
+
+/*
+ * System specific VPD macros
+ */
+#ifndef SK_DIAG
+#ifndef VPD_DO_IO
+#define VPD_OUT8(pAC,IoC,Addr,Val)	(void)SkPciWriteCfgByte(pAC,PCI_C1(pAC,Addr),Val)
+#define VPD_OUT16(pAC,IoC,Addr,Val)	(void)SkPciWriteCfgWord(pAC,PCI_C1(pAC,Addr),Val)
+#define VPD_OUT32(pAC,IoC,Addr,Val)	(void)SkPciWriteCfgDWord(pAC,PCI_C1(pAC,Addr),Val)
+#define VPD_IN8(pAC,IoC,Addr,pVal)	(void)SkPciReadCfgByte(pAC,PCI_C1(pAC,Addr),pVal)
+#define VPD_IN16(pAC,IoC,Addr,pVal)	(void)SkPciReadCfgWord(pAC,PCI_C1(pAC,Addr),pVal)
+#define VPD_IN32(pAC,IoC,Addr,pVal)	(void)SkPciReadCfgDWord(pAC,PCI_C1(pAC,Addr),pVal)
+#else	/* VPD_DO_IO */
+#define VPD_OUT8(pAC,IoC,Addr,Val)	SK_OUT8(IoC,PCI_C2(pAC,IoC,Addr),Val)
+#define VPD_OUT16(pAC,IoC,Addr,Val)	SK_OUT16(IoC,PCI_C2(pAC,IoC,Addr),Val)
+#define VPD_OUT32(pAC,IoC,Addr,Val)	SK_OUT32(IoC,PCI_C2(pAC,IoC,Addr),Val)
+#define VPD_IN8(pAC,IoC,Addr,pVal)	SK_IN8(IoC,PCI_C2(pAC,IoC,Addr),pVal)
+#define VPD_IN16(pAC,IoC,Addr,pVal)	SK_IN16(IoC,PCI_C2(pAC,IoC,Addr),pVal)
+#define VPD_IN32(pAC,IoC,Addr,pVal)	SK_IN32(IoC,PCI_C2(pAC,IoC,Addr),pVal)
+#endif	/* VPD_DO_IO */
+#else	/* SK_DIAG */
+#define VPD_OUT8(pAC,Ioc,Addr,Val) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciWriteCfgByte(pAC,PCI_C1(pAC, Addr),Val);	\
+		else												\
+			SK_OUT8(pAC,PCI_C2(pAC,IoC,Addr),Val);			\
+		}
+#define VPD_OUT16(pAC,Ioc,Addr,Val) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciWriteCfgWord(pAC,PCI_C1(pAC, Addr),Val);	\
+		else												\
+			SK_OUT16(pAC,PCI_C2(pAC,IoC,Addr),Val);			\
+		}
+#define VPD_OUT32(pAC,Ioc,Addr,Val) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciWriteCfgDWord(pAC,PCI_C1(pAC, Addr),Val);	\
+		else												\
+			SK_OUT32(pAC,PCI_C2(pAC,IoC,Addr),Val);			\
+		}
+#define VPD_IN8(pAC,Ioc,Addr,pVal) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciReadCfgByte(pAC,PCI_C1(pAC, Addr),pVal);	\
+		else												\
+			SK_IN8(pAC,PCI_C2(pAC,IoC,Addr),pVal);			\
+		}
+#define VPD_IN16(pAC,Ioc,Addr,pVal) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciReadCfgWord(pAC,PCI_C1(pAC, Addr),pVal);	\
+		else												\
+			SK_IN16(pAC,PCI_C2(pAC,IoC,Addr),pVal);			\
+		}
+#define VPD_IN32(pAC,Ioc,Addr,pVal) {						\
+		if ((pAC)->DgT.DgUseCfgCycle)						\
+			SkPciReadCfgDWord(pAC,PCI_C1(pAC, Addr),pVal);	\
+		else												\
+			SK_IN32(pAC,PCI_C2(pAC,IoC,Addr),pVal);			\
+		}
+#endif /* SK_DIAG */
+
+/* function prototypes ********************************************************/
+
+#ifndef	SK_KR_PROTO
+#ifdef SK_DIAG
+extern SK_U32	VpdReadDWord(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	int			addr);
+#endif /* SK_DIAG */
+
+extern int	VpdSetupPara(
+	SK_AC		*pAC,
+	const char	*key,
+	const char	*buf,
+	int			len,
+	int			type,
+	int			op);
+
+extern SK_VPD_STATUS	*VpdStat(
+	SK_AC		*pAC,
+	SK_IOC		IoC);
+
+extern int	VpdKeys(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	char		*buf,
+	int			*len,
+	int			*elements);
+
+extern int	VpdRead(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	const char	*key,
+	char		*buf,
+	int			*len);
+
+extern SK_BOOL	VpdMayWrite(
+	char		*key);
+
+extern int	VpdWrite(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	const char	*key,
+	const char	*buf);
+
+extern int	VpdDelete(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	char		*key);
+
+extern int	VpdUpdate(
+	SK_AC		*pAC,
+	SK_IOC		IoC);
+
+extern void	VpdErrLog(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	char		*msg);
+
+int VpdInit(
+	SK_AC		*pAC,
+	SK_IOC		IoC);
+
+extern int	VpdReadBlock(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	char		*buf,
+	int			addr,
+	int			len);
+
+extern int	VpdWriteBlock(
+	SK_AC		*pAC,
+	SK_IOC		IoC,
+	char		*buf,
+	int			addr,
+	int			len);
+
+#else	/* SK_KR_PROTO */
+extern SK_U32	VpdReadDWord();
+extern int	VpdSetupPara();
+extern SK_VPD_STATUS	*VpdStat();
+extern int	VpdKeys();
+extern int	VpdRead();
+extern SK_BOOL	VpdMayWrite();
+extern int	VpdWrite();
+extern int	VpdDelete();
+extern int	VpdUpdate();
+extern void	VpdErrLog();
+#endif	/* SK_KR_PROTO */
+
+#endif	/* __INC_SKVPD_H_ */
+
diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h
--- linux/drivers/net/sk98lin/h/sky2le.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/sky2le.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,982 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/sky2le.h#7 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #7 $, $Change: 4376 $
+ * Date:	$DateTime: 2010/11/10 18:08:48 $
+ * Purpose:	Common List Element definitions and access macros
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#ifndef __INC_SKY2LE_H
+#define __INC_SKY2LE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* __cplusplus */
+
+/* defines ********************************************************************/
+
+#define MIN_LEN_OF_LE_TAB	128
+#define MAX_LEN_OF_LE_TAB	4096
+#ifdef USE_POLLING_UNIT
+#define NUM_LE_POLLING_UNIT	2
+#endif
+#define MAX_FRAG_OVERHEAD	10
+
+/* Macro for aligning a given value */
+#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) {					\
+	(AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
+}
+
+/******************************************************************************
+ *
+ * LE2DWord() - Converts the given Little Endian value to machine order value
+ *
+ * Description:
+ *	This function converts the Little Endian value received as an argument to
+ *	the machine order value.
+ *
+ * Returns:
+ *	The converted value
+ *
+ */
+
+#ifdef SK_LITTLE_ENDIAN
+
+#ifndef	SK_USE_REV_DESC
+#define LE2DWord(value)	(value)
+#else	/* SK_USE_REV_DESC */
+#define LE2DWord(value)					\
+	((((value)<<24L) & 0xff000000L) +	\
+	 (((value)<< 8L) & 0x00ff0000L) +	\
+	 (((value)>> 8L) & 0x0000ff00L) +	\
+	 (((value)>>24L) & 0x000000ffL))
+#endif	/* SK_USE_REV_DESC */
+
+#else	/* !SK_LITTLE_ENDIAN */
+
+#ifndef	SK_USE_REV_DESC
+#define LE2DWord(value)					\
+	((((value)<<24L) & 0xff000000L) +	\
+	 (((value)<< 8L) & 0x00ff0000L) +	\
+	 (((value)>> 8L) & 0x0000ff00L) +	\
+	 (((value)>>24L) & 0x000000ffL))
+#else	/* SK_USE_REV_DESC */
+#define LE2DWord(value)	(value)
+#endif	/* SK_USE_REV_DESC */
+
+#endif	/* !SK_LITTLE_ENDIAN */
+
+/******************************************************************************
+ *
+ * DWord2LE() - Converts the given value to a Little Endian value
+ *
+ * Description:
+ *	This function converts the value received as an argument to a Little Endian
+ *	value on Big Endian machines. If the machine running the code is Little
+ *	Endian, then no conversion is done.
+ *
+ * Returns:
+ *	The converted value
+ *
+ */
+
+#ifdef SK_LITTLE_ENDIAN
+
+#ifndef	SK_USE_REV_DESC
+#define DWord2LE(value) (value)
+#else	/* SK_USE_REV_DESC */
+#define DWord2LE(value)					\
+	((((value)<<24L) & 0xff000000L) +	\
+	 (((value)<< 8L) & 0x00ff0000L) +	\
+	 (((value)>> 8L) & 0x0000ff00L) +	\
+	 (((value)>>24L) & 0x000000ffL))
+#endif	/* SK_USE_REV_DESC */
+
+#else	/* !SK_LITTLE_ENDIAN */
+
+#ifndef	SK_USE_REV_DESC
+#define DWord2LE(value)					\
+	((((value)<<24L) & 0xff000000L) +	\
+	 (((value)<< 8L) & 0x00ff0000L) +	\
+	 (((value)>> 8L) & 0x0000ff00L) +	\
+	 (((value)>>24L) & 0x000000ffL))
+#else	/* SK_USE_REV_DESC */
+#define DWord2LE(value) (value)
+#endif	/* SK_USE_REV_DESC */
+#endif	/* !SK_LITTLE_ENDIAN */
+
+/******************************************************************************
+ *
+ * LE2Word() - Converts the given Little Endian value to machine order value
+ *
+ * Description:
+ *	This function converts the Little Endian value received as an argument to
+ *	the machine order value.
+ *
+ * Returns:
+ *	The converted value
+ *
+ */
+
+#ifdef SK_LITTLE_ENDIAN
+#ifndef	SK_USE_REV_DESC
+#define LE2Word(value) (value)
+#else	/* SK_USE_REV_DESC */
+#define LE2Word(value)				\
+	((((value)<< 8L) & 0xff00) +	\
+	 (((value)>> 8L) & 0x00ff))
+#endif	/* SK_USE_REV_DESC */
+
+#else	/* !SK_LITTLE_ENDIAN */
+#ifndef	SK_USE_REV_DESC
+#define LE2Word(value)				\
+	((((value)<< 8L) & 0xff00) +	\
+	 (((value)>> 8L) & 0x00ff))
+#else	/* SK_USE_REV_DESC */
+#define LE2Word(value) (value)
+#endif	/* SK_USE_REV_DESC */
+#endif	/* !SK_LITTLE_ENDIAN */
+
+/******************************************************************************
+ *
+ * Word2LE() - Converts the given value to a Little Endian value
+ *
+ * Description:
+ *	This function converts the value received as an argument to a Little Endian
+ *	value on Big Endian machines. If the machine running the code is Little
+ *	Endian, then no conversion is done.
+ *
+ * Returns:
+ *	The converted value
+ *
+ */
+
+#ifdef SK_LITTLE_ENDIAN
+#ifndef	SK_USE_REV_DESC
+#define Word2LE(value) (value)
+#else	/* SK_USE_REV_DESC */
+#define Word2LE(value)				\
+	((((value)<< 8L) & 0xff00) +	\
+	 (((value)>> 8L) & 0x00ff))
+#endif	/* SK_USE_REV_DESC */
+
+#else	/* !SK_LITTLE_ENDIAN */
+#ifndef	SK_USE_REV_DESC
+#define Word2LE(value)				\
+	((((value)<< 8L) & 0xff00) +	\
+	 (((value)>> 8L) & 0x00ff))
+#else	/* SK_USE_REV_DESC */
+#define Word2LE(value) (value)
+#endif	/* SK_USE_REV_DESC */
+#endif	/* !SK_LITTLE_ENDIAN */
+
+/******************************************************************************
+ *
+ * Transmit list element macros
+ *
+ */
+
+#define TXLE_SET_ADDR(pLE, Addr)	\
+	((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
+#define TXLE_SET_LSLEN(pLE, Len)	\
+	((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
+#define TXLE_SET_STACS(pLE, Start)	\
+	((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
+#define TXLE_SET_WRICS(pLE, Write)	\
+	((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
+#define TXLE_SET_INICS(pLE, Ini)	((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
+#define TXLE_SET_LEN(pLE, Len)		((pLE)->Tx.Send.BufLen = Word2LE(Len))
+#define TXLE_SET_VLAN(pLE, Vlan)	((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
+#define TXLE_SET_LCKCS(pLE, Lock)	((pLE)->Tx.ControlFlags = (Lock))
+#define TXLE_SET_CTRL(pLE, Ctrl)	((pLE)->Tx.ControlFlags = (Ctrl))
+#define TXLE_SET_OPC(pLE, Opc)		((pLE)->Tx.Opcode = (Opc))
+
+#define TXLE_GET_ADDR(pLE)		LE2DWord((pLE)->Tx.TxUn.BufAddr)
+#define TXLE_GET_LSLEN(pLE)		LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
+#define TXLE_GET_STACS(pLE)		LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
+#define TXLE_GET_WRICS(pLE)		LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
+#define TXLE_GET_INICS(pLE)		LE2Word((pLE)->Tx.Send.InitCsum)
+#define TXLE_GET_LEN(pLE)		LE2Word((pLE)->Tx.Send.BufLen)
+#define TXLE_GET_VLAN(pLE)		LE2Word((pLE)->Tx.Send.VlanTag)
+#define TXLE_GET_LCKCS(pLE)		((pLE)->Tx.ControlFlags)
+#define TXLE_GET_CTRL(pLE)		((pLE)->Tx.ControlFlags)
+#define TXLE_GET_OPC(pLE)		((pLE)->Tx.Opcode)
+
+	/* Yukon-Extreme only */
+#define TXLE_SET_LSOV2(pLE, Len)	\
+	((pLE)->Tx.TxUn.LsoV2Len = DWord2LE(Len))
+#define TXLE_SET_MSSVAL(pLE, Val)	\
+((pLE)->Tx.TxUn.Mss.TxMssVal = Word2LE(Val))
+
+#define TXLE_GET_LSOV2(pLE)		LE2DWord((pLE)->Tx.TxUn.LsoV2Len)
+#define TXLE_GET_MSSVAL(pLE)	LE2Word((pLE)->Tx.TxUn.Mss.TxMssVal)
+
+/******************************************************************************
+ *
+ * Receive list element macros
+ *
+ */
+
+#define RXLE_SET_ADDR(pLE, Addr)	\
+	((pLE)->Rx.RxUn.BufAddr = (SK_U32)DWord2LE(Addr))
+#define RXLE_SET_STACS2(pLE, Offs)	\
+	((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
+#define RXLE_SET_STACS1(pLE, Offs)	\
+	((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
+#define RXLE_SET_LEN(pLE, Len)		((pLE)->Rx.BufferLength = Word2LE(Len))
+#define RXLE_SET_CTRL(pLE, Ctrl)	((pLE)->Rx.ControlFlags = (Ctrl))
+#define RXLE_SET_OPC(pLE, Opc)		((pLE)->Rx.Opcode = (Opc))
+
+#define RXLE_GET_ADDR(pLE)		LE2DWord((pLE)->Rx.RxUn.BufAddr)
+#define RXLE_GET_STACS2(pLE)	LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
+#define RXLE_GET_STACS1(pLE)	LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
+#define RXLE_GET_LEN(pLE)		LE2Word((pLE)->Rx.BufferLength)
+#define RXLE_GET_CTRL(pLE)		((pLE)->Rx.ControlFlags)
+#define RXLE_GET_OPC(pLE)		((pLE)->Rx.Opcode)
+
+/******************************************************************************
+ *
+ * Status list element macros
+ *
+ */
+
+#define STLE_SET_OPC(pLE, Opc)		((pLE)->St.Opcode = (Opc))
+
+#define STLE_GET_FRSTATUS(pLE)	LE2DWord((pLE)->St.StUn.StRxStatWord)
+#define STLE_GET_TIST(pLE)		LE2DWord((pLE)->St.StUn.StRxTimeStamp)
+#define STLE_GET_TCP1(pLE)		LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
+#define STLE_GET_TCP2(pLE)		LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
+#define STLE_GET_LEN(pLE)		LE2Word((pLE)->St.Stat.BufLen)
+#define STLE_GET_VLAN(pLE)		LE2Word((pLE)->St.Stat.VlanTag)
+
+/*
+ * SKLE_GET_LINK() returns the link field including TCP checksum information.
+ * To select the port from the link field use (STLE_GET_LINK(pLe) & 1)
+ */
+#define STLE_GET_LINK(pLE)		((pLE)->St.Link)
+#define STLE_GET_OPC(pLE)		((pLE)->St.Opcode)
+#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) {			\
+	(LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow);	\
+	(HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi);		\
+}
+#define STLE_GET_TXDONE1_IDX(pLE) ((pLE)->St.StUn.TxDone.TxDone1&STLE_TXA1_MSKL)
+#define STLE_GET_TXDONE2_IDX(pLE) ((pLE)->St.StUn.TxDone.TxDone2&STLE_TXA1_MSKL)
+#define STLE_GET_TXDONE3_IDX(pLE) ((pLE)->St.Stat.TxDone3&STLE_TXA1_MSKL)
+#define STLE_GET_TXDONE_VALID_BITS(pLE) (STLE_GET_LINK(pLE)&7)
+#define STLE_GET_TXDONE_BASE(pLE) (((pLE)->St.Opcode-OP_TXINDEXLE)*3)
+
+#define STLE_GET_RSS(pLE)		LE2DWord((pLE)->St.StUn.StRxRssValue)
+#define STLE_GET_IPV6BIT(pLE)	((pLE)->St.Stat.Rss.FlagField & RSS_IPV6_FLAG)
+#define STLE_GET_IPBIT(pLE)		((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
+#define STLE_GET_TCPBIT(pLE)	((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
+
+/* Yukon-Extreme only */
+#define STLE_GET_MX_STAT(pLE)	((pLE)->St.StUn.StMacSecWord)
+
+/* Yukon-Ext CSum Status defines (Rx Status, Link field) */
+#define CSS_GET_PORT(Link)			(Link & CSS_LINK_BIT)
+#define CSS_IS_IPV4(Link)			(Link & CSS_ISIPV4)
+#define CSS_IPV4_CSUM_OK(Link)		(Link & CSS_IPV4CSUMOK)
+#define CSS_IS_IPV6(Link)			(Link & CSS_ISIPV6)
+#define CSS_IS_IPFRAG(Link)			(Link & CSS_ISIPFRAG)
+#define CSS_IS_TCP(Link)			(Link & CSS_ISTCP)
+#define CSS_IS_UDP(Link)			(Link & CSS_ISUDP)
+#define CSS_TCPUDP_CSUM_OK(Link)	(Link & CSS_TCPUDPCSOK)
+
+/* always take both values as a parameter to avoid typos */
+#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal)			\
+	(((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
+#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal)			\
+	((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
+#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal)			\
+	(((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) +	\
+	((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
+#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal)			\
+	((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
+
+
+#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) {			\
+	(IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) &&			\
+			 (((RxStat) & GMR_FS_ANY_ERR) == 0);			\
+															\
+	if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >>	\
+		GMR_FS_LEN_SHIFT) != (Len))) {						\
+		/* length in MAC status differs from length in LE */\
+		(IsOk) = SK_FALSE;									\
+	}														\
+}
+
+
+/******************************************************************************
+ *
+ * Polling unit list element macros
+ *
+ * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
+ *
+ */
+
+#ifdef USE_POLLING_UNIT
+
+#define POLE_SET_OPC(pLE, Opc)		((pLE)->Sa.Opcode = (Opc))
+#define POLE_SET_LINK(pLE, Port)	((pLE)->Sa.Link = (Port))
+#define POLE_SET_RXIDX(pLE, Idx)	((pLE)->Sa.RxIdxVld = Word2LE(Idx))
+#define POLE_SET_TXAIDX(pLE, Idx)	((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
+#define POLE_SET_TXSIDX(pLE, Idx)	((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
+
+#define POLE_GET_OPC(pLE)		((pLE)->Sa.Opcode)
+#define POLE_GET_LINK(pLE)		((pLE)->Sa.Link)
+#define POLE_GET_RXIDX(pLE)		LE2Word((pLE)->Sa.RxIdxVld)
+#define POLE_GET_TXAIDX(pLE)	LE2Word((pLE)->Sa.TxAIdxVld)
+#define POLE_GET_TXSIDX(pLE)	LE2Word((pLE)->Sa.TxSIdxVld)
+
+#endif /* USE_POLLING_UNIT */
+
+/******************************************************************************
+ *
+ * Debug macros for list elements
+ *
+ */
+
+#ifdef DEBUG
+
+#define SK_DBG_DUMP_RX_LE(pLE)	{										\
+	SK_U8	Opcode;														\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",	\
+		pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
+		((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],		\
+		((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));						\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("\t (16bit) %04x %04x %04x %04x\n",							\
+		((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],	\
+		((SK_U16 *) pLE)[3]));											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("\t (32bit) %08x %08x\n",										\
+		((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));						\
+	Opcode = RXLE_GET_OPC(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?	\
+		 "Hardware" : "Software"));										\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("\tOpc: 0x%x ",Opcode));										\
+	switch (Opcode & (~HW_OWNER)) {										\
+	case OP_BUFFER:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tOP_BUFFER\n"));											\
+		break;															\
+	case OP_PACKET:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tOP_PACKET\n"));											\
+		break;															\
+	case OP_ADDR64:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tOP_ADDR64\n"));											\
+		break;															\
+	case OP_TCPSTART:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tOP_TCPPAR\n"));											\
+		break;															\
+	case SW_OWNER:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tunused LE\n"));											\
+		break;															\
+	default:															\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tunknown Opcode!!!\n"));									\
+	}																	\
+	if ((Opcode & OP_BUFFER) == OP_BUFFER) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE)));					\
+	}																	\
+	if ((Opcode & OP_ADDR64) == OP_ADDR64) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE)));				\
+	}																	\
+	if ((Opcode & OP_TCPSTART) == OP_TCPSTART) {						\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE)));		\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,					\
+			("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE)));		\
+	}																	\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_RX,						\
+		("=====================\n"));									\
+}
+
+#define SK_DBG_DUMP_TX_LE(pLE)	{										\
+	SK_U8	Opcode;														\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",	\
+		pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
+		((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],		\
+		((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));						\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("\t (16bit) %04x %04x %04x %04x\n",							\
+		((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],	\
+		((SK_U16 *) pLE)[3]));											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("\t (32bit) %08x %08x\n",										\
+		((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));						\
+	Opcode = TXLE_GET_OPC(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?	\
+		"Hardware" : "Software"));										\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("\tOpc: 0x%x ",Opcode));										\
+	switch (Opcode & (~HW_OWNER)) {										\
+	case OP_TCPCHKSUM:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPCHKSUM\n"));										\
+		break;															\
+	case OP_TCPIS:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPIS\n"));											\
+		break;															\
+	case OP_TCPLCK:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPLCK\n"));											\
+		break;															\
+	case OP_TCPLW:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPLW\n"));											\
+		break;															\
+	case OP_TCPLSW:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPLSW\n"));											\
+		break;															\
+	case OP_TCPLISW:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_TCPLISW\n"));										\
+		break;															\
+	case OP_ADDR64:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_ADDR64\n"));											\
+		break;															\
+	case OP_VLAN:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_VLAN\n"));											\
+		break;															\
+	case OP_ADDR64VLAN:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_ADDR64VLAN\n"));										\
+		break;															\
+	case OP_LRGLEN:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_LRGLEN\n"));											\
+		break;															\
+	case OP_LRGLENVLAN:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_LRGLENVLAN\n"));										\
+		break;															\
+	case OP_BUFFER:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_BUFFER\n"));											\
+		break;															\
+	case OP_PACKET:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_PACKET\n"));											\
+		break;															\
+	case OP_LARGESEND:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_LARGESEND\n"));										\
+		break;															\
+	case OP_MSS:		/* Yukon-Extreme only */						\
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_MSS\n"))												\
+		break;															\
+	case OP_MSSVLAN:	/* Yukon-Extreme only */						\
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_MSSVLAN\n"))											\
+		break;															\
+	case OP_LSOV2:		/* Yukon-Extreme only */						\
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tOP_LSOV2\n"))											\
+		break;															\
+	case SW_OWNER:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tunused LE\n"));											\
+		break;															\
+	default:															\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tunknown Opcode!!!\n"));									\
+	}																	\
+	if ((Opcode & OP_BUFFER) == OP_BUFFER) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE)));					\
+	}																	\
+	if ((Opcode & OP_ADDR64) == OP_ADDR64) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE)));				\
+	}																	\
+	if ((Opcode & OP_VLAN) == OP_VLAN) {								\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE)));					\
+	}																	\
+	if ((Opcode & OP_LRGLEN) == OP_LRGLEN) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE)));		\
+	}																	\
+	if ((Opcode & OP_MSS) == OP_MSS) {		/* Yukon-Extreme only */	\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tMSS value: 0x%x\n", TXLE_GET_MSSVAL(pLE)));				\
+	}																	\
+	if ((Opcode & OP_LSOV2) == OP_LSOV2) {	/* Yukon-Extreme only */	\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,					\
+			("\tLSOv2 lenght: 0x%x\n", TXLE_GET_LSOV2(pLE)));			\
+	}																	\
+	if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) {							\
+		if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) {					\
+			SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,				\
+				("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE)));		\
+		}																\
+		if ((Opcode & OP_TCPSTART) == OP_TCPSTART) {					\
+			SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,				\
+				("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE)));		\
+		}																\
+		if ((Opcode & OP_TCPINIT) == OP_TCPINIT) {						\
+			SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,				\
+				("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE)));		\
+		}																\
+		if ((Opcode & OP_TCPLCK) == OP_TCPLCK) {						\
+			SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,				\
+				("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE)));		\
+		}																\
+	}																	\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_TX,						\
+		("=====================\n"));									\
+}
+
+#define SK_DBG_DUMP_ST_LE(pLE)	{										\
+	SK_U8	Opcode;														\
+	SK_U16	HighVal;													\
+	SK_U32	LowVal;														\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
+		pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
+		((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],		\
+		((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));						\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("\t (16bit) %04x %04x %04x %04x\n",							\
+		((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],	\
+		((SK_U16 *) pLE)[3]));											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("\t (32bit) %08x %08x\n",										\
+		((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));						\
+	Opcode = STLE_GET_OPC(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ?	\
+		"Hardware" : "Software"));										\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("\tOpc: 0x%x",	Opcode));										\
+	Opcode &= (~HW_OWNER);												\
+	switch (Opcode) {													\
+	case OP_RXSTAT:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXSTAT\n"));											\
+		break;															\
+	case OP_RXTIMESTAMP:												\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXTIMESTAMP\n"));									\
+		break;															\
+	case OP_RXVLAN:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXVLAN\n"));											\
+		break;															\
+	case OP_RXCHKS:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXCHKS\n"));											\
+		break;															\
+	case OP_RXCHKSVLAN:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXCHKSVLAN\n"));										\
+		break;															\
+	case OP_RXTIMEVLAN:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RXTIMEVLAN\n"));										\
+		break;															\
+	case OP_RSS_HASH:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_RSS_HASH\n"));										\
+		break;															\
+	case OP_TXINDEXLE:													\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_TXINDEXLE\n"));										\
+		break;															\
+	case OP_MACSEC:		/* Yukon-Extreme only */						\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_MACSEC\n"));											\
+		break;															\
+	case OP_MACSECVLAN:	/* Yukon-Extreme only */						\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tOP_MACSECVLAN\n"));										\
+		break;															\
+	case HW_OWNER:														\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tunused LE\n"));											\
+		break;															\
+	default:															\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tunknown status list element!!!\n"));					\
+	}																	\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("\tPort: %c\n", 'A' + (CSS_GET_PORT(STLE_GET_LINK(pLE)))));	\
+	if (Opcode == OP_RXSTAT) {											\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE)));			\
+		if (HW_IS_EXT_LE_FORMAT(pAc)) {									\
+			SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,				\
+				("\tChecksum Status Field: 0x%x\n", STLE_GET_LINK(pLE)));\
+		}																\
+	}																	\
+	if ((Opcode & OP_RXVLAN) == OP_RXVLAN) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE)));					\
+	}																	\
+	if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE)));				\
+	}																	\
+	if ((Opcode & OP_RXCHKS) == OP_RXCHKS) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE),					\
+			STLE_GET_TCP2(pLE)));										\
+	}																	\
+	if (Opcode == OP_TXINDEXLE) {										\
+		STLE_GET_DONE_IDX(pLE, LowVal, HighVal);						\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTx Index TxA1: 0x%x\n",									\
+			STLE_GET_DONE_IDX_TXA1(LowVal,HighVal)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTx Index TxS1: 0x%x\n",									\
+			STLE_GET_DONE_IDX_TXS1(LowVal,HighVal)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTx Index TxA2: 0x%x\n",									\
+			STLE_GET_DONE_IDX_TXA2(LowVal,HighVal)));					\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tTx Index TxS2: 0x%x\n",									\
+			STLE_GET_DONE_IDX_TXS2(LowVal,HighVal)));					\
+	}																	\
+	if ((Opcode & OP_MACSEC) == OP_MACSEC) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,					\
+			("\tMACSec Status Field\n", STLE_GET_MX_STAT(pLE)));		\
+	}																	\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,						\
+		("=====================\n"));									\
+}
+
+#ifdef USE_POLLING_UNIT
+#define SK_DBG_DUMP_PO_LE(pLE)	{										\
+	SK_U8	Opcode;														\
+	SK_U16	Idx;														\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",	\
+		pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
+		((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],		\
+		((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));						\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\t (16bit) %04x %04x %04x %04x\n",							\
+		((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],	\
+		((SK_U16 *) pLE)[3]));											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\t (32bit) %08x %08x\n",										\
+		((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));						\
+	Opcode = POLE_GET_OPC(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		 ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?	\
+		  "Hardware" : "Software"));									\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		 ("\tOpc: 0x%x ",Opcode));										\
+	if ((Opcode & ~HW_OWNER) == OP_PUTIDX) {							\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,					\
+			("\tOP_PUTIDX\n"));											\
+	}																	\
+	else {																\
+		SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,					\
+			("\tunknown Opcode!!!\n"));									\
+	}																	\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\tPort %c\n", 'A' + POLE_GET_LINK(pLE)));						\
+	Idx = POLE_GET_TXAIDX(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\tTxA Index is 0x%X and %svalid\n", Idx,						\
+		(Idx & PU_PUTIDX_VALID) ? "" : "not "));						\
+	Idx = POLE_GET_TXSIDX(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\tTxS Index is 0x%X and %svalid\n", Idx,						\
+		(Idx & PU_PUTIDX_VALID) ? "" : "not "));						\
+	Idx = POLE_GET_RXIDX(pLE);											\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("\tRx Index is 0x%X and %svalid\n", Idx,						\
+		(Idx & PU_PUTIDX_VALID) ? "" : "not "));						\
+	SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,						\
+		("=====================\n"));									\
+}
+#endif /* USE_POLLING_UNIT */
+
+#else	/* !DEBUG */
+
+#define SK_DBG_DUMP_RX_LE(pLE)
+#define SK_DBG_DUMP_TX_LE(pLE)
+#define SK_DBG_DUMP_ST_LE(pLE)
+#define SK_DBG_DUMP_PO_LE(pLE)
+
+#endif	/* !DEBUG */
+
+/******************************************************************************
+ *
+ * Macros for list element tables
+ *
+ */
+
+#define LE_SIZE sizeof(SK_HWLE)
+#define LE_TAB_SIZE(NumElements)	((NumElements) * LE_SIZE)
+
+/* total number of list elements in table */
+#define NUM_LE_IN_TABLE(pTable)		((pTable)->Num)
+
+/* Number of unused list elements in table
+ * this macro always returns the number of free listelements - 1
+ * this way we want to guarantee that always one LE remains unused
+ */
+#define NUM_FREE_LE_IN_TABLE(pTable)								\
+	( ((pTable)->Put >= (pTable)->Done) ?							\
+	(NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
+	((pTable)->Done - (pTable)->Put - 1) )
+
+/* get next unused Rx list element */
+#define GET_RX_LE(pLE, pTable) {									\
+	pLE = &(pTable)->pLETab[(pTable)->Put];							\
+	(pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
+}
+
+/* get next unused Tx list element */
+#define GET_TX_LE(pLE, pTable)	GET_RX_LE(pLE, pTable)
+
+/* get next status list element expected to be finished by HW */
+#define GET_ST_LE(pLE, pTable) {									\
+	pLE = &(pTable)->pLETab[(pTable)->Done];						\
+	(pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
+}
+
+#ifdef USE_POLLING_UNIT
+/* get next polling unit list element for port */
+#define GET_PO_LE(pLE, pTable, Port)	(pLE = &(pTable)->pLETab[(Port)])
+}
+#endif /* USE_POLLING_UNIT */
+
+#define GET_PUT_IDX(pTable)			((pTable)->Put)
+
+#define UPDATE_HWPUT_IDX(pTable)	((pTable)->HwPut = (pTable)->Put)
+
+/*
+ * get own bit of next status LE
+ * if the result is != 0 there has been at least one status LE finished
+ */
+#define OWN_OF_FIRST_LE(pTable)									\
+	(STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
+
+#define SET_DONE_INDEX(pTable, Idx)	(pTable)->Done = (Idx)
+
+#define GET_DONE_INDEX(pTable)	((pTable)->Done)
+
+#ifdef SAFE_BUT_SLOW
+
+/* check own bit of LE before current done idx */
+#define CHECK_STLE_OVERFLOW(pTable, IsOk) {						\
+		unsigned i;												\
+		if ((i = (pTable)->Done) == 0) {						\
+			i = NUM_LE_IN_TABLE(pTable);						\
+		}														\
+		else {													\
+			i = i - 1;											\
+		}														\
+		if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) {	\
+			(IsOk) = SK_TRUE;									\
+		}														\
+		else {													\
+			(IsOk) = SK_FALSE;									\
+		}														\
+	}
+
+
+/*
+ * for Yukon-2 the hardware is not polling the list elements, so it
+ * is not necessary to change the own-bit of Rx or Tx LEs before
+ * reusing them
+ * but it might make debugging easier if one simply can see whether
+ * a LE has been worked on
+ */
+
+#define CLEAR_LE_OWN(pTable, Idx)								\
+	STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
+
+/*
+ * clear all own bits starting from old done index up to the LE before
+ * the new done index
+ */
+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) {					\
+		int i;													\
+		i = (pTable)->Done;										\
+		while (i != To) {										\
+			CLEAR_LE_OWN(pTable, i);							\
+			i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1);		\
+		}														\
+	}
+
+#else	/* !SAFE_BUT_SLOW */
+
+#define CHECK_STLE_OVERFLOW(pTable, IsOk)
+#define CLEAR_LE_OWN(pTable, Idx)
+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
+
+#endif	/* !SAFE_BUT_SLOW */
+
+
+/* typedefs ******************************************************************/
+
+typedef struct s_LetRxTx {
+	SK_U16	VlanId;			/* VLAN Id given down last time */
+	SK_U16	TcpWp;			/* TCP Checksum Write Position */
+	SK_U16	TcpSp1;			/* TCP Checksum Calculation Start Position 1 */
+	SK_U16	TcpSp2;			/* TCP Checksum Calculation Start Position 2 */
+	SK_U16	MssValue;		/* Maximum Segment Size */
+	SK_U16	Reserved1;		/* reserved word for future extensions */
+	SK_U16	Reserved2;		/* reserved word for future extensions */
+	SK_U16	Reserved3;		/* reserved word for future extensions */
+} SK_LET_RX_TX;
+
+typedef struct s_LetStat {
+	SK_U32	RxTimeStamp;	/* Receive Timestamp */
+	SK_U32	RssHashValue;	/* RSS Hash Value */
+	SK_BOOL	RssIsIpV6;		/* RSS Hash Value: IPv6 packet detected */
+	SK_BOOL	RssIsIp;		/* RSS Hash Value: IP packet detected */
+	SK_BOOL	RssIsTcp;		/* RSS Hash Value: IP+TCP packet detected */
+	SK_BOOL	CalcHashIpV4;	/* RSS is computed over source IPv4 address */
+							/* and destination IPv4 address */
+	SK_BOOL	CalcHashTCPIPv4;/* RSS is computed over source IPv4 address, */
+							/* destination IPv4 address, source TCP port and */
+							/* destination TCP port */
+	SK_BOOL	CalcHashIPv6;	/* RSS is computed over source IPv6 address */
+							/* and destination IPv6 address */
+	SK_BOOL	CalcHashTCPIPv6;/* RSS is computed over source IPv6 address, */
+							/* destination IPv6 address, source TCP port and */
+							/* destination TCP port */
+	SK_BOOL	CalcHashIPv6Ex;	/* RSS is computed over home address */
+							/* (if not present, source IPv6 address is used) */
+							/* and routing header type 2 (if not present, */
+							/* destination IPv6 address is used) */
+	SK_BOOL	CalcHashTCPIPv6Ex;	/* RSS is computed over home address */
+							/* (if not present, source IPv6 address is used) */
+							/* and routing header type 2 (if not present, */
+							/* destination IPv6 address is used), */
+							/* source TCP port and destiantion TCP port */
+	SK_U16	VlanId;			/* VLAN Id given received by Status BMU */
+	SK_U16	TcpSum1;		/* TCP checksum 1 (status BMU) */
+	SK_U16	TcpSum2;		/* TCP checksum 2 (status BMU) */
+	SK_U32	MacSecStatus;	/* MAC Security status for packet */
+} SK_LET_STAT;
+
+typedef union s_LetBmuSpec {
+	SK_LET_RX_TX	RxTx;	/* Rx/Tx BMU specific variables */
+	SK_LET_STAT		Stat;	/* Status BMU specific variables */
+} SK_LET_BMU_S;
+
+typedef struct s_LeTable {
+	/* all LEs between Done and HWPut are owned by the hardware */
+	/* all LEs between Put and Done can be used from software */
+	/* all LEs between HWPut and Put are currently processed in DriverSend */
+	unsigned Done;			/* done index - consumed from HW and available */
+	unsigned Put;			/* put index - to be given to hardware */
+	unsigned HwPut;			/* put index actually given to hardware */
+	unsigned Num;			/* total number of list elements */
+	SK_HWLE *pLETab;		/* virtual address of list element table */
+	SK_U32	pPhyLETABLow;	/* physical address of list element table */
+	SK_U32	pPhyLETABHigh;	/* physical address of list element table */
+	/* values to remember in order to save some LEs */
+	SK_U32	BufHighAddr;	/* high address given down last time */
+	SK_LET_BMU_S Bmu;		/* contains BMU specific information */
+	SK_U32	Private;		/* driver private variable free usable */
+	SK_U16	TcpInitCsum;	/* init checksum */
+#if defined(SK_LSO_V2) && defined(SK_EXTREME)
+	unsigned DoneCorrection;	/* number of LSOv2 LEs send modulo Num */
+	unsigned BadDone;			/* real done index from HW - in Done is a corrected value */
+#endif
+} SK_LE_TABLE;
+
+/* function prototypes ********************************************************/
+
+#ifndef	SK_KR_PROTO
+
+/*
+ * public functions in sky2le.c
+ */
+extern void SkGeY2SetPutIndex(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int StartAddrPrefUnit,
+	SK_LE_TABLE *pLETab);
+
+extern void SkGeY2InitPrefetchUnit(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	unsigned int Queue,
+	SK_LE_TABLE *pLETab);
+
+extern void SkGeY2InitStatBmu(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_LE_TABLE *pLETab);
+
+extern void SkGeY2InitPollUnit(
+	SK_AC	*pAC,
+	SK_IOC	IoC,
+	SK_LE_TABLE *pLETab);
+
+extern void SkGeY2InitSingleLETable(
+	SK_AC	*pAC,
+	SK_LE_TABLE *pLETab,
+	unsigned int NumLE,
+	void	*pVMem,
+	SK_U32	PMemLowAddr,
+	SK_U32	PMemHighAddr);
+
+#else	/* SK_KR_PROTO */
+extern void SkGeY2SetPutIndex();
+extern void SkGeY2InitPrefetchUnit();
+extern void SkGeY2InitStatBmu();
+extern void SkGeY2InitPollUnit();
+extern void SkGeY2InitSingleLETable();
+#endif	/* SK_KR_PROTO */
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
+#endif	/* __INC_SKY2LE_H */
+
diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h
--- linux/drivers/net/sk98lin/h/xmac_ii.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/h/xmac_ii.h	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1865 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/h/xmac_ii.h#11 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #11 $, $Change: 5019 $
+ * Date:	$DateTime: 2011/01/14 13:50:09 $
+ * Purpose:	Defines and Macros for Gigabit Ethernet Controller
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+ 
+#ifndef __INC_XMAC_H
+#define __INC_XMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines ********************************************************************/
+
+/*
+ * XMAC II registers
+ *
+ * The XMAC registers are 16 or 32 bits wide.
+ * The XMACs host processor interface is set to 16 bit mode,
+ * therefore ALL registers will be addressed with 16 bit accesses.
+ *
+ * The following macros are provided to access the XMAC registers
+ * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(),
+ * XM_INHASH(), and XM_OUTHASH().
+ * The macros are defined in SkGeHw.h.
+ *
+ * Note:	NA reg	= Network Address e.g DA, SA etc.
+ *
+ */
+#define XM_MMU_CMD		0x0000	/* 16 bit r/w	MMU Command Register */
+	/* 0x0004:		reserved */
+#define XM_POFF			0x0008	/* 32 bit r/w	Packet Offset Register */
+#define XM_BURST		0x000c	/* 32 bit r/w	Burst Register for half duplex*/
+#define XM_1L_VLAN_TAG	0x0010	/* 16 bit r/w	One Level VLAN Tag ID */
+#define XM_2L_VLAN_TAG	0x0014	/* 16 bit r/w	Two Level VLAN Tag ID */
+	/* 0x0018 - 0x001e:	reserved */
+#define XM_TX_CMD		0x0020	/* 16 bit r/w	Transmit Command Register */
+#define XM_TX_RT_LIM	0x0024	/* 16 bit r/w	Transmit Retry Limit Register */
+#define XM_TX_STIME		0x0028	/* 16 bit r/w	Transmit Slottime Register */
+#define XM_TX_IPG		0x002c	/* 16 bit r/w	Transmit Inter Packet Gap */
+#define XM_RX_CMD		0x0030	/* 16 bit r/w	Receive Command Register */
+#define XM_PHY_ADDR		0x0034	/* 16 bit r/w	PHY Address Register */
+#define XM_PHY_DATA		0x0038	/* 16 bit r/w	PHY Data Register */
+	/* 0x003c:		reserved */
+#define XM_GP_PORT		0x0040	/* 32 bit r/w	General Purpose Port Register */
+#define XM_IMSK			0x0044	/* 16 bit r/w	Interrupt Mask Register */
+#define XM_ISRC			0x0048	/* 16 bit r/o	Interrupt Status Register */
+#define XM_HW_CFG		0x004c	/* 16 bit r/w	Hardware Config Register */
+	/* 0x0050 - 0x005e:	reserved */
+#define XM_TX_LO_WM		0x0060	/* 16 bit r/w	Tx FIFO Low Water Mark */
+#define XM_TX_HI_WM		0x0062	/* 16 bit r/w	Tx FIFO High Water Mark */
+#define XM_TX_THR		0x0064	/* 16 bit r/w	Tx Request Threshold */
+#define XM_HT_THR		0x0066	/* 16 bit r/w	Host Request Threshold */
+#define XM_PAUSE_DA		0x0068	/* NA reg r/w	Pause Destination Address */
+	/* 0x006e:		reserved */
+#define XM_CTL_PARA		0x0070	/* 32 bit r/w	Control Parameter Register */
+#define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
+#define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
+#define XM_TX_STAT		0x0078	/* 32 bit r/o	Tx Status LIFO Register */
+
+	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exact Match Address Registers */
+	/*				use the XM_EXM() macro to address */
+#define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */
+
+	/*
+	 * XM_EXM(Reg)
+	 *
+	 * returns the XMAC address offset of specified Exact Match Addr Reg
+	 *
+	 * para:	Reg	EXM register to addr	(0 .. 15)
+	 *
+	 * usage:	XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]);
+	 */
+#define XM_EXM(Reg)	(XM_EXM_START + ((Reg) << 3))
+
+#define XM_SRC_CHK		0x0100	/* NA reg r/w	Source Check Address Register */
+#define XM_SA			0x0108	/* NA reg r/w	Station Address Register */
+#define XM_HSM			0x0110	/* 64 bit r/w	Hash Match Address Registers */
+#define XM_RX_LO_WM		0x0118	/* 16 bit r/w	Receive Low Water Mark */
+#define XM_RX_HI_WM		0x011a	/* 16 bit r/w	Receive High Water Mark */
+#define XM_RX_THR		0x011c	/* 32 bit r/w	Receive Request Threshold */
+#define XM_DEV_ID		0x0120	/* 32 bit r/o	Device ID Register */
+#define XM_MODE			0x0124	/* 32 bit r/w	Mode Register */
+#define XM_LSA			0x0128	/* NA reg r/o	Last Source Register */
+	/* 0x012e:		reserved */
+#define XM_TS_READ		0x0130	/* 32 bit r/o	Time Stamp Read Register */
+#define XM_TS_LOAD		0x0134	/* 32 bit r/o	Time Stamp Load Value */
+	/* 0x0138 - 0x01fe:	reserved */
+#define XM_STAT_CMD	0x0200	/* 16 bit r/w	Statistics Command Register */
+#define XM_RX_CNT_EV	0x0204	/* 32 bit r/o	Rx Counter Event Register */
+#define XM_TX_CNT_EV	0x0208	/* 32 bit r/o	Tx Counter Event Register */
+#define XM_RX_EV_MSK	0x020c	/* 32 bit r/w	Rx Counter Event Mask */
+#define XM_TX_EV_MSK	0x0210	/* 32 bit r/w	Tx Counter Event Mask */
+	/* 0x0204 - 0x027e:	reserved */
+#define XM_TXF_OK		0x0280	/* 32 bit r/o	Frames Transmitted OK Conuter */
+#define XM_TXO_OK_HI	0x0284	/* 32 bit r/o	Octets Transmitted OK High Cnt*/
+#define XM_TXO_OK_LO	0x0288	/* 32 bit r/o	Octets Transmitted OK Low Cnt */
+#define XM_TXF_BC_OK	0x028c	/* 32 bit r/o	Broadcast Frames Xmitted OK */
+#define XM_TXF_MC_OK	0x0290	/* 32 bit r/o	Multicast Frames Xmitted OK */
+#define XM_TXF_UC_OK	0x0294	/* 32 bit r/o	Unicast Frames Xmitted OK */
+#define XM_TXF_LONG		0x0298	/* 32 bit r/o	Tx Long Frame Counter */
+#define XM_TXE_BURST	0x029c	/* 32 bit r/o	Tx Burst Event Counter */
+#define XM_TXF_MPAUSE	0x02a0	/* 32 bit r/o	Tx Pause MAC Ctrl Frame Cnt */
+#define XM_TXF_MCTRL	0x02a4	/* 32 bit r/o	Tx MAC Ctrl Frame Counter */
+#define XM_TXF_SNG_COL	0x02a8	/* 32 bit r/o	Tx Single Collision Counter */
+#define XM_TXF_MUL_COL	0x02ac	/* 32 bit r/o	Tx Multiple Collision Counter */
+#define XM_TXF_ABO_COL	0x02b0	/* 32 bit r/o	Tx aborted due to Exces. Col. */
+#define XM_TXF_LAT_COL	0x02b4	/* 32 bit r/o	Tx Late Collision Counter */
+#define XM_TXF_DEF		0x02b8	/* 32 bit r/o	Tx Deferred Frame Counter */
+#define XM_TXF_EX_DEF	0x02bc	/* 32 bit r/o	Tx Excessive Deferall Counter */
+#define XM_TXE_FIFO_UR	0x02c0	/* 32 bit r/o	Tx FIFO Underrun Event Cnt */
+#define XM_TXE_CS_ERR	0x02c4	/* 32 bit r/o	Tx Carrier Sense Error Cnt */
+#define XM_TXP_UTIL		0x02c8	/* 32 bit r/o	Tx Utilization in % */
+	/* 0x02cc - 0x02ce:	reserved */
+#define XM_TXF_64B		0x02d0	/* 32 bit r/o	64 Byte Tx Frame Counter */
+#define XM_TXF_127B		0x02d4	/* 32 bit r/o	65-127 Byte Tx Frame Counter */
+#define XM_TXF_255B		0x02d8	/* 32 bit r/o	128-255 Byte Tx Frame Counter */
+#define XM_TXF_511B		0x02dc	/* 32 bit r/o	256-511 Byte Tx Frame Counter */
+#define XM_TXF_1023B	0x02e0	/* 32 bit r/o	512-1023 Byte Tx Frame Counter*/
+#define XM_TXF_MAX_SZ	0x02e4	/* 32 bit r/o	1024-MaxSize Byte Tx Frame Cnt*/
+	/* 0x02e8 - 0x02fe:	reserved */
+#define XM_RXF_OK		0x0300	/* 32 bit r/o	Frames Received OK */
+#define XM_RXO_OK_HI	0x0304	/* 32 bit r/o	Octets Received OK High Cnt */
+#define XM_RXO_OK_LO	0x0308	/* 32 bit r/o	Octets Received OK Low Counter*/
+#define XM_RXF_BC_OK	0x030c	/* 32 bit r/o	Broadcast Frames Received OK */
+#define XM_RXF_MC_OK	0x0310	/* 32 bit r/o	Multicast Frames Received OK */
+#define XM_RXF_UC_OK	0x0314	/* 32 bit r/o	Unicast Frames Received OK */
+#define XM_RXF_MPAUSE	0x0318	/* 32 bit r/o	Rx Pause MAC Ctrl Frame Cnt */
+#define XM_RXF_MCTRL	0x031c	/* 32 bit r/o	Rx MAC Ctrl Frame Counter */
+#define XM_RXF_INV_MP	0x0320	/* 32 bit r/o	Rx invalid Pause Frame Cnt */
+#define XM_RXF_INV_MOC	0x0324	/* 32 bit r/o	Rx Frames with inv. MAC Opcode*/
+#define XM_RXE_BURST	0x0328	/* 32 bit r/o	Rx Burst Event Counter */
+#define XM_RXE_FMISS	0x032c	/* 32 bit r/o	Rx Missed Frames Event Cnt */
+#define XM_RXF_FRA_ERR	0x0330	/* 32 bit r/o	Rx Framing Error Counter */
+#define XM_RXE_FIFO_OV	0x0334	/* 32 bit r/o	Rx FIFO overflow Event Cnt */
+#define XM_RXF_JAB_PKT	0x0338	/* 32 bit r/o	Rx Jabber Packet Frame Cnt */
+#define XM_RXE_CAR_ERR	0x033c	/* 32 bit r/o	Rx Carrier Event Error Cnt */
+#define XM_RXF_LEN_ERR	0x0340	/* 32 bit r/o	Rx in Range Length Error */
+#define XM_RXE_SYM_ERR	0x0344	/* 32 bit r/o	Rx Symbol Error Counter */
+#define XM_RXE_SHT_ERR	0x0348	/* 32 bit r/o	Rx Short Event Error Cnt */
+#define XM_RXE_RUNT		0x034c	/* 32 bit r/o	Rx Runt Event Counter */
+#define XM_RXF_LNG_ERR	0x0350	/* 32 bit r/o	Rx Frame too Long Error Cnt */
+#define XM_RXF_FCS_ERR	0x0354	/* 32 bit r/o	Rx Frame Check Seq. Error Cnt */
+	/* 0x0358 - 0x035a:	reserved */
+#define XM_RXF_CEX_ERR	0x035c	/* 32 bit r/o	Rx Carrier Ext Error Frame Cnt*/
+#define XM_RXP_UTIL		0x0360	/* 32 bit r/o	Rx Utilization in % */
+	/* 0x0364 - 0x0366:	reserved */
+#define XM_RXF_64B		0x0368	/* 32 bit r/o	64 Byte Rx Frame Counter */
+#define XM_RXF_127B		0x036c	/* 32 bit r/o	65-127 Byte Rx Frame Counter */
+#define XM_RXF_255B		0x0370	/* 32 bit r/o	128-255 Byte Rx Frame Counter */
+#define XM_RXF_511B		0x0374	/* 32 bit r/o	256-511 Byte Rx Frame Counter */
+#define XM_RXF_1023B	0x0378	/* 32 bit r/o	512-1023 Byte Rx Frame Counter*/
+#define XM_RXF_MAX_SZ	0x037c	/* 32 bit r/o	1024-MaxSize Byte Rx Frame Cnt*/
+	/* 0x02e8 - 0x02fe:	reserved */
+
+
+/*----------------------------------------------------------------------------*/
+/*
+ * XMAC Bit Definitions
+ *
+ * If the bit access behaviour differs from the register access behaviour
+ * (r/w, r/o) this is documented after the bit number.
+ * The following bit access behaviours are used:
+ *	(sc)	self clearing
+ *	(ro)	read only
+ */
+
+/*	XM_MMU_CMD	16 bit r/w	MMU Command Register */
+								/* Bit 15..13:	reserved */
+#define XM_MMU_PHY_RDY	(1<<12)	/* Bit 12:	PHY Read Ready */
+#define XM_MMU_PHY_BUSY	(1<<11)	/* Bit 11:	PHY Busy */
+#define XM_MMU_IGN_PF	(1<<10)	/* Bit 10:	Ignore Pause Frame */
+#define XM_MMU_MAC_LB	(1<<9)	/* Bit  9:	Enable MAC Loopback */
+								/* Bit  8:	reserved */
+#define XM_MMU_FRC_COL	(1<<7)	/* Bit  7:	Force Collision */
+#define XM_MMU_SIM_COL	(1<<6)	/* Bit  6:	Simulate Collision */
+#define XM_MMU_NO_PRE	(1<<5)	/* Bit  5:	No MDIO Preamble */
+#define XM_MMU_GMII_FD	(1<<4)	/* Bit  4:	GMII uses Full Duplex */
+#define XM_MMU_RAT_CTRL	(1<<3)	/* Bit  3:	Enable Rate Control */
+#define XM_MMU_GMII_LOOP (1<<2)	/* Bit  2:	PHY is in Loopback Mode */
+#define XM_MMU_ENA_RX	(1<<1)	/* Bit  1:	Enable Receiver */
+#define XM_MMU_ENA_TX	(1<<0)	/* Bit  0:	Enable Transmitter */
+
+
+/*	XM_TX_CMD	16 bit r/w	Transmit Command Register */
+								/* Bit 15..7:	reserved */
+#define XM_TX_BK2BK		(1<<6)	/* Bit  6:	Ignor Carrier Sense (Tx Bk2Bk) */
+#define XM_TX_ENC_BYP	(1<<5)	/* Bit  5:	Set Encoder in Bypass Mode */
+#define XM_TX_SAM_LINE	(1<<4)	/* Bit  4: (sc)	Start utilization calculation */
+#define XM_TX_NO_GIG_MD	(1<<3)	/* Bit  3:	Disable Carrier Extension */
+#define XM_TX_NO_PRE	(1<<2)	/* Bit  2:	Disable Preamble Generation */
+#define XM_TX_NO_CRC	(1<<1)	/* Bit  1:	Disable CRC Generation */
+#define XM_TX_AUTO_PAD	(1<<0)	/* Bit  0:	Enable Automatic Padding */
+
+
+/*	XM_TX_RT_LIM	16 bit r/w	Transmit Retry Limit Register */
+								/* Bit 15..5:	reserved */
+#define XM_RT_LIM_MSK	0x1f	/* Bit  4..0:	Tx Retry Limit */
+
+
+/*	XM_TX_STIME	16 bit r/w	Transmit Slottime Register */
+								/* Bit 15..7:	reserved */
+#define XM_STIME_MSK	0x7f	/* Bit  6..0:	Tx Slottime bits */
+
+
+/*	XM_TX_IPG	16 bit r/w	Transmit Inter Packet Gap */
+								/* Bit 15..8:	reserved */
+#define XM_IPG_MSK		0xff	/* Bit  7..0:	IPG value bits */
+
+
+/*	XM_RX_CMD	16 bit r/w	Receive Command Register */
+								/* Bit 15..9:	reserved */
+#define XM_RX_LENERR_OK (1<<8)	/* Bit  8	don't set Rx Err bit for */
+								/*		inrange error packets */
+#define XM_RX_BIG_PK_OK	(1<<7)	/* Bit  7	don't set Rx Err bit for */
+								/*		jumbo packets */
+#define XM_RX_IPG_CAP	(1<<6)	/* Bit  6	repl. type field with IPG */
+#define XM_RX_TP_MD		(1<<5)	/* Bit  5:	Enable transparent Mode */
+#define XM_RX_STRIP_FCS	(1<<4)	/* Bit  4:	Enable FCS Stripping */
+#define XM_RX_SELF_RX	(1<<3)	/* Bit  3:	Enable Rx of own packets */
+#define XM_RX_SAM_LINE	(1<<2)	/* Bit  2: (sc)	Start utilization calculation */
+#define XM_RX_STRIP_PAD	(1<<1)	/* Bit  1:	Strip pad bytes of Rx frames */
+#define XM_RX_DIS_CEXT	(1<<0)	/* Bit  0:	Disable carrier ext. check */
+
+
+/*	XM_PHY_ADDR	16 bit r/w	PHY Address Register */
+								/* Bit 15..5:	reserved */
+#define XM_PHY_ADDR_SZ	0x1f	/* Bit  4..0:	PHY Address bits */
+
+
+/*	XM_GP_PORT	32 bit r/w	General Purpose Port Register */
+								/* Bit 31..7:	reserved */
+#define XM_GP_ANIP		(1L<<6)	/* Bit  6: (ro)	Auto-Neg. in progress */
+#define XM_GP_FRC_INT	(1L<<5)	/* Bit  5: (sc)	Force Interrupt */
+								/* Bit  4:	reserved */
+#define XM_GP_RES_MAC	(1L<<3)	/* Bit  3: (sc)	Reset MAC and FIFOs */
+#define XM_GP_RES_STAT	(1L<<2)	/* Bit  2: (sc)	Reset the statistics module */
+								/* Bit  1:	reserved */
+#define XM_GP_INP_ASS	(1L<<0)	/* Bit  0: (ro) GP Input Pin asserted */
+
+
+/*	XM_IMSK		16 bit r/w	Interrupt Mask Register */
+/*	XM_ISRC		16 bit r/o	Interrupt Status Register */
+								/* Bit 15:	reserved */
+#define XM_IS_LNK_AE	(1<<14) /* Bit 14:	Link Asynchronous Event */
+#define XM_IS_TX_ABORT	(1<<13) /* Bit 13:	Transmit Abort, late Col. etc */
+#define XM_IS_FRC_INT	(1<<12) /* Bit 12:	Force INT bit set in GP */
+#define XM_IS_INP_ASS	(1<<11)	/* Bit 11:	Input Asserted, GP bit 0 set */
+#define XM_IS_LIPA_RC	(1<<10)	/* Bit 10:	Link Partner requests config */
+#define XM_IS_RX_PAGE	(1<<9)	/* Bit  9:	Page Received */
+#define XM_IS_TX_PAGE	(1<<8)	/* Bit  8:	Next Page Loaded for Transmit */
+#define XM_IS_AND		(1<<7)	/* Bit  7:	Auto-Negotiation Done */
+#define XM_IS_TSC_OV	(1<<6)	/* Bit  6:	Time Stamp Counter Overflow */
+#define XM_IS_RXC_OV	(1<<5)	/* Bit  5:	Rx Counter Event Overflow */
+#define XM_IS_TXC_OV	(1<<4)	/* Bit  4:	Tx Counter Event Overflow */
+#define XM_IS_RXF_OV	(1<<3)	/* Bit  3:	Receive FIFO Overflow */
+#define XM_IS_TXF_UR	(1<<2)	/* Bit  2:	Transmit FIFO Underrun */
+#define XM_IS_TX_COMP	(1<<1)	/* Bit  1:	Frame Tx Complete */
+#define XM_IS_RX_COMP	(1<<0)	/* Bit  0:	Frame Rx Complete */
+
+#define XM_DEF_MSK	(~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
+			XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR))
+
+
+/*	XM_HW_CFG	16 bit r/w	Hardware Config Register */
+								/* Bit 15.. 4:	reserved */
+#define XM_HW_GEN_EOP	(1<<3)	/* Bit  3:	generate End of Packet pulse */
+#define XM_HW_COM4SIG	(1<<2)	/* Bit  2:	use Comma Detect for Sig. Det.*/
+								/* Bit  1:	reserved */
+#define XM_HW_GMII_MD	(1<<0)	/* Bit  0:	GMII Interface selected */
+
+
+/*	XM_TX_LO_WM	16 bit r/w	Tx FIFO Low Water Mark */
+/*	XM_TX_HI_WM	16 bit r/w	Tx FIFO High Water Mark */
+								/* Bit 15..10	reserved */
+#define XM_TX_WM_MSK	0x01ff	/* Bit  9.. 0	Tx FIFO Watermark bits */
+
+/*	XM_TX_THR	16 bit r/w	Tx Request Threshold */
+/*	XM_HT_THR	16 bit r/w	Host Request Threshold */
+/*	XM_RX_THR	16 bit r/w	Rx Request Threshold */
+								/* Bit 15..11	reserved */
+#define XM_THR_MSK		0x03ff	/* Bit 10.. 0	Rx/Tx Request Threshold bits */
+
+
+/*	XM_TX_STAT	32 bit r/o	Tx Status LIFO Register */
+#define XM_ST_VALID		(1UL<<31)	/* Bit 31:	Status Valid */
+#define XM_ST_BYTE_CNT	(0x3fffL<<17)	/* Bit 30..17:	Tx frame Length */
+#define XM_ST_RETRY_CNT	(0x1fL<<12)	/* Bit 16..12:	Retry Count */
+#define XM_ST_EX_COL	(1L<<11)	/* Bit 11:	Excessive Collisions */
+#define XM_ST_EX_DEF	(1L<<10)	/* Bit 10:	Excessive Deferral */
+#define XM_ST_BURST		(1L<<9)		/* Bit  9:	p. xmitted in burst md*/
+#define XM_ST_DEFER		(1L<<8)		/* Bit  8:	packet was defered */
+#define XM_ST_BC		(1L<<7)		/* Bit  7:	Broadcast packet */
+#define XM_ST_MC		(1L<<6)		/* Bit  6:	Multicast packet */
+#define XM_ST_UC		(1L<<5)		/* Bit  5:	Unicast packet */
+#define XM_ST_TX_UR		(1L<<4)		/* Bit  4:	FIFO Underrun occurred */
+#define XM_ST_CS_ERR	(1L<<3)		/* Bit  3:	Carrier Sense Error */
+#define XM_ST_LAT_COL	(1L<<2)		/* Bit  2:	Late Collision Error */
+#define XM_ST_MUL_COL	(1L<<1)		/* Bit  1:	Multiple Collisions */
+#define XM_ST_SGN_COL	(1L<<0)		/* Bit  0:	Single Collision */
+
+/*	XM_RX_LO_WM	16 bit r/w	Receive Low Water Mark */
+/*	XM_RX_HI_WM	16 bit r/w	Receive High Water Mark */
+									/* Bit 15..11:	reserved */
+#define XM_RX_WM_MSK	0x03ff		/* Bit 11.. 0:	Rx FIFO Watermark bits */
+
+
+/*	XM_DEV_ID	32 bit r/o	Device ID Register */
+#define XM_DEV_OUI	(0x00ffffffUL<<8)	/* Bit 31..8:	Device OUI */
+#define XM_DEV_REV	(0x07L << 5)		/* Bit  7..5:	Chip Rev Num */
+
+
+/*	XM_MODE		32 bit r/w	Mode Register */
+									/* Bit 31..27:	reserved */
+#define XM_MD_ENA_REJ	(1L<<26)	/* Bit 26:	Enable Frame Reject */
+#define XM_MD_SPOE_E	(1L<<25)	/* Bit 25:	Send Pause on Edge */
+									/*		extern generated */
+#define XM_MD_TX_REP	(1L<<24)	/* Bit 24:	Transmit Repeater Mode */
+#define XM_MD_SPOFF_I	(1L<<23)	/* Bit 23:	Send Pause on FIFO full */
+									/*		intern generated */
+#define XM_MD_LE_STW	(1L<<22)	/* Bit 22:	Rx Stat Word in Little Endian */
+#define XM_MD_TX_CONT	(1L<<21)	/* Bit 21:	Send Continuous */
+#define XM_MD_TX_PAUSE	(1L<<20)	/* Bit 20: (sc)	Send Pause Frame */
+#define XM_MD_ATS		(1L<<19)	/* Bit 19:	Append Time Stamp */
+#define XM_MD_SPOL_I	(1L<<18)	/* Bit 18:	Send Pause on Low */
+									/*		intern generated */
+#define XM_MD_SPOH_I	(1L<<17)	/* Bit 17:	Send Pause on High */
+									/*		intern generated */
+#define XM_MD_CAP		(1L<<16)	/* Bit 16:	Check Address Pair */
+#define XM_MD_ENA_HASH	(1L<<15)	/* Bit 15:	Enable Hashing */
+#define XM_MD_CSA		(1L<<14)	/* Bit 14:	Check Station Address */
+#define XM_MD_CAA		(1L<<13)	/* Bit 13:	Check Address Array */
+#define XM_MD_RX_MCTRL	(1L<<12)	/* Bit 12:	Rx MAC Control Frame */
+#define XM_MD_RX_RUNT	(1L<<11)	/* Bit 11:	Rx Runt Frames */
+#define XM_MD_RX_IRLE	(1L<<10)	/* Bit 10:	Rx in Range Len Err Frame */
+#define XM_MD_RX_LONG	(1L<<9)		/* Bit  9:	Rx Long Frame */
+#define XM_MD_RX_CRCE	(1L<<8)		/* Bit  8:	Rx CRC Error Frame */
+#define XM_MD_RX_ERR	(1L<<7)		/* Bit  7:	Rx Error Frame */
+#define XM_MD_DIS_UC	(1L<<6)		/* Bit  6:	Disable Rx Unicast */
+#define XM_MD_DIS_MC	(1L<<5)		/* Bit  5:	Disable Rx Multicast */
+#define XM_MD_DIS_BC	(1L<<4)		/* Bit  4:	Disable Rx Broadcast */
+#define XM_MD_ENA_PROM	(1L<<3)		/* Bit  3:	Enable Promiscuous */
+#define XM_MD_ENA_BE	(1L<<2)		/* Bit  2:	Enable Big Endian */
+#define XM_MD_FTF		(1L<<1)		/* Bit  1: (sc)	Flush Tx FIFO */
+#define XM_MD_FRF		(1L<<0)		/* Bit  0: (sc)	Flush Rx FIFO */
+
+#define XM_PAUSE_MODE	(XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
+#define XM_DEF_MODE		(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
+				XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
+
+/*	XM_STAT_CMD	16 bit r/w	Statistics Command Register */
+								/* Bit 16..6:	reserved */
+#define XM_SC_SNP_RXC	(1<<5)	/* Bit  5: (sc)	Snap Rx Counters */
+#define XM_SC_SNP_TXC	(1<<4)	/* Bit  4: (sc)	Snap Tx Counters */
+#define XM_SC_CP_RXC	(1<<3)	/* Bit  3:	Copy Rx Counters Continuously */
+#define XM_SC_CP_TXC	(1<<2)	/* Bit  2:	Copy Tx Counters Continuously */
+#define XM_SC_CLR_RXC	(1<<1)	/* Bit  1: (sc)	Clear Rx Counters */
+#define XM_SC_CLR_TXC	(1<<0)	/* Bit  0: (sc)	Clear Tx Counters */
+
+
+/*	XM_RX_CNT_EV	32 bit r/o	Rx Counter Event Register */
+/*	XM_RX_EV_MSK	32 bit r/w	Rx Counter Event Mask */
+#define XMR_MAX_SZ_OV	(1UL<<31)	/* Bit 31:	1024-MaxSize Rx Cnt Ov */
+#define XMR_1023B_OV	(1L<<30)	/* Bit 30:	512-1023Byte Rx Cnt Ov */
+#define XMR_511B_OV		(1L<<29)	/* Bit 29:	256-511 Byte Rx Cnt Ov */
+#define XMR_255B_OV		(1L<<28)	/* Bit 28:	128-255 Byte Rx Cnt Ov */
+#define XMR_127B_OV		(1L<<27)	/* Bit 27:	65-127 Byte Rx Cnt Ov */
+#define XMR_64B_OV		(1L<<26)	/* Bit 26:	64 Byte Rx Cnt Ov */
+#define XMR_UTIL_OV		(1L<<25)	/* Bit 25:	Rx Util Cnt Overflow */
+#define XMR_UTIL_UR		(1L<<24)	/* Bit 24:	Rx Util Cnt Underrun */
+#define XMR_CEX_ERR_OV	(1L<<23)	/* Bit 23:	CEXT Err Cnt Ov */
+									/* Bit 22:	reserved */
+#define XMR_FCS_ERR_OV	(1L<<21)	/* Bit 21:	Rx FCS Error Cnt Ov */
+#define XMR_LNG_ERR_OV	(1L<<20)	/* Bit 20:	Rx too Long Err Cnt Ov */
+#define XMR_RUNT_OV		(1L<<19)	/* Bit 19:	Runt Event Cnt Ov */
+#define XMR_SHT_ERR_OV	(1L<<18)	/* Bit 18:	Rx Short Ev Err Cnt Ov */
+#define XMR_SYM_ERR_OV	(1L<<17)	/* Bit 17:	Rx Sym Err Cnt Ov */
+									/* Bit 16:	reserved */
+#define XMR_CAR_ERR_OV	(1L<<15)	/* Bit 15:	Rx Carr Ev Err Cnt Ov */
+#define XMR_JAB_PKT_OV	(1L<<14)	/* Bit 14:	Rx Jabb Packet Cnt Ov */
+#define XMR_FIFO_OV		(1L<<13)	/* Bit 13:	Rx FIFO Ov Ev Cnt Ov */
+#define XMR_FRA_ERR_OV	(1L<<12)	/* Bit 12:	Rx Framing Err Cnt Ov */
+#define XMR_FMISS_OV	(1L<<11)	/* Bit 11:	Rx Missed Ev Cnt Ov */
+#define XMR_BURST		(1L<<10)	/* Bit 10:	Rx Burst Event Cnt Ov */
+#define XMR_INV_MOC		(1L<<9)		/* Bit  9:	Rx with inv. MAC OC Ov */
+#define XMR_INV_MP		(1L<<8)		/* Bit  8:	Rx inv Pause Frame Ov */
+#define XMR_MCTRL_OV	(1L<<7)		/* Bit  7:	Rx MAC Ctrl-F Cnt Ov */
+#define XMR_MPAUSE_OV	(1L<<6)		/* Bit  6:	Rx Pause MAC Ctrl-F Ov */
+#define XMR_UC_OK_OV	(1L<<5)		/* Bit  5:	Rx Unicast Frame Cnt Ov */
+#define XMR_MC_OK_OV	(1L<<4)		/* Bit  4:	Rx Multicast Cnt Ov */
+#define XMR_BC_OK_OV	(1L<<3)		/* Bit  3:	Rx Broadcast Cnt Ov */
+#define XMR_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Rx OK Low Cnt Ov */
+#define XMR_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Rx OK High Cnt Ov */
+#define XMR_OK_OV		(1L<<0)		/* Bit  0:	Frames Received OK Ov */
+
+#define XMR_DEF_MSK		(XMR_OK_LO_OV | XMR_OK_HI_OV)
+
+/*	XM_TX_CNT_EV	32 bit r/o	Tx Counter Event Register */
+/*	XM_TX_EV_MSK	32 bit r/w	Tx Counter Event Mask */
+									/* Bit 31..26:	reserved */
+#define XMT_MAX_SZ_OV	(1L<<25)	/* Bit 25:	1024-MaxSize Tx Cnt Ov */
+#define XMT_1023B_OV	(1L<<24)	/* Bit 24:	512-1023Byte Tx Cnt Ov */
+#define XMT_511B_OV		(1L<<23)	/* Bit 23:	256-511 Byte Tx Cnt Ov */
+#define XMT_255B_OV		(1L<<22)	/* Bit 22:	128-255 Byte Tx Cnt Ov */
+#define XMT_127B_OV		(1L<<21)	/* Bit 21:	65-127 Byte Tx Cnt Ov */
+#define XMT_64B_OV		(1L<<20)	/* Bit 20:	64 Byte Tx Cnt Ov */
+#define XMT_UTIL_OV		(1L<<19)	/* Bit 19:	Tx Util Cnt Overflow */
+#define XMT_UTIL_UR		(1L<<18)	/* Bit 18:	Tx Util Cnt Underrun */
+#define XMT_CS_ERR_OV	(1L<<17)	/* Bit 17:	Tx Carr Sen Err Cnt Ov */
+#define XMT_FIFO_UR_OV	(1L<<16)	/* Bit 16:	Tx FIFO Ur Ev Cnt Ov */
+#define XMT_EX_DEF_OV	(1L<<15)	/* Bit 15:	Tx Ex Deferall Cnt Ov */
+#define XMT_DEF			(1L<<14)	/* Bit 14:	Tx Deferred Cnt Ov */
+#define XMT_LAT_COL_OV	(1L<<13)	/* Bit 13:	Tx Late Col Cnt Ov */
+#define XMT_ABO_COL_OV	(1L<<12)	/* Bit 12:	Tx abo dueto Ex Col Ov */
+#define XMT_MUL_COL_OV	(1L<<11)	/* Bit 11:	Tx Mult Col Cnt Ov */
+#define XMT_SNG_COL		(1L<<10)	/* Bit 10:	Tx Single Col Cnt Ov */
+#define XMT_MCTRL_OV	(1L<<9)		/* Bit  9:	Tx MAC Ctrl Counter Ov */
+#define XMT_MPAUSE		(1L<<8)		/* Bit  8:	Tx Pause MAC Ctrl-F Ov */
+#define XMT_BURST		(1L<<7)		/* Bit  7:	Tx Burst Event Cnt Ov */
+#define XMT_LONG		(1L<<6)		/* Bit  6:	Tx Long Frame Cnt Ov */
+#define XMT_UC_OK_OV	(1L<<5)		/* Bit  5:	Tx Unicast Cnt Ov */
+#define XMT_MC_OK_OV	(1L<<4)		/* Bit  4:	Tx Multicast Cnt Ov */
+#define XMT_BC_OK_OV	(1L<<3)		/* Bit  3:	Tx Broadcast Cnt Ov */
+#define XMT_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Tx OK Low Cnt Ov */
+#define XMT_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Tx OK High Cnt Ov */
+#define XMT_OK_OV		(1L<<0)		/* Bit  0:	Frames Tx OK Ov */
+
+#define XMT_DEF_MSK		(XMT_OK_LO_OV | XMT_OK_HI_OV)
+
+/*
+ * Receive Frame Status Encoding
+ */
+#define XMR_FS_LEN_MSK	(0x3fffUL<<18)	/* Bit 31..18:	Rx Frame Length */
+#define XMR_FS_2L_VLAN	(1L<<17)	/* Bit 17:	Tagged wh 2Lev VLAN ID */
+#define XMR_FS_1L_VLAN	(1L<<16)	/* Bit 16:	Tagged wh 1Lev VLAN ID */
+#define XMR_FS_BC		(1L<<15)	/* Bit 15:	Broadcast Frame */
+#define XMR_FS_MC		(1L<<14)	/* Bit 14:	Multicast Frame */
+#define XMR_FS_UC		(1L<<13)	/* Bit 13:	Unicast Frame */
+									/* Bit 12:	reserved */
+#define XMR_FS_BURST	(1L<<11)	/* Bit 11:	Burst Mode */
+#define XMR_FS_CEX_ERR	(1L<<10)	/* Bit 10:	Carrier Ext. Error */
+#define XMR_FS_802_3	(1L<<9)		/* Bit  9:	802.3 Frame */
+#define XMR_FS_COL_ERR	(1L<<8)		/* Bit  8:	Collision Error */
+#define XMR_FS_CAR_ERR	(1L<<7)		/* Bit  7:	Carrier Event Error */
+#define XMR_FS_LEN_ERR	(1L<<6)		/* Bit  6:	In-Range Length Error */
+#define XMR_FS_FRA_ERR	(1L<<5)		/* Bit  5:	Framing Error */
+#define XMR_FS_RUNT		(1L<<4)		/* Bit  4:	Runt Frame */
+#define XMR_FS_LNG_ERR	(1L<<3)		/* Bit  3:	Giant (Jumbo) Frame */
+#define XMR_FS_FCS_ERR	(1L<<2)		/* Bit  2:	Frame Check Sequ Err */
+#define XMR_FS_ERR		(1L<<1)		/* Bit  1:	Frame Error */
+#define XMR_FS_MCTRL	(1L<<0)		/* Bit  0:	MAC Control Packet */
+
+#define XMR_FS_LEN_SHIFT	18
+
+/*
+ * XMR_FS_ERR will be set if
+ *	XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
+ *	XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
+ * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
+ * XMR_FS_ERR unless the corresponding bit in the Receive Command
+ * Register is set.
+ */
+#define XMR_FS_ANY_ERR	XMR_FS_ERR
+
+/*----------------------------------------------------------------------------*/
+/*
+ * XMAC-PHY Registers, indirect addressed over the XMAC
+ */
+#define PHY_XMAC_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
+#define PHY_XMAC_STAT		0x01	/* 16 bit r/w	PHY Status Register */
+#define PHY_XMAC_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
+#define PHY_XMAC_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
+#define PHY_XMAC_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
+#define PHY_XMAC_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
+#define PHY_XMAC_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
+#define PHY_XMAC_NEPG		0x07	/* 16 bit r/w	Next Page Register */
+#define PHY_XMAC_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
+	/* 0x09 - 0x0e:		reserved */
+#define PHY_XMAC_EXT_STAT	0x0f	/* 16 bit r/o	Ext Status Register */
+#define PHY_XMAC_RES_ABI	0x10	/* 16 bit r/o	PHY Resolved Ability */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Broadcom-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_BCOM_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
+#define PHY_BCOM_STAT		0x01	/* 16 bit r/o	PHY Status Register */
+#define PHY_BCOM_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
+#define PHY_BCOM_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
+#define PHY_BCOM_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
+#define PHY_BCOM_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
+#define PHY_BCOM_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
+#define PHY_BCOM_NEPG		0x07	/* 16 bit r/w	Next Page Register */
+#define PHY_BCOM_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
+	/* Broadcom-specific registers */
+#define PHY_BCOM_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
+#define PHY_BCOM_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
+	/* 0x0b - 0x0e:		reserved */
+#define PHY_BCOM_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
+#define PHY_BCOM_P_EXT_CTRL	0x10	/* 16 bit r/w	PHY Extended Ctrl Reg */
+#define PHY_BCOM_P_EXT_STAT	0x11	/* 16 bit r/o	PHY Extended Stat Reg */
+#define PHY_BCOM_RE_CTR		0x12	/* 16 bit r/w	Receive Error Counter */
+#define PHY_BCOM_FC_CTR		0x13	/* 16 bit r/w	False Carrier Sense Cnt */
+#define PHY_BCOM_RNO_CTR	0x14	/* 16 bit r/w	Receiver NOT_OK Cnt */
+	/* 0x15 - 0x17:		reserved */
+#define PHY_BCOM_AUX_CTRL	0x18	/* 16 bit r/w	Auxiliary Control Reg */
+#define PHY_BCOM_AUX_STAT	0x19	/* 16 bit r/o	Auxiliary Stat Summary */
+#define PHY_BCOM_INT_STAT	0x1a	/* 16 bit r/o	Interrupt Status Reg */
+#define PHY_BCOM_INT_MASK	0x1b	/* 16 bit r/w	Interrupt Mask Reg */
+	/* 0x1c:		reserved */
+	/* 0x1d - 0x1f:		test registers */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Marvell-PHY Registers, indirect addressed over GMAC
+ */
+#define PHY_MARV_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
+#define PHY_MARV_STAT		0x01	/* 16 bit r/o	PHY Status Register */
+#define PHY_MARV_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
+#define PHY_MARV_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
+#define PHY_MARV_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
+#define PHY_MARV_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
+#define PHY_MARV_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
+#define PHY_MARV_NEPG		0x07	/* 16 bit r/w	Next Page Register */
+#define PHY_MARV_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
+	/* Marvell-specific registers */
+#define PHY_MARV_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
+#define PHY_MARV_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
+	/* 0x0b - 0x0e:		reserved */
+#define PHY_MARV_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
+#define PHY_MARV_PHY_CTRL	0x10	/* 16 bit r/w	PHY Specific Control Reg */
+#define PHY_MARV_PHY_STAT	0x11	/* 16 bit r/o	PHY Specific Status Reg */
+#define PHY_MARV_INT_MASK	0x12	/* 16 bit r/w	Interrupt Mask Reg */
+#define PHY_MARV_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */
+#define PHY_MARV_EXT_CTRL	0x14	/* 16 bit r/w	Ext. PHY Specific Ctrl */
+#define PHY_MARV_RXE_CNT	0x15	/* 16 bit r/w	Receive Error Counter */
+#define PHY_MARV_EXT_ADR	0x16	/* 16 bit r/w	Ext. Ad. for Cable Diag. */
+#define PHY_MARV_PORT_IRQ	0x17	/* 16 bit r/o	Port 0 IRQ (88E1111 only) */
+#define PHY_MARV_LED_CTRL	0x18	/* 16 bit r/w	LED Control Reg */
+#define PHY_MARV_LED_OVER	0x19	/* 16 bit r/w	Manual LED Override Reg */
+#define PHY_MARV_EXT_CTRL_2	0x1a	/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */
+#define PHY_MARV_EXT_P_STAT	0x1b	/* 16 bit r/w	Ext. PHY Spec. Stat Reg */
+#define PHY_MARV_CABLE_DIAG	0x1c	/* 16 bit r/o	Cable Diagnostic Reg */
+#define PHY_MARV_PAGE_ADDR	0x1d	/* 16 bit r/w	Extended Page Address Reg */
+#define PHY_MARV_PAGE_DATA	0x1e	/* 16 bit r/w	Extended Page Data Reg */
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_MARV_FE_LED_PAR	0x16	/* 16 bit r/w	LED Parallel Select Reg. */
+#define PHY_MARV_FE_LED_SER	0x17	/* 16 bit r/w	LED Stream Select S. LED */
+#define PHY_MARV_FE_VCT_TX	0x1a	/* 16 bit r/w	VCT Reg. for TXP/N Pins */
+#define PHY_MARV_FE_VCT_RX	0x1b	/* 16 bit r/o	VCT Reg. for RXP/N Pins */
+#define PHY_MARV_FE_SPEC_2	0x1c	/* 16 bit r/w	Specific Control Reg. 2 */
+
+/* for Yukon-Ultra & Yukon-Extreme PHY only */
+#define PHY_MARV_MAC_CTRL	0x15	/* 16 bit r/w	MAC Spec. Ctrl (page 2) */
+
+/* for Advanced VCT (Yukon-Extreme and newer PHY) */
+#define PHY_MARV_ADV_VCT_C	0x17	/* 16 bit r/w	Adv. VCT Ctrl (page 5) */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Level One-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_LONE_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
+#define PHY_LONE_STAT		0x01	/* 16 bit r/o	PHY Status Register */
+#define PHY_LONE_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */
+#define PHY_LONE_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */
+#define PHY_LONE_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
+#define PHY_LONE_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Ability Reg */
+#define PHY_LONE_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
+#define PHY_LONE_NEPG		0x07	/* 16 bit r/w	Next Page Register */
+#define PHY_LONE_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner */
+	/* Level One-specific registers */
+#define PHY_LONE_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
+#define PHY_LONE_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
+	/* 0x0b - 0x0e:		reserved */
+#define PHY_LONE_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */
+#define PHY_LONE_PORT_CFG	0x10	/* 16 bit r/w	Port Configuration Reg*/
+#define PHY_LONE_Q_STAT		0x11	/* 16 bit r/o	Quick Status Reg */
+#define PHY_LONE_INT_ENAB	0x12	/* 16 bit r/w	Interrupt Enable Reg */
+#define PHY_LONE_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */
+#define PHY_LONE_LED_CFG	0x14	/* 16 bit r/w	LED Configuration Reg */
+#define PHY_LONE_PORT_CTRL	0x15	/* 16 bit r/w	Port Control Reg */
+#define PHY_LONE_CIM		0x16	/* 16 bit r/o	CIM Reg */
+	/* 0x17 - 0x1c:		reserved */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * National-PHY Registers, indirect addressed over XMAC
+ */
+#define PHY_NAT_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
+#define PHY_NAT_STAT		0x01	/* 16 bit r/w	PHY Status Register */
+#define PHY_NAT_ID0			0x02	/* 16 bit r/o	PHY ID0 Register */
+#define PHY_NAT_ID1			0x03	/* 16 bit r/o	PHY ID1 Register */
+#define PHY_NAT_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */
+#define PHY_NAT_AUNE_LP		0x05	/* 16 bit r/o	Link Partner Ability Reg */
+#define PHY_NAT_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */
+#define PHY_NAT_NEPG		0x07	/* 16 bit r/w	Next Page Register */
+#define PHY_NAT_NEPG_LP		0x08	/* 16 bit r/o	Next Page Link Partner Reg */
+	/* National-specific registers */
+#define PHY_NAT_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
+#define PHY_NAT_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */
+	/* 0x0b - 0x0e:		reserved */
+#define PHY_NAT_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Register */
+#define PHY_NAT_EXT_CTRL1	0x10	/* 16 bit r/o	Extended Control Reg1 */
+#define PHY_NAT_Q_STAT1		0x11	/* 16 bit r/o	Quick Status Reg1 */
+#define PHY_NAT_10B_OP		0x12	/* 16 bit r/o	10Base-T Operations Reg */
+#define PHY_NAT_EXT_CTRL2	0x13	/* 16 bit r/o	Extended Control Reg1 */
+#define PHY_NAT_Q_STAT2		0x14	/* 16 bit r/o	Quick Status Reg2 */
+	/* 0x15 - 0x18:		reserved */
+#define PHY_NAT_PHY_ADDR	0x19	/* 16 bit r/o	PHY Address Register */
+
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * PHY bit definitions
+ * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
+ * XMAC/Broadcom/LevelOne/National/Marvell-specific.
+ * All other are general.
+ */
+
+/*****  PHY_XMAC_CTRL	16 bit r/w	PHY Control Register *****/
+/*****  PHY_BCOM_CTRL	16 bit r/w	PHY Control Register *****/
+/*****  PHY_MARV_CTRL	16 bit r/w	PHY Status Register *****/
+/*****  PHY_LONE_CTRL	16 bit r/w	PHY Control Register *****/
+#define PHY_CT_RESET	(1<<15)	/* Bit 15: (sc)	clear all PHY related regs */
+#define PHY_CT_LOOP		(1<<14)	/* Bit 14:	enable Loopback over PHY */
+#define PHY_CT_SPS_LSB	(1<<13) /* Bit 13:	Speed select, lower bit */
+#define PHY_CT_ANE		(1<<12)	/* Bit 12:	Auto-Negotiation Enabled */
+#define PHY_CT_PDOWN	(1<<11)	/* Bit 11:	Power Down Mode */
+#define PHY_CT_ISOL		(1<<10)	/* Bit 10:	Isolate Mode */
+#define PHY_CT_RE_CFG	(1<<9)	/* Bit  9:	(sc) Restart Auto-Negotiation */
+#define PHY_CT_DUP_MD	(1<<8)	/* Bit  8:	Duplex Mode */
+#define PHY_CT_COL_TST	(1<<7)	/* Bit  7:	Collision Test enabled */
+#define PHY_CT_SPS_MSB	(1<<6)	/* Bit  6:	Speed select, upper bit */
+								/* Bit  5..0:	reserved */
+
+#define PHY_CT_SP1000	PHY_CT_SPS_MSB	/* enable speed of 1000 Mbps */
+#define PHY_CT_SP100	PHY_CT_SPS_LSB	/* enable speed of  100 Mbps */
+#define PHY_CT_SP10		(0)				/* enable speed of   10 Mbps */
+
+
+/*****  PHY_XMAC_STAT	16 bit r/w	PHY Status Register *****/
+/*****  PHY_BCOM_STAT	16 bit r/w	PHY Status Register *****/
+/*****  PHY_MARV_STAT	16 bit r/w	PHY Status Register *****/
+/*****  PHY_LONE_STAT	16 bit r/w	PHY Status Register *****/
+								/* Bit 15..9:	reserved */
+				/*	(BC/L1) 100/10 Mbps cap bits ignored */
+#define PHY_ST_EXT_ST	(1<<8)	/* Bit  8:	Extended Status Present */
+								/* Bit  7:	reserved */
+#define PHY_ST_PRE_SUP	(1<<6)	/* Bit  6:	Preamble Suppression */
+#define PHY_ST_AN_OVER	(1<<5)	/* Bit  5:	Auto-Negotiation Over */
+#define PHY_ST_REM_FLT	(1<<4)	/* Bit  4:	Remote Fault Condition Occurred */
+#define PHY_ST_AN_CAP	(1<<3)	/* Bit  3:	Auto-Negotiation Capability */
+#define PHY_ST_LSYNC	(1<<2)	/* Bit  2:	Link Synchronized */
+#define PHY_ST_JAB_DET	(1<<1)	/* Bit  1:	Jabber Detected */
+#define PHY_ST_EXT_REG	(1<<0)	/* Bit  0:	Extended Register available */
+
+
+/*****  PHY_XMAC_ID1		16 bit r/o	PHY ID1 Register */
+/*****  PHY_BCOM_ID1		16 bit r/o	PHY ID1 Register */
+/*****  PHY_MARV_ID1		16 bit r/o	PHY ID1 Register */
+/*****  PHY_LONE_ID1		16 bit r/o	PHY ID1 Register */
+#define PHY_I1_OUI_MSK	(0x3f<<10)	/* Bit 15..10:	Organization Unique ID */
+#define PHY_I1_MOD_NUM	(0x3f<<4)	/* Bit  9.. 4:	Model Number */
+#define PHY_I1_REV_MSK	0xf			/* Bit  3.. 0:	Revision Number */
+
+/* different Broadcom PHY Ids */
+#define PHY_BCOM_ID1_A1		0x6041
+#define PHY_BCOM_ID1_B2		0x6043
+#define PHY_BCOM_ID1_C0		0x6044
+#define PHY_BCOM_ID1_C5		0x6047
+
+/* different Marvell PHY Ids */
+#define PHY_MARV_ID0_VAL	0x0141		/* Marvell Unique Identifier */
+
+#define PHY_MARV_ID1_B0		0x0C23		/* Yukon      (PHY 88E1040 Rev.C0) */
+#define PHY_MARV_ID1_B2		0x0C25		/* Yukon-Plus (PHY 88E1040 Rev.D0) */
+#define PHY_MARV_ID1_C2		0x0CC2		/* Yukon-EC   (PHY 88E1111 Rev.B1) */
+#define PHY_MARV_ID1_Y2		0x0C91		/* Yukon-XL   (PHY 88E1112 Rev.B0) */
+#define PHY_MARV_ID1_FE		0x0C83		/* Yukon-FE   (PHY 88E3082 Rev.A1) */
+#define PHY_MARV_ID1_FEP	0x0E60		/* Yukon-FE+  (PHY 88E3016 Rev.A1?) */
+#define PHY_MARV_ID1_ECU	0x0CB0		/* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
+#define PHY_MARV_ID1_EX		0x0CB1		/* Yukon-Ext. (PHY 88E1149R Rev.?) */
+										/* Yukon-ECU Rev. A2 and newer */
+#define PHY_MARV_ID1_OPT	0x0E70		/* Yukon-Opt. (PHY PHYG65G Rev.?) */
+
+/*****  PHY_XMAC_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
+/*****  PHY_XMAC_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
+#define PHY_AN_NXT_PG	(1<<15)	/* Bit 15:	Request Next Page */
+#define PHY_X_AN_ACK	(1<<14)	/* Bit 14:	(ro) Acknowledge Received */
+#define PHY_X_AN_RFB	(3<<12)	/* Bit 13..12:	Remote Fault Bits */
+								/* Bit 11.. 9:	reserved */
+#define PHY_X_AN_PAUSE	(3<<7)	/* Bit  8.. 7:	Pause Bits */
+#define PHY_X_AN_HD		(1<<6)	/* Bit  6:	Half Duplex */
+#define PHY_X_AN_FD		(1<<5)	/* Bit  5:	Full Duplex */
+								/* Bit  4.. 0:	reserved */
+
+/*****  PHY_BCOM_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
+/*****  PHY_BCOM_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_B_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
+#define PHY_B_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
+#define PHY_B_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
+								/* Bit  9..5:	100/10 BT cap bits ingnored */
+#define PHY_B_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/
+
+/*****  PHY_LONE_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
+/*****  PHY_LONE_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_L_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
+#define PHY_L_AN_ASP	(1<<11)	/* Bit 11:	Asymmetric Pause */
+#define PHY_L_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
+								/* Bit  9..5:	100/10 BT cap bits ingnored */
+#define PHY_L_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/
+
+/*****  PHY_NAT_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
+/*****  PHY_NAT_AUNE_LP		16 bit r/o	Link Partner Ability Reg *****/
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_N_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
+#define PHY_N_AN_100F	(1<<11)	/* Bit 11:	100Base-T2 FD Support */
+#define PHY_N_AN_100H	(1<<10)	/* Bit 10:	100Base-T2 HD Support */
+								/* Bit  9..5:	100/10 BT cap bits ingnored */
+#define PHY_N_AN_SEL	0x1f	/* Bit 4..0:	Selector Field, 00001=Ethernet*/
+
+/* field type definition for PHY_x_AN_SEL */
+#define PHY_SEL_TYPE	0x01	/* 00001 = Ethernet */
+
+/*****  PHY_XMAC_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
+								/* Bit 15..4:	reserved */
+#define PHY_ANE_LP_NP	(1<<3)	/* Bit  3:	Link Partner can Next Page */
+#define PHY_ANE_LOC_NP	(1<<2)	/* Bit  2:	Local PHY can Next Page */
+#define PHY_ANE_RX_PG	(1<<1)	/* Bit  1:	Page Received */
+								/* Bit  0:	reserved */
+
+/*****  PHY_BCOM_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
+/*****  PHY_LONE_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
+/*****  PHY_MARV_AUNE_EXP	16 bit r/o	Auto-Negotiation Expansion Reg *****/
+								/* Bit 15..5:	reserved */
+#define PHY_ANE_PAR_DF	(1<<4)	/* Bit  4:	Parallel Detection Fault */
+/*	PHY_ANE_LP_NP		(see XMAC) Bit  3:	Link Partner can Next Page */
+/*	PHY_ANE_LOC_NP		(see XMAC) Bit  2:	Local PHY can Next Page */
+/*	PHY_ANE_RX_PG		(see XMAC) Bit  1:	Page Received */
+#define PHY_ANE_LP_CAP	(1<<0)	/* Bit  0:	Link Partner Auto-Neg. Able */
+
+/*****  PHY_XMAC_NEPG		16 bit r/w	Next Page Register *****/
+/*****  PHY_BCOM_NEPG		16 bit r/w	Next Page Register *****/
+/*****  PHY_LONE_NEPG		16 bit r/w	Next Page Register *****/
+/*****  PHY_XMAC_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
+/*****  PHY_BCOM_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
+/*****  PHY_LONE_NEPG_LP	16 bit r/o	Next Page Link Partner *****/
+#define PHY_NP_MORE		(1<<15)	/* Bit 15:	More, Next Pages to follow */
+#define PHY_NP_ACK1		(1<<14)	/* Bit 14: (ro)	Ack1, for receiving a message */
+#define PHY_NP_MSG_VAL	(1<<13)	/* Bit 13:	Message Page valid */
+#define PHY_NP_ACK2		(1<<12)	/* Bit 12:	Ack2, comply with msg content */
+#define PHY_NP_TOG		(1<<11)	/* Bit 11:	Toggle Bit, ensure sync */
+#define PHY_NP_MSG		0x07ff	/* Bit 10..0:	Message from/to Link Partner */
+
+/*
+ * XMAC-Specific
+ */
+/*****  PHY_XMAC_EXT_STAT	16 bit r/w	Extended Status Register *****/
+#define PHY_X_EX_FD		(1<<15)	/* Bit 15:	Device Supports Full Duplex */
+#define PHY_X_EX_HD		(1<<14)	/* Bit 14:	Device Supports Half Duplex */
+								/* Bit 13..0:	reserved */
+
+/*****  PHY_XMAC_RES_ABI	16 bit r/o	PHY Resolved Ability *****/
+								/* Bit 15..9:	reserved */
+#define PHY_X_RS_PAUSE	(3<<7)	/* Bit  8..7:	selected Pause Mode */
+#define PHY_X_RS_HD		(1<<6)	/* Bit  6:	Half Duplex Mode selected */
+#define PHY_X_RS_FD		(1<<5)	/* Bit  5:	Full Duplex Mode selected */
+#define PHY_X_RS_ABLMIS (1<<4)	/* Bit  4:	duplex or pause cap mismatch */
+#define PHY_X_RS_PAUMIS (1<<3)	/* Bit  3:	pause capability mismatch */
+								/* Bit  2..0:	reserved */
+/*
+ * Remote Fault Bits (PHY_X_AN_RFB) encoding
+ */
+#define X_RFB_OK		(0<<12)	/* Bit 13..12	No errors, Link OK */
+#define X_RFB_LF		(1<<12)	/* Bit 13..12	Link Failure */
+#define X_RFB_OFF		(2<<12)	/* Bit 13..12	Offline */
+#define X_RFB_AN_ERR	(3<<12)	/* Bit 13..12	Auto-Negotiation Error */
+
+/*
+ * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
+ */
+#define PHY_X_P_NO_PAUSE	(0<<7)	/* Bit  8..7:	no Pause Mode */
+#define PHY_X_P_SYM_MD		(1<<7)	/* Bit  8..7:	symmetric Pause Mode */
+#define PHY_X_P_ASYM_MD		(2<<7)	/* Bit  8..7:	asymmetric Pause Mode */
+#define PHY_X_P_BOTH_MD		(3<<7)	/* Bit  8..7:	both Pause Mode */
+
+
+/*
+ * Broadcom-Specific
+ */
+/*****  PHY_BCOM_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
+#define PHY_B_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */
+#define PHY_B_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */
+#define PHY_B_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */
+#define PHY_B_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */
+#define PHY_B_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */
+#define PHY_B_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */
+									/* Bit  7..0:	reserved */
+
+/*****  PHY_BCOM_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
+/*****  PHY_MARV_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
+#define PHY_B_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */
+#define PHY_B_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */
+#define PHY_B_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */
+#define PHY_B_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status */
+#define PHY_B_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */
+#define PHY_B_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */
+									/* Bit  9..8:	reserved */
+#define PHY_B_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count */
+
+/*****  PHY_BCOM_EXT_STAT	16 bit r/o	Extended Status Register *****/
+#define PHY_B_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */
+#define PHY_B_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
+#define PHY_B_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
+#define PHY_B_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
+									/* Bit 11..0:	reserved */
+
+/*****  PHY_BCOM_P_EXT_CTRL	16 bit r/w	PHY Extended Control Reg *****/
+#define PHY_B_PEC_MAC_PHY	(1<<15)	/* Bit 15:	10BIT/GMI-Interface */
+#define PHY_B_PEC_DIS_CROSS	(1<<14)	/* Bit 14:	Disable MDI Crossover */
+#define PHY_B_PEC_TX_DIS	(1<<13)	/* Bit 13:	Tx output Disabled */
+#define PHY_B_PEC_INT_DIS	(1<<12)	/* Bit 12:	Interrupts Disabled */
+#define PHY_B_PEC_F_INT		(1<<11)	/* Bit 11:	Force Interrupt */
+#define PHY_B_PEC_BY_45		(1<<10)	/* Bit 10:	Bypass 4B5B-Decoder */
+#define PHY_B_PEC_BY_SCR	(1<<9)	/* Bit  9:	Bypass Scrambler */
+#define PHY_B_PEC_BY_MLT3	(1<<8)	/* Bit  8:	Bypass MLT3 Encoder */
+#define PHY_B_PEC_BY_RXA	(1<<7)	/* Bit  7:	Bypass Rx Alignm. */
+#define PHY_B_PEC_RES_SCR	(1<<6)	/* Bit  6:	Reset Scrambler */
+#define PHY_B_PEC_EN_LTR	(1<<5)	/* Bit  5:	Enable LED Traffic Mode */
+#define PHY_B_PEC_LED_ON	(1<<4)	/* Bit  4:	Force LEDs on */
+#define PHY_B_PEC_LED_OFF	(1<<3)	/* Bit  3:	Force LEDs off */
+#define PHY_B_PEC_EX_IPG	(1<<2)	/* Bit  2:	Extend Tx IPG Mode */
+#define PHY_B_PEC_3_LED		(1<<1)	/* Bit  1:	Three Link LED mode */
+#define PHY_B_PEC_HIGH_LA	(1<<0)	/* Bit  0:	GMII FIFO Elasticy */
+
+/*****  PHY_BCOM_P_EXT_STAT	16 bit r/o	PHY Extended Status Reg *****/
+									/* Bit 15..14:	reserved */
+#define PHY_B_PES_CROSS_STAT	(1<<13)	/* Bit 13:	MDI Crossover Status */
+#define PHY_B_PES_INT_STAT	(1<<12)	/* Bit 12:	Interrupt Status */
+#define PHY_B_PES_RRS		(1<<11)	/* Bit 11:	Remote Receiver Stat. */
+#define PHY_B_PES_LRS		(1<<10)	/* Bit 10:	Local Receiver Stat. */
+#define PHY_B_PES_LOCKED	(1<<9)	/* Bit  9:	Locked */
+#define PHY_B_PES_LS		(1<<8)	/* Bit  8:	Link Status */
+#define PHY_B_PES_RF		(1<<7)	/* Bit  7:	Remote Fault */
+#define PHY_B_PES_CE_ER		(1<<6)	/* Bit  6:	Carrier Ext Error */
+#define PHY_B_PES_BAD_SSD	(1<<5)	/* Bit  5:	Bad SSD */
+#define PHY_B_PES_BAD_ESD	(1<<4)	/* Bit  4:	Bad ESD */
+#define PHY_B_PES_RX_ER		(1<<3)	/* Bit  3:	Receive Error */
+#define PHY_B_PES_TX_ER		(1<<2)	/* Bit  2:	Transmit Error */
+#define PHY_B_PES_LOCK_ER	(1<<1)	/* Bit  1:	Lock Error */
+#define PHY_B_PES_MLT3_ER	(1<<0)	/* Bit  0:	MLT3 code Error */
+
+/*****  PHY_BCOM_FC_CTR		16 bit r/w	False Carrier Counter *****/
+									/* Bit 15..8:	reserved */
+#define PHY_B_FC_CTR		0xff	/* Bit  7..0:	False Carrier Counter */
+
+/*****  PHY_BCOM_RNO_CTR	16 bit r/w	Receive NOT_OK Counter *****/
+#define PHY_B_RC_LOC_MSK	0xff00	/* Bit 15..8:	Local Rx NOT_OK cnt */
+#define PHY_B_RC_REM_MSK	0x00ff	/* Bit  7..0:	Remote Rx NOT_OK cnt */
+
+/*****  PHY_BCOM_AUX_CTRL	16 bit r/w	Auxiliary Control Reg *****/
+#define PHY_B_AC_L_SQE		(1<<15)	/* Bit 15:	Low Squelch */
+#define PHY_B_AC_LONG_PACK	(1<<14)	/* Bit 14:	Rx Long Packets */
+#define PHY_B_AC_ER_CTRL	(3<<12)	/* Bit 13..12:	Edgerate Control */
+									/* Bit 11:	reserved */
+#define PHY_B_AC_TX_TST		(1<<10) /* Bit 10:	Tx test bit, always 1 */
+									/* Bit  9.. 8:	reserved */
+#define PHY_B_AC_DIS_PRF	(1<<7)	/* Bit  7:	dis part resp filter */
+									/* Bit  6:	reserved */
+#define PHY_B_AC_DIS_PM		(1<<5)	/* Bit  5:	dis power management */
+									/* Bit  4:	reserved */
+#define PHY_B_AC_DIAG		(1<<3)	/* Bit  3:	Diagnostic Mode */
+									/* Bit  2.. 0:	reserved */
+
+/*****  PHY_BCOM_AUX_STAT	16 bit r/o	Auxiliary Status Reg *****/
+#define PHY_B_AS_AN_C		(1<<15)	/* Bit 15:	AutoNeg complete */
+#define PHY_B_AS_AN_CA		(1<<14)	/* Bit 14:	AN Complete Ack */
+#define PHY_B_AS_ANACK_D	(1<<13)	/* Bit 13:	AN Ack Detect */
+#define PHY_B_AS_ANAB_D		(1<<12)	/* Bit 12:	AN Ability Detect */
+#define PHY_B_AS_NPW		(1<<11)	/* Bit 11:	AN Next Page Wait */
+#define PHY_B_AS_AN_RES_MSK	(7<<8)	/* Bit 10..8:	AN HDC */
+#define PHY_B_AS_PDF		(1<<7)	/* Bit  7:	Parallel Detect. Fault */
+#define PHY_B_AS_RF			(1<<6)	/* Bit  6:	Remote Fault */
+#define PHY_B_AS_ANP_R		(1<<5)	/* Bit  5:	AN Page Received */
+#define PHY_B_AS_LP_ANAB	(1<<4)	/* Bit  4:	LP AN Ability */
+#define PHY_B_AS_LP_NPAB	(1<<3)	/* Bit  3:	LP Next Page Ability */
+#define PHY_B_AS_LS			(1<<2)	/* Bit  2:	Link Status */
+#define PHY_B_AS_PRR		(1<<1)	/* Bit  1:	Pause Resolution-Rx */
+#define PHY_B_AS_PRT		(1<<0)	/* Bit  0:	Pause Resolution-Tx */
+
+#define PHY_B_AS_PAUSE_MSK	(PHY_B_AS_PRR | PHY_B_AS_PRT)
+
+/*****  PHY_BCOM_INT_STAT	16 bit r/o	Interrupt Status Reg *****/
+/*****  PHY_BCOM_INT_MASK	16 bit r/w	Interrupt Mask Reg *****/
+									/* Bit 15:	reserved */
+#define PHY_B_IS_PSE		(1<<14)	/* Bit 14:	Pair Swap Error */
+#define PHY_B_IS_MDXI_SC	(1<<13)	/* Bit 13:	MDIX Status Change */
+#define PHY_B_IS_HCT		(1<<12)	/* Bit 12:	counter above 32k */
+#define PHY_B_IS_LCT		(1<<11)	/* Bit 11:	counter above 128 */
+#define PHY_B_IS_AN_PR		(1<<10)	/* Bit 10:	Page Received */
+#define PHY_B_IS_NO_HDCL	(1<<9)	/* Bit  9:	No HCD Link */
+#define PHY_B_IS_NO_HDC		(1<<8)	/* Bit  8:	No HCD */
+#define PHY_B_IS_NEG_USHDC	(1<<7)	/* Bit  7:	Negotiated Unsup. HCD */
+#define PHY_B_IS_SCR_S_ER	(1<<6)	/* Bit  6:	Scrambler Sync Error */
+#define PHY_B_IS_RRS_CHANGE	(1<<5)	/* Bit  5:	Remote Rx Stat Change */
+#define PHY_B_IS_LRS_CHANGE	(1<<4)	/* Bit  4:	Local Rx Stat Change */
+#define PHY_B_IS_DUP_CHANGE	(1<<3)	/* Bit  3:	Duplex Mode Change */
+#define PHY_B_IS_LSP_CHANGE	(1<<2)	/* Bit  2:	Link Speed Change */
+#define PHY_B_IS_LST_CHANGE	(1<<1)	/* Bit  1:	Link Status Changed */
+#define PHY_B_IS_CRC_ER		(1<<0)	/* Bit  0:	CRC Error */
+
+#define PHY_B_DEF_MSK	(~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
+
+/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
+#define PHY_B_P_NO_PAUSE	(0<<10)	/* Bit 11..10:	no Pause Mode */
+#define PHY_B_P_SYM_MD		(1<<10)	/* Bit 11..10:	symmetric Pause Mode */
+#define PHY_B_P_ASYM_MD		(2<<10)	/* Bit 11..10:	asymmetric Pause Mode */
+#define PHY_B_P_BOTH_MD		(3<<10)	/* Bit 11..10:	both Pause Mode */
+
+/*
+ * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
+ */
+#define PHY_B_RES_1000FD	(7<<8)	/* Bit 10..8:	1000Base-T Full Dup. */
+#define PHY_B_RES_1000HD	(6<<8)	/* Bit 10..8:	1000Base-T Half Dup. */
+/* others: 100/10: invalid for us */
+
+/*
+ * Level One-Specific
+ */
+/*****  PHY_LONE_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
+#define PHY_L_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */
+#define PHY_L_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */
+#define PHY_L_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */
+#define PHY_L_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */
+#define PHY_L_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */
+#define PHY_L_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */
+									/* Bit  7..0:	reserved */
+
+/*****  PHY_LONE_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
+#define PHY_L_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */
+#define PHY_L_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */
+#define PHY_L_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */
+#define PHY_L_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status */
+#define PHY_L_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */
+#define PHY_L_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */
+									/* Bit  9..8:	reserved */
+#define PHY_B_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count */
+
+/*****  PHY_LONE_EXT_STAT	16 bit r/o	Extended Status Register *****/
+#define PHY_L_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */
+#define PHY_L_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
+#define PHY_L_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
+#define PHY_L_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
+									/* Bit 11..0:	reserved */
+
+/*****  PHY_LONE_PORT_CFG	16 bit r/w	Port Configuration Reg *****/
+#define PHY_L_PC_REP_MODE	(1<<15)	/* Bit 15:	Repeater Mode */
+									/* Bit 14:	reserved */
+#define PHY_L_PC_TX_DIS		(1<<13)	/* Bit 13:	Tx output Disabled */
+#define PHY_L_PC_BY_SCR		(1<<12)	/* Bit 12:	Bypass Scrambler */
+#define PHY_L_PC_BY_45		(1<<11)	/* Bit 11:	Bypass 4B5B-Decoder */
+#define PHY_L_PC_JAB_DIS	(1<<10)	/* Bit 10:	Jabber Disabled */
+#define PHY_L_PC_SQE		(1<<9)	/* Bit  9:	Enable Heartbeat */
+#define PHY_L_PC_TP_LOOP	(1<<8)	/* Bit  8:	TP Loopback */
+#define PHY_L_PC_SSS		(1<<7)	/* Bit  7:	Smart Speed Selection */
+#define PHY_L_PC_FIFO_SIZE	(1<<6)	/* Bit  6:	FIFO Size */
+#define PHY_L_PC_PRE_EN		(1<<5)	/* Bit  5:	Preamble Enable */
+#define PHY_L_PC_CIM		(1<<4)	/* Bit  4:	Carrier Integrity Mon */
+#define PHY_L_PC_10_SER		(1<<3)	/* Bit  3:	Use Serial Output */
+#define PHY_L_PC_ANISOL		(1<<2)	/* Bit  2:	Unisolate Port */
+#define PHY_L_PC_TEN_BIT	(1<<1)	/* Bit  1:	10bit iface mode on */
+#define PHY_L_PC_ALTCLOCK	(1<<0)	/* Bit  0: (ro)	ALTCLOCK Mode on */
+
+/*****  PHY_LONE_Q_STAT		16 bit r/o	Quick Status Reg *****/
+#define PHY_L_QS_D_RATE		(3<<14)	/* Bit 15..14:	Data Rate */
+#define PHY_L_QS_TX_STAT	(1<<13)	/* Bit 13:	Transmitting */
+#define PHY_L_QS_RX_STAT	(1<<12)	/* Bit 12:	Receiving */
+#define PHY_L_QS_COL_STAT	(1<<11)	/* Bit 11:	Collision */
+#define PHY_L_QS_L_STAT		(1<<10)	/* Bit 10:	Link is up */
+#define PHY_L_QS_DUP_MOD	(1<<9)	/* Bit  9:	Full/Half Duplex */
+#define PHY_L_QS_AN			(1<<8)	/* Bit  8:	AutoNeg is On */
+#define PHY_L_QS_AN_C		(1<<7)	/* Bit  7:	AN is Complete */
+#define PHY_L_QS_LLE		(7<<4)	/* Bit  6..4:	Line Length Estim. */
+#define PHY_L_QS_PAUSE		(1<<3)	/* Bit  3:	LP advertised Pause */
+#define PHY_L_QS_AS_PAUSE	(1<<2)	/* Bit  2:	LP adv. asym. Pause */
+#define PHY_L_QS_ISOLATE	(1<<1)	/* Bit  1:	CIM Isolated */
+#define PHY_L_QS_EVENT		(1<<0)	/* Bit  0:	Event has occurred */
+
+/*****  PHY_LONE_INT_ENAB	16 bit r/w	Interrupt Enable Reg *****/
+/*****  PHY_LONE_INT_STAT	16 bit r/o	Interrupt Status Reg *****/
+									/* Bit 15..14:	reserved */
+#define PHY_L_IS_AN_F		(1<<13)	/* Bit 13:	Auto-Negotiation fault */
+									/* Bit 12:	not described */
+#define PHY_L_IS_CROSS		(1<<11)	/* Bit 11:	Crossover used */
+#define PHY_L_IS_POL		(1<<10)	/* Bit 10:	Polarity correct. used */
+#define PHY_L_IS_SS			(1<<9)	/* Bit  9:	Smart Speed Downgrade */
+#define PHY_L_IS_CFULL		(1<<8)	/* Bit  8:	Counter Full */
+#define PHY_L_IS_AN_C		(1<<7)	/* Bit  7:	AutoNeg Complete */
+#define PHY_L_IS_SPEED		(1<<6)	/* Bit  6:	Speed Changed */
+#define PHY_L_IS_DUP		(1<<5)	/* Bit  5:	Duplex Changed */
+#define PHY_L_IS_LS			(1<<4)	/* Bit  4:	Link Status Changed */
+#define PHY_L_IS_ISOL		(1<<3)	/* Bit  3:	Isolate Occurred */
+#define PHY_L_IS_MDINT		(1<<2)	/* Bit  2: (ro)	STAT: MII Int Pending */
+#define PHY_L_IS_INTEN		(1<<1)	/* Bit  1:	ENAB: Enable IRQs */
+#define PHY_L_IS_FORCE		(1<<0)	/* Bit  0:	ENAB: Force Interrupt */
+
+/* int. mask */
+#define PHY_L_DEF_MSK		(PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
+
+/*****  PHY_LONE_LED_CFG	16 bit r/w	LED Configuration Reg *****/
+#define PHY_L_LC_LEDC		(3<<14)	/* Bit 15..14:	Col/Blink/On/Off */
+#define PHY_L_LC_LEDR		(3<<12)	/* Bit 13..12:	Rx/Blink/On/Off */
+#define PHY_L_LC_LEDT		(3<<10)	/* Bit 11..10:	Tx/Blink/On/Off */
+#define PHY_L_LC_LEDG		(3<<8)	/* Bit  9..8:	Giga/Blink/On/Off */
+#define PHY_L_LC_LEDS		(3<<6)	/* Bit  7..6:	10-100/Blink/On/Off */
+#define PHY_L_LC_LEDL		(3<<4)	/* Bit  5..4:	Link/Blink/On/Off */
+#define PHY_L_LC_LEDF		(3<<2)	/* Bit  3..2:	Duplex/Blink/On/Off */
+#define PHY_L_LC_PSTRECH	(1<<1)	/* Bit  1:	Strech LED Pulses */
+#define PHY_L_LC_FREQ		(1<<0)	/* Bit  0:	30/100 ms */
+
+/*****  PHY_LONE_PORT_CTRL	16 bit r/w	Port Control Reg *****/
+#define PHY_L_PC_TX_TCLK	(1<<15)	/* Bit 15:	Enable TX_TCLK */
+									/* Bit 14:	reserved */
+#define PHY_L_PC_ALT_NP		(1<<13)	/* Bit 14:	Alternate Next Page */
+#define PHY_L_PC_GMII_ALT	(1<<12)	/* Bit 13:	Alternate GMII driver */
+									/* Bit 11:	reserved */
+#define PHY_L_PC_TEN_CRS	(1<<10)	/* Bit 10:	Extend CRS*/
+									/* Bit  9..0:	not described */
+
+/*****  PHY_LONE_CIM		16 bit r/o	CIM Reg *****/
+#define PHY_L_CIM_ISOL		(0xff<<8)	/* Bit 15..8:	Isolate Count */
+#define PHY_L_CIM_FALSE_CAR	0xff		/* Bit  7..0:	False Carrier Count */
+
+/*
+ * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
+ */
+#define PHY_L_P_NO_PAUSE	(0<<10)	/* Bit 11..10:	no Pause Mode */
+#define PHY_L_P_SYM_MD		(1<<10)	/* Bit 11..10:	symmetric Pause Mode */
+#define PHY_L_P_ASYM_MD		(2<<10)	/* Bit 11..10:	asymmetric Pause Mode */
+#define PHY_L_P_BOTH_MD		(3<<10)	/* Bit 11..10:	both Pause Mode */
+
+/*
+ * National-Specific
+ */
+/*****  PHY_NAT_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
+#define PHY_N_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */
+#define PHY_N_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */
+#define PHY_N_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */
+#define PHY_N_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */
+#define PHY_N_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */
+#define PHY_N_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */
+#define PHY_N_1000C_APC		(1<<7)	/* Bit  7:	Asymmetric Pause Cap. */
+									/* Bit  6..0:	reserved */
+
+/*****  PHY_NAT_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
+#define PHY_N_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */
+#define PHY_N_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */
+#define PHY_N_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */
+#define PHY_N_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status*/
+#define PHY_N_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */
+#define PHY_N_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */
+#define PHY_N_1000C_LP_APC	(1<<9)	/* Bit  9:	LP Asym. Pause Cap. */
+									/* Bit  8:	reserved */
+#define PHY_N_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count */
+
+/*****  PHY_NAT_EXT_STAT	16 bit r/o	Extended Status Register *****/
+#define PHY_N_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */
+#define PHY_N_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
+#define PHY_N_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
+#define PHY_N_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
+									/* Bit 11..0:	reserved */
+
+/* todo: those are still missing */
+/*****  PHY_NAT_EXT_CTRL1	16 bit r/o	Extended Control Reg1 *****/
+/*****  PHY_NAT_Q_STAT1		16 bit r/o	Quick Status Reg1 *****/
+/*****  PHY_NAT_10B_OP		16 bit r/o	10Base-T Operations Reg *****/
+/*****  PHY_NAT_EXT_CTRL2	16 bit r/o	Extended Control Reg1 *****/
+/*****  PHY_NAT_Q_STAT2		16 bit r/o	Quick Status Reg2 *****/
+/*****  PHY_NAT_PHY_ADDR	16 bit r/o	PHY Address Register *****/
+
+/*
+ * Marvell-Specific
+ */
+/*****  PHY_MARV_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
+/*****  PHY_MARV_AUNE_LP	16 bit r/w	Link Partner Ability Reg *****/
+#define PHY_M_AN_NXT_PG		BIT_15S	/* Request Next Page */
+#define PHY_M_AN_ACK		BIT_14S	/* (ro)	Acknowledge Received */
+#define PHY_M_AN_RF			BIT_13S	/* Remote Fault */
+								/* Bit 12:	reserved */
+#define PHY_M_AN_ASP		BIT_11S	/* Asymmetric Pause */
+#define PHY_M_AN_PC			BIT_10S	/* MAC Pause implemented */
+#define PHY_M_AN_100_T4		BIT_9S	/* Not cap. 100Base-T4 (always 0) */
+#define PHY_M_AN_100_FD		BIT_8S	/* Advertise 100Base-TX Full Duplex */
+#define PHY_M_AN_100_HD		BIT_7S	/* Advertise 100Base-TX Half Duplex */
+#define PHY_M_AN_10_FD		BIT_6S	/* Advertise 10Base-TX Full Duplex */
+#define PHY_M_AN_10_HD		BIT_5S	/* Advertise 10Base-TX Half Duplex */
+#define PHY_M_AN_SEL_MSK	(0x1f<<4)	/* Bit  4.. 0: Selector Field Mask */
+
+#define PHY_M_AN_100_FD_HD	(PHY_M_AN_100_FD | PHY_M_AN_100_HD)
+#define PHY_M_AN_10_FD_HD	(PHY_M_AN_10_FD | PHY_M_AN_10_HD)
+
+/* special defines for FIBER (88E1040S only) */
+#define PHY_M_AN_ASP_X		BIT_8S	/* Asymmetric Pause */
+#define PHY_M_AN_PC_X		BIT_7S	/* MAC Pause implemented */
+#define PHY_M_AN_1000X_AHD	BIT_6S	/* Advertise 10000Base-X Half Duplex */
+#define PHY_M_AN_1000X_AFD	BIT_5S	/* Advertise 10000Base-X Full Duplex */
+
+/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
+#define PHY_M_P_NO_PAUSE_X	(0<<7)	/* Bit  8.. 7:	no Pause Mode */
+#define PHY_M_P_SYM_MD_X	(1<<7)	/* Bit  8.. 7:	symmetric Pause Mode */
+#define PHY_M_P_ASYM_MD_X	(2<<7)	/* Bit  8.. 7:	asymmetric Pause Mode */
+#define PHY_M_P_BOTH_MD_X	(3<<7)	/* Bit  8.. 7:	both Pause Mode */
+
+/*****  PHY_MARV_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
+#define PHY_M_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */
+#define PHY_M_1000C_MSE		BIT_12S	/* Manual Master/Slave Enable */
+#define PHY_M_1000C_MSC		BIT_11S	/* M/S Configuration (1=Master) */
+#define PHY_M_1000C_MPD		BIT_10S	/* Multi-Port Device */
+#define PHY_M_1000C_AFD		BIT_9S	/* Advertise Full Duplex */
+#define PHY_M_1000C_AHD		BIT_8S	/* Advertise Half Duplex */
+									/* Bit  7..0:	reserved */
+
+/*****  PHY_MARV_PHY_CTRL	16 bit r/w	PHY Specific Ctrl Reg *****/
+#define PHY_M_PC_TX_FFD_MSK	(3<<14)	/* Bit 15..14: Tx FIFO Depth Mask */
+#define PHY_M_PC_RX_FFD_MSK	(3<<12)	/* Bit 13..12: Rx FIFO Depth Mask */
+#define PHY_M_PC_ASS_CRS_TX	BIT_11S	/* Assert CRS on Transmit */
+#define PHY_M_PC_FL_GOOD	BIT_10S	/* Force Link Good */
+#define PHY_M_PC_EN_DET_MSK	(3<<8)	/* Bit  9.. 8: Energy Detect Mask */
+#define PHY_M_PC_ENA_EXT_D	BIT_7S	/* Enable Ext. Distance (10BT) */
+#define PHY_M_PC_MDIX_MSK	(3<<5)	/* Bit  6.. 5: MDI/MDIX Config. Mask */
+#define PHY_M_PC_DIS_125CLK	BIT_4S	/* Disable 125 CLK */
+#define PHY_M_PC_MAC_POW_UP	BIT_3S	/* MAC Power up */
+#define PHY_M_PC_SQE_T_ENA	BIT_2S	/* SQE Test Enabled */
+#define PHY_M_PC_POL_R_DIS	BIT_1S	/* Polarity Reversal Disabled */
+#define PHY_M_PC_DIS_JABBER	BIT_0S	/* Disable Jabber */
+
+#define PHY_M_PC_EN_DET			SHIFT8(2)	/* Energy Detect (Mode 1) */
+#define PHY_M_PC_EN_DET_PLUS	SHIFT8(3)	/* Energy Detect Plus (Mode 2) */
+
+#define PHY_M_PC_MDI_XMODE(x)	(SHIFT5(x) & PHY_M_PC_MDIX_MSK)
+
+#define PHY_M_PC_MAN_MDI	0		/* 00 = Manual MDI configuration */
+#define PHY_M_PC_MAN_MDIX	1		/* 01 = Manual MDIX configuration */
+#define PHY_M_PC_ENA_AUTO	3		/* 11 = Enable Automatic Crossover */
+
+/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
+#define PHY_M_PC_DIS_LINK_P	BIT_15S	/* Disable Link Pulses */
+#define PHY_M_PC_DSC_MSK	(7<<12)	/* Bit 14..12:	Downshift Counter */
+#define PHY_M_PC_DOWN_S_ENA	BIT_11S	/* Downshift Enable */
+									/* !!! Errata in spec. (1 = disable) */
+
+#define PHY_M_PC_DSC(x)			(SHIFT12(x) & PHY_M_PC_DSC_MSK)
+										/* 000=1x; 001=2x; 010=3x; 011=4x */
+										/* 100=5x; 101=6x; 110=7x; 111=8x */
+
+/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
+								/* Bit  4:	reserved */
+#define PHY_M_PC_COP_TX_DIS	BIT_3S	/* Copper Transmitter Disable */
+#define PHY_M_PC_POW_D_ENA	BIT_2S	/* Power Down Enable */
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PC_ENA_DTE_DT	BIT_15S	/* Enable Data Terminal Equ. (DTE) Detect */
+#define PHY_M_PC_ENA_ENE_DT	BIT_14S	/* Enable Energy Detect (sense & pulse) */
+#define PHY_M_PC_DIS_NLP_CK	BIT_13S	/* Disable Normal Link Puls (NLP) Check */
+#define PHY_M_PC_ENA_LIP_NP	BIT_12S	/* Enable Link Partner Next Page Reg. */
+#define PHY_M_PC_DIS_NLP_GN	BIT_11S	/* Disable Normal Link Puls Generation */
+
+#define PHY_M_PC_DIS_SCRAMB	BIT_9S	/* Disable Scrambler */
+#define PHY_M_PC_DIS_FEFI	BIT_8S	/* Disable Far End Fault Indic. (FEFI) */
+
+#define PHY_M_PC_SH_TP_SEL	BIT_6S	/* Shielded Twisted Pair Select */
+#define PHY_M_PC_RX_FD_MSK	(3<<2)	/* Bit  3.. 2: Rx FIFO Depth Mask */
+
+/*****  PHY_MARV_PHY_STAT	16 bit r/o	PHY Specific Status Reg *****/
+#define PHY_M_PS_SPEED_MSK	(3<<14)	/* Bit 15..14: Speed Mask */
+#define PHY_M_PS_SPEED_1000	BIT_15S	/*		10 = 1000 Mbps */
+#define PHY_M_PS_SPEED_100	BIT_14S	/*		01 =  100 Mbps */
+#define PHY_M_PS_SPEED_10	0		/*		00 =   10 Mbps */
+#define PHY_M_PS_FULL_DUP	BIT_13S	/* Full Duplex */
+#define PHY_M_PS_PAGE_REC	BIT_12S	/* Page Received */
+#define PHY_M_PS_SPDUP_RES	BIT_11S	/* Speed & Duplex Resolved */
+#define PHY_M_PS_LINK_UP	BIT_10S	/* Link Up */
+#define PHY_M_PS_CABLE_MSK	(7<<7)	/* Bit  9.. 7: Cable Length Mask */
+#define PHY_M_PS_MDI_X_STAT	BIT_6S	/* MDI Crossover Stat (1=MDIX) */
+#define PHY_M_PS_DOWNS_STAT	BIT_5S	/* Downshift Status (1=downshift) */
+#define PHY_M_PS_ENDET_STAT	BIT_4S	/* Energy Detect Status (1=sleep) */
+#define PHY_M_PS_TX_P_EN	BIT_3S	/* Tx Pause Enabled */
+#define PHY_M_PS_RX_P_EN	BIT_2S	/* Rx Pause Enabled */
+#define PHY_M_PS_POL_REV	BIT_1S	/* Polarity Reversed */
+#define PHY_M_PS_JABBER		BIT_0S	/* Jabber */
+
+#define PHY_M_PS_PAUSE_MSK	(PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PS_DTE_DETECT	BIT_15S	/* Data Terminal Equipment (DTE) Detected */
+#define PHY_M_PS_RES_SPEED	BIT_14S	/* Resolved Speed (1=100 Mbps, 0=10 Mbps */
+
+/*****  PHY_MARV_INT_MASK	16 bit r/w	Interrupt Mask Reg *****/
+/*****  PHY_MARV_INT_STAT	16 bit r/o	Interrupt Status Reg *****/
+#define PHY_M_IS_AN_ERROR	BIT_15S	/* Auto-Negotiation Error */
+#define PHY_M_IS_LSP_CHANGE	BIT_14S	/* Link Speed Changed */
+#define PHY_M_IS_DUP_CHANGE	BIT_13S	/* Duplex Mode Changed */
+#define PHY_M_IS_AN_PR		BIT_12S	/* Page Received */
+#define PHY_M_IS_AN_COMPL	BIT_11S	/* Auto-Negotiation Completed */
+#define PHY_M_IS_LST_CHANGE	BIT_10S	/* Link Status Changed */
+#define PHY_M_IS_SYMB_ERROR	BIT_9S	/* Symbol Error */
+#define PHY_M_IS_FALSE_CARR	BIT_8S	/* False Carrier */
+#define PHY_M_IS_FIFO_ERROR	BIT_7S	/* FIFO Overflow/Underrun Error */
+#define PHY_M_IS_MDI_CHANGE	BIT_6S	/* MDI Crossover Changed */
+#define PHY_M_IS_DOWNSH_DET	BIT_5S	/* Downshift Detected */
+#define PHY_M_IS_END_CHANGE	BIT_4S	/* Energy Detect Changed */
+								/* Bit   3:	reserved */
+#define PHY_M_IS_DTE_CHANGE	BIT_2S	/* DTE Power Det. Status Changed */
+									/* (88E1111 only) */
+#define PHY_M_IS_POL_CHANGE	BIT_1S	/* Polarity Changed */
+#define PHY_M_IS_JABBER		BIT_0S	/* Jabber */
+
+#define PHY_M_DEF_MSK		(PHY_M_IS_AN_ERROR | PHY_M_IS_LST_CHANGE | \
+							 PHY_M_IS_FIFO_ERROR | PHY_M_IS_END_CHANGE)
+
+/*****  PHY_MARV_EXT_CTRL	16 bit r/w	Ext. PHY Specific Ctrl *****/
+#define PHY_M_EC_ENA_BC_EXT	BIT_15S	/* Enable Block Carr. Ext. (88E1111 only) */
+#define PHY_M_EC_ENA_LIN_LB	BIT_14S	/* Enable Line Loopback (88E1111 only) */
+								/* Bit 13:	reserved */
+#define PHY_M_EC_DIS_LINK_P	BIT_12S	/* Disable Link Pulses (88E1111 only) */
+#define PHY_M_EC_M_DSC_MSK	(3<<10)	/* Bit 11..10:	Master Downshift Counter */
+									/* (88E1040 Rev.C0 only) */
+#define PHY_M_EC_S_DSC_MSK	(3<<8)	/* Bit  9.. 8:	Slave  Downshift Counter */
+									/* (88E1040 Rev.C0 only) */
+#define PHY_M_EC_DSC_MSK_2	(7<<9)	/* Bit 11.. 9:	Downshift Counter */
+									/* (88E1040 Rev.D0 and higher) */
+#define PHY_M_EC_DOWN_S_ENA	BIT_8S	/* Downshift Enable (88E1040 Rev.D0 and */
+									/* 88E1111 !!! Errata in spec. (1=dis.) */
+#define PHY_M_EC_RX_TIM_CT	BIT_7S	/* RGMII Rx Timing Control*/
+#define PHY_M_EC_MAC_S_MSK	(7<<4)	/* Bit  6.. 4:	Def. MAC interface speed */
+#define PHY_M_EC_FIB_AN_ENA	BIT_3S	/* Fiber Auto-Neg. Enable 88E1040S only) */
+#define PHY_M_EC_DTE_D_ENA	BIT_2S	/* DTE Detect Enable (88E1111 only) */
+#define PHY_M_EC_TX_TIM_CT	BIT_1S	/* RGMII Tx Timing Control */
+#define PHY_M_EC_TRANS_DIS	BIT_0S	/* Transmitter Disable (88E1111 only) */
+/* ---------------------------- */
+#define PHY_M_10B_TE_ENABLE	BIT_7S	/* 10Base-Te Enable (88E8079 and above) */
+
+#define PHY_M_EC_M_DSC(x)		(SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
+									/* 00=1x; 01=2x; 10=3x; 11=4x */
+#define PHY_M_EC_S_DSC(x)		(SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
+									/* 00=dis; 01=1x; 10=2x; 11=3x */
+#define PHY_M_EC_MAC_S(x)		(SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
+									/* 01X=0; 110=2.5; 111=25 (MHz) */
+
+#define PHY_M_EC_DSC_2(x)		(SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
+									/* 000=1x; 001=2x; 010=3x; 011=4x */
+									/* 100=5x; 101=6x; 110=7x; 111=8x */
+#define MAC_TX_CLK_0_MHZ	2
+#define MAC_TX_CLK_2_5_MHZ	6
+#define MAC_TX_CLK_25_MHZ	7
+
+/*****  PHY_MARV_LED_CTRL	16 bit r/w	LED Control Reg *****/
+#define PHY_M_LEDC_DIS_LED	BIT_15S	/* Disable LED */
+#define PHY_M_LEDC_PULS_MSK	(7<<12)	/* Bit 14..12: Pulse Stretch Mask */
+#define PHY_M_LEDC_F_INT	BIT_11S	/* Force Interrupt */
+#define PHY_M_LEDC_BL_R_MSK	(7<<8)	/* Bit 10.. 8: Blink Rate Mask */
+#define PHY_M_LEDC_DP_C_LSB	BIT_7S	/* Duplex Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_TX_C_LSB	BIT_6S	/* Tx Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_LK_C_MSK	(7<<3)	/* Bit  5.. 3: Link Control Mask */
+									/* (88E1111 only) */
+								/* Bit  7.. 5:	reserved (88E1040 only) */
+#define PHY_M_LEDC_LINK_MSK	(3<<3)	/* Bit  4.. 3: Link Control Mask */
+									/* (88E1040 only) */
+#define PHY_M_LEDC_DP_CTRL	BIT_2S	/* Duplex Control */
+#define PHY_M_LEDC_DP_C_MSB	BIT_2S	/* Duplex Control (MSB, 88E1111 only) */
+#define PHY_M_LEDC_RX_CTRL	BIT_1S	/* Rx Activity / Link */
+#define PHY_M_LEDC_TX_CTRL	BIT_0S	/* Tx Activity / Link */
+#define PHY_M_LEDC_TX_C_MSB	BIT_0S	/* Tx Control (MSB, 88E1111 only) */
+
+#define PHY_M_LED_PULS_DUR(x)	(SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
+
+#define PULS_NO_STR		0		/* no pulse stretching */
+#define PULS_21MS		1		/* 21 ms to 42 ms */
+#define PULS_42MS		2		/* 42 ms to 84 ms */
+#define PULS_84MS		3		/* 84 ms to 170 ms */
+#define PULS_170MS		4		/* 170 ms to 340 ms */
+#define PULS_340MS		5		/* 340 ms to 670 ms */
+#define PULS_670MS		6		/* 670 ms to 1.3 s */
+#define PULS_1300MS		7		/* 1.3 s to 2.7 s */
+
+#define PHY_M_LED_BLINK_RT(x)	(SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
+
+#define BLINK_42MS		0		/* 42 ms */
+#define BLINK_84MS		1		/* 84 ms */
+#define BLINK_170MS		2		/* 170 ms */
+#define BLINK_340MS		3		/* 340 ms */
+#define BLINK_670MS		4		/* 670 ms */
+								/* values 5 - 7: reserved */
+
+/*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/
+#define PHY_M_LED_MO_SGMII(x)	SHIFT14(x)	/* Bit 15..14:  SGMII AN Timer */
+										/* Bit 13..12:	reserved */
+#define PHY_M_LED_MO_DUP(x)		SHIFT10(x)	/* Bit 11..10:  Duplex */
+#define PHY_M_LED_MO_10(x)		SHIFT8(x)	/* Bit  9.. 8:  Link 10 */
+#define PHY_M_LED_MO_100(x)		SHIFT6(x)	/* Bit  7.. 6:  Link 100 */
+#define PHY_M_LED_MO_1000(x)	SHIFT4(x)	/* Bit  5.. 4:  Link 1000 */
+#define PHY_M_LED_MO_RX(x)		SHIFT2(x)	/* Bit  3.. 2:  Rx */
+#define PHY_M_LED_MO_TX(x)		SHIFT0(x)	/* Bit  1.. 0:  Tx */
+
+#define MO_LED_NORM			0
+#define MO_LED_BLINK		1
+#define MO_LED_OFF			2
+#define MO_LED_ON			3
+
+/*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
+								/* Bit 15.. 7:	reserved */
+#define PHY_M_EC2_FI_IMPED	BIT_6S	/* Fiber Input  Impedance */
+#define PHY_M_EC2_FO_IMPED	BIT_5S	/* Fiber Output Impedance */
+#define PHY_M_EC2_FO_M_CLK	BIT_4S	/* Fiber Mode Clock Enable */
+#define PHY_M_EC2_FO_BOOST	BIT_3S	/* Fiber Output Boost */
+#define PHY_M_EC2_FO_AM_MSK	7		/* Bit  2.. 0:	Fiber Output Amplitude */
+
+/*****  PHY_MARV_EXT_P_STAT 16 bit r/w	Ext. PHY Specific Status *****/
+#define PHY_M_FC_AUTO_SEL	BIT_15S	/* Fiber/Copper Auto Sel. Dis. */
+#define PHY_M_FC_AN_REG_ACC	BIT_14S	/* Fiber/Copper AN Reg. Access */
+#define PHY_M_FC_RESOLUTION	BIT_13S	/* Fiber/Copper Resolution */
+#define PHY_M_SER_IF_AN_BP	BIT_12S	/* Ser. IF AN Bypass Enable */
+#define PHY_M_SER_IF_BP_ST	BIT_11S	/* Ser. IF AN Bypass Status */
+#define PHY_M_IRQ_POLARITY	BIT_10S	/* IRQ polarity */
+#define PHY_M_DIS_AUT_MED	BIT_9S	/* Disable Aut. Medium Reg. Selection */
+									/* (88E1111 only) */
+								/* Bit  9.. 4: reserved (88E1040 only) */
+#define PHY_M_UNDOC1		BIT_7S	/* undocumented bit !! */
+#define PHY_M_DTE_POW_STAT	BIT_4S	/* DTE Power Status (88E1111 only) */
+#define PHY_M_MODE_MASK		0xf		/* Bit  3.. 0: copy of HWCFG MODE[3:0] */
+
+/*****  PHY_MARV_CABLE_DIAG	16 bit r/o	Cable Diagnostic Reg *****/
+#define PHY_M_CABD_ENA_TEST	BIT_15S		/* Enable Test (Page 0) */
+#define PHY_M_CABD_DIS_WAIT	BIT_15S		/* Disable Waiting Period (Page 1) */
+										/* (88E1111 only) */
+
+#define PHY_M_CABD_COMPLETE	BIT_14S		/* Test Completed (88E1149 only) */
+
+#define PHY_M_CABD_MODE_MSK	(3<<6)		/* Bit  7.. 6: Mode Mask */
+#define PHY_M_CABD_TEST_MODE(x)	(SHIFT6(x) & PHY_M_CABD_MODE_MSK)
+
+#define PHY_M_CABD_PWID_MSK	(3<<10)		/* Bit 11..10: Pulse Width Mask */
+#define PHY_M_CABD_PAMP_MSK	(3<<8)		/* Bit  9.. 8: Pulse Ampl. Mask */
+
+#define PHY_M_CABD_PULS_WIDT(x)	(SHIFT10(x) & PHY_M_CABD_PWID_MSK)
+#define PHY_M_CABD_PULS_AMPL(x)	(SHIFT8(x) & PHY_M_CABD_PAMP_MSK)
+
+#define PHY_M_CABD_STAT_MSK	(3<<13)		/* Bit 14..13: Status Mask */
+
+#define PHY_M_CABD_AMPL_MSK	(0x7f<<8)	/* Bit 14.. 8: Amplitude Mask */
+										/* (88E1149 only) */
+#define PHY_M_CABD_DIST_MSK	0xff		/* Bit  7.. 0: Distance Mask */
+
+/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
+#define CABD_STAT_NORMAL	0
+#define CABD_STAT_SHORT		1
+#define CABD_STAT_OPEN		2
+#define CABD_STAT_FAIL		3
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+/*****  PHY_MARV_FE_LED_PAR		16 bit r/w	LED Parallel Select Reg. *****/
+									/* Bit 15..12: reserved (used internally) */
+#define PHY_M_FELP_LED2_MSK	(0xf<<8)	/* Bit 11.. 8: LED2 Mask (LINK) */
+#define PHY_M_FELP_LED1_MSK	(0xf<<4)	/* Bit  7.. 4: LED1 Mask (ACT) */
+#define PHY_M_FELP_LED0_MSK	0xf			/* Bit  3.. 0: LED0 Mask (SPEED) */
+
+#define PHY_M_FELP_LED2_CTRL(x)	(SHIFT8(x) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x)	(SHIFT4(x) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x)	(SHIFT0(x) & PHY_M_FELP_LED0_MSK)
+
+#define LED_PAR_CTRL_COLX	0x00
+#define LED_PAR_CTRL_ERROR	0x01
+#define LED_PAR_CTRL_DUPLEX	0x02
+#define LED_PAR_CTRL_DP_COL	0x03
+#define LED_PAR_CTRL_SPEED	0x04
+#define LED_PAR_CTRL_LINK	0x05
+#define LED_PAR_CTRL_TX		0x06
+#define LED_PAR_CTRL_RX		0x07
+#define LED_PAR_CTRL_ACT	0x08
+#define LED_PAR_CTRL_LNK_RX	0x09
+#define LED_PAR_CTRL_LNK_AC	0x0a
+#define LED_PAR_CTRL_ACT_BL	0x0b
+#define LED_PAR_CTRL_TX_BL	0x0c
+#define LED_PAR_CTRL_RX_BL	0x0d
+#define LED_PAR_CTRL_COL_BL	0x0e
+#define LED_PAR_CTRL_INACT	0x0f
+
+/*****  PHY_MARV_FE_SPEC_2		16 bit r/w	Specific Control Reg. 2 *****/
+#define PHY_M_FESC_DIS_WAIT	BIT_2S	/* Disable TDR Waiting Period */
+#define PHY_M_FESC_ENA_MCLK	BIT_1S	/* Enable MAC Rx Clock in sleep mode */
+#define PHY_M_FESC_SEL_CL_A	BIT_0S	/* Select Class A driver (100B-TX) */
+
+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
+/*****  PHY_MARV_PHY_CTRL (page 1)		16 bit r/w	Fiber Specific Ctrl *****/
+#define PHY_M_FIB_FORCE_LNK	BIT_10S	/* Force Link Good */
+#define PHY_M_FIB_SIGD_POL	BIT_9S	/* SIGDET Polarity */
+#define PHY_M_FIB_TX_DIS	BIT_3S	/* Transmitter Disable */
+
+/*****  PHY_MARV_PHY_CTRL (page 2)		16 bit r/w	MAC Specific Ctrl *****/
+#define PHY_M_MAC_MD_MSK	(7<<7)	/* Bit  9.. 7: Mode Select Mask */
+#define PHY_M_MAC_GMIF_PUP	BIT_3S	/* GMII Power Up (88E1149 only) */
+
+#define PHY_M_MAC_MD_AUTO		3	/* Auto Copper/1000Base-X */
+#define PHY_M_MAC_MD_COPPER		5	/* Copper only */
+#define PHY_M_MAC_MD_1000BX		7	/* 1000Base-X only */
+#define PHY_M_MAC_MODE_SEL(x)	(SHIFT7(x) & PHY_M_MAC_MD_MSK)
+
+/*****  PHY_MARV_PHY_CTRL (page 3)		16 bit r/w	LED Control Reg. *****/
+#define PHY_M_LEDC_LOS_MSK	(0xf<<12)	/* Bit 15..12: LOS LED Ctrl. Mask */
+#define PHY_M_LEDC_INIT_MSK	(0xf<<8)	/* Bit 11.. 8: INIT LED Ctrl. Mask */
+#define PHY_M_LEDC_STA1_MSK	(0xf<<4)	/* Bit  7.. 4: STAT1 LED Ctrl. Mask */
+#define PHY_M_LEDC_STA0_MSK	0xf			/* Bit  3.. 0: STAT0 LED Ctrl. Mask */
+
+#define PHY_M_LEDC_LOS_CTRL(x)	(SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
+#define PHY_M_LEDC_INIT_CTRL(x)	(SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
+#define PHY_M_LEDC_STA1_CTRL(x)	(SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
+#define PHY_M_LEDC_STA0_CTRL(x)	(SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
+
+#define LC_LNK_ON_ACT_BL	0x01
+#define LC_DUPLEX_ON		0x06
+#define LC_LINK_ON			0x07
+#define LC_FORCE_OFF		0x08
+#define LC_FORCE_ON			0x09
+#define LC_FORCE_HI_Z		0x0a
+#define LC_FORCE_BLINK		0x0b
+
+/*****  PHY_MARV_PHY_STAT (page 3)		16 bit r/w	Polarity Control Reg. *****/
+#define PHY_M_POLC_LS1M_MSK	(0xf<<12)	/* Bit 15..12: LOS,STAT1 Mix % Mask */
+#define PHY_M_POLC_IS0M_MSK	(0xf<<8)	/* Bit 11.. 8: INIT,STAT0 Mix % Mask */
+#define PHY_M_POLC_LOS_MSK	(0x3<<6)	/* Bit  7.. 6: LOS Pol. Ctrl. Mask */
+#define PHY_M_POLC_INIT_MSK	(0x3<<4)	/* Bit  5.. 4: INIT Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA1_MSK	(0x3<<2)	/* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA0_MSK	0x3			/* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
+
+#define PHY_M_POLC_LS1_P_MIX(x)	(SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
+#define PHY_M_POLC_IS0_P_MIX(x)	(SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
+#define PHY_M_POLC_LOS_CTRL(x)	(SHIFT6(x) & PHY_M_POLC_LOS_MSK)
+#define PHY_M_POLC_INIT_CTRL(x)	(SHIFT4(x) & PHY_M_POLC_INIT_MSK)
+#define PHY_M_POLC_STA1_CTRL(x)	(SHIFT2(x) & PHY_M_POLC_STA1_MSK)
+#define PHY_M_POLC_STA0_CTRL(x)	(SHIFT0(x) & PHY_M_POLC_STA0_MSK)
+
+/*
+ * GMAC registers
+ *
+ * The GMAC registers are 16 or 32 bits wide.
+ * The GMACs host processor interface is 16 bits wide,
+ * therefore ALL registers will be addressed with 16 bit accesses.
+ *
+ * The following macros are provided to access the GMAC registers
+ * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(),
+ * GM_INHASH(), and GM_OUTHASH().
+ * The macros are defined in SkGeHw.h.
+ *
+ * Note:	NA reg	= Network Address e.g DA, SA etc.
+ *
+ */
+
+/* Port Registers */
+#define GM_GP_STAT		0x0000		/* 16 bit r/o	General Purpose Status */
+#define GM_GP_CTRL		0x0004		/* 16 bit r/w	General Purpose Control */
+#define GM_TX_CTRL		0x0008		/* 16 bit r/w	Transmit Control Reg. */
+#define GM_RX_CTRL		0x000c		/* 16 bit r/w	Receive Control Reg. */
+#define GM_TX_FLOW_CTRL	0x0010		/* 16 bit r/w	Transmit Flow-Control */
+#define GM_TX_PARAM		0x0014		/* 16 bit r/w	Transmit Parameter Reg. */
+#define GM_SERIAL_MODE	0x0018		/* 16 bit r/w	Serial Mode Register */
+
+/* Source Address Registers */
+#define GM_SRC_ADDR_1L	0x001c		/* 16 bit r/w	Source Address 1 (low) */
+#define GM_SRC_ADDR_1M	0x0020		/* 16 bit r/w	Source Address 1 (middle) */
+#define GM_SRC_ADDR_1H	0x0024		/* 16 bit r/w	Source Address 1 (high) */
+#define GM_SRC_ADDR_2L	0x0028		/* 16 bit r/w	Source Address 2 (low) */
+#define GM_SRC_ADDR_2M	0x002c		/* 16 bit r/w	Source Address 2 (middle) */
+#define GM_SRC_ADDR_2H	0x0030		/* 16 bit r/w	Source Address 2 (high) */
+
+/* Multicast Address Hash Registers */
+#define GM_MC_ADDR_H1	0x0034		/* 16 bit r/w	Multicast Address Hash 1 */
+#define GM_MC_ADDR_H2	0x0038		/* 16 bit r/w	Multicast Address Hash 2 */
+#define GM_MC_ADDR_H3	0x003c		/* 16 bit r/w	Multicast Address Hash 3 */
+#define GM_MC_ADDR_H4	0x0040		/* 16 bit r/w	Multicast Address Hash 4 */
+
+/* Interrupt Source Registers */
+#define GM_TX_IRQ_SRC	0x0044		/* 16 bit r/o	Tx Overflow IRQ Source */
+#define GM_RX_IRQ_SRC	0x0048		/* 16 bit r/o	Rx Overflow IRQ Source */
+#define GM_TR_IRQ_SRC	0x004c		/* 16 bit r/o	Tx/Rx Over. IRQ Source */
+
+/* Interrupt Mask Registers */
+#define GM_TX_IRQ_MSK	0x0050		/* 16 bit r/w	Tx Overflow IRQ Mask */
+#define GM_RX_IRQ_MSK	0x0054		/* 16 bit r/w	Rx Overflow IRQ Mask */
+#define GM_TR_IRQ_MSK	0x0058		/* 16 bit r/w	Tx/Rx Over. IRQ Mask */
+#define GM_FC_TIMEOUT	0x005c		/* 16 bit r/w	Flow-Control Timeout */
+
+/* Serial Management Interface (SMI) Registers */
+#define GM_SMI_CTRL		0x0080		/* 16 bit r/w	SMI Control Register */
+#define GM_SMI_DATA		0x0084		/* 16 bit r/w	SMI Data Register */
+#define GM_PHY_ADDR		0x0088		/* 16 bit r/w	GPHY Address Register */
+
+/* MIB Counters */
+#define GM_MIB_CNT_BASE	0x0100		/* Base Address of MIB Counters */
+#define GM_MIB_CNT_SIZE	44			/* Number of MIB Counters */
+
+/*
+ * MIB Counters base address definitions (low word) -
+ * use offset 4 for access to high word	(32 bit r/o)
+ */
+#define GM_RXF_UC_OK \
+			(GM_MIB_CNT_BASE + 0)	/* Unicast Frames Received OK */
+#define GM_RXF_BC_OK \
+			(GM_MIB_CNT_BASE + 8)	/* Broadcast Frames Received OK */
+#define GM_RXF_MPAUSE \
+			(GM_MIB_CNT_BASE + 16)	/* Pause MAC Ctrl Frames Received */
+#define GM_RXF_MC_OK \
+			(GM_MIB_CNT_BASE + 24)	/* Multicast Frames Received OK */
+#define GM_RXF_FCS_ERR \
+			(GM_MIB_CNT_BASE + 32)	/* Rx Frame Check Seq. Error */
+	/* GM_MIB_CNT_BASE + 40:	reserved */
+#define GM_RXO_OK_LO \
+			(GM_MIB_CNT_BASE + 48)	/* Octets Received OK Low */
+#define GM_RXO_OK_HI \
+			(GM_MIB_CNT_BASE + 56)	/* Octets Received OK High */
+#define GM_RXO_ERR_LO \
+			(GM_MIB_CNT_BASE + 64)	/* Octets Received Invalid Low */
+#define GM_RXO_ERR_HI \
+			(GM_MIB_CNT_BASE + 72)	/* Octets Received Invalid High */
+#define GM_RXF_SHT \
+			(GM_MIB_CNT_BASE + 80)	/* Frames < 64 Byte Received OK */
+#define GM_RXE_FRAG \
+			(GM_MIB_CNT_BASE + 88)	/* Frames < 64 Byte Received with FCS Err */
+#define GM_RXF_64B \
+			(GM_MIB_CNT_BASE + 96)	/* 64 Byte Rx Frame */
+#define GM_RXF_127B \
+			(GM_MIB_CNT_BASE + 104)	/* 65-127 Byte Rx Frame */
+#define GM_RXF_255B \
+			(GM_MIB_CNT_BASE + 112)	/* 128-255 Byte Rx Frame */
+#define GM_RXF_511B \
+			(GM_MIB_CNT_BASE + 120)	/* 256-511 Byte Rx Frame */
+#define GM_RXF_1023B \
+			(GM_MIB_CNT_BASE + 128)	/* 512-1023 Byte Rx Frame */
+#define GM_RXF_1518B \
+			(GM_MIB_CNT_BASE + 136)	/* 1024-1518 Byte Rx Frame */
+#define GM_RXF_MAX_SZ \
+			(GM_MIB_CNT_BASE + 144)	/* 1519-MaxSize Byte Rx Frame */
+#define GM_RXF_LNG_ERR \
+			(GM_MIB_CNT_BASE + 152)	/* Rx Frame too Long Error */
+#define GM_RXF_JAB_PKT \
+			(GM_MIB_CNT_BASE + 160)	/* Rx Jabber Packet Frame */
+	/* GM_MIB_CNT_BASE + 168:	reserved */
+#define GM_RXE_FIFO_OV \
+			(GM_MIB_CNT_BASE + 176)	/* Rx FIFO overflow Event */
+	/* GM_MIB_CNT_BASE + 184:	reserved */
+#define GM_TXF_UC_OK \
+			(GM_MIB_CNT_BASE + 192)	/* Unicast Frames Xmitted OK */
+#define GM_TXF_BC_OK \
+			(GM_MIB_CNT_BASE + 200)	/* Broadcast Frames Xmitted OK */
+#define GM_TXF_MPAUSE \
+			(GM_MIB_CNT_BASE + 208)	/* Pause MAC Ctrl Frames Xmitted */
+#define GM_TXF_MC_OK \
+			(GM_MIB_CNT_BASE + 216)	/* Multicast Frames Xmitted OK */
+#define GM_TXO_OK_LO \
+			(GM_MIB_CNT_BASE + 224)	/* Octets Transmitted OK Low */
+#define GM_TXO_OK_HI \
+			(GM_MIB_CNT_BASE + 232)	/* Octets Transmitted OK High */
+#define GM_TXF_64B \
+			(GM_MIB_CNT_BASE + 240)	/* 64 Byte Tx Frame */
+#define GM_TXF_127B \
+			(GM_MIB_CNT_BASE + 248)	/* 65-127 Byte Tx Frame */
+#define GM_TXF_255B \
+			(GM_MIB_CNT_BASE + 256)	/* 128-255 Byte Tx Frame */
+#define GM_TXF_511B \
+			(GM_MIB_CNT_BASE + 264)	/* 256-511 Byte Tx Frame */
+#define GM_TXF_1023B \
+			(GM_MIB_CNT_BASE + 272)	/* 512-1023 Byte Tx Frame */
+#define GM_TXF_1518B \
+			(GM_MIB_CNT_BASE + 280)	/* 1024-1518 Byte Tx Frame */
+#define GM_TXF_MAX_SZ \
+			(GM_MIB_CNT_BASE + 288)	/* 1519-MaxSize Byte Tx Frame */
+	/* GM_MIB_CNT_BASE + 296:	reserved */
+#define GM_TXF_COL \
+			(GM_MIB_CNT_BASE + 304)	/* Tx Collision */
+#define GM_TXF_LAT_COL \
+			(GM_MIB_CNT_BASE + 312)	/* Tx Late Collision */
+#define GM_TXF_ABO_COL \
+			(GM_MIB_CNT_BASE + 320)	/* Tx aborted due to Exces. Col. */
+#define GM_TXF_MUL_COL \
+			(GM_MIB_CNT_BASE + 328)	/* Tx Multiple Collision */
+#define GM_TXF_SNG_COL \
+			(GM_MIB_CNT_BASE + 336)	/* Tx Single Collision */
+#define GM_TXE_FIFO_UR \
+			(GM_MIB_CNT_BASE + 344)	/* Tx FIFO Underrun Event */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * GMAC Bit Definitions
+ *
+ * If the bit access behaviour differs from the register access behaviour
+ * (r/w, r/o) this is documented after the bit number.
+ * The following bit access behaviours are used:
+ *	(sc)	self clearing
+ *	(r/o)	read only
+ */
+
+/*	GM_GP_STAT	16 bit r/o	General Purpose Status Register */
+#define GM_GPSR_SPEED		BIT_15S	/* Port Speed (1 = 100 Mbps) */
+#define GM_GPSR_DUPLEX		BIT_14S	/* Duplex Mode (1 = Full) */
+#define GM_GPSR_FC_TX_DIS	BIT_13S	/* Tx Flow-Control Mode Disabled */
+#define GM_GPSR_LINK_UP		BIT_12S	/* Link Up Status */
+#define GM_GPSR_PAUSE		BIT_11S	/* Pause State */
+#define GM_GPSR_TX_ACTIVE	BIT_10S	/* Tx in Progress */
+#define GM_GPSR_EXC_COL		BIT_9S	/* Excessive Collisions Occurred */
+#define GM_GPSR_LAT_COL		BIT_8S	/* Late Collisions Occurred */
+								/* Bit   7.. 6:	reserved */
+#define GM_GPSR_PHY_ST_CH	BIT_5S	/* PHY Status Change */
+#define GM_GPSR_GIG_SPEED	BIT_4S	/* Gigabit Speed (1 = 1000 Mbps) */
+#define GM_GPSR_PART_MODE	BIT_3S	/* Partition mode */
+#define GM_GPSR_FC_RX_DIS	BIT_2S	/* Rx Flow-Control Mode Disabled */
+								/* Bit   2.. 0:	reserved */
+
+/*	GM_GP_CTRL	16 bit r/w	General Purpose Control Register */
+#define GM_GPCR_RMII_PH_ENA	BIT_15S	/* Enable RMII for PHY (Yukon-FE only) */
+#define GM_GPCR_RMII_LB_ENA	BIT_14S	/* Enable RMII Loopback (Yukon-FE only) */
+#define GM_GPCR_FC_TX_DIS	BIT_13S	/* Disable Tx Flow-Control Mode */
+#define GM_GPCR_TX_ENA		BIT_12S	/* Enable Transmit */
+#define GM_GPCR_RX_ENA		BIT_11S	/* Enable Receive */
+								/* Bit 10:	reserved */
+#define GM_GPCR_LOOP_ENA	BIT_9S	/* Enable MAC Loopback Mode */
+#define GM_GPCR_PART_ENA	BIT_8S	/* Enable Partition Mode */
+#define GM_GPCR_GIGS_ENA	BIT_7S	/* Gigabit Speed (1000 Mbps) */
+#define GM_GPCR_FL_PASS		BIT_6S	/* Force Link Pass */
+#define GM_GPCR_DUP_FULL	BIT_5S	/* Full Duplex Mode */
+#define GM_GPCR_FC_RX_DIS	BIT_4S	/* Disable Rx Flow-Control Mode */
+#define GM_GPCR_SPEED_100	BIT_3S	/* Port Speed 100 Mbps */
+#define GM_GPCR_AU_DUP_DIS	BIT_2S	/* Disable Auto-Update Duplex */
+#define GM_GPCR_AU_FCT_DIS	BIT_1S	/* Disable Auto-Update Flow-C. */
+#define GM_GPCR_AU_SPD_DIS	BIT_0S	/* Disable Auto-Update Speed */
+
+#define GM_GPCR_SPEED_1000	(GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
+#define GM_GPCR_AU_ALL_DIS	(GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
+							 GM_GPCR_AU_SPD_DIS)
+
+/*	GM_TX_CTRL				16 bit r/w	Transmit Control Register */
+#define GM_TXCR_FORCE_JAM	BIT_15S	/* Force Jam / Flow-Control */
+#define GM_TXCR_CRC_DIS		BIT_14S	/* Disable insertion of CRC */
+#define GM_TXCR_PAD_DIS		BIT_13S	/* Disable padding of packets */
+#define GM_TXCR_COL_THR_MSK	(7<<10)	/* Bit 12..10: Collision Threshold Mask */
+								/* Bit   9.. 8:	reserved */
+#define GM_TXCR_PAD_PAT_MSK	0xff	/* Bit  7.. 0: Padding Pattern Mask */
+									/* (Yukon-2 only) */
+
+#define TX_COL_THR(x)		(SHIFT10(x) & GM_TXCR_COL_THR_MSK)
+
+#define TX_COL_DEF			0x04
+
+/*	GM_RX_CTRL				16 bit r/w	Receive Control Register */
+#define GM_RXCR_UCF_ENA		BIT_15S	/* Enable Unicast filtering */
+#define GM_RXCR_MCF_ENA		BIT_14S	/* Enable Multicast filtering */
+#define GM_RXCR_CRC_DIS		BIT_13S	/* Remove 4-byte CRC */
+#define GM_RXCR_PASS_FC		BIT_12S	/* Pass FC packets to FIFO (Yukon-1 only) */
+								/* Bit  11.. 0:	reserved */
+
+/*	GM_TX_PARAM				16 bit r/w	Transmit Parameter Register */
+#define GM_TXPA_JAMLEN_MSK	(3<<14)		/* Bit 15..14: Jam Length Mask */
+#define GM_TXPA_JAMIPG_MSK	(0x1f<<9)	/* Bit 13.. 9: Jam IPG Mask */
+#define GM_TXPA_JAMDAT_MSK	(0x1f<<4)	/* Bit  8.. 4: IPG Jam to Data Mask */
+#define GM_TXPA_BO_LIM_MSK	0x0f		/* Bit  3.. 0: Backoff Limit Mask */
+										/* (Yukon-2 only) */
+
+#define TX_JAM_LEN_VAL(x)	(SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
+#define TX_JAM_IPG_VAL(x)	(SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
+#define TX_IPG_JAM_DATA(x)	(SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
+#define TX_BACK_OFF_LIM(x)	((x) & GM_TXPA_BO_LIM_MSK)
+
+#define TX_JAM_LEN_DEF		0x03
+#define TX_JAM_IPG_DEF		0x0b
+#define TX_IPG_JAM_DEF		0x1c
+#define TX_BOF_LIM_DEF		0x04
+
+/*	GM_SERIAL_MODE			16 bit r/w	Serial Mode Register */
+#define GM_SMOD_DATABL_MSK	(0x1f<<11)	/* Bit 15..11:	Data Blinder */
+										/* r/o on Yukon, r/w on Yukon-EC */
+#define GM_SMOD_LIMIT_4		BIT_10S	/* 4 consecutive Tx trials */
+#define GM_SMOD_VLAN_ENA	BIT_9S	/* Enable VLAN  (Max. Frame Len) */
+#define GM_SMOD_JUMBO_ENA	BIT_8S	/* Enable Jumbo (Max. Frame Len) */
+								/* Bit   7:	reserved */
+#define GM_NEW_FLOW_CTRL	BIT_6S	/* Enable New Flow-Control */
+								/* Bit   5:	reserved */
+#define GM_SMOD_IPG_MSK		0x1f	/* Bit  4.. 0:	Inter-Packet Gap (IPG) */
+
+#define DATA_BLIND_VAL(x)	(SHIFT11(x) & GM_SMOD_DATABL_MSK)
+#define IPG_DATA_VAL(x)		((x) & GM_SMOD_IPG_MSK)
+
+#define DATA_BLIND_DEF		0x04
+#define IPG_DATA_DEF_1000	0x1e
+#define IPG_DATA_DEF_10_100 0x18
+
+/*	GM_SMI_CTRL				16 bit r/w	SMI Control Register */
+#define GM_SMI_CT_PHY_A_MSK	(0x1f<<11)	/* Bit 15..11:	PHY Device Address */
+#define GM_SMI_CT_REG_A_MSK	(0x1f<<6)	/* Bit 10.. 6:	PHY Register Address */
+#define GM_SMI_CT_OP_RD		BIT_5S	/* OpCode Read (0=Write) */
+#define GM_SMI_CT_RD_VAL	BIT_4S	/* Read Valid (Read completed) */
+#define GM_SMI_CT_BUSY		BIT_3S	/* Busy (Operation in progress) */
+								/* Bit   2.. 0:	reserved */
+
+#define GM_SMI_CT_PHY_AD(x)	(SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
+#define GM_SMI_CT_REG_AD(x)	(SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
+
+/*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */
+								/* Bit  15.. 6:	reserved */
+#define GM_PAR_MIB_CLR		BIT_5S	/* Set MIB Clear Counter Mode */
+#define GM_PAR_MIB_TST		BIT_4S	/* MIB Load Counter (Test Mode) */
+								/* Bit   3.. 0:	reserved */
+
+/* Receive Frame Status Encoding */
+#define GMR_FS_LKUP_BIT2	BIT_31	/* MACSec Lookup entry b2 (Yukon-Ext only)*/
+#define GMR_FS_LEN_MSK	(0x7fffUL<<16)	/* Bit 30..16:	Rx Frame Length */
+#define GMR_FS_LKUP_BIT1	BIT_15	/* MACSec Lookup entry b1 (Yukon-Ext only)*/
+#define GMR_FS_LKUP_BIT0	BIT_14	/* MACSec Lookup entry b0 (Yukon-Ext only)*/
+#define GMR_FS_VLAN			BIT_13	/* VLAN Packet */
+#define GMR_FS_JABBER		BIT_12	/* Jabber Packet */
+#define GMR_FS_UN_SIZE		BIT_11	/* Undersize Packet */
+#define GMR_FS_MC			BIT_10	/* Multicast Packet */
+#define GMR_FS_BC			BIT_9	/* Broadcast Packet */
+#define GMR_FS_RX_OK		BIT_8	/* Receive OK (Good Packet) */
+#define GMR_FS_GOOD_FC		BIT_7	/* Good Flow-Control Packet */
+#define GMR_FS_BAD_FC		BIT_6	/* Bad  Flow-Control Packet */
+#define GMR_FS_MII_ERR		BIT_5	/* MII Error */
+#define GMR_FS_LONG_ERR		BIT_4	/* Too Long Packet */
+#define GMR_FS_FRAGMENT		BIT_3	/* Fragment */
+#define GMR_FS_LKUP_HIT		BIT_2	/* MACSec Lookup tab hit (Yukon-Ext only) */
+#define GMR_FS_CRC_ERR		BIT_1	/* CRC Error */
+#define GMR_FS_RX_FF_OV		BIT_0	/* Rx FIFO Overflow */
+
+/* Yukon-Ext only */
+#define GMR_FS_MACSEC_BITS	( \
+			GMR_FS_LKUP_BIT2 |\
+			GMR_FS_LKUP_BIT1 |\
+			GMR_FS_LKUP_BIT0 |\
+			GMR_FS_LKUP_HIT)
+
+#define GMR_FS_LEN_SHIFT	16
+
+/*
+ * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
+ */
+#ifdef SK_DIAG
+#define GMR_FS_ANY_ERR		( \
+			GMR_FS_RX_FF_OV | \
+			GMR_FS_CRC_ERR | \
+			GMR_FS_FRAGMENT | \
+			GMR_FS_MII_ERR | \
+			GMR_FS_BAD_FC | \
+			GMR_FS_GOOD_FC | \
+			GMR_FS_JABBER)
+#else
+#define GMR_FS_ANY_ERR		( \
+			GMR_FS_RX_FF_OV | \
+			GMR_FS_CRC_ERR | \
+			GMR_FS_FRAGMENT | \
+			GMR_FS_LONG_ERR | \
+			GMR_FS_MII_ERR | \
+			GMR_FS_BAD_FC | \
+			GMR_FS_GOOD_FC | \
+			GMR_FS_UN_SIZE | \
+			GMR_FS_JABBER)
+#endif
+
+/* Rx GMAC FIFO Flush Mask (default) */
+#define RX_FF_FL_DEF_MSK	GMR_FS_ANY_ERR
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Marvell-PTP Registers, indirect addressed over AVB Command Register
+ */
+#define PTP_GLOBAL_CONF_0		0x00	/* 16 bit r/w	Global Configuration */
+#define PTP_GLOBAL_CONF_1		0x01	/* 16 bit r/w	Global Configuration */
+#define PTP_GLOBAL_CONF_2		0x02	/* 16 bit r/w	Global Configuration */
+#define PTP_GLOBAL_CONF_3		0x03	/* 16 bit r/w	Global Configuration */
+
+#define PTP_GLOBAL_STATUS		0x08	/* 16 bit r/w	Global Status */
+
+#define PTP_PORT_CONFIG_0		0x00	/* 16 bit r/w	PTP Port Config 0 */
+#define PTP_PORT_CONFIG_1		0x01	/* 16 bit r/w	PTP Port Config 1 */
+#define PTP_PORT_CONFIG_2		0x02	/* 16 bit r/w	PTP Port Config 2 */
+
+#define PTP_PORT_STATUS_0		0x08	/* 16 bit r/w	PTP Port Status 0 */
+
+/*****  PTP_PORT_CONFIG_0	16 bit r/w	PTP Port Config 0 *****/
+#define PTP_TRANS_SPEC_MSK	(0xf<<12)	/* Bit 15..12: Transport Spec. Mask */
+#define PTP_DIS_T_SPEC_CHK	BIT_11S		/* Disable Transport Specific Check */
+									/* Bit 10.. 2:	reserved */
+#define PTP_DIS_TS_OVERWR	BIT_1S		/* Disable Time Stamp Counter Overwr. */
+#define PTP_DIS_TS_LOGIC	BIT_0S		/* Disable Precise Time Stamp Logic */
+
+/*****  PTP_PORT_CONFIG_1	16 bit r/w	PTP Port Config 1 *****/
+									/* Bit 15..14:	reserved */
+#define PTP_IP_JUMP_MSK		(0x3f<<8)	/* Bit 13.. 8: IP Jump Mask */
+										/* Bit  7.. 5:	reserved */
+#define PTP_ETHTYP_JUMP_MSK	0x1f		/* Bit  4.. 0: EtherType Jump Mask */
+
+/*****  PTP_PORT_CONFIG_2	16 bit r/w	PTP Port Config 2 *****/
+									/* Bit 15.. 2:	reserved */
+#define PTP_DEP_INT_ENA		BIT_1S		/* Port Depart. Interrupt enable */
+#define PTP_ARR_INT_ENA		BIT_0S		/* Port Arrival Interrupt enable */
+
+/*****  PTP_PORT_STATUS_0	16 bit r/w	PTP Port Status 0 *****/
+									/* Bit 15.. 3:	reserved */
+#define PTP_ARR_INT_STS_MSK	(0x3<<1)	/* Bit  2.. 1: Arrival Status Mask */
+#define PTP_ARR_TIME_VALID	BIT_0S		/* Port Arrival Time Valid */
+
+/*****  PTP_PORT_STATUS_0+0x10	16 bit r/w	PTP Port Status 0 *****/
+									/* Bit 15.. 3:	reserved */
+#define PTP_DEP_INT_STS_MSK	(0x3<<1)	/* Bit  2.. 1: Departure Status Mask */
+#define PTP_DEP_TIME_VALID	BIT_0S		/* Port Departure Time Valid */
+
+
+/*
+ * MAC Security macros (Yukon-Ext only)
+ */
+/* EAPOL frame: hit + tab entry == 0 */
+#define GMR_IS_EAPOL_FRAME(status)	(\
+	((status) & GMR_FS_MACSEC_BITS) == GMR_FS_LKUP_HIT)
+
+/* Uncontrolled port frame: no table hit */
+#define GMR_IS_UNCON_FRAME(status)	(\
+	((status) & GMR_FS_LKUP_HIT) == 0)
+
+/* Controlled port: check key number: key = {1, 2}, key = tab entry */
+#define GMR_IS_SECKEY_MATCH(status, key) (\
+	(status) & GMR_FS_MACSEC_BITS) == (GMR_FS_LKUP_HIT | ((key) << 14)))
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INC_XMAC_H */
+
diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile
--- linux/drivers/net/sk98lin/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/Makefile	2011-07-07 21:13:31.000000000 -0700
@@ -0,0 +1,130 @@
+#******************************************************************************
+#
+# Project:      GEnesis, PCI Gigabit Ethernet Adapter
+# Version:      $Revision: 1.5 $
+# Date:         $Date: 2009/07/27 12:43:38 $
+# Purpose:      The main driver source module
+#
+#******************************************************************************
+
+#******************************************************************************
+#
+#	(C)Copyright 1998-2002 SysKonnect GmbH.
+#	(C)Copyright 2002-2007 Marvell.
+#
+#	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet 
+#      Server Adapters.
+#
+#	Address all question to: msgg-linux@marvell.com
+#
+#      LICENSE:
+#      (C)Copyright Marvell.
+#      
+#      This program is free software; you can redistribute it and/or modify
+#      it under the terms of the GNU General Public License as published by
+#      the Free Software Foundation; either version 2 of the License, or
+#      (at your option) any later version.
+#      
+#      The information in this file is provided "AS IS" without warranty.
+#      /LICENSE
+#
+#******************************************************************************
+
+
+# Include the SDK support
+# SDKPARAM += -DMV_INCLUDE_SDK_SUPPORT
+
+ifdef SDKPARAM
+	SDK_OPS += \
+		fwptrn.o	\
+		skspi.o		\
+		skpflash.o	\
+		skgeasfapi.o	\
+		skgespilole.o	\
+		fwfunctions.o	\
+		fwapp.o		\
+		fwhci.o		\
+		fwimage.o	\
+		fwmain.o	\
+		fwos.o
+else
+	SDK_OPS +=
+endif
+
+obj-$(CONFIG_SK98LIN) += sk98lin.o
+sk98lin-objs    :=	\
+		skge.o		\
+		sky2.o		\
+		skethtool.o	\
+		sky2le.o	\
+		skdim.o		\
+		skaddr.o	\
+		skgehwt.o	\
+		skgeinit.o	\
+		skgepnmi.o	\
+		skgesirq.o	\
+		sktwsi.o	\
+		sklm80.o	\
+		skqueue.o	\
+		sktimer.o	\
+		skvpd.o		\
+		skxmac2.o	\
+		skproc.o	\
+		skcsum.o	\
+		$(SDK_OPS)
+# DBGDEF =  \
+# -DDEBUG
+
+ifdef DEBUG
+DBGDEF +=  \
+-DSK_DEBUG_CHKMOD=0x00000000L \
+-DSK_DEBUG_CHKCAT=0x00000000L
+endif
+
+
+# **** possible debug modules for SK_DEBUG_CHKMOD *****************
+# SK_DBGMOD_MERR        0x00000001L     /* general module error indication */
+# SK_DBGMOD_HWM         0x00000002L     /* Hardware init module */
+# SK_DBGMOD_RLMT        0x00000004L     /* RLMT module */
+# SK_DBGMOD_VPD         0x00000008L     /* VPD module */
+# SK_DBGMOD_I2C         0x00000010L     /* I2C module */
+# SK_DBGMOD_PNMI        0x00000020L     /* PNMI module */
+# SK_DBGMOD_CSUM        0x00000040L     /* CSUM module */
+# SK_DBGMOD_ADDR        0x00000080L     /* ADDR module */
+# SK_DBGMOD_DRV         0x00010000L     /* DRV module */
+
+# **** possible debug categories for SK_DEBUG_CHKCAT **************
+# *** common modules ***
+# SK_DBGCAT_INIT        0x00000001L     module/driver initialization
+# SK_DBGCAT_CTRL        0x00000002L     controlling: add/rmv MCA/MAC and other controls (IOCTL)
+# SK_DBGCAT_ERR         0x00000004L     error handling paths
+# SK_DBGCAT_TX          0x00000008L     transmit path
+# SK_DBGCAT_RX          0x00000010L     receive path
+# SK_DBGCAT_IRQ         0x00000020L     general IRQ handling
+# SK_DBGCAT_QUEUE       0x00000040L     any queue management
+# SK_DBGCAT_DUMP        0x00000080L     large data output e.g. hex dump
+# SK_DBGCAT_FATAL       0x00000100L     large data output e.g. hex dump
+
+# *** driver (file skge.c) ***
+# SK_DBGCAT_DRV_ENTRY           0x00010000      entry points
+# SK_DBGCAT_DRV_???             0x00020000      not used
+# SK_DBGCAT_DRV_MCA             0x00040000      multicast
+# SK_DBGCAT_DRV_TX_PROGRESS     0x00080000      tx path
+# SK_DBGCAT_DRV_RX_PROGRESS     0x00100000      rx path
+# SK_DBGCAT_DRV_PROGRESS        0x00200000      general runtime
+# SK_DBGCAT_DRV_???             0x00400000      not used
+# SK_DBGCAT_DRV_PROM            0x00800000      promiscuous mode
+# SK_DBGCAT_DRV_TX_FRAME        0x01000000      display tx frames
+# SK_DBGCAT_DRV_ERROR           0x02000000      error conditions
+# SK_DBGCAT_DRV_INT_SRC         0x04000000      interrupts sources
+# SK_DBGCAT_DRV_EVENT           0x08000000      driver events
+
+EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
+		-DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
+		-DSK_EXTREME -DSK_NO_RLMT -DSK_LINUX -DUSE_SK_RSS_SUPPORT \
+		$(DBGDEF) $(SKPARAM) $(SDKPARAM) $(ADDPARAM)
+
+clean:
+	rm -f core *.o *.a *.s
+
+
diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c
--- linux/drivers/net/sk98lin/skaddr.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skaddr.c	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,1508 @@
+/******************************************************************************
+ *
+ * Name:	skaddr.c
+ * Project:	Gigabit Ethernet Adapters, ADDR-Module
+ * Version:	$Revision: #4 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skaddr.c,v $
+ *	Revision 2.16  2009/10/27 08:15:16  tschilli
+ *	Added changes to support compilation without RMLT (SK_NO_RLMT)
+ *	
+ *	Revision 2.15  2008/04/02 10:42:40  tschilli
+ *	Fix: Editorial changes.
+ *	
+ *	Revision 2.14  2008/04/01 09:02:42  tschilli
+ *	Fix: Removed unused variable DWord in SkAddrSwap().
+ *	
+ *	Revision 2.13  2008/03/20 08:24:31  tschilli
+ *	Removed support of GENESIS adapters.
+ *	
+ *	Revision 2.12  2007/02/12 16:40:28  tschilli
+ *	Fix: Changed NULL pointer check of pNewAddr in SkAddrOverride() to enable DualNetMode again.
+ *
+ *	Revision 2.11  2006/08/22 09:10:55  tschilli
+ *	Fix: Set pAC->Addr.Port[PortNumber].PromMode to NewPromMode
+ *
+ *	Revision 2.10  2006/07/13 08:00:41  tschilli
+ *	SkAddrOverride(): Added NULL pointer check of pNewAddr.
+ *	SkAddrGmacPromiscuousChange() rewritten to fix Windows problem.
+ *
+ *	Revision 2.9  2005/12/14 16:11:44  ibrueder
+ *	added copyright header flags
+ *
+ *	Revision 2.8  2005/07/21 12:01:30  tschilli
+ *	Removed access to RLMT struct for SK_SLIM code.
+ *
+ *	Revision 2.7  2005/07/21 10:27:01  rschmidt
+ *	Added workaround for deviation #4.24 (Yukon-EC).
+ *	Editorial changes.
+ *
+ *	Revision 2.6  2005/05/11 10:05:14  tschilli
+ *	SkAddrOverride(): Suppress physical MAC address check of the
+ *	other port and logical MAC address check of the same port if
+ *	the physical MAC address is to be changed and dual net mode
+ *	is active.
+ *
+ *	Revision 2.5  2005/05/02 13:11:45  tschilli
+ *	SkAddrOverride(): Suppress physical MAC address check if the
+ *	logical MAC address is to be changed and dual net mode is active.
+ *
+ *	Revision 2.4  2004/11/12 14:03:54  mkunz
+ *	Changed calculation of second Net Mac Addresses
+ *
+ *	Revision 2.3  2004/08/25 15:39:27  mlindner
+ *	Fix: Return value Race condition
+ *
+ *	Revision 2.2  2003/11/24 12:22:01  mkarl
+ *	Added ifdefs for GENENSIS and YUKON and semicolons at the end of
+ *	SK_DBG_MSG macros.
+ *
+ *	Revision 2.1  2003/10/27 14:16:07  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:17  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.52  2003/06/02 13:46:15  tschilli
+ *	Editorial changes.
+ *
+ *	Revision 1.51  2003/05/13 17:12:43  mkarl
+ *	Changes for SLIM Driver via SK_SLIM.
+ *	Changes for driver not using RLMT via SK_NO_RLMT.
+ *	Changes for driver not supporting MAC address override via SK_NO_MAO.
+ *	Separeted GENESIS and YUKON only code to reduce code size.
+ *	Editorial changes.
+ *
+ *	Revision 1.50  2003/05/08 12:29:31  rschmidt
+ *	Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
+ *	Changed initialisation for Next0[SK_MAX_MACS] to avoid
+ *	compiler errors when SK_MAX_MACS=1.
+ *	Editorial changes.
+ *
+ *	Revision 1.49  2003/04/15 09:30:51  tschilli
+ *	Copyright messages changed.
+ *	"#error C++ is not yet supported." removed.
+ *
+ *	Revision 1.48  2003/02/12 17:09:37  tschilli
+ *	Fix in SkAddrOverride() to set both (physical and logical) MAC addresses
+ *	in case that both addresses are identical.
+ *
+ *	Revision 1.47  2002/09/17 06:31:10  tschilli
+ *	Handling of SK_PROM_MODE_ALL_MC flag in SkAddrGmacMcUpdate()
+ *	and SkAddrGmacPromiscuousChange() fixed.
+ *	Editorial changes.
+ *
+ *	Revision 1.46  2002/08/22 07:55:41  tschilli
+ *	New function SkGmacMcHash() for GMAC multicast hashing algorithm added.
+ *	Editorial changes.
+ *
+ *	Revision 1.45  2002/08/15 12:29:35  tschilli
+ *	SkAddrGmacMcUpdate() and SkAddrGmacPromiscuousChange() changed.
+ *
+ *	Revision 1.44  2002/08/14 12:18:03  rschmidt
+ *	Replaced direct handling of MAC Hashing (XMAC and GMAC)
+ *	with routine SkMacHashing().
+ *	Replaced wrong 3rd para 'i' with 'PortNumber' in SkMacPromiscMode().
+ *
+ *	Revision 1.43  2002/08/13 09:37:43  rschmidt
+ *	Corrected some SK_DBG_MSG outputs.
+ *	Replaced wrong 2nd para pAC with IoC in SkMacPromiscMode().
+ *	Editorial changes.
+ *
+ *	Revision 1.42  2002/08/12 11:24:36  rschmidt
+ *	Remove setting of logical MAC address GM_SRC_ADDR_2 in SkAddrInit().
+ *	Replaced direct handling of MAC Promiscuous Mode (XMAC and GMAC)
+ *	with routine SkMacPromiscMode().
+ *	Editorial changes.
+ *
+ *	Revision 1.41  2002/06/10 13:52:18  tschilli
+ *	Changes for handling YUKON.
+ *	All changes are internally and not visible to the programmer
+ *	using this module.
+ *
+ *	Revision 1.40  2001/02/14 14:04:59  rassmann
+ *	Editorial changes.
+ *
+ *	Revision 1.39  2001/01/30 10:30:04  rassmann
+ *	Editorial changes.
+ *
+ *	Revision 1.38  2001/01/25 16:26:52  rassmann
+ *	Ensured that logical address overrides are done on net's active port.
+ *
+ *	Revision 1.37  2001/01/22 13:41:34  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *
+ *	Revision 1.36  2000/08/07 11:10:39  rassmann
+ *	Editorial changes.
+ *
+ *	Revision 1.35  2000/05/04 09:38:41  rassmann
+ *	Editorial changes.
+ *	Corrected multicast address hashing.
+ *
+ *	Revision 1.34  1999/11/22 13:23:44  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.33  1999/05/28 10:56:06  rassmann
+ *	Editorial changes.
+ *
+ *	Revision 1.32  1999/03/31 10:59:20  rassmann
+ *	Returning Success instead of DupAddr if address shall be overridden
+ *	with same value.
+ *
+ *	Revision 1.31  1999/01/14 16:18:17  rassmann
+ *	Corrected multicast initialization.
+ *
+ *	Revision 1.30  1999/01/04 10:30:35  rassmann
+ *	SkAddrOverride only possible after SK_INIT_IO phase.
+ *
+ *	Revision 1.29  1998/12/29 13:13:10  rassmann
+ *	An address override is now preserved in the SK_INIT_IO phase.
+ *	All functions return an int now.
+ *	Extended parameter checking.
+ *
+ *	Revision 1.28  1998/12/01 11:45:53  rassmann
+ *	Code cleanup.
+ *
+ *	Revision 1.27  1998/12/01 09:22:49  rassmann
+ *	SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT
+ *	too often.
+ *
+ *	Revision 1.26  1998/11/24 12:39:44  rassmann
+ *	Reserved multicast entry for BPDU address.
+ *	13 multicast entries left for protocol.
+ *
+ *	Revision 1.25  1998/11/17 16:54:23  rassmann
+ *	Using exact match for up to 14 multicast addresses.
+ *	Still receiving all multicasts if more addresses are added.
+ *
+ *	Revision 1.24  1998/11/13 17:24:31  rassmann
+ *	Changed return value of SkAddrOverride to int.
+ *
+ *	Revision 1.23  1998/11/13 16:56:18  rassmann
+ *	Added macro SK_ADDR_COMPARE.
+ *	Changed return type of SkAddrOverride to SK_BOOL.
+ *
+ *	Revision 1.22  1998/11/04 17:06:17  rassmann
+ *	Corrected McUpdate and PromiscuousChange functions.
+ *
+ *	Revision 1.21  1998/10/29 14:34:04  rassmann
+ *	Clearing SK_ADDR struct at startup.
+ *
+ *	Revision 1.20  1998/10/28 18:16:34  rassmann
+ *	Avoiding I/Os before SK_INIT_RUN level.
+ *	Aligning InexactFilter.
+ *
+ *	Revision 1.19  1998/10/28 11:29:28  rassmann
+ *	Programming physical address in SkAddrMcUpdate.
+ *	Corrected programming of exact match entries.
+ *
+ *	Revision 1.18  1998/10/28 10:34:48  rassmann
+ *	Corrected reading of physical addresses.
+ *
+ *	Revision 1.17  1998/10/28 10:26:13  rassmann
+ *	Getting ports' current MAC addresses from EPROM now.
+ *	Added debug output.
+ *
+ *	Revision 1.16  1998/10/27 16:20:12  rassmann
+ *	Reading MAC address byte by byte.
+ *
+ *	Revision 1.15  1998/10/22 11:39:09  rassmann
+ *	Corrected signed/unsigned mismatches.
+ *
+ *	Revision 1.14  1998/10/19 17:12:35  rassmann
+ *	Syntax corrections.
+ *
+ *	Revision 1.13  1998/10/19 17:02:19  rassmann
+ *	Now reading permanent MAC addresses from CRF.
+ *
+ *	Revision 1.12  1998/10/15 15:15:48  rassmann
+ *	Changed Flags Parameters from SK_U8 to int.
+ *	Checked with lint.
+ *
+ *	Revision 1.11  1998/09/24 19:15:12  rassmann
+ *	Code cleanup.
+ *
+ *	Revision 1.10  1998/09/18 20:18:54  rassmann
+ *	Added HW access.
+ *	Implemented swapping.
+ *
+ *	Revision 1.9  1998/09/16 11:32:00  rassmann
+ *	Including skdrv1st.h again. :(
+ *
+ *	Revision 1.8  1998/09/16 11:09:34  rassmann
+ *	Syntax corrections.
+ *
+ *	Revision 1.7  1998/09/14 17:06:34  rassmann
+ *	Minor changes.
+ *
+ *	Revision 1.6  1998/09/07 08:45:41  rassmann
+ *	Syntax corrections.
+ *
+ *	Revision 1.5  1998/09/04 19:40:19  rassmann
+ *	Interface enhancements.
+ *
+ *	Revision 1.4  1998/09/04 12:14:12  rassmann
+ *	Interface cleanup.
+ *
+ *	Revision 1.3  1998/09/02 16:56:40  rassmann
+ *	Updated interface.
+ *
+ *	Revision 1.2  1998/08/27 14:26:09  rassmann
+ *	Updated interface.
+ *
+ *	Revision 1.1  1998/08/21 08:30:22  rassmann
+ *	First public version.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This module is intended to manage multicast addresses, address override,
+ * and promiscuous mode on Yukon adapters.
+ *
+ * Address Layout:
+ *	port address:		physical MAC address
+ *
+ * Include File Hierarchy:
+ *
+ *	"skdrv1st.h"
+ *	"skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/addr/V5/skaddr.c#4 $ (C) Marvell.";
+#endif /* DEBUG ||!LINT || !SK_SLIM */
+
+#define __SKADDR_C
+
+#ifdef __cplusplus
+extern "C" {
+#endif	/* cplusplus */
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+#define XMAC_POLY	0xEDB88320UL	/* CRC32-Poly - XMAC: Little Endian */
+#define GMAC_POLY	0x04C11DB7L	/* CRC16-Poly - GMAC: Little Endian */
+#define HASH_BITS	6				/* #bits in hash */
+#define SK_MC_BIT	0x01
+
+/* Error numbers and messages. */
+
+#define SKERR_ADDR_E001		(SK_ERRBASE_ADDR + 0)
+#define SKERR_ADDR_E001MSG	"Bad Flags."
+#define SKERR_ADDR_E002		(SKERR_ADDR_E001 + 1)
+#define SKERR_ADDR_E002MSG	"New Error."
+
+/* typedefs *******************************************************************/
+
+/* None. */
+
+/* global variables ***********************************************************/
+
+/* 64-bit hash values with all bits set. */
+
+SK_U16	OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
+
+/* local variables ************************************************************/
+
+#ifdef DEBUG
+static int	Next0[SK_MAX_MACS] = {0};
+#endif	/* DEBUG */
+
+/* functions ******************************************************************/
+
+/******************************************************************************
+ *
+ *	SkAddrInit - initialize data, set state to init
+ *
+ * Description:
+ *
+ *	SK_INIT_DATA
+ *	============
+ *
+ *	This routine clears the multicast tables and resets promiscuous mode.
+ *	Some entries are reserved for the "logical MAC address", the
+ *	SK-RLMT multicast address, and the BPDU multicast address.
+ *
+ *
+ *	SK_INIT_IO
+ *	==========
+ *
+ *	All permanent MAC addresses are read from EPROM.
+ *	If the current MAC addresses are not already set in software,
+ *	they are set to the values of the permanent addresses.
+ *	The current addresses are written to the corresponding MAC.
+ *
+ *
+ *	SK_INIT_RUN
+ *	===========
+ *
+ *	Nothing.
+ *
+ * Context:
+ *	init, pageable
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ */
+int	SkAddrInit(
+SK_AC	*pAC,	/* the adapter context */
+SK_IOC	IoC,	/* I/O context */
+int		Level)	/* initialization level */
+{
+	int			j;
+	SK_U32		i;
+	SK_U8		*InAddr;
+	SK_U16		*OutAddr;
+	SK_ADDR_PORT	*pAPort;
+
+	switch (Level) {
+	case SK_INIT_DATA:
+		SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
+
+		for (i = 0; i < SK_MAX_MACS; i++) {
+			pAPort = &pAC->Addr.Port[i];
+			pAPort->PromMode = SK_PROM_MODE_NONE;
+
+			pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
+			pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
+			pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
+			pAPort->NextExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
+		}
+#ifdef xDEBUG
+		for (i = 0; i < SK_MAX_MACS; i++) {
+			if (pAC->Addr.Port[i].NextExactMatchRlmt <
+				SK_ADDR_FIRST_MATCH_RLMT) {
+				Next0[i] |= 4;
+			}
+		}
+#endif	/* DEBUG */
+		break;
+
+	case SK_INIT_IO:
+#ifndef SK_NO_RLMT
+		for (i = 0; i < SK_MAX_NETS; i++) {
+			pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
+		}
+#else
+		for (i = 0; i < SK_MAX_NETS; i++) {
+			pAC->Addr.Net[i].ActivePort = i;
+		}
+#endif /* SK_NO_RLMT */
+#ifdef xDEBUG
+		for (i = 0; i < SK_MAX_MACS; i++) {
+			if (pAC->Addr.Port[i].NextExactMatchRlmt <
+				SK_ADDR_FIRST_MATCH_RLMT) {
+				Next0[i] |= 8;
+			}
+		}
+#endif	/* DEBUG */
+
+		/* Read permanent logical MAC address from Control Register File. */
+		for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
+			InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
+			SK_IN8(IoC, B2_MAC_1 + j, InAddr);
+		}
+
+		if (!pAC->Addr.Net[0].CurrentMacAddressSet) {
+			/* Set the current logical MAC address to the permanent one. */
+			pAC->Addr.Net[0].CurrentMacAddress =
+				pAC->Addr.Net[0].PermanentMacAddress;
+			pAC->Addr.Net[0].CurrentMacAddressSet = SK_TRUE;
+		}
+
+		/* Set the current logical MAC address. */
+		pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
+			pAC->Addr.Net[0].CurrentMacAddress;
+#if SK_MAX_NETS > 1
+		/* Set logical MAC address for net 2, too. */
+		if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
+			pAC->Addr.Net[1].PermanentMacAddress =
+				pAC->Addr.Net[0].PermanentMacAddress;
+			pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
+
+			/* Set the current logical MAC address to the permanent one. */
+			pAC->Addr.Net[1].CurrentMacAddress =
+				pAC->Addr.Net[1].PermanentMacAddress;
+			pAC->Addr.Net[1].CurrentMacAddressSet = SK_TRUE;
+#ifdef SK_NO_RLMT
+			/* Set the current logical MAC address. */
+			pAC->Addr.Port[pAC->Addr.Net[1].ActivePort].Exact[0] =
+				pAC->Addr.Net[1].CurrentMacAddress;
+#endif
+		}
+#endif	/* SK_MAX_NETS > 1 */
+
+#ifdef DEBUG
+		for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
+				("Permanent MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
+					i,
+					pAC->Addr.Net[i].PermanentMacAddress.a[0],
+					pAC->Addr.Net[i].PermanentMacAddress.a[1],
+					pAC->Addr.Net[i].PermanentMacAddress.a[2],
+					pAC->Addr.Net[i].PermanentMacAddress.a[3],
+					pAC->Addr.Net[i].PermanentMacAddress.a[4],
+					pAC->Addr.Net[i].PermanentMacAddress.a[5]));
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
+				("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
+					i,
+					pAC->Addr.Net[i].CurrentMacAddress.a[0],
+					pAC->Addr.Net[i].CurrentMacAddress.a[1],
+					pAC->Addr.Net[i].CurrentMacAddress.a[2],
+					pAC->Addr.Net[i].CurrentMacAddress.a[3],
+					pAC->Addr.Net[i].CurrentMacAddress.a[4],
+					pAC->Addr.Net[i].CurrentMacAddress.a[5]));
+		}
+#endif	/* DEBUG */
+
+		for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+			pAPort = &pAC->Addr.Port[i];
+
+			/* Read permanent port addresses from Control Register File. */
+			for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
+				InAddr = (SK_U8 *) &pAPort->PermanentMacAddress.a[j];
+				SK_IN8(IoC, B2_MAC_2 + 8 * i + j, InAddr);
+			}
+
+			if (!pAPort->CurrentMacAddressSet) {
+				/*
+				 * Set the current and previous physical MAC address
+				 * of this port to its permanent MAC address.
+				 */
+				pAPort->CurrentMacAddress = pAPort->PermanentMacAddress;
+				pAPort->PreviousMacAddress = pAPort->PermanentMacAddress;
+				pAPort->CurrentMacAddressSet = SK_TRUE;
+			}
+
+			/* Set port's current physical MAC address. */
+			OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
+			GM_OUTADDR(IoC, i, GM_SRC_ADDR_1L, OutAddr);
+
+#ifdef DEBUG
+			SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
+				("SkAddrInit: Permanent Physical MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+					i,
+					pAPort->PermanentMacAddress.a[0],
+					pAPort->PermanentMacAddress.a[1],
+					pAPort->PermanentMacAddress.a[2],
+					pAPort->PermanentMacAddress.a[3],
+					pAPort->PermanentMacAddress.a[4],
+					pAPort->PermanentMacAddress.a[5]));
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
+				("SkAddrInit: Physical MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+					i,
+					pAPort->CurrentMacAddress.a[0],
+					pAPort->CurrentMacAddress.a[1],
+					pAPort->CurrentMacAddress.a[2],
+					pAPort->CurrentMacAddress.a[3],
+					pAPort->CurrentMacAddress.a[4],
+					pAPort->CurrentMacAddress.a[5]));
+#endif /* DEBUG */
+		}
+		break;
+
+	case SK_INIT_RUN:
+#ifdef xDEBUG
+		for (i = 0; i < SK_MAX_MACS; i++) {
+			if (pAC->Addr.Port[i].NextExactMatchRlmt <
+				SK_ADDR_FIRST_MATCH_RLMT) {
+				Next0[i] |= 16;
+			}
+		}
+#endif	/* DEBUG */
+		break;
+
+	default:	/* error */
+		break;
+	}
+
+	return (SK_ADDR_SUCCESS);
+
+}	/* SkAddrInit */
+
+#ifndef SK_SLIM
+
+/******************************************************************************
+ *
+ *	SkAddrMcClear - clear the multicast table
+ *
+ * Description:
+ *	This routine clears the multicast table.
+ *
+ *	If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated
+ *	immediately.
+ *
+ *	It calls either SkAddrXmacMcClear or SkAddrGmacMcClear, according
+ *	to the adapter in use. The real work is done there.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY
+ *	may be called after SK_INIT_IO without limitation
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrMcClear(
+SK_AC	*pAC,		/* adapter context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	PortNumber,	/* Index of affected port */
+int		Flags)		/* permanent/non-perm, sw-only */
+{
+	int ReturnCode;
+
+	if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+	ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
+	return (ReturnCode);
+
+}	/* SkAddrMcClear */
+
+
+/******************************************************************************
+ *
+ *	SkAddrGmacMcClear - clear the multicast table
+ *
+ * Description:
+ *	This routine clears the multicast hashing table (InexactFilter)
+ *	(either the RLMT or the driver bits) of the given port.
+ *
+ *	If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated
+ *	immediately.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY
+ *	may be called after SK_INIT_IO without limitation
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrGmacMcClear(
+SK_AC	*pAC,		/* adapter context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	PortNumber,	/* Index of affected port */
+int		Flags)		/* permanent/non-perm, sw-only */
+{
+	int i;
+
+#ifdef DEBUG
+	SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("GMAC InexactFilter (not cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
+#endif	/* DEBUG */
+
+	/* Clear InexactFilter */
+	for (i = 0; i < 8; i++) {
+		pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
+	}
+
+	if (Flags & SK_ADDR_PERMANENT) {	/* permanent => RLMT */
+
+		/* Copy DRV bits to InexactFilter. */
+		for (i = 0; i < 8; i++) {
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
+				pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
+
+			/* Clear InexactRlmtFilter. */
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
+		}
+	}
+	else {	/* not permanent => DRV */
+
+		/* Copy RLMT bits to InexactFilter. */
+		for (i = 0; i < 8; i++) {
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
+				pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
+
+			/* Clear InexactDrvFilter. */
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
+		}
+	}
+
+#ifdef DEBUG
+	SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
+#endif	/* DEBUG */
+
+	if (!(Flags & SK_MC_SW_ONLY)) {
+		(void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
+	}
+
+	return (SK_ADDR_SUCCESS);
+
+}	/* SkAddrGmacMcClear */
+
+#ifndef SK_ADDR_CHEAT
+
+/******************************************************************************
+ *
+ *	SkGmacMcHash - hash multicast address
+ *
+ * Description:
+ *	This routine computes the hash value for a multicast address.
+ *	A CRC16 algorithm is used.
+ *
+ * Notes:
+ *
+ *
+ * Context:
+ *	runtime, pageable
+ *
+ * Returns:
+ *	Hash value of multicast address.
+ */
+SK_U32 SkGmacMcHash(
+unsigned char *pMc)	/* Multicast address */
+{
+	SK_U32 Data;
+	SK_U32 TmpData;
+	SK_U32 Crc;
+	int Byte;
+	int Bit;
+
+	Crc = 0xFFFFFFFFUL;
+	for (Byte = 0; Byte < 6; Byte++) {
+		/* Get next byte. */
+		Data = (SK_U32) pMc[Byte];
+
+		/* Change bit order in byte. */
+		TmpData = Data;
+		for (Bit = 0; Bit < 8; Bit++) {
+			if (TmpData & 1L) {
+				Data |=  1L << (7 - Bit);
+			}
+			else {
+				Data &= ~(1L << (7 - Bit));
+			}
+			TmpData >>= 1;
+		}
+
+		Crc ^= (Data << 24);
+		for (Bit = 0; Bit < 8; Bit++) {
+			if (Crc & 0x80000000) {
+				Crc = (Crc << 1) ^ GMAC_POLY;
+			}
+			else {
+				Crc <<= 1;
+			}
+		}
+	}
+
+	return (Crc & ((1 << HASH_BITS) - 1));
+
+}	/* SkGmacMcHash */
+
+#endif	/* !SK_ADDR_CHEAT */
+
+/******************************************************************************
+ *
+ *	SkAddrMcAdd - add a multicast address to a port
+ *
+ * Description:
+ *	This routine enables reception for a given address on the given port.
+ *
+ *	It calls either SkAddrXmacMcAdd or SkAddrGmacMcAdd, according to the
+ *	adapter in use. The real work is done there.
+ *
+ * Notes:
+ *	The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_DATA
+ *
+ * Returns:
+ *	SK_MC_FILTERING_EXACT
+ *	SK_MC_FILTERING_INEXACT
+ *	SK_MC_ILLEGAL_ADDRESS
+ *	SK_MC_ILLEGAL_PORT
+ *	SK_MC_RLMT_OVERFLOW
+ */
+int	SkAddrMcAdd(
+SK_AC		*pAC,		/* adapter context */
+SK_IOC		IoC,		/* I/O context */
+SK_U32		PortNumber,	/* Port Number */
+SK_MAC_ADDR	*pMc,		/* multicast address to be added */
+int			Flags)		/* permanent/non-permanent */
+{
+	int ReturnCode;
+
+	if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+	ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
+	return (ReturnCode);
+
+}	/* SkAddrMcAdd */
+
+
+/******************************************************************************
+ *
+ *	SkAddrGmacMcAdd - add a multicast address to a port
+ *
+ * Description:
+ *	This routine enables reception for a given address on the given port.
+ *
+ * Notes:
+ *	The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_DATA
+ *
+ * Returns:
+ *	SK_MC_FILTERING_INEXACT
+ *	SK_MC_ILLEGAL_ADDRESS
+ */
+int	SkAddrGmacMcAdd(
+SK_AC		*pAC,		/* adapter context */
+SK_IOC		IoC,		/* I/O context */
+SK_U32		PortNumber,	/* Port Number */
+SK_MAC_ADDR	*pMc,		/* multicast address to be added */
+int		Flags)		/* permanent/non-permanent */
+{
+	int	i;
+#ifndef SK_ADDR_CHEAT
+	SK_U32 HashBit;
+#endif	/* !defined(SK_ADDR_CHEAT) */
+
+	if (!(pMc->a[0] & SK_MC_BIT)) {
+		/* Hashing only possible with multicast addresses */
+		return (SK_MC_ILLEGAL_ADDRESS);
+	}
+
+#ifndef SK_ADDR_CHEAT
+
+	/* Compute hash value of address. */
+	HashBit = SkGmacMcHash(&pMc->a[0]);
+
+	if (Flags & SK_ADDR_PERMANENT) {	/* permanent => RLMT */
+
+		/* Add bit to InexactRlmtFilter. */
+		pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
+			1 << (HashBit % 8);
+
+		/* Copy bit to InexactFilter. */
+		for (i = 0; i < 8; i++) {
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
+				pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
+		}
+
+#ifdef DEBUG
+		SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[0],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[1],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[2],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[3],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
+			pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
+#endif	/* DEBUG */
+	}
+	else {	/* not permanent => DRV */
+
+		/* Add bit to InexactDrvFilter. */
+		pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
+			1 << (HashBit % 8);
+
+		/* Copy bit to InexactFilter. */
+		for (i = 0; i < 8; i++) {
+			pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
+				pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
+		}
+
+#ifdef DEBUG
+		SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[0],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[1],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[2],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[3],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
+			pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
+#endif	/* DEBUG */
+	}
+
+#else	/* SK_ADDR_CHEAT */
+
+	/* Set all bits in InexactFilter. */
+	for (i = 0; i < 8; i++) {
+		pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
+	}
+#endif	/* SK_ADDR_CHEAT */
+
+	return (SK_MC_FILTERING_INEXACT);
+
+}	/* SkAddrGmacMcAdd */
+
+#endif /* !SK_SLIM */
+
+/******************************************************************************
+ *
+ *	SkAddrMcUpdate - update the HW MC address table and set the MAC address
+ *
+ * Description:
+ *	This routine enables reception of the addresses contained in a local
+ *	table for a given port.
+ *	It also programs the port's current physical MAC address.
+ *
+ *	It calls either SkAddrXmacMcUpdate or SkAddrGmacMcUpdate, according
+ *	to the adapter in use. The real work is done there.
+ *
+ * Notes:
+ *	The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_MC_FILTERING_EXACT
+ *	SK_MC_FILTERING_INEXACT
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrMcUpdate(
+SK_AC	*pAC,		/* adapter context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	PortNumber)	/* Port Number */
+{
+	int ReturnCode = SK_ADDR_ILLEGAL_PORT;
+
+#if (!defined(SK_SLIM) || defined(DEBUG))
+	if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+#endif /* !SK_SLIM || DEBUG */
+	ReturnCode = SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
+	return (ReturnCode);
+
+}	/* SkAddrMcUpdate */
+
+
+/******************************************************************************
+ *
+ *	SkAddrGmacMcUpdate - update the HW MC address table and set the MAC address
+ *
+ * Description:
+ *	This routine enables reception of the addresses contained in a local
+ *	table for a given port.
+ *	It also programs the port's current physical MAC address.
+ *
+ * Notes:
+ *	The return code is only valid for SK_PROM_MODE_NONE.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_MC_FILTERING_EXACT
+ *	SK_MC_FILTERING_INEXACT
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrGmacMcUpdate(
+SK_AC	*pAC,		/* adapter context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	PortNumber)	/* Port Number */
+{
+#ifndef SK_SLIM
+	SK_U32		i;
+	SK_U8		Inexact;
+#endif	/* not SK_SLIM */
+	SK_U16		*OutAddr;
+	SK_ADDR_PORT	*pAPort;
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
+
+	pAPort = &pAC->Addr.Port[PortNumber];
+
+#ifdef DEBUG
+	SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
+#endif /* DEBUG */
+
+#ifndef SK_SLIM
+	for (Inexact = 0, i = 0; i < 8; i++) {
+		Inexact |= pAPort->InexactFilter.Bytes[i];
+	}
+
+	/* Set 64-bit hash register to InexactFilter. */
+	GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
+		&pAPort->InexactFilter.Bytes[0]);
+
+	if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
+
+		/* Set all bits in 64-bit hash register. */
+		GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
+
+		/* Enable Hashing */
+		SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
+	}
+	else {
+		/* Enable Hashing. */
+		SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
+	}
+
+	if (pAPort->PromMode != SK_PROM_MODE_NONE) {
+		(void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
+	}
+#else /* SK_SLIM */
+
+	/* Set all bits in 64-bit hash register. */
+	GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
+
+	/* Enable Hashing */
+	SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
+
+	(void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
+
+#endif /* SK_SLIM */
+
+	/* Set port's current physical MAC address. */
+	OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
+	GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
+
+	/* Set port's current logical MAC address. */
+	OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
+	GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
+
+#ifdef DEBUG
+	SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("SkAddrGmacMcUpdate: Current logical MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+			PortNumber,
+			pAPort->Exact[0].a[0],
+			pAPort->Exact[0].a[1],
+			pAPort->Exact[0].a[2],
+			pAPort->Exact[0].a[3],
+			pAPort->Exact[0].a[4],
+			pAPort->Exact[0].a[5]));
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+		("SkAddrGmacMcUpdate: Current physical MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+			PortNumber,
+			pAPort->CurrentMacAddress.a[0],
+			pAPort->CurrentMacAddress.a[1],
+			pAPort->CurrentMacAddress.a[2],
+			pAPort->CurrentMacAddress.a[3],
+			pAPort->CurrentMacAddress.a[4],
+			pAPort->CurrentMacAddress.a[5]));
+#endif /* DEBUG */
+
+#ifndef SK_SLIM
+	/* Determine return value. */
+	if (Inexact == 0 && pAPort->PromMode == 0) {
+		return (SK_MC_FILTERING_EXACT);
+	}
+	else {
+		return (SK_MC_FILTERING_INEXACT);
+	}
+#else /* SK_SLIM */
+	return (SK_MC_FILTERING_INEXACT);
+#endif /* SK_SLIM */
+
+}	/* SkAddrGmacMcUpdate */
+
+#ifndef SK_NO_MAO
+
+/******************************************************************************
+ *
+ *	SkAddrOverride - override a port's MAC address
+ *
+ * Description:
+ *	This routine overrides the MAC address of one port.
+ *
+ * NOTE: It can be called with pNewAddr set to NULL from the RLMT module!
+ *       This is correct in combination with Flags set to SK_ADDR_SET_LOGICAL
+ *       or SK_ADDR_CLEAR_LOGICAL. All other calls will be handled as an error
+ *       and SK_MC_ILLEGAL_ADDRESS will be returned then.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS if successful.
+ *	SK_ADDR_DUPLICATE_ADDRESS if duplicate MAC address.
+ *	SK_ADDR_MULTICAST_ADDRESS if multicast or broadcast address.
+ *	SK_ADDR_TOO_EARLY if SK_INIT_IO was not executed before.
+ */
+int	SkAddrOverride(
+SK_AC		*pAC,				/* adapter context */
+SK_IOC		IoC,				/* I/O context */
+SK_U32		PortNumber,			/* Port Number */
+SK_MAC_ADDR	SK_FAR *pNewAddr,	/* new MAC address */
+int			Flags)				/* logical/physical MAC address */
+{
+#ifndef SK_NO_RLMT
+	SK_EVPARA	Para;
+#endif /* !SK_NO_RLMT */
+	SK_U32		NetNumber;
+	SK_U32		i;
+	SK_U16		SK_FAR *OutAddr;
+
+#ifndef SK_NO_RLMT
+	NetNumber = pAC->Rlmt.Port[PortNumber].Net->NetNumber;
+#else
+#ifndef SK_SLIM
+	NetNumber = PortNumber;
+#else
+	NetNumber = 0;
+#endif /* SK_SLIM */
+#endif /* SK_NO_RLMT */
+#if (!defined(SK_SLIM) || defined(DEBUG))
+	if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+#endif /* !SK_SLIM || DEBUG */
+
+	if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) {
+		return (SK_ADDR_MULTICAST_ADDRESS);
+	}
+
+	if (!pAC->Addr.Net[NetNumber].CurrentMacAddressSet) {
+		return (SK_ADDR_TOO_EARLY);
+	}
+
+	if (Flags & SK_ADDR_SET_LOGICAL) {	/* Activate logical MAC address. */
+		/* Parameter *pNewAddr is ignored. */
+		for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+			if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+				return (SK_ADDR_TOO_EARLY);
+			}
+		}
+#ifndef SK_NO_RLMT
+		/* Set PortNumber to number of net's active port. */
+		PortNumber = pAC->Rlmt.Net[NetNumber].
+			Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber;
+#endif /* !SK_NO_RLMT */
+		pAC->Addr.Port[PortNumber].Exact[0] =
+			pAC->Addr.Net[NetNumber].CurrentMacAddress;
+
+		/* Write address to first exact match entry of active port. */
+		(void) SkAddrMcUpdate(pAC, IoC, PortNumber);
+	}
+	else if (Flags & SK_ADDR_CLEAR_LOGICAL) {
+		/* Deactivate logical MAC address. */
+		/* Parameter *pNewAddr is ignored. */
+		for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+			if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+				return (SK_ADDR_TOO_EARLY);
+			}
+		}
+#ifndef SK_NO_RLMT
+		/* Set PortNumber to number of net's active port. */
+		PortNumber = pAC->Rlmt.Net[NetNumber].
+			Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber;
+#endif /* !SK_NO_RLMT */
+		for (i = 0; i < SK_MAC_ADDR_LEN; i++ ) {
+			pAC->Addr.Port[PortNumber].Exact[0].a[i] = 0;
+		}
+
+		/* Write address to first exact match entry of active port. */
+		(void) SkAddrMcUpdate(pAC, IoC, PortNumber);
+	}
+	else if (pNewAddr == NULL) {
+		/* Prevent accessing a NULL pointer (was complained by Prefast)  */
+		return (SK_MC_ILLEGAL_ADDRESS);
+	}
+	else {
+		if (Flags & SK_ADDR_PHYSICAL_ADDRESS) {	/* Physical MAC address. */
+
+			for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+				if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+					return (SK_ADDR_TOO_EARLY);
+				}
+			}
+
+			/*
+			 * In dual net mode it should be possible to set all MAC
+			 * addresses independently. Therefore the equality checks
+			 * against the locical address of the same port and the
+			 * physical address of the other port are suppressed here.
+			 */
+#ifndef SK_NO_RLMT
+			if (pAC->Rlmt.NumNets == 1) {
+#endif /* SK_NO_RLMT */
+				if (SK_ADDR_EQUAL(pNewAddr->a,
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
+					return (SK_ADDR_DUPLICATE_ADDRESS);
+				}
+
+				for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+					if (SK_ADDR_EQUAL(pNewAddr->a,
+						pAC->Addr.Port[i].CurrentMacAddress.a)) {
+						if (i == PortNumber) {
+							return (SK_ADDR_SUCCESS);
+						}
+						else {
+							return (SK_ADDR_DUPLICATE_ADDRESS);
+						}
+					}
+				}
+#ifndef SK_NO_RLMT
+			}
+			else {
+				if (SK_ADDR_EQUAL(pNewAddr->a,
+					pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
+					return (SK_ADDR_SUCCESS);
+				}
+			}
+#endif /* SK_NO_RLMT */
+
+			pAC->Addr.Port[PortNumber].PreviousMacAddress =
+				pAC->Addr.Port[PortNumber].CurrentMacAddress;
+			pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
+
+			/* Change port's physical MAC address. */
+			OutAddr = (SK_U16 SK_FAR *) pNewAddr;
+			GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
+
+#ifndef SK_NO_RLMT
+			/* Report address change to RLMT. */
+			Para.Para32[0] = PortNumber;
+			Para.Para32[0] = -1;
+			SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
+#endif /* !SK_NO_RLMT */
+		}
+		else {	/* Logical MAC address. */
+			if (SK_ADDR_EQUAL(pNewAddr->a,
+				pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
+				return (SK_ADDR_SUCCESS);
+			}
+
+			for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+				if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
+					return (SK_ADDR_TOO_EARLY);
+				}
+			}
+
+			/*
+			 * In dual net mode on Yukon-2 adapters the physical address
+			 * of port 0 and the logical address of port 1 are equal - in
+			 * this case the equality check of the physical address leads
+			 * to an error and is suppressed here.
+			 */
+#ifndef SK_NO_RLMT
+			if (pAC->Rlmt.NumNets == 1) {
+#endif /* SK_NO_RLMT */
+				for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
+					if (SK_ADDR_EQUAL(pNewAddr->a,
+						pAC->Addr.Port[i].CurrentMacAddress.a)) {
+						return (SK_ADDR_DUPLICATE_ADDRESS);
+					}
+				}
+#ifndef SK_NO_RLMT
+			}
+#endif /* SK_NO_RLMT */
+
+			/*
+			 * In case that the physical and the logical MAC addresses are equal
+			 * we must also change the physical MAC address here.
+			 * In this case we have an adapter which initially was programmed with
+			 * two identical MAC addresses.
+			 */
+			if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
+					pAC->Addr.Port[PortNumber].Exact[0].a)) {
+
+				pAC->Addr.Port[PortNumber].PreviousMacAddress =
+					pAC->Addr.Port[PortNumber].CurrentMacAddress;
+				pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
+
+#ifndef SK_NO_RLMT
+				/* Report address change to RLMT. */
+				Para.Para32[0] = PortNumber;
+				Para.Para32[0] = -1;
+				SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
+#endif /* !SK_NO_RLMT */
+			}
+
+#ifndef SK_NO_RLMT
+			/* Set PortNumber to number of net's active port. */
+			PortNumber = pAC->Rlmt.Net[NetNumber].
+				Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber;
+#endif /* !SK_NO_RLMT */
+			pAC->Addr.Net[NetNumber].CurrentMacAddress = *pNewAddr;
+			pAC->Addr.Port[PortNumber].Exact[0] = *pNewAddr;
+
+#ifdef DEBUG
+			SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+				("SkAddrOverride: Permanent MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+					NetNumber,
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[0],
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[1],
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
+					pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
+
+			SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
+				("SkAddrOverride: New logical MAC Address[%d]: %02X %02X %02X %02X %02X %02X\n",
+					NetNumber,
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[1],
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
+					pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
+#endif /* DEBUG */
+
+			/* Write address to first exact match entry of active port. */
+			(void)SkAddrMcUpdate(pAC, IoC, PortNumber);
+		}
+	}
+
+	return (SK_ADDR_SUCCESS);
+
+}	/* SkAddrOverride */
+
+#endif /* SK_NO_MAO */
+
+/******************************************************************************
+ *
+ *	SkAddrPromiscuousChange - set promiscuous mode for given port
+ *
+ * Description:
+ *	This routine manages promiscuous mode:
+ *	- none
+ *	- all LLC frames
+ *	- all MC frames
+ *
+ *	It calls either SkAddrXmacPromiscuousChange or
+ *	SkAddrGmacPromiscuousChange, according to the adapter in use.
+ *	The real work is done there.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrPromiscuousChange(
+SK_AC	*pAC,			/* adapter context */
+SK_IOC	IoC,			/* I/O context */
+SK_U32	PortNumber,		/* port whose promiscuous mode changes */
+int		NewPromMode)	/* new promiscuous mode */
+{
+	int ReturnCode = SK_ADDR_ILLEGAL_PORT;
+
+#if (!defined(SK_SLIM) || defined(DEBUG))
+	if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+#endif /* !SK_SLIM || DEBUG */
+
+	ReturnCode =
+		SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode);
+	return (ReturnCode);
+
+}	/* SkAddrPromiscuousChange */
+
+
+/******************************************************************************
+ *
+ *	SkAddrGmacPromiscuousChange - set promiscuous mode for given port
+ *
+ * Description:
+ *	This routine manages promiscuous mode:
+ *	- none
+ *	- all LLC frames
+ *	- all MC frames
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrGmacPromiscuousChange(
+SK_AC	*pAC,			/* adapter context */
+SK_IOC	IoC,			/* I/O context */
+SK_U32	PortNumber,		/* port whose promiscuous mode changes */
+int		NewPromMode)	/* new promiscuous mode */
+{
+	if (PortNumber >= (SK_U32)pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+
+	pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
+
+	switch(NewPromMode) {
+	case (SK_PROM_MODE_NONE):							/* 0 */
+
+		/* Normal receive mode */
+		SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
+		break;
+
+	case (SK_PROM_MODE_LLC):							/* 1 */
+		/* This mode is ignored and mapped to prom. mode */
+	case (SK_PROM_MODE_LLC | SK_PROM_MODE_ALL_MC):		/* 3 */
+
+		/* Set the MAC to promiscuous mode. */
+		SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
+		break;
+
+	case (SK_PROM_MODE_ALL_MC):							/* 2 */
+
+		/* Disable MC hashing */
+		SkMacHashing(pAC, IoC, (int) PortNumber, SK_FALSE);
+		break;
+
+	default:
+		break;
+	}
+
+	return (SK_ADDR_SUCCESS);
+}	/* SkAddrGmacPromiscuousChange */
+
+#if (!defined(SK_SLIM) && !defined(SK_NO_RLMT))
+
+/******************************************************************************
+ *
+ *	SkAddrSwap - swap address info
+ *
+ * Description:
+ *	This routine swaps address info of two ports.
+ *
+ * Context:
+ *	runtime, pageable
+ *	may be called after SK_INIT_IO
+ *
+ * Returns:
+ *	SK_ADDR_SUCCESS
+ *	SK_ADDR_ILLEGAL_PORT
+ */
+int	SkAddrSwap(
+SK_AC	*pAC,			/* adapter context */
+SK_IOC	IoC,			/* I/O context */
+SK_U32	FromPortNumber,		/* Port1 Index */
+SK_U32	ToPortNumber)		/* Port2 Index */
+{
+	int			i;
+	SK_U8		Byte;
+	SK_MAC_ADDR	MacAddr;
+
+	if (FromPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+
+	if (ToPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+
+	if (pAC->Rlmt.Port[FromPortNumber].Net != pAC->Rlmt.Port[ToPortNumber].Net) {
+		return (SK_ADDR_ILLEGAL_PORT);
+	}
+
+	/*
+	 * Swap:
+	 * - Exact Match Entries:
+	 *   Yukon uses first entry for the logical MAC
+	 *   address (stored in the second GMAC register).
+	 * - 64-bit filter (InexactFilter)
+	 * - Promiscuous Mode
+	 * of ports.
+	 */
+
+	for (i = 0; i < SK_ADDR_EXACT_MATCHES; i++) {
+		MacAddr = pAC->Addr.Port[FromPortNumber].Exact[i];
+		pAC->Addr.Port[FromPortNumber].Exact[i] =
+			pAC->Addr.Port[ToPortNumber].Exact[i];
+		pAC->Addr.Port[ToPortNumber].Exact[i] = MacAddr;
+	}
+
+	for (i = 0; i < 8; i++) {
+		Byte = pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i];
+		pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i] =
+			pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
+		pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
+	}
+
+	i = pAC->Addr.Port[FromPortNumber].PromMode;
+	pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
+	pAC->Addr.Port[ToPortNumber].PromMode = i;
+
+	/* CAUTION: Solution works if only ports of one adapter are in use. */
+	for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
+		Net->NetNumber].NumPorts; i++) {
+		if (pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber].
+			Port[i]->PortNumber == ToPortNumber) {
+			pAC->Addr.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber].
+				ActivePort = i;
+			/* 20001207 RA: Was "ToPortNumber;". */
+		}
+	}
+
+	(void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
+	(void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
+
+	return (SK_ADDR_SUCCESS);
+
+}	/* SkAddrSwap */
+
+#endif /* !SK_SLIM && !SK_NO_RLMT */
+
+#ifdef __cplusplus
+}
+#endif	/* __cplusplus */
+
diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c
--- linux/drivers/net/sk98lin/skcsum.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skcsum.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1215 @@
+/******************************************************************************
+ *
+ * Name:	skcsum.c
+ * Project:	GEnesis, PCI Gigabit Ethernet Adapter
+ * Version:	$Revision: #3 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Store/verify Internet checksum in send/receive packets.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skcsum.c,v $
+ *	Revision 2.4  2007/03/14 16:20:40  rassmann
+ *	Updated IPv6 header parsing in RX path.
+ *	
+ *	Revision 2.3  2007/02/16 13:06:33  rassmann
+ *	Merged changes from Windows Yukon-Extreme branch:
+ *	- Moved defines for IP header length to header file.
+ *	- Check frame length before accessing the buffer in SkCsGetReceiveInfo.
+ *	- Corrected handling of malformed frames in SkCsGetReceiveInfo.
+ *	- SkCsGetReceiveInfo(): Packets with unknown IPv6 headers are returned as "not checkable".
+ *	Editorial changes.
+ *	
+ *	Revision 2.2  2005/12/14 16:11:26  ibrueder
+ *	added copyright header flags
+ *	
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *	
+ *	Revision 1.1  2003/10/27 14:14:17  amock
+ *	Copied to yukon2 module branch
+ *	
+ *	Revision 1.12  2003/08/20 13:55:53  mschmid
+ *	Changed notation of #ifndef SkCsCalculateChecksum to
+ *	#ifndef SK_CS_CALCULATE_CHECKSUM
+ *	
+ *	Revision 1.11  2003/03/11 14:05:55  rschmidt
+ *	Replaced memset() by macro SK_MEMSET()
+ *	Editorial changes
+ *	
+ *	Revision 1.10  2002/04/11 10:02:04  rwahl
+ *	Fix in SkCsGetSendInfo():
+ *	- function did not return ProtocolFlags in every case.
+ *	- pseudo header csum calculated wrong for big endian.
+ *	
+ *	Revision 1.9  2001/06/13 07:42:08  gklug
+ *	fix: NetNumber was wrong in CLEAR_STAT event
+ *	add: check for good NetNumber in Clear STAT
+ *	
+ *	Revision 1.8  2001/02/06 11:15:36  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *	
+ *	Revision 1.7  2000/06/29 13:17:05  rassmann
+ *	Corrected reception of a packet with UDP checksum == 0 (which means there
+ *	is no UDP checksum).
+ *	
+ *	Revision 1.6  2000/02/21 12:35:10  cgoos
+ *	Fixed license header comment.
+ *	
+ *	Revision 1.5  2000/02/21 11:05:19  cgoos
+ *	Merged changes back to common source.
+ *	Fixed rx path for BIG ENDIAN architecture.
+ *	
+ *	Revision 1.1  1999/07/26 15:28:12  mkarl
+ *	added return SKCS_STATUS_IP_CSUM_ERROR_UDP and
+ *	SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester
+ *	changed from common source to windows specific source
+ *	therefore restarting with v1.0
+ *	
+ *	Revision 1.3  1999/05/10 08:39:33  mkarl
+ *	prevent overflows in SKCS_HTON16
+ *	fixed a bug in pseudo header checksum calculation
+ *	added some comments
+ *	
+ *	Revision 1.2  1998/10/22 11:53:28  swolf
+ *	Now using SK_DBG_MSG.
+ *	
+ *	Revision 1.1  1998/09/01 15:35:41  swolf
+ *	initial revision
+ *
+ *	13-May-1998 sw	Created.
+ *
+ ******************************************************************************/
+
+#ifdef SK_USE_CSUM	/* Check if CSUM is to be used. */
+
+#ifndef lint
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/csum/V5/skcsum.c#3 $ (C) SysKonnect.";
+#endif	/* !lint */
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ * This is the "GEnesis" common module "CSUM".
+ *
+ * This module contains the code necessary to calculate, store, and verify the
+ * Internet Checksum of IP, TCP, and UDP frames.
+ *
+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
+ * and is the code name of this SysKonnect project.
+ *
+ * Compilation Options:
+ *
+ *	SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
+ *	empty module.
+ *
+ *	SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
+ *	definitions. In this case, all SKCS_PROTO_xxx definitions must be made
+ *	external.
+ *
+ *	SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
+ *	definitions. In this case, all SKCS_STATUS_xxx definitions must be made
+ *	external.
+ *
+ * Include File Hierarchy:
+ *
+ *	"h/skdrv1st.h"
+ *	"h/skcsum.h"
+ *	"h/sktypes.h"
+ *	"h/skqueue.h"
+ *	"h/skdrv2nd.h"
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skcsum.h"
+#include "h/skdrv2nd.h"
+
+/* defines ********************************************************************/
+
+/* The size of an Ethernet MAC header. */
+#define SKCS_ETHERNET_MAC_HEADER_SIZE			(6+6+2)
+
+/* The size of the used topology's MAC header. */
+#define	SKCS_MAC_HEADER_SIZE	SKCS_ETHERNET_MAC_HEADER_SIZE
+
+/*
+ * Field offsets within the IPv4 header.
+ */
+
+/* "Internet Header Version" and "Length". */
+#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH	0
+
+/* "Total Length". */
+#define SKCS_OFS_IP_TOTAL_LENGTH				2
+
+/* "Flags" "Fragment Offset". */
+#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET	6
+
+/* "Next Level Protocol" identifier. */
+#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL			9
+
+/* Source IP address. */
+#define SKCS_OFS_IP_SOURCE_ADDRESS				12
+
+/* Destination IP address. */
+#define SKCS_OFS_IP_DESTINATION_ADDRESS			16
+
+#ifdef SK_IPV6_SUPPORT
+/*
+ * Field offsets in the IPv6 header
+ */
+
+/* Payload length field (size without IP header) */
+#define SKCS_OFS_IP6_PAYLOAD_LENGTH				4
+
+/* Next header identifier */
+#define SKCS_OFS_IP6_NEXT_HEADER				6
+
+/* Source IP adress (16 byte) */
+#define SKCS_OFS_IP6_SOURCE_ADDRESS				8
+
+/* Destination IP address (16 byte) */
+#define SKCS_OFS_IP6_DESTINATION_ADDRESS		32
+
+#endif	/* SK_IPV6_SUPPORT */
+
+/*
+ * Field offsets within the UDP header.
+ */
+
+/* UDP checksum. */
+#define SKCS_OFS_UDP_CHECKSUM					6
+
+/* IP "Next Level Protocol" identifiers (see RFC 790). */
+#define SKCS_PROTO_ID_TCP		6	/* Transport Control Protocol */
+#define SKCS_PROTO_ID_UDP		17	/* User Datagram Protocol */
+#ifdef SK_IPV6_SUPPORT
+#define SKCS_PROTO_ID_ICMPV6	58	/* ICMPv6 */
+#define SKCS_PROTO_ID_NONE		59	/* No next header (used with IPv6) */
+#endif	/* SK_IPV6_SUPPORT */
+
+/* IP "Don't Fragment" bit. */
+#define SKCS_IP_DONT_FRAGMENT	SKCS_HTON16(0x4000)
+
+/* Add a byte offset to a pointer. */
+#define SKCS_IDX(pPtr, Ofs)	((void *) ((char *) (pPtr) + (Ofs)))
+
+/* Check whether offset is within buffer. */
+#define SKCS_IDX_CHECK(Le, Ofs)	((Le) <= (Ofs))
+
+/*
+ * Macros that convert host to network representation and vice versa, i.e.
+ * little/big endian conversion on little endian machines only.
+ */
+#ifdef SK_LITTLE_ENDIAN
+#define SKCS_HTON16(Val16)	(((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
+#endif	/* SK_LITTLE_ENDIAN */
+#ifdef SK_BIG_ENDIAN
+#define SKCS_HTON16(Val16)	(Val16)
+#endif	/* SK_BIG_ENDIAN */
+#define SKCS_NTOH16(Val16)	SKCS_HTON16(Val16)
+
+/* typedefs *******************************************************************/
+
+/* function prototypes ********************************************************/
+
+/******************************************************************************
+ *
+ *	SkCsGetSendInfo - get checksum information for a send packet
+ *
+ * Description:
+ *	Get all checksum information necessary to send a TCP or UDP packet. The
+ *	function checks the IP header passed to it. If the high-level protocol
+ *	is either TCP or UDP the pseudo header checksum is calculated and
+ *	returned.
+ *
+ *	The function returns the total length of the IP header (including any
+ *	IP option fields), which is the same as the start offset of the IP data
+ *	which in turn is the start offset of the TCP or UDP header.
+ *
+ *	The function also returns the TCP or UDP pseudo header checksum, which
+ *	should be used as the start value for the hardware checksum calculation.
+ *	(Note that any actual pseudo header checksum can never calculate to
+ *	zero.)
+ *
+ * Note:
+ *	There is a bug in the GENESIS ASIC which may lead to wrong checksums.
+ *
+ * Arguments:
+ *	pAc - A pointer to the adapter context struct.
+ *
+ *	pIpHeader - Pointer to IP header. Must be at least the IP header *not*
+ *	including any option fields, i.e. at least 20 bytes.
+ *
+ *	Note: This pointer will be used to address 8-, 16-, and 32-bit
+ *	variables with the respective alignment offsets relative to the pointer.
+ *	Thus, the pointer should point to a 32-bit aligned address. If the
+ *	target system cannot address 32-bit variables on non 32-bit aligned
+ *	addresses, then the pointer *must* point to a 32-bit aligned address.
+ *
+ *	pPacketInfo - A pointer to the packet information structure for this
+ *	packet. Before calling this SkCsGetSendInfo(), the following field must
+ *	be initialized:
+ *
+ *		ProtocolFlags - Initialize with any combination of
+ *		SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
+ *		the protocols specified here. Any protocol(s) not specified
+ *		here will be ignored.
+ *
+ *		Note: Only one checksum can be calculated in hardware. Thus, if
+ *		SKCS_PROTO_IP is specified in the 'ProtocolFlags',
+ *		SkCsGetSendInfo() must calculate the IP header checksum in
+ *		software. It might be a better idea to have the calling
+ *		protocol stack calculate the IP header checksum.
+ *
+ * Returns: N/A
+ *	On return, the following fields in 'pPacketInfo' may or may not have
+ *	been filled with information, depending on the protocol(s) found in the
+ *	packet:
+ *
+ *	ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
+ *	that were both requested by the caller and actually found in the packet.
+ *	Protocol(s) not specified by the caller and/or not found in the packet
+ *	will have their respective SKCS_PROTO_XXX bit flags reset.
+ *
+ *	Note: For IP fragments, TCP and UDP packet information is ignored.
+ *
+ *	IpHeaderLength - The total length in bytes of the complete IP header
+ *	including any option fields is returned here. This is the start offset
+ *	of the IP data, i.e. the TCP or UDP header if present.
+ *
+ *	IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
+ *	16-bit Internet Checksum of the IP header is returned here. This value
+ *	is to be stored into the packet's 'IP Header Checksum' field.
+ *
+ *	PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
+ *	has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
+ *	of the TCP or UDP pseudo header is returned here.
+ */
+void SkCsGetSendInfo(
+SK_AC				*pAc,			/* Adapter context struct. */
+void				*pIpHeader,		/* IP header. */
+SKCS_PACKET_INFO	*pPacketInfo,	/* Packet information struct. */
+int					NetNumber)		/* Net number */
+{
+	/* Internet Header Version found in IP header. */
+	unsigned InternetHeaderVersion;
+
+	/* Length of the IP header as found in IP header. */
+	unsigned IpHeaderLength;
+
+	/* Bit field specifiying the desired/found protocols. */
+	unsigned ProtocolFlags;
+
+	/* Next level protocol identifier found in IP header. */
+	unsigned NextLevelProtocol;
+
+	/* Length of IP data portion. */
+	unsigned IpDataLength;
+
+	/* TCP/UDP pseudo header checksum. */
+	unsigned long PseudoHeaderChecksum;
+
+	/* Pointer to next level protocol statistics structure. */
+	SKCS_PROTO_STATS *NextLevelProtoStats;
+
+	/* Temporary variable. */
+	unsigned Tmp;
+
+	Tmp = *(SK_U8 *)
+		SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
+
+	/* Get the Internet Header Version (IHV). */
+	/* Note: The IHV is stored in the upper four bits. */
+
+	InternetHeaderVersion = Tmp >> 4;
+
+	/* Check the Internet Header Version. */
+	/* Note: We currently only support IP version 4. */
+
+	if (InternetHeaderVersion != 4) {	/* IPv4? */
+		SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
+			("Tx: Unknown Internet Header Version %u.\n",
+			InternetHeaderVersion));
+		pPacketInfo->ProtocolFlags = 0;
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
+		return;
+	}
+
+	/* Get the IP header length (IHL). */
+	/*
+	 * Note: The IHL is stored in the lower four bits as the number of
+	 * 4-byte words.
+	 */
+
+	IpHeaderLength = (Tmp & 0xf) * 4;
+	pPacketInfo->IpHeaderLength = IpHeaderLength;
+
+	/* Check the IP header length. */
+
+	/* 04-Aug-1998 sw - Really check the IHL? Necessary? */
+
+	if (IpHeaderLength < 5*4) {
+		SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
+			("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
+		pPacketInfo->ProtocolFlags = 0;
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
+		return;
+	}
+
+	/* This is an IPv4 frame with a header of valid length. */
+
+	pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
+
+	/* Check if we should calculate the IP header checksum. */
+
+	ProtocolFlags = pPacketInfo->ProtocolFlags;
+
+	if (ProtocolFlags & SKCS_PROTO_IP) {
+		pPacketInfo->IpHeaderChecksum =
+			SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
+	}
+
+	/* Get the next level protocol identifier. */
+
+	NextLevelProtocol =
+		*(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
+
+	/*
+	 * Check if this is a TCP or UDP frame and if we should calculate the
+	 * TCP/UDP pseudo header checksum.
+	 *
+	 * Also clear all protocol bit flags of protocols not present in the
+	 * frame.
+	 */
+
+	if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
+		NextLevelProtocol == SKCS_PROTO_ID_TCP) {
+		/* TCP/IP frame. */
+		ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
+		NextLevelProtoStats =
+			&pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
+	}
+	else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
+		NextLevelProtocol == SKCS_PROTO_ID_UDP) {
+		/* UDP/IP frame. */
+		ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
+		NextLevelProtoStats =
+			&pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
+	}
+	else {
+		/*
+		 * Either not a TCP or UDP frame and/or TCP/UDP processing not
+		 * specified.
+		 */
+		pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
+		return;
+	}
+
+	/* Check if this is an IP fragment. */
+
+	/*
+	 * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
+	 * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
+	 * and the "More Fragments" are zero, it is *not* a fragment. We can
+	 * easily check both at the same time since they are in the same 16-bit
+	 * word.
+	 */
+
+	if ((*(SK_U16 *)
+		SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
+		~SKCS_IP_DONT_FRAGMENT) != 0) {
+		/* IP fragment; ignore all other protocols. */
+		pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
+		NextLevelProtoStats->TxUnableCts++;
+		return;
+	}
+
+	/*
+	 * Calculate the TCP/UDP pseudo header checksum.
+	 */
+
+	/* Get total length of IP header and data. */
+
+	IpDataLength =
+		*(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
+
+	/* Get length of IP data portion. */
+
+	IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
+
+	/* Calculate the sum of all pseudo header fields (16-bit). */
+
+	PseudoHeaderChecksum =
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
+		(unsigned long) SKCS_HTON16(NextLevelProtocol) +
+		(unsigned long) SKCS_HTON16(IpDataLength);
+	
+	/* Add-in any carries. */
+
+	SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
+
+	/* Add-in any new carry. */
+
+	SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
+
+	pPacketInfo->ProtocolFlags = ProtocolFlags;
+	NextLevelProtoStats->TxOkCts++;	/* Success. */
+}	/* SkCsGetSendInfo */
+
+
+/******************************************************************************
+ *
+ *	SkCsGetReceiveInfo - verify checksum information for a received packet
+ *
+ * Description:
+ *	Verify a received frame's checksum. The function returns a status code
+ *	reflecting the result of the verification.
+ *
+ * Note:
+ *	Before calling this function you have to verify that the frame is
+ *	not padded and Checksum1 and Checksum2 are bigger than 1.
+ *
+ * Arguments:
+ *	pAc - Pointer to adapter context struct.
+ *
+ *	pIpHeader - Pointer to IP header. Must be at least the length in bytes
+ *	of the received IP header including any option fields. For UDP packets,
+ *	8 additional bytes are needed to access the UDP checksum.
+ *
+ *	Note: The actual length of the IP header is stored in the lower four
+ *	bits of the first octet of the IP header as the number of 4-byte words,
+ *	so it must be multiplied by four to get the length in bytes. Thus, the
+ *	maximum IP header length is 15 * 4 = 60 bytes.
+ *
+ *	Checksum1 - The first 16-bit Internet Checksum calculated by the
+ *	hardware starting at the offset returned by SkCsSetReceiveFlags().
+ *
+ *	Checksum2 - The second 16-bit Internet Checksum calculated by the
+ *	hardware starting at the offset returned by SkCsSetReceiveFlags().
+ *
+ *  NetNumber - The net number.
+ *
+ *  Len - The packet length (without MAC header) - never access memory
+ *	behind pIpHeader[Len].
+ *
+ * Returns:
+ *	SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
+ *	SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
+ *	SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
+ *	SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
+ *	SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
+ *	SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
+ *	SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
+ *	SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
+ *	SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
+ *	SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
+ *	SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
+ *	SKCS_STATUS_NO_CSUM_POSSIBLE - Checksum could not be built (various reasons).
+ *
+ *	Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
+ *	returned here can be defined in some header file by the module using CSUM.
+ *	In this way, the calling module can assign return values for its own needs,
+ *	e.g. by assigning bit flags to the individual protocols.
+ */
+SKCS_STATUS SkCsGetReceiveInfo(
+SK_AC		*pAc,		/* Adapter context struct. */
+void		*pIpHeader,	/* IP header. */
+unsigned	Checksum1,	/* Hardware checksum 1. */
+unsigned	Checksum2,	/* Hardware checksum 2. */
+int			NetNumber,	/* Net number. */
+unsigned	Len)		/* Packet length (without MAC header). */
+{
+	/* Internet Header Version found in IP header. */
+	unsigned InternetHeaderVersion;
+
+	/* Length of the IP header as found in IP header. */
+	unsigned IpHeaderLength;
+
+	/* Length of IP data portion. */
+	unsigned IpDataLength;
+
+	/* IP header checksum. */
+	unsigned IpHeaderChecksum;
+
+	/* IP header options checksum, if any. */
+	unsigned IpOptionsChecksum;
+
+	/* IP data checksum, i.e. TCP/UDP checksum. */
+	unsigned IpDataChecksum;
+
+	/* Next level protocol identifier found in IP header. */
+	unsigned NextLevelProtocol;
+
+	/* The checksum of the "next level protocol", i.e. TCP or UDP. */
+	unsigned long NextLevelProtocolChecksum;
+
+	/* Pointer to next level protocol statistics structure. */
+	SKCS_PROTO_STATS *NextLevelProtoStats;
+
+	/* Temporary variable. */
+	unsigned Tmp;
+
+#ifdef SK_IPV6_SUPPORT
+	/* For parsing IPv6 packets */
+	SK_U8	*pDst;
+	SK_U32	ProtCsum;
+	SK_U32	Pseudo;
+	SK_U32	Pseudo2;
+	SK_U16	Offset;
+	SK_U16	NextHeaderOffset;
+	SK_U16	OptSize;
+	SK_U8	NextHeader;
+#endif
+
+	if (SKCS_IDX_CHECK(Len, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH)) {
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+		return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+	}
+
+	Tmp = *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
+
+	/* Get the Internet Header Version (IHV). */
+	/* Note: The IHV is stored in the upper four bits. */
+
+	InternetHeaderVersion = Tmp >> 4;
+
+	/* Check the Internet Header Version. */
+
+#ifdef SK_IPV6_SUPPORT
+	if (InternetHeaderVersion == 6) {	/* IPv6? */
+
+		if ((pAc->Csum.ReceiveFlags[NetNumber] &
+			(SKCS_PROTO_TCPV6 | SKCS_PROTO_UDPV6)) == 0) {
+
+			/* The OS/stack told us not to verify IPv6 checksum. */
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+
+		/* Get the payload length. the payload starts immediately after the
+		 * IPv6 header. This value includes all additional headers!
+		 */
+		 /* first test if the frame has at least the length of the IPv6 header */
+		if (Len < SKCS_IP6_HEADER_SIZE) {
+			pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+		IpDataLength = *(SK_U16 *)
+			SKCS_IDX(pIpHeader, SKCS_OFS_IP6_PAYLOAD_LENGTH);
+		IpDataLength = SKCS_NTOH16(IpDataLength);
+
+		/* Before we can proceed we need to find the protocol frame that
+		 * contains the checksum. We support TCP and UDP.
+		 */
+
+		Offset = SKCS_IP6_HEADER_SIZE;
+		NextHeaderOffset = SKCS_OFS_IP6_NEXT_HEADER;
+		/* this access has been secured by checking frame len against SKCS_IP6_HEADER_SIZE */
+		NextHeader = *(SK_U8 *) SKCS_IDX(pIpHeader, NextHeaderOffset);
+
+		pDst = (SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP6_DESTINATION_ADDRESS);
+
+		do {
+			if ((NextHeader == SKCS_PROTO_ID_TCP) ||
+				(NextHeader == SKCS_PROTO_ID_UDP)) {
+
+				/* We found the TCP/UDP header */
+				break;
+			}
+
+			/* Check type of next header to find "Next Header" field */
+			switch (NextHeader) {
+
+			case 0:		/* hop-by-hop options header	*/
+			case 60:	/* Destination options header	*/
+				NextHeaderOffset = Offset;
+
+				/*
+				 * Calculate the size of the option header. The size is in
+				 * units of 8-octets and does not contain the first 8 octets.
+				 */
+				if (SKCS_IDX_CHECK(Len, (unsigned) (NextHeaderOffset + 1))) {
+					pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+					return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+				}
+				OptSize = *(SK_U8 *) SKCS_IDX(pIpHeader, NextHeaderOffset + 1);
+				OptSize *= 8;
+				Offset += OptSize + 8;
+				break;
+
+			case 43:	/* routing header				*/
+				NextHeaderOffset = Offset;
+
+				/*
+				 * Calculate the size of the option header. The size is in
+				 * units of 8-octets and does not contain the first 8 octets.
+				 */
+				if (SKCS_IDX_CHECK(Len, (unsigned) (NextHeaderOffset + 1))) {
+					pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+					return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+				}
+				OptSize = *(SK_U8 *) SKCS_IDX(pIpHeader, NextHeaderOffset + 1);
+				OptSize *= 8;
+				Offset += OptSize + 8;
+
+				/*
+				 * If SegLeft != 0, use the last address in the routing header
+				 * as IP dst in the pseudo header (for both, type 0 and type 2).
+				 */
+				if (*(SK_U8 *) SKCS_IDX(pIpHeader, NextHeaderOffset + 3) != 0) {
+					SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+						("Rx: IPv6 Routing Header with SegLeft != 0.\n"));
+					pDst = (SK_U8 *) SKCS_IDX(pIpHeader, Offset - 16);
+				}
+				break;
+
+			case 44:	/* fragment header */
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+				return (SKCS_STATUS_IP_FRAGMENT);
+
+			case 46:	/* resource ReSerVation protocol */
+			case 41:	/* encapsulated IPv6 header */
+			case 59:	/* No next header */
+				SK_DBG_MSG(
+					pAc,
+					SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+					("Rx: Header in IPv6 packet can not be processed: %u.\n",
+						NextHeader));
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+				return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+
+			case 51:	/* authentication header, would have to use OptSize *= 4! */
+			case 50:	/* encapsulating security payload */
+			case 58:	/* ICMP v6 */
+			default:
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+				return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+			}
+
+			/* Continue with the next header */
+			if (SKCS_IDX_CHECK(Len, NextHeaderOffset)) {
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+				return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+			}
+			NextHeader = *(SK_U8 *) SKCS_IDX(pIpHeader, NextHeaderOffset);
+		} while (Offset < (IpDataLength + SKCS_IP6_HEADER_SIZE));
+
+		if (Offset >= (IpDataLength + SKCS_IP6_HEADER_SIZE)) {
+			/* We passed the end of the packet without finding the payload. */
+			SK_DBG_MSG(
+				pAc,
+				SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+				("Rx: malformed IPv6 packet.\n"));
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+				return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+
+		/* Before starting checksum calculating, check if we really need to. */
+		if ((NextHeader == SKCS_PROTO_ID_TCP) &&
+			(((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCPV6) == 0))) {
+
+			/* Header is TCP but we shall not verify TCP checksum. */
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+		if ((NextHeader == SKCS_PROTO_ID_UDP) &&
+			(((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDPV6) == 0))) {
+
+			/* Header is UDP but we shall not verify UDP checksum. */
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+
+		if (IpDataLength + SKCS_IP6_HEADER_SIZE > Len) {
+			pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+		ProtCsum = SkCsCalculateChecksum(
+			SKCS_IDX(pIpHeader, Offset),
+			IpDataLength + SKCS_IP6_HEADER_SIZE -Offset);
+
+		/*
+		 * Calculate the pseudo header checksum.
+		 */
+
+		/* Start with src and dest address */
+		/* this access has been secured by checking frame len against SKCS_IP6_HEADER_SIZE */
+		Pseudo = SkCsCalculateChecksum(
+					SKCS_IDX(pIpHeader, SKCS_OFS_IP6_SOURCE_ADDRESS), 16);
+
+		Pseudo2 = SkCsCalculateChecksum(pDst, 16);
+		SKCS_OC_ADD(Pseudo, Pseudo, Pseudo2);
+		SKCS_OC_ADD(Pseudo, Pseudo, 0);		/* Add-in any carries. */
+
+		SKCS_OC_ADD(Pseudo, Pseudo,
+			SKCS_HTON16(IpDataLength + SKCS_IP6_HEADER_SIZE -Offset));
+		SKCS_OC_ADD(Pseudo, Pseudo, SKCS_HTON16(NextHeader));
+		SKCS_OC_ADD(Pseudo, Pseudo, 0);		/* Add-in any carries. */
+
+		/* Add to protocol part's checksum */
+		SKCS_OC_ADD(ProtCsum, ProtCsum, Pseudo);
+		SKCS_OC_ADD(ProtCsum, ProtCsum, 0);	/* Add-in any carries. */
+
+		/*
+		 * Check result. We can only process TCP or UDP.
+		 */
+		switch (NextHeader) {
+		case SKCS_PROTO_ID_TCP:
+			if (ProtCsum != 0xFFFF) {
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP].RxErrCts++;
+				return (SKCS_STATUS_TCP_CSUM_ERROR);
+			}
+			pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP].RxOkCts++;
+			return (SKCS_STATUS_TCP_CSUM_OK);
+
+		case SKCS_PROTO_ID_UDP:
+
+			if (ProtCsum != 0xFFFF) {
+				pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP].RxErrCts++;
+				return (SKCS_STATUS_UDP_CSUM_ERROR);
+			}
+			pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP].RxOkCts++;
+			return (SKCS_STATUS_UDP_CSUM_OK);
+
+		default:
+			/* This case should already be eliminated because we only compute
+			 * the checksum for TCP, UDP or ICMPv6
+			 */
+			return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+		}
+	}
+#endif	/* SK_IPV6_SUPPORT */
+
+	if (InternetHeaderVersion != 4) {	/* IPv4? */
+		SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+			("Rx: Unknown Internet Header Version %u.\n",
+			InternetHeaderVersion));
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+		return (SKCS_STATUS_UNKNOWN_IP_VERSION);
+	}
+
+	/* Get the IP header length (IHL). */
+	/*
+	 * Note: The IHL is stored in the lower four bits as the number of
+	 * 4-byte words.
+	 */
+
+	IpHeaderLength = (Tmp & 0xf) * 4;
+
+	/* Check the IP header length. */
+
+	/* 04-Aug-1998 sw - Really check the IHL? Necessary? */
+
+	if (IpHeaderLength < 5*4) {
+		SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
+			("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
+		return (SKCS_STATUS_IP_CSUM_ERROR);
+	}
+
+	/* This is an IPv4 frame with a header of valid length. */
+
+	/* First test if the frame has at least the length of the IP header. */
+	if (Len < IpHeaderLength) {
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+		return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+	}
+
+	/* Get the IP header and data checksum. */
+	IpDataChecksum = Checksum2;
+
+	/* Get the next level protocol identifier. */
+	/* this access has been secured by checking frame len against IpHeaderLength */
+	NextLevelProtocol = *(SK_U8 *)
+		SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
+
+	if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_IP) != 0) {
+
+		/* IPv4 checksum verification is specified */
+
+		/*
+		 * The IP header checksum is calculated as follows:
+		 *
+		 *	IpHeaderChecksum = Checksum1 - Checksum2
+		 */
+
+		SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
+
+		/* Check if any IP header options. */
+
+		if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
+
+			/*
+			 * Get the IP options checksum.
+			 *
+			 * This access has been secured by checking the frame length
+			 * against IpHeaderLength.
+			 */
+			IpOptionsChecksum = SkCsCalculateChecksum(
+				SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
+				IpHeaderLength - SKCS_IP_HEADER_SIZE);
+
+			/* Adjust the IP header and IP data checksums. */
+
+			SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
+
+			SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
+		}
+
+		/*
+		 * Check if the IP header checksum is ok.
+		 *
+		 * NOTE: We must check the IP header checksum even if the caller
+		 * just wants us to check upper-layer checksums, because we cannot do
+		 * any further processing of the packet without a valid IP checksum.
+		 */
+
+		if (IpHeaderChecksum != 0xffff) {
+			pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
+			/* The NDIS tester wants to know the upper level protocol, too. */
+			if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
+				return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
+			}
+			else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
+				return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
+			}
+			return (SKCS_STATUS_IP_CSUM_ERROR);
+		}
+	}
+
+	/*
+	 * Check if this is a TCP or UDP frame and if we should calculate the
+	 * TCP/UDP pseudo header checksum.
+	 *
+	 * Also clear all protocol bit flags of protocols not present in the
+	 * frame.
+	 */
+
+	if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
+		NextLevelProtocol == SKCS_PROTO_ID_TCP) {
+		/* TCP/IP frame. */
+		NextLevelProtoStats =
+			&pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
+	}
+	else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
+		NextLevelProtocol == SKCS_PROTO_ID_UDP) {
+		/* UDP/IP frame. */
+		NextLevelProtoStats =
+			&pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
+	}
+	else {
+		/*
+		 * Either not a TCP or UDP frame and/or TCP/UDP processing not
+		 * specified.
+		 */
+		return (SKCS_STATUS_IP_CSUM_OK);
+	}
+
+	/* Check if this is an IP fragment. */
+
+	/*
+	 * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
+	 * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
+	 * and the "More Fragments" are zero, it is *not* a fragment. We can
+	 * easily check both at the same time since they are in the same 16-bit
+	 * word.
+	 *
+	 * This access has been secured by checking the frame length
+	 * against IpHeaderLength.
+	 */
+
+	if ((*(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
+		~SKCS_IP_DONT_FRAGMENT) != 0) {
+		/* IP fragment; ignore all other protocols. */
+		NextLevelProtoStats->RxUnableCts++;
+		return (SKCS_STATUS_IP_FRAGMENT);
+	}
+
+	if (SKCS_IDX_CHECK(Len, (IpHeaderLength + 6 + 1))) {
+		pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
+		return (SKCS_STATUS_NO_CSUM_POSSIBLE);
+	}
+
+	/*
+	 * A checksum value of 0 in UDP over IPv4 frames means that no checksum
+	 * was inserted by the sender (RFC 768).
+	 */
+
+	if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
+		*(SK_U16 *) SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
+
+		NextLevelProtoStats->RxOkCts++;
+		
+		return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
+	}
+
+	/*
+	 * Calculate the TCP/UDP checksum.
+	 */
+
+	/*
+	 * Get total length of IP header and data.
+	 *
+	 * This access has been secured by checking the frame length
+	 * against IpHeaderLength.
+	 */
+
+	IpDataLength =
+		*(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
+
+	/* Get length of IP data portion. */
+
+	IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
+
+	/*
+	 * This access has been secured by checking the frame length
+	 * against IpHeaderLength.
+	 */
+
+	NextLevelProtocolChecksum =
+
+		/* Calculate the pseudo header checksum. */
+
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
+		(unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
+			SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
+		(unsigned long) SKCS_HTON16(NextLevelProtocol) +
+		(unsigned long) SKCS_HTON16(IpDataLength) +
+
+		/* Add the TCP/UDP header checksum. */
+
+		(unsigned long) IpDataChecksum;
+
+	/* Add-in any carries. */
+
+	SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
+
+	/* Add-in any new carry. */
+
+	SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
+
+	/* Check if the TCP/UDP checksum is ok. */
+
+	if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
+
+		/* TCP/UDP checksum ok. */
+
+		NextLevelProtoStats->RxOkCts++;
+
+		return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
+			SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
+	}
+	
+	/* TCP/UDP checksum error. */
+
+	NextLevelProtoStats->RxErrCts++;
+
+	return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
+		SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
+}	/* SkCsGetReceiveInfo */
+
+
+/******************************************************************************
+ *
+ *	SkCsSetReceiveFlags - set checksum receive flags
+ *
+ * Description:
+ *	Use this function to set the various receive flags. According to the
+ *	protocol flags set by the caller, the start offsets within received
+ *	packets of the two hardware checksums are returned. These offsets must
+ *	be stored in all receive descriptors.
+ *
+ * Arguments:
+ *	pAc - Pointer to adapter context struct.
+ *
+ *	ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
+ *	for which the caller wants checksum information on received frames.
+ *
+ *	pChecksum1Offset - The start offset of the first receive descriptor
+ *	hardware checksum to be calculated for received frames is returned
+ *	here.
+ *
+ *	pChecksum2Offset - The start offset of the second receive descriptor
+ *	hardware checksum to be calculated for received frames is returned
+ *	here.
+ *
+ * Returns: N/A
+ *	Returns the two hardware checksum start offsets.
+ */
+void SkCsSetReceiveFlags(
+SK_AC		*pAc,				/* Adapter context struct. */
+unsigned	ReceiveFlags,		/* New receive flags. */
+unsigned	*pChecksum1Offset,	/* Offset for hardware checksum 1. */
+unsigned	*pChecksum2Offset,	/* Offset for hardware checksum 2. */
+int			NetNumber)
+{
+	/* Save the receive flags. */
+
+	pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
+
+	/* First checksum start offset is the IP header. */
+	*pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
+
+	/*
+	 * Second checksum start offset is the IP data. Note that this may vary
+	 * if there are any IP header options in the actual packet.
+	 */
+	*pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
+}	/* SkCsSetReceiveFlags */
+
+#ifndef SK_CS_CALCULATE_CHECKSUM
+
+/******************************************************************************
+ *
+ *	SkCsCalculateChecksum - calculate checksum for specified data
+ *
+ * Description:
+ *	Calculate and return the 16-bit Internet Checksum for the specified
+ *	data.
+ *
+ * Arguments:
+ *	pData - Pointer to data for which the checksum shall be calculated.
+ *	Note: The pointer should be aligned on a 16-bit boundary.
+ *
+ *	Length - Length in bytes of data to checksum.
+ *
+ * Returns:
+ *	The 16-bit Internet Checksum for the specified data.
+ *
+ *	Note: The checksum is calculated in the machine's natural byte order,
+ *	i.e. little vs. big endian. Thus, the resulting checksum is different
+ *	for the same input data on little and big endian machines.
+ *
+ *	However, when written back to the network packet, the byte order is
+ *	always in correct network order.
+ */
+unsigned SkCsCalculateChecksum(
+void		*pData,		/* Data to checksum. */
+unsigned	Length)		/* Length of data. */
+{
+	SK_U16 *pU16;		/* Pointer to the data as 16-bit words. */
+	unsigned long Checksum;	/* Checksum; must be at least 32 bits. */
+
+	/* Sum up all 16-bit words. */
+
+	pU16 = (SK_U16 *) pData;
+	for (Checksum = 0; Length > 1; Length -= 2) {
+		Checksum += *pU16++;
+	}
+
+	/* If this is an odd number of bytes, add-in the last byte. */
+
+	if (Length > 0) {
+#ifdef SK_BIG_ENDIAN
+		/* Add the last byte as the high byte. */
+		Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
+#else	/* !SK_BIG_ENDIAN */
+		/* Add the last byte as the low byte. */
+		Checksum += *(SK_U8 *) pU16;
+#endif	/* !SK_BIG_ENDIAN */
+	}
+
+	/* Add-in any carries. */
+
+	SKCS_OC_ADD(Checksum, Checksum, 0);
+
+	/* Add-in any new carry. */
+
+	SKCS_OC_ADD(Checksum, Checksum, 0);
+
+	/* Note: All bits beyond the 16-bit limit are now zero. */
+
+	return ((unsigned) Checksum);
+}	/* SkCsCalculateChecksum */
+
+#endif /* SK_CS_CALCULATE_CHECKSUM */
+
+/******************************************************************************
+ *
+ *	SkCsEvent - the CSUM event dispatcher
+ *
+ * Description:
+ *	This is the event handler for the CSUM module.
+ *
+ * Arguments:
+ *	pAc - Pointer to adapter context.
+ *
+ *	Ioc - I/O context.
+ *
+ *	Event -	 Event id.
+ *
+ *	Param - Event dependent parameter.
+ *
+ * Returns:
+ *	0 (Success)
+ */
+int SkCsEvent(
+SK_AC		*pAc,	/* Pointer to adapter context. */
+SK_IOC		Ioc,	/* I/O context. */
+SK_U32		Event,	/* Event id. */
+SK_EVPARA	Param)	/* Event dependent parameter. */
+{
+	int ProtoIndex;
+	int	NetNumber;
+
+	switch (Event) {
+	/*
+	 * Clear protocol statistics.
+	 *
+	 * Param - Protocol index, or -1 for all protocols.
+	 *		 - Net number.
+	 */
+	case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
+		ProtoIndex = (int)Param.Para32[1];
+		NetNumber = (int)Param.Para32[0];
+		if (ProtoIndex < 0) {	/* Clear for all protocols. */
+			if (NetNumber >= 0) {
+				SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
+					sizeof(pAc->Csum.ProtoStats[NetNumber]));
+			}
+		}
+		else {					/* Clear for individual protocol. */
+			SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
+				sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
+		}
+		break;
+
+	default:
+		break;
+	}
+	return (0);	/* Success. */
+}	/* SkCsEvent */
+
+#endif	/* SK_USE_CSUM */
diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c
--- linux/drivers/net/sk98lin/skdim.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skdim.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,386 @@
+/******************************************************************************
+ *
+ * Name:        skdim.c
+ * Project:     GEnesis, PCI Gigabit Ethernet Adapter
+ * Purpose:     All functions regardig interrupt moderation
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	    (C)Copyright 1998-2002 SysKonnect GmbH.
+ *	    (C)Copyright 2002-2011 Marvell.
+ *
+ *	    Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	    Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/******************************************************************************
+ *
+ * Local Function Prototypes
+ *
+ *****************************************************************************/
+
+static SK_U64 getIsrCalls(SK_AC *pAC);
+static SK_BOOL isIntModEnabled(SK_AC *pAC);
+static void setCurrIntCtr(SK_AC *pAC);
+static void enableIntMod(SK_AC *pAC);
+static void disableIntMod(SK_AC *pAC);
+
+#define M_DIMINFO pAC->DynIrqModInfo
+
+/******************************************************************************
+ *
+ * Global Functions
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *
+ * 	SkDimModerate - Moderates the IRQs depending on the current needs
+ *
+ * Description:
+ *	Moderation of IRQs depends on the number of occurred IRQs with
+ *	respect to the previous moderation cycle.
+ *
+ * Returns:	N/A
+ *
+ */
+void SkDimModerate(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	SK_U64  IsrCalls = getIsrCalls(pAC);
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
+
+	if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
+		if (isIntModEnabled(pAC)) {
+			if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
+				disableIntMod(pAC);
+			}
+		} else {
+			if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
+				enableIntMod(pAC);
+			}
+		}
+	}
+	setCurrIntCtr(pAC);
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkDimStartModerationTimer - Starts the moderation timer
+ *
+ * Description:
+ *	Dynamic interrupt moderation is regularly checked using the
+ *	so-called moderation timer. This timer is started with this function.
+ *
+ * Returns:	N/A
+ */
+void SkDimStartModerationTimer(
+SK_AC *pAC) /* pointer to adapter control context */
+{
+	SK_EVPARA   EventParam;   /* Event struct for timer event */
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("==> SkDimStartModerationTimer\n"));
+
+	if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
+		SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
+		EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
+		SkTimerStart(pAC, pAC->IoBase,
+			&pAC->DynIrqModInfo.ModTimer,
+			pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
+			SKGE_DRV, SK_DRV_TIMER, EventParam);
+	}
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== SkDimStartModerationTimer\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
+ *
+ * Description:
+ *	This function effectively initializes the IRQ moderation of a network
+ *	adapter. Depending on the configuration, this might be either static
+ *	or dynamic. If no moderation is configured, this function will do
+ *	nothing.
+ *
+ * Returns:	N/A
+ */
+void SkDimEnableModerationIfNeeded(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("==> SkDimEnableModerationIfNeeded\n"));
+
+	if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
+		if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
+			enableIntMod(pAC);
+		} else { /* must be C_INT_MOD_DYNAMIC */
+			SkDimStartModerationTimer(pAC);
+		}
+	}
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== SkDimEnableModerationIfNeeded\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkDimDisableModeration - disables moderation if it is enabled
+ *
+ * Description:
+ *	Disabling of the moderation requires that is enabled already.
+ *
+ * Returns:	N/A
+ */
+void SkDimDisableModeration(
+SK_AC  *pAC,                /* pointer to adapter control context */
+int     CurrentModeration)  /* type of current moderation         */
+{
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("==> SkDimDisableModeration\n"));
+
+	if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
+		if (CurrentModeration == C_INT_MOD_STATIC) {
+			disableIntMod(pAC);
+		} else { /* must be C_INT_MOD_DYNAMIC */
+			SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
+			disableIntMod(pAC);
+		}
+	}
+
+	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== SkDimDisableModeration\n"));
+}
+
+/******************************************************************************
+ *
+ * Local Functions
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *
+ * 	getIsrCalls - evaluate the number of IRQs handled in mod interval
+ *
+ * Description:
+ *	Depending on the selected moderation mask, this function will return
+ *	the number of interrupts handled in the previous moderation interval.
+ *	This evaluated number is based on the current number of interrupts
+ *	stored in PNMI-context and the previous stored interrupts.
+ *
+ * Returns:
+ *	the number of IRQs handled
+ */
+static SK_U64 getIsrCalls(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	SK_U64   RxPort0IntDiff = 0, RxPort1IntDiff = 0;
+	SK_U64   TxPort0IntDiff = 0, TxPort1IntDiff = 0;
+	SK_U64   StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
+
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
+		    (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
+			if (pAC->GIni.GIMacsFound == 2) {
+				TxPort1IntDiff =
+					pAC->Pnmi.Port[1].TxIntrCts -
+					M_DIMINFO.PrevPort1TxIntrCts;
+			}
+			TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
+					M_DIMINFO.PrevPort0TxIntrCts;
+		} else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
+		           (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
+			if (pAC->GIni.GIMacsFound == 2) {
+				RxPort1IntDiff =
+					pAC->Pnmi.Port[1].RxIntrCts -
+					M_DIMINFO.PrevPort1RxIntrCts;
+			}
+			RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
+					M_DIMINFO.PrevPort0RxIntrCts;
+		} else {
+			if (pAC->GIni.GIMacsFound == 2) {
+				RxPort1IntDiff =
+					pAC->Pnmi.Port[1].RxIntrCts -
+					M_DIMINFO.PrevPort1RxIntrCts;
+				TxPort1IntDiff =
+					pAC->Pnmi.Port[1].TxIntrCts -
+					M_DIMINFO.PrevPort1TxIntrCts;
+			}
+			RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
+					M_DIMINFO.PrevPort0RxIntrCts;
+			TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
+					M_DIMINFO.PrevPort0TxIntrCts;
+		}
+        	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+				("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
+		return (RxPort0IntDiff + RxPort1IntDiff +
+		        TxPort0IntDiff + TxPort1IntDiff);
+	}
+
+	/*
+	** We have a Yukon2 compliant chipset if we come up to here
+	**
+	if (pAC->GIni.GIMacsFound == 2) {
+		StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
+					M_DIMINFO.PrevPort1StatusIntrCts;
+	}
+	StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
+				M_DIMINFO.PrevPort0StatusIntrCts;
+	*/
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
+	return (StatusPort0IntDiff + StatusPort1IntDiff);
+}
+
+/*****************************************************************************
+ *
+ * 	setCurrIntCtr - stores the current number of interrupts
+ *
+ * Description:
+ *	Stores the current number of occurred interrupts in the adapter
+ *	context. This is needed to evaluate the  umber of interrupts within
+ *	the moderation interval.
+ *
+ * Returns:	N/A
+ *
+ */
+static void setCurrIntCtr(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		if (pAC->GIni.GIMacsFound == 2) {
+			M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
+			M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
+		}
+		M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
+		M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
+        	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+				("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
+		return;
+	}
+
+	/*
+	** We have a Yukon2 compliant chipset if we come up to here
+	**
+	if (pAC->GIni.GIMacsFound == 2) {
+		M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
+	}
+	M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
+	*/
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	isIntModEnabled - returns the current state of interrupt moderation
+ *
+ * Description:
+ *	This function retrieves the current value of the interrupt moderation
+ *	command register. Its content determines whether any moderation is
+ *	running or not.
+ *
+ * Returns:
+ *	SK_TRUE : IRQ moderation is currently active
+ *	SK_FALSE: No IRQ moderation is active
+ */
+static SK_BOOL isIntModEnabled(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	unsigned long CtrCmd;
+
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
+
+	SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
+	if ((CtrCmd & TIM_START) == TIM_START) {
+        	SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== isIntModEnabled (SK_TRUE)\n"));
+		return SK_TRUE;
+	}
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
+			("<== isIntModEnabled (SK_FALSE)\n"));
+	return SK_FALSE;
+}
+
+/*****************************************************************************
+ *
+ * 	enableIntMod - enables the interrupt moderation
+ *
+ * Description:
+ *	Enabling the interrupt moderation is done by putting the desired
+ *	moderation interval in the B2_IRQM_INI register, specifying the
+ *	desired maks in the B2_IRQM_MSK register and finally starting the
+ *	IRQ moderation timer using the B2_IRQM_CTRL register.
+ *
+ * Returns:	N/A
+ *
+ */
+static void enableIntMod(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	unsigned long ModBase;
+
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
+	ModBase = ((62500L/100) * pAC->GIni.GIHstClkFact * 1000) / M_DIMINFO.MaxModIntsPerSec;
+
+	SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
+	SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
+	SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
+
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	disableIntMod - disables the interrupt moderation
+ *
+ * Description:
+ *	Disabling the interrupt moderation is done by stopping the
+ *	IRQ moderation timer using the B2_IRQM_CTRL register.
+ *
+ * Returns:	N/A
+ *
+ */
+static void disableIntMod(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
+
+	SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
+
+        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
+}
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c
--- linux/drivers/net/sk98lin/skethtool.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skethtool.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1268 @@
+/******************************************************************************
+ *
+ * Name:        skethtool.c
+ * Project:     Yukon/Yukon2, PCI Gigabit Ethernet Adapter
+ * Purpose:     All functions regarding ethtool handling
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	    (C)Copyright 1998-2002 SysKonnect GmbH.
+ *	    (C)Copyright 2002-2011 Marvell.
+ *
+ *	    Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	    Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include "h/skversion.h"
+#include <linux/ethtool.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+
+/******************************************************************************
+ *
+ * Local Functions
+ *
+ *****************************************************************************/
+static void toggleLeds(unsigned long ptr);
+
+/******************************************************************************
+ *
+ * External Functions and Data
+ *
+ *****************************************************************************/
+
+extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
+
+/******************************************************************************
+ *
+ * Defines
+ *
+ *****************************************************************************/
+
+#ifndef ETHT_STATSTRING_LEN
+#define ETHT_STATSTRING_LEN 32
+#endif
+
+#define SK98LIN_STAT(m)	sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
+
+#define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half  | SUPPORTED_10baseT_Full  | \
+                         SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
+                         SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
+                         SUPPORTED_TP)
+
+#define ADV_COPPER_ALL  (ADVERTISED_10baseT_Half  | ADVERTISED_10baseT_Full  | \
+                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
+                         ADVERTISED_1000baseT_Half| ADVERTISED_1000baseT_Full| \
+                         ADVERTISED_TP)
+
+#define SUPP_FIBRE_ALL  (SUPPORTED_1000baseT_Full | \
+                         SUPPORTED_FIBRE          | \
+                         SUPPORTED_Autoneg)
+
+#define ADV_FIBRE_ALL   (ADVERTISED_1000baseT_Full | \
+                         ADVERTISED_FIBRE          | \
+                         ADVERTISED_Autoneg)
+
+struct sk98lin_stats {
+	char stat_string[ETHT_STATSTRING_LEN];
+	int  sizeof_stat;
+	int  stat_offset;
+};
+
+static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
+	{ "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
+	{ "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
+	{ "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
+	{ "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
+	{ "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
+	{ "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
+	{ "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
+	{ "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
+	{ "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
+	{ "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
+	{ "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
+	{ "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
+	{ "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
+	{ "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
+	{ "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
+	{ "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
+	{ "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
+	{ "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
+	{ "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
+	{ "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
+	{ "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
+	{ "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
+	{ "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
+	{ "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
+	{ "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
+	{ "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
+	{ "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
+};
+
+static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
+	{ "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
+	{ "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
+	{ "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
+	{ "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
+	{ "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
+	{ "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
+	{ "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
+	{ "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
+	{ "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
+	{ "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
+	{ "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
+	{ "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
+	{ "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
+	{ "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
+	{ "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
+	{ "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
+	{ "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
+	{ "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
+	{ "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
+	{ "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
+	{ "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
+	{ "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
+	{ "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
+	{ "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
+	{ "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
+	{ "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
+	{ "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
+};
+
+static int DuplexAutoNegConfMap[9][3]= {
+	{ -1                     , -1         , -1              },
+	{ 0                      , -1         , -1              },
+	{ SK_LMODE_HALF          , DUPLEX_HALF, AUTONEG_DISABLE },
+	{ SK_LMODE_FULL          , DUPLEX_FULL, AUTONEG_DISABLE },
+	{ SK_LMODE_AUTOHALF      , DUPLEX_HALF, AUTONEG_ENABLE  },
+	{ SK_LMODE_AUTOFULL      , DUPLEX_FULL, AUTONEG_ENABLE  },
+	{ SK_LMODE_AUTOBOTH      , DUPLEX_FULL, AUTONEG_ENABLE  },
+	{ SK_LMODE_AUTOSENSE     , -1         , -1              },
+	{ SK_LMODE_INDETERMINATED, -1         , -1              }
+};
+
+static int SpeedConfMap[6][2] = {
+	{ 0                       , -1         },
+	{ SK_LSPEED_AUTO          , -1         },
+	{ SK_LSPEED_10MBPS        , SPEED_10   },
+	{ SK_LSPEED_100MBPS       , SPEED_100  },
+	{ SK_LSPEED_1000MBPS      , SPEED_1000 },
+	{ SK_LSPEED_INDETERMINATED, -1         }
+};
+
+static int AdvSpeedMap[6][2] = {
+	{ 0                       , -1         },
+	{ SK_LSPEED_AUTO          , -1         },
+	{ SK_LSPEED_10MBPS        , ADVERTISED_10baseT_Half   | ADVERTISED_10baseT_Full },
+	{ SK_LSPEED_100MBPS       , ADVERTISED_100baseT_Half  | ADVERTISED_100baseT_Full },
+	{ SK_LSPEED_1000MBPS      , ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full},
+	{ SK_LSPEED_INDETERMINATED, -1         }
+};
+
+#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
+
+static int nbrBlinkQuarterSeconds;
+static int currentPortIndex;
+static SK_BOOL isLocateNICrunning   = SK_FALSE;
+static SK_BOOL isDualNetCard        = SK_FALSE;
+static SK_BOOL doSwitchLEDsOn       = SK_FALSE;
+static SK_BOOL boardWasDown[2]      = { SK_FALSE, SK_FALSE };
+static struct timer_list locateNICtimer;
+
+
+/******************************************************************************
+ *
+ * Ethtool Functions
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *
+ * 	SkGeGetSettings - retrieves the current settings of the selected adapter
+ *
+ * Description:
+ *	The current configuration of the selected adapter is returned.
+ *	This configuration involves a)speed, b)duplex and c)autoneg plus
+ *	a number of other variables.
+ *
+ * Returns:	N/A
+ *
+ */
+int SkGeGetSettings(struct net_device *dev,
+			struct ethtool_cmd *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+	SK_GEPORT		*pPort       = &pAC->GIni.GP[port];
+
+	ecmd->phy_address = port;
+	ecmd->speed       = SpeedConfMap[pPort->PLinkSpeedUsed][1];
+	ecmd->duplex      = DuplexAutoNegConfMap[pPort->PLinkModeStatus][1];
+	ecmd->autoneg     = DuplexAutoNegConfMap[pPort->PLinkModeStatus][2];
+	ecmd->transceiver = XCVR_INTERNAL;
+
+	if (pAC->GIni.GICopperType) {
+		ecmd->port        = PORT_TP;
+		ecmd->supported   = (SUPP_COPPER_ALL|SUPPORTED_Autoneg);
+		ecmd->supported   &= ~(SUPPORTED_1000baseT_Half);
+
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
+			ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
+		}
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P)) {
+			ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
+			ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
+		}
+
+		if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
+			ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
+			if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
+				ecmd->advertising &= ~(SUPPORTED_1000baseT_Half);
+			}
+		} else {
+			ecmd->advertising = ecmd->supported;
+		}
+		if (ecmd->autoneg == AUTONEG_ENABLE) {
+			ecmd->advertising |= ADVERTISED_Autoneg;
+		} else {
+			ecmd->advertising = ADVERTISED_TP;
+		}
+	} else {
+		ecmd->port        = PORT_FIBRE;
+		ecmd->supported   = (SUPP_FIBRE_ALL);
+		ecmd->advertising = (ADV_FIBRE_ALL);
+	}
+	return(0);
+}
+
+
+
+/*****************************************************************************
+ *
+ * 	SkGeGetDrvInfo - returns generic driver and adapter information
+ *
+ * Description:
+ *	Generic driver information is returned via this function, such as
+ *	the name of the driver, its version and and firmware version.
+ *	In addition to this, the location of the selected adapter is
+ *	returned as a bus info string (e.g. '01:05.0').
+ *
+ * Returns:	N/A
+ *
+ */
+void SkGeGetDrvInfo(struct net_device *dev,
+			struct ethtool_drvinfo *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	char			versionString[32];
+
+	snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
+	strncpy(ecmd->driver, DRIVER_FILE_NAME , 32);
+	strncpy(ecmd->version, versionString , 32);
+	strncpy(ecmd->fw_version, "N/A", 32);
+	strncpy(ecmd->bus_info, pci_name(pAC->PciDev), 32);
+	ecmd->n_stats = SK98LIN_STATS_LEN;
+}
+
+/*****************************************************************************
+ *
+ * 	SkGeGetWolSettings - retrieves the WOL settings of the
+ *	selected adapter
+ *
+ * Description:
+ *	All current WOL settings of a selected adapter are placed in the
+ *	passed ethtool_wolinfo structure and are returned to the caller.
+ *
+ * Returns:	N/A
+ *
+ */
+void SkGeGetWolSettings(struct net_device *dev,
+			struct ethtool_wolinfo *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+
+	ecmd->supported = pAC->WolInfo.SupportedWolOptions;
+	ecmd->wolopts   = pAC->WolInfo.ConfiguredWolOptions;
+}
+
+/*****************************************************************************
+ *
+ * 	SkGeGetPauseParam - retrieves the pause parameters
+ *
+ * Description:
+ *	All current pause parameters of a selected adapter are placed
+ *	in the passed ethtool_pauseparam structure and are returned.
+ *
+ * Returns:	N/A
+ *
+ */
+void SkGeGetPauseParam(struct net_device *dev,
+			struct ethtool_pauseparam *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+	SK_GEPORT		*pPort       = &pAC->GIni.GP[port];
+
+	/* Get the pause parameters */
+	ecmd->rx_pause = 0;
+	ecmd->tx_pause = 0;
+
+	if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
+		ecmd->tx_pause = 1;
+	}
+
+	if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
+	    (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
+		ecmd->rx_pause = 1;
+		ecmd->tx_pause = 1;
+	}
+
+	/* Check the autoneg value */
+	ecmd->autoneg = 0;
+	ecmd->autoneg = pPort->PLinkMode != SK_LMODE_HALF &&
+		pPort->PLinkMode != SK_LMODE_FULL;
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeGetCoalesce - retrieves the IRQ moderation settings
+ *
+ * Description:
+ *	All current IRQ moderation settings of a selected adapter are placed
+ *	in the passed ethtool_coalesce structure and are returned.
+ *
+ * Returns:	N/A
+ *
+ */
+int SkGeGetCoalesce(struct net_device *dev,
+			struct ethtool_coalesce *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+
+	DIM_INFO *Info = &pAC->DynIrqModInfo;
+	SK_BOOL UseTxIrqModeration = SK_FALSE;
+	SK_BOOL UseRxIrqModeration = SK_FALSE;
+
+	if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
+		if (CHIP_ID_YUKON_2(pAC)) {
+			UseRxIrqModeration = SK_TRUE;
+			UseTxIrqModeration = SK_TRUE;
+		} else {
+			if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
+			    (Info->MaskIrqModeration == IRQ_MASK_SP_RX)   ||
+			    (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
+				UseRxIrqModeration = SK_TRUE;
+			}
+			if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
+			    (Info->MaskIrqModeration == IRQ_MASK_SP_TX)   ||
+			    (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
+				UseTxIrqModeration = SK_TRUE;
+			}
+		}
+
+		if (UseRxIrqModeration) {
+			ecmd->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
+		}
+		if (UseTxIrqModeration) {
+			ecmd->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
+		}
+		if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
+			ecmd->rate_sample_interval = Info->DynIrqModSampleInterval;
+			if (UseRxIrqModeration) {
+				ecmd->use_adaptive_rx_coalesce = 1;
+				ecmd->rx_coalesce_usecs_low =
+					1000000 / Info->MaxModIntsPerSecLowerLimit;
+				ecmd->rx_coalesce_usecs_high =
+					1000000 / Info->MaxModIntsPerSecUpperLimit;
+			}
+			if (UseTxIrqModeration) {
+				ecmd->use_adaptive_tx_coalesce = 1;
+				ecmd->tx_coalesce_usecs_low =
+					1000000 / Info->MaxModIntsPerSecLowerLimit;
+				ecmd->tx_coalesce_usecs_high =
+					1000000 / Info->MaxModIntsPerSecUpperLimit;
+			}
+		}
+	}
+	return(0);
+}
+
+/*****************************************************************************
+ *
+ * 	SkGeGetRxCsum - retrieves the RxCsum parameters
+ *
+ * Description:
+ *	All current RxCsum parameters of a selected adapter are placed
+ *	in the passed net_device structure and are returned.
+ *
+ * Returns:	N/A
+ *
+ */
+SK_U32 SkGeGetRxCsum(struct net_device *dev)
+{
+
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+
+	return pAC->RxPort[port].UseRxCsum;
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeGetStrings - retrieves the statistic strings
+ *
+ * Description:
+ *	N/A
+ *
+ * Returns:	N/A
+ *
+ */
+void SkGeGetStrings(struct net_device *dev,
+	u32 stringset,
+	u8 *strings)
+{
+	DEV_NET	*pNet     = PPRIV;
+	int	port      = pNet->PortNr;
+	int	i;
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,19)
+	struct sk98lin_stats *sk98lin_etht_stats =
+		(port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
+
+	switch(stringset) {
+		case ETH_SS_STATS: {
+			for(i=0; i < SK98LIN_STATS_LEN; i++) {
+				memcpy(&strings[i * ETHT_STATSTRING_LEN],
+					&(sk98lin_etht_stats[i].stat_string),
+					ETHT_STATSTRING_LEN);
+			}
+			break;
+		}
+	}
+#endif
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeGetStatsLen - retrieves the statistic count
+ *
+ * Description:
+ *	N/A
+ *
+ * Returns:	N/A
+ *
+ */
+int SkGeGetStatsLen(struct net_device *dev)
+{
+	return SK98LIN_STATS_LEN;
+}
+
+/*****************************************************************************
+ *
+ * 	 SkGeGetSsetCount - retrieves the new statistic count
+ *
+ * Description:
+ *	N/A
+ *
+ * Returns:	N/A
+ *
+ */
+int SkGeGetSsetCount(struct net_device *dev, int sset)
+{
+        switch (sset) {
+        case ETH_SS_STATS:
+                return SK98LIN_STATS_LEN;
+        default:
+                return -EOPNOTSUPP;
+        }
+}
+
+/*****************************************************************************
+ *
+ * 	SkGeGetEthStats - retrieves the card statistics
+ *
+ * Description:
+ *	All current statistics of a selected adapter are placed
+ *	in the passed ethtool_stats structure and are returned.
+ *
+ * Returns:	N/A
+ *
+ */
+void SkGeGetEthStats(struct net_device *dev,
+			struct ethtool_stats *stats,
+			u64 *data)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	SK_U32			Size         = sizeof(SK_PNMI_STRUCT_DATA);
+	SK_PNMI_STRUCT_DATA     *pPnmiStruct = &pAC->PnmiStruct;
+	int			port         = pNet->PortNr;
+	int			i;
+
+	struct sk98lin_stats *sk98lin_etht_stats =
+		(port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
+
+	if (netif_running(pAC->dev[port])) {
+		SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
+	}
+
+	for(i = 0; i < SK98LIN_STATS_LEN; i++) {
+		if (netif_running(pAC->dev[port])) {
+			data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
+				sizeof(uint64_t)) ?
+				*(uint64_t *)((char *)pAC +
+				sk98lin_etht_stats[i].stat_offset) :
+				*(uint32_t *)((char *)pAC +
+				sk98lin_etht_stats[i].stat_offset);
+		} else {
+			data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
+				sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
+		}
+	}
+}
+
+
+/*****************************************************************************
+ *
+ *	SkGeSetSettings - configures the settings of a selected adapter
+ *
+ * Description:
+ *	Possible settings that may be altered are a)speed, b)duplex or
+ *	c)autonegotiation.
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetSettings(struct net_device *dev,
+			struct ethtool_cmd *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+
+	SK_U32       Instance;
+	char         Buf[4];
+	unsigned int Len = 1;
+	int Ret;
+
+	if (port == 0) {
+		Instance = (pAC->RlmtNets == 2) ? 1 : 2;
+	} else {
+		Instance = (pAC->RlmtNets == 2) ? 2 : 3;
+	}
+
+	/* Not supported configuration */
+	if ((ecmd->autoneg == AUTONEG_DISABLE) && (ecmd->speed == SPEED_1000) &&
+		(ecmd->duplex == DUPLEX_HALF)) {
+		printk("Unsupported speed/duplex configuration. 1000HD not available.\n");
+		return -EINVAL;
+	}
+
+	if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
+	    ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
+		if (ecmd->autoneg == AUTONEG_DISABLE) {
+			if (ecmd->duplex == DUPLEX_FULL) {
+				*Buf = (char) SK_LMODE_FULL;
+			} else {
+				*Buf = (char) SK_LMODE_HALF;
+			}
+		} else {
+		/* Autoneg on. Enable autoparam */
+			*Buf = (char) SK_LMODE_AUTOBOTH;
+		}
+
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
+					&Buf, &Len, Instance, pNet->NetNr);
+
+		if (Ret != SK_PNMI_ERR_OK) {
+			return -EINVAL;
+		} else {
+		/* Set the parameter */
+			pAC->LinkInfo[port].PLinkModeConf = (int) *Buf;
+		}
+	} else if (ecmd->autoneg == AUTONEG_ENABLE) {
+	/* Set default values */
+		*Buf = (char) SK_LMODE_AUTOBOTH;
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
+					&Buf, &Len, Instance, pNet->NetNr);
+		pAC->LinkInfo[port].PLinkModeConf = SK_LMODE_AUTOBOTH;
+	}
+
+	if ((ecmd->speed == SPEED_1000) ||
+	    (ecmd->speed == SPEED_100)  ||
+	    (ecmd->speed == SPEED_10)) {
+
+		if (ecmd->autoneg == AUTONEG_ENABLE) {
+			*Buf = (char) SK_LSPEED_AUTO;
+		} else if (ecmd->speed == SPEED_1000) {
+			*Buf = (char) SK_LSPEED_1000MBPS;
+		} else if (ecmd->speed == SPEED_100) {
+			*Buf = (char) SK_LSPEED_100MBPS;
+		} else {
+			*Buf = (char) SK_LSPEED_10MBPS;
+		}
+
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
+					&Buf, &Len, Instance, pNet->NetNr);
+
+		if (Ret != SK_PNMI_ERR_OK) {
+			return -EINVAL;
+		} else {
+			pAC->LinkInfo[port].PLinkSpeed = (int) *Buf;
+		}
+	} else if (ecmd->autoneg == AUTONEG_ENABLE) {
+		*Buf = (char) SK_LSPEED_AUTO;
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
+					&Buf, &Len, Instance, pNet->NetNr);
+		pAC->LinkInfo[port].PLinkSpeed = SK_LSPEED_AUTO;
+	} else {
+		return -EINVAL;
+	}
+
+	return(0);
+}
+
+/*****************************************************************************
+ *
+ *	SkGeSetWolSettings - configures the WOL settings of a selected adapter
+ *
+ * Description:
+ *	The WOL settings of a selected adapter are configured regarding
+ *	the parameters in the passed ethtool_wolinfo structure.
+ *	Note that currently only wake on magic packet is supported!
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetWolSettings(struct net_device *dev,
+			struct ethtool_wolinfo *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+
+	if (ecmd->wolopts != WAKE_MAGIC && ecmd->wolopts != 0)
+		return -EOPNOTSUPP;
+
+	if (((ecmd->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ecmd->wolopts == 0)) {
+		pAC->WolInfo.ConfiguredWolOptions = ecmd->wolopts;
+		return 0;
+	}
+	return -EFAULT;
+}
+
+
+/*****************************************************************************
+ *
+ *	SkGeSetPauseParam - configures the pause parameters of an adapter
+ *
+ * Description:
+ *	This function sets the Rx or Tx pause parameters
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetPauseParam(struct net_device *dev,
+			struct ethtool_pauseparam *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+	SK_GEPORT		*pPort = &pAC->GIni.GP[port];
+	int			PrevSpeedVal = pPort->PLinkSpeedUsed;
+	SK_U32			Instance;
+	char			Buf[4];
+	int			Ret = SK_PNMI_ERR_OK;
+	SK_BOOL			prevAutonegValue = SK_TRUE;
+	int			prevTxPause      = 0;
+	int			prevRxPause      = 0;
+	unsigned int		Len              = 1;
+
+
+        if (port == 0) {
+                Instance = (pAC->RlmtNets == 2) ? 1 : 2;
+        } else {
+                Instance = (pAC->RlmtNets == 2) ? 2 : 3;
+        }
+
+	if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
+	    (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
+		prevTxPause = 1;
+		prevRxPause = 1;
+	}
+
+	/* Bugfix for not supported TX only mode */
+	if (ecmd->rx_pause != ecmd->tx_pause) {
+		printk("Unsupported flow control configuration. Single tx or rx configuration not supported.\n");
+		return 1;
+	}
+
+	if ((ecmd->rx_pause != prevRxPause) || 
+	(ecmd->tx_pause != prevTxPause)) {
+	/* Pause frames changed - Set the new value*/
+		if(ecmd->rx_pause && ecmd->tx_pause) {
+			*Buf = (char) SK_FLOW_MODE_SYMMETRIC;
+		} else if (ecmd->rx_pause && !ecmd->tx_pause) {
+			printk("Unsupported flow control configuration. Single tx not available.\n");
+			*Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
+		} else if(!ecmd->rx_pause && ecmd->tx_pause) {
+			*Buf = (char) SK_FLOW_MODE_LOC_SEND;
+		} else {
+			*Buf = (char) SK_FLOW_MODE_NONE;
+		}
+
+		/* Set the data */
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
+			&Buf, &Len, Instance, pNet->NetNr);
+
+		if (Ret != SK_PNMI_ERR_OK) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
+			("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
+		}
+	}
+
+	/* Auto-negotiation */
+	prevAutonegValue = 0;
+	prevAutonegValue = pPort->PLinkMode != SK_LMODE_HALF &&
+		pPort->PLinkMode != SK_LMODE_FULL;
+
+	if (ecmd->autoneg != prevAutonegValue) {
+	/* Autoneg changed */
+		if (ecmd->autoneg == AUTONEG_DISABLE) { 
+			*Buf = (char) SK_LMODE_FULL;
+		} else {
+		/* Autoneg on. Enable autoparam */
+			*Buf = (char) SK_LMODE_AUTOBOTH;
+		}
+
+		Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
+			&Buf, &Len, Instance, pNet->NetNr);
+
+		if (Ret != SK_PNMI_ERR_OK) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
+			("ethtool (sk98lin): error changing link mode (%i)\n", Ret));
+		} 
+	}
+
+	/*
+	** It may be that autoneg has been disabled! Therefore
+	** set the speed to the previously used value...
+	*/
+	*Buf = (char) PrevSpeedVal;
+
+	Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
+			&Buf, &Len, Instance, pNet->NetNr);
+
+	if (Ret != SK_PNMI_ERR_OK) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
+		("ethtool (sk98lin): error setting speed (%i)\n", Ret));
+	}
+        return 0;
+}
+
+
+/*****************************************************************************
+ *
+ *	SkGeSetCoalesce - configures the IRQ moderation of an adapter
+ *
+ * Description:
+ *	Depending on the desired IRQ moderation parameters, either a) static,
+ *	b) dynamic or c) no moderation is configured.
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ *
+ * Notes:
+ *	The supported timeframe for the coalesced interrupts ranges from
+ *	33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
+ *	Any requested value that is not in this range will abort the request!
+ */
+int SkGeSetCoalesce(struct net_device *dev,
+			struct ethtool_coalesce *ecmd)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	DIM_INFO		*Info        = &pAC->DynIrqModInfo;
+	int			PrevModeration = Info->IntModTypeSelect;
+
+	Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
+
+	if ((ecmd->rx_coalesce_usecs) || (ecmd->tx_coalesce_usecs)) {
+		if (ecmd->rx_coalesce_usecs) {
+			if ((ecmd->rx_coalesce_usecs < 25) ||
+			    (ecmd->rx_coalesce_usecs > 33333)) {
+				return -EINVAL;
+			}
+		}
+		if (ecmd->tx_coalesce_usecs) {
+			if ((ecmd->tx_coalesce_usecs < 25) ||
+			    (ecmd->tx_coalesce_usecs > 33333)) {
+				return -EINVAL;
+			}
+		}
+		if (!CHIP_ID_YUKON_2(pAC)) {
+			if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
+			    (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
+			    (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
+				Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
+			}
+		}
+		Info->IntModTypeSelect = C_INT_MOD_STATIC;
+		if (ecmd->rx_coalesce_usecs) {
+			Info->MaxModIntsPerSec =
+				1000000 / ecmd->rx_coalesce_usecs;
+			if (!CHIP_ID_YUKON_2(pAC)) {
+				if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
+					Info->MaskIrqModeration = IRQ_MASK_TX_RX;
+				}
+				if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
+					Info->MaskIrqModeration = IRQ_MASK_SP_RX;
+				}
+				if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
+					Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
+				}
+			} else {
+				Info->MaskIrqModeration = Y2_IRQ_MASK;
+			}
+		}
+		if (ecmd->tx_coalesce_usecs) {
+			Info->MaxModIntsPerSec =
+				1000000 / ecmd->tx_coalesce_usecs;
+			if (!CHIP_ID_YUKON_2(pAC)) {
+				if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
+					Info->MaskIrqModeration = IRQ_MASK_TX_RX;
+				}
+				if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
+					Info->MaskIrqModeration = IRQ_MASK_SP_TX;
+				}
+				if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
+					Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
+				}
+			} else {
+				Info->MaskIrqModeration = Y2_IRQ_MASK;
+			}
+		}
+	}
+	if ((ecmd->rate_sample_interval)  ||
+	    (ecmd->rx_coalesce_usecs_low) ||
+	    (ecmd->tx_coalesce_usecs_low) ||
+	    (ecmd->rx_coalesce_usecs_high)||
+	    (ecmd->tx_coalesce_usecs_high)) {
+		if (ecmd->rate_sample_interval) {
+			if ((ecmd->rate_sample_interval < 1) ||
+			    (ecmd->rate_sample_interval > 10)) {
+				return -EINVAL;
+			}
+		}
+		if (ecmd->rx_coalesce_usecs_low) {
+			if ((ecmd->rx_coalesce_usecs_low < 25) ||
+			    (ecmd->rx_coalesce_usecs_low > 33333)) {
+				return -EINVAL;
+			}
+		}
+		if (ecmd->rx_coalesce_usecs_high) {
+			if ((ecmd->rx_coalesce_usecs_high < 25) ||
+			    (ecmd->rx_coalesce_usecs_high > 33333)) {
+				return -EINVAL;
+			}
+		}
+		if (ecmd->tx_coalesce_usecs_low) {
+			if ((ecmd->tx_coalesce_usecs_low < 25) ||
+			    (ecmd->tx_coalesce_usecs_low > 33333)) {
+				return -EINVAL;
+			}
+		}
+		if (ecmd->tx_coalesce_usecs_high) {
+			if ((ecmd->tx_coalesce_usecs_high < 25) ||
+			    (ecmd->tx_coalesce_usecs_high > 33333)) {
+				return -EINVAL;
+			}
+		}
+
+		Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
+		if (ecmd->rate_sample_interval) {
+			Info->DynIrqModSampleInterval =
+				ecmd->rate_sample_interval;
+		}
+		if (ecmd->rx_coalesce_usecs_low) {
+			Info->MaxModIntsPerSecLowerLimit =
+				1000000 / ecmd->rx_coalesce_usecs_low;
+		}
+		if (ecmd->tx_coalesce_usecs_low) {
+			Info->MaxModIntsPerSecLowerLimit =
+				1000000 / ecmd->tx_coalesce_usecs_low;
+		}
+		if (ecmd->rx_coalesce_usecs_high) {
+			Info->MaxModIntsPerSecUpperLimit =
+				1000000 / ecmd->rx_coalesce_usecs_high;
+		}
+		if (ecmd->tx_coalesce_usecs_high) {
+			Info->MaxModIntsPerSecUpperLimit =
+				1000000 / ecmd->tx_coalesce_usecs_high;
+		}
+	}
+
+	if ((PrevModeration         == C_INT_MOD_NONE) &&
+	    (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
+		SkDimEnableModerationIfNeeded(pAC);
+	}
+	if (PrevModeration != C_INT_MOD_NONE) {
+		SkDimDisableModeration(pAC, PrevModeration);
+		if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
+			SkDimEnableModerationIfNeeded(pAC);
+		}
+	}
+
+        return 0;
+}
+
+/*****************************************************************************
+ *
+ *	SkGeSetSG - set the SG parameters
+ *
+ * Description:
+ *	This function sets the SG parameters
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetSG(struct net_device *dev,
+			u32 data)
+{
+	return ethtool_op_set_sg(dev, data);
+}
+
+/*****************************************************************************
+ *
+ *	SkGeSetTxCsum - set the TxCsum parameters
+ *
+ * Description:
+ *	This function sets the TxCsum parameters
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetTxCsum(struct net_device *dev,
+			u32 data)
+{
+	return ethtool_op_set_tx_csum(dev, data);
+}
+
+/*****************************************************************************
+ *
+ *	SkGeSetRxCsum - set the SkGeSetRxCsum parameters
+ *
+ * Description:
+ *	This function sets the RxCsum parameters
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetRxCsum(struct net_device *dev,
+			u32 data)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	int			port         = pNet->PortNr;
+
+	pAC->RxPort[port].UseRxCsum = data;
+	return 0;
+}
+
+/*****************************************************************************
+ *
+ * 	SkGePhysId - start the locate NIC feature of the elected adapter
+ *
+ * Description:
+ *	This function is used if the user want to locate a particular NIC.
+ *	All LEDs are regularly switched on and off, so the NIC can easily
+ *	be identified.
+ *
+ * Returns:
+ *	==0:	everything fine, no error, locateNIC test was started
+ *	!=0:	one locateNIC test runs already
+ *
+ */
+int SkGePhysId(struct net_device *dev,
+			u32 data)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+	SK_IOC                   IoC       = pAC->IoBase;
+	int			port         = pNet->PortNr;
+	struct SK_NET_DEVICE	*pDev        = pAC->dev[port];
+	int			OtherPort    = (port) ? 0 : 1;
+	struct SK_NET_DEVICE	*pOtherDev   = pAC->dev[OtherPort];
+
+	if (isLocateNICrunning) {
+		return -EFAULT;
+	}
+	isLocateNICrunning = SK_TRUE;
+	currentPortIndex = port;
+	isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
+	doSwitchLEDsOn = SK_FALSE;
+
+	if (netif_running(pAC->dev[port])) {
+		boardWasDown[0] = SK_FALSE;
+	} else {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
+		(*pDev->netdev_ops->ndo_open)(pDev);
+#else
+		(*pDev->open)(pDev);
+#endif
+		boardWasDown[0] = SK_TRUE;
+	}
+
+	if (isDualNetCard) {
+		if (netif_running(pAC->dev[OtherPort])) {
+			boardWasDown[1] = SK_FALSE;
+		} else {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
+			(*pOtherDev->netdev_ops->ndo_open)(pOtherDev);
+#else
+			(*pOtherDev->open)(pOtherDev);
+#endif
+			boardWasDown[1] = SK_TRUE;
+		}
+	}
+
+	if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
+	     (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
+	  SkMacClearRst(pAC, IoC, port);
+	}
+
+
+	if ((data < 1) || (data > 30)) {
+		data = 3; /* three seconds default */
+	}
+	nbrBlinkQuarterSeconds = 4*data;
+
+	init_timer(&locateNICtimer);
+	locateNICtimer.function = toggleLeds;
+	locateNICtimer.data     = (unsigned long) pNet;
+	locateNICtimer.expires  = jiffies + HZ; /* initially 1sec */
+	add_timer(&locateNICtimer);
+
+	return 0;
+}
+
+/*****************************************************************************
+ *
+ * 	toggleLeds - Changes the LED state of an adapter
+ *
+ * Description:
+ *	This function changes the current state of all LEDs of an adapter so
+ *	that it can be located by a user. If the requested time interval for
+ *	this test has elapsed, this function cleans up everything that was
+ *	temporarily setup during the locate NIC test. This involves of course
+ *	also closing or opening any adapter so that the initial board state
+ *	is recovered.
+ *
+ * Returns:	N/A
+ *
+ */
+static void toggleLeds(
+unsigned long ptr)  /* holds the pointer to adapter control context */
+{
+	DEV_NET              *pNet      = (DEV_NET*) ptr;
+	SK_AC                *pAC       = pNet->pAC;
+	int                   port      = pNet->PortNr;
+	SK_IOC                IoC       = pAC->IoBase;
+	struct SK_NET_DEVICE *pDev      = pAC->dev[port];
+	int                   OtherPort = (port) ? 0 : 1;
+	struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
+	SK_U16                PageSelect;
+	SK_BOOL               YukLedState;
+
+	SK_U16  YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON)  |
+			    PHY_M_LED_MO_10(MO_LED_ON)   |
+			    PHY_M_LED_MO_100(MO_LED_ON)  |
+			    PHY_M_LED_MO_1000(MO_LED_ON) |
+			    PHY_M_LED_MO_RX(MO_LED_ON));
+	SK_U16  YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF)  |
+			     PHY_M_LED_MO_10(MO_LED_OFF)   |
+			     PHY_M_LED_MO_100(MO_LED_OFF)  |
+			     PHY_M_LED_MO_1000(MO_LED_OFF) |
+			     PHY_M_LED_MO_RX(MO_LED_OFF) |
+			     PHY_M_LED_MO_TX(MO_LED_OFF));
+
+	nbrBlinkQuarterSeconds--;
+	if (nbrBlinkQuarterSeconds <= 0) {
+	  /*
+	   * We have to stop the device again in case the device has no
+	   * been up.
+	   */
+
+	  if (!boardWasDown[0]) {
+	    /*
+	     * The board is already up as we bring it up in case it is not.
+	     */
+	  } else {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
+	    (*pDev->netdev_ops->ndo_stop)(pDev);
+#else
+	    (*pDev->stop)(pDev);
+#endif
+	  }
+	  if (isDualNetCard) {
+	    if (!boardWasDown[1]) {
+	      /*
+	       * The board is already up as we bring it up in case it is not.
+	       */
+	    } else {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
+	      (*pOtherDev->netdev_ops->ndo_stop)(pOtherDev);
+#else
+	      (*pOtherDev->stop)(pOtherDev);
+#endif
+	    }
+
+	  }
+
+	  isDualNetCard      = SK_FALSE;
+	  isLocateNICrunning = SK_FALSE;
+	  return;
+	}
+	doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
+
+	if ( (doSwitchLEDsOn) && (nbrBlinkQuarterSeconds > 2) ){
+		if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON_2(pAC)) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
+
+			YukLedOn = 0;
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_INIT_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_STA1_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_STA0_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_LOS_CTRL(YukLedState ? 9 : 8);
+
+			/* save page register */
+			SkGmPhyRead(pAC, IoC, port, PHY_MARV_EXT_ADR, &PageSelect);
+
+			/* select page 3 for LED control */
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, 3);
+
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_PHY_CTRL, YukLedOn);
+
+			/* restore page register */
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, PageSelect);
+		} else {
+			SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
+		}
+	} else {
+		if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON_2(pAC)) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
+
+			YukLedOn = 0;
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_INIT_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_STA1_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_STA0_CTRL(YukLedState ? 9 : 8);
+			YukLedState = 1;
+			YukLedOn |= PHY_M_LEDC_LOS_CTRL(YukLedState ? 9 : 8);
+
+			/* save page register */
+			SkGmPhyRead(pAC, IoC, port, PHY_MARV_EXT_ADR, &PageSelect);
+
+			/* select page 3 for LED control */
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, 3);
+
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_PHY_CTRL, YukLedOff);
+
+			/* restore page register */
+			SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, PageSelect);
+		} else {
+			SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
+		}
+	}
+
+	locateNICtimer.function = toggleLeds;
+	locateNICtimer.data     = (unsigned long) pNet;
+	locateNICtimer.expires  = jiffies + (HZ/4);
+	add_timer(&locateNICtimer);
+}
+
+#ifdef NETIF_F_TSO
+/*****************************************************************************
+ *
+ *	SkGeSetTSO - set the TSO parameters
+ *
+ * Description:
+ *	This function sets the TSO parameters
+ *
+ * Returns:
+ *	==0:	everything fine, no error
+ *	!=0:	the return value is the error code of the failure
+ */
+int SkGeSetTSO(struct net_device *dev,
+			u32 data)
+{
+	DEV_NET			*pNet        = PPRIV;
+	SK_AC			*pAC         = pNet->pAC;
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		if (data) {
+			if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) && (dev->mtu > ETH_MAX_MTU)) {
+				dev->features &= ~NETIF_F_TSO;
+			} else {
+				dev->features |= NETIF_F_TSO;
+			}
+		} else {
+			dev->features &= ~NETIF_F_TSO;
+		}
+		return 0;
+	}
+	return -EOPNOTSUPP;
+
+}
+#endif
+
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/skgeasfapi.c linux-new/drivers/net/sk98lin/skgeasfapi.c
--- linux/drivers/net/sk98lin/skgeasfapi.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgeasfapi.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,960 @@
+/******************************************************************************
+ *
+ * Name:        skgeasfapi.c
+ * Project:     GEnesis, PCI Gigabit Ethernet Adapter
+ * Purpose:     ASF API module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *	Server Adapters.
+ *
+ *	Address all question to: gr-msgg-linux@marvell.com
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Defines
+ *
+ ******************************************************************************/
+#include "h/sktypes.h"
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+extern int SkFwApiGet (SK_AC *pAC , SK_IOC IoC );
+extern SK_U32 HandleDrvCommand (SK_AC *pAC, SK_GE_CMDIOCTL *pFwCommand, SK_U32 FrameLength);
+extern SK_U32 SendFwCommand (SK_AC *pAC, SK_U32 DatagramType, char *pFwDataBuff, SK_U32 FrameLength);
+static SK_U8 SkWriteRamBuf(SK_AC *, SK_U32 *, SK_U32, SK_U32);
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+static void PrintDataBuffer(char *pInfo, char *pData, SK_U32 Framelength);
+#endif
+static SK_U32 SkWriteData(SK_AC *pAC, SK_U32 *pMsgBuff, SK_U32 WPointer, SK_U32 MsgSize);
+static SK_U32 SkReadDta(SK_AC *pAC, SK_U32 *pMsgBuff, SK_U32 RamAddrOffset, SK_U32 RamAddrMaxValue,
+	SK_U32 RPointer, SK_U32 MsgSize);
+
+/******************************************************************************
+ *
+ *	SetRamAddr() - set the RAM address
+ *
+ * Description:
+ *	Set the RAM address used in ReadRamQWord and WriteRamQWord.
+ *
+ * Returns:
+ *	nothing
+ */
+void SetRamAddr(
+SK_AC	*pAC,		/* Adapter context */
+int		BufNumber,	/* Number of RAM buffer: 3 (ASF Fifo) */
+int		AddrLoWord,	/* Address low word:     Address/8 (quadword) */
+int		AddrHiWord)	/* Address high word:    0 */
+{
+	/* Support for Yukon Extreme and Yukon Supreme */
+	if ((pAC->FwApp.ChipMode == SK_GEASF_CHIP_EX) ||
+		(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)) {
+		if (BufNumber >= 0 && BufNumber <= 3) {
+			pAC->RamSelect = BufNumber;
+		}
+	}
+	else {
+		return;
+	}
+
+	pAC->RamAddr = (SK_U32)((SK_U32)AddrLoWord & 0xffff) +
+			(((SK_U32)AddrHiWord << 16) & 0xffff0000L);
+
+} /* SetRamAddr */
+
+/******************************************************************************
+ *
+ *      RamWriteAddr() - Writes one quadword to board RAM
+ *
+ * Description:
+ *      Write one quadword to board RAM.
+ *      For Yukon Extreme, if Addr == 2^29 then the qword
+ *      at the current position of the hardware pointer is read.
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+static int RamWriteAddr(
+SK_AC   *pAC,                    /* Adapter context */
+SK_U32  Addr,                   /* Address to be write at */
+SK_U32  LowDword,               /* Lower Dword to be write */
+SK_U32  HighDword,              /* Upper Dword to be write */
+int     SelectedRam)            /* Selected RAM buffer 0, 1 or 3 */
+{
+        /* Support for Yukon Extreme and Supreme */
+        if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EX) ||
+                (pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)) {
+                if (Addr == BIT_29) {
+                        Addr = SelectedRam << 30;
+                }
+                else {
+                        /* Use given address (lower 8 bits for TX, lower 9 bits for RX). */
+                        Addr = (Addr & 0x7fffL) | BIT_29 | (SelectedRam << 30);
+                }
+                SelectedRam = 0;
+        }
+        else {
+                return(1);
+        }
+
+        SK_OUT32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_ADDR), Addr);
+        SK_OUT32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_DATA_LO), LowDword);
+        SK_OUT32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_DATA_HI), HighDword);
+
+        return(0);
+}
+
+/******************************************************************************
+ *
+ *      RamReadAddr() - Reads one quadword from board RAM
+ *
+ * Description:
+ *      Read one quadword from board RAM.
+ *      For Yukon Extreme, if Addr == 2^29 then the qword
+ *      at the current position of the hardware pointer is read.
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+static int RamReadAddr(
+SK_AC   *pAC,                   /* Adapter context */
+SK_U32  Addr,                   /* Address to be read at */
+SK_U32  *pLowDword,             /* Lower Dword to be read */
+SK_U32  *pHighDword,    /* Upper Dword to be read */
+int     SelectedRam)    /* Selected RAM buffer 0, 1 or 3 */
+{
+
+        /* Support for Yukon Extreme and Supreme */
+        if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EX) ||
+		(pAC->FwApp.ChipMode == SK_GEASF_CHIP_SU)) {
+                if (Addr == BIT_29) {
+                        Addr = SelectedRam << 30;
+                }
+                else {
+                        /* Use given address (lower 8 bits for TX, lower 9 bits for RX). */
+                        Addr = (Addr & 0x7fffL) | BIT_29 | (SelectedRam << 30);
+                }
+                SelectedRam = 0;
+        }
+        else {
+                return(1);
+        }
+
+        SK_OUT32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_ADDR), Addr);
+        /* Read Access is initiated by reading the lower dword. */
+        SK_IN32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_DATA_LO), pLowDword);
+        SK_IN32(pAC->IoBase, SELECT_RAM_BUFFER(SelectedRam, B3_RAM_DATA_HI), pHighDword);
+
+        return(0);
+}
+
+
+/******************************************************************************
+ *
+ *      SkReadDta() - Read data from board RAM
+ *
+ * Description:
+ *      Read a data block from board RAM.
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+
+static SK_U32 SkReadDta(
+SK_AC   *pAC,            /* Adapter context */
+SK_U32  *pMsgBuff,       /* Message buffer */
+SK_U32  RamAddrOffset,   /* First RAM address (qword) */
+SK_U32  RamAddrMaxValue, /* Last RAM address (qword) */
+SK_U32  RPointer,        /* Read pointer (qword) */
+SK_U32  MsgSize)         /* Message size */
+{
+	SK_U32  LowDword = 0x0;
+	SK_U32  HighDword = 0x0;
+	SK_U32  *pWriteDword = NULL;
+	SK_U32  i = 0;
+
+	pWriteDword = pMsgBuff;
+
+	/* Get the payload */
+	for (i=0; i<MsgSize; i+=8) {
+		/* Overflow check */
+		if (RPointer >= RamAddrMaxValue) {
+			RPointer = RamAddrOffset+2;
+		}
+
+		(void) RamReadAddr(pAC, RPointer,
+					&LowDword, &HighDword, pAC->RamSelect);
+		*pWriteDword = LowDword;
+		pWriteDword++;
+		*pWriteDword = HighDword;
+		pWriteDword++;
+		RPointer++;
+	}
+	return RPointer;
+}
+
+
+/******************************************************************************
+
+ *
+ *      SkHandleStatusMsgFromFW() - Print a status message from the FW
+ *
+ * Description:
+ *      Print a status message buffer from the firmware
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+void SkHandleStatusMsgFromFW(
+SK_AC   *pAC,				/* Adapter context */
+SK_U32  *pMsgBuff,			/* Message buffer */
+SK_U32  FrameLength)		/* Message size */
+{
+
+	printk("%s: FW Status -> Time:0x%x  Status:0x%x  Base:0x%x\n",
+		SK_DRV_NAME,
+		(SK_U32) pMsgBuff[0],
+		(SK_U32) pMsgBuff[1],
+		(SK_U32) pMsgBuff[2]);
+}
+
+/******************************************************************************
+ *
+ *      SkHandleDataPacket() - Send a data packet to upper layer
+ *
+ * Description:
+ *      Send a data packet to the commonication protocol stack
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+void SkHandleDataPacket(
+SK_AC   *pAC,				/* Adapter context */
+SK_U32  *pMsgBuff,			/* Message buffer */
+SK_U32  FrameLength)		/* Message size */
+{
+	struct  sk_buff *pMsg = NULL;
+
+	pMsg = alloc_skb(FrameLength+2, GFP_ATOMIC);
+	if (pMsg == NULL) {
+		printk("SkHandleDataPacket: No RX buffer!!\n");
+		return;
+	}
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("SkHandleDataPacket: Send packet!!\n");
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
+	skb_copy_to_linear_data(pMsg, pMsgBuff,
+		FrameLength);
+#else
+	eth_copy_and_sum(pMsg, (char *) pMsgBuff,
+		FrameLength, 0);
+#endif
+	skb_put(pMsg, FrameLength);
+	pMsg->ip_summed = CHECKSUM_NONE;
+	pMsg->dev = pAC->dev[0];
+	pMsg->protocol = eth_type_trans(pMsg, pAC->dev[0]);
+
+#ifdef CONFIG_SK98LIN_NAPI
+	netif_receive_skb(pMsg);
+#else
+	netif_rx(pMsg);
+#endif
+	pAC->dev[0]->last_rx = jiffies;
+	return;
+}
+
+
+/******************************************************************************
+ *
+ *      SkHandleResultPacket() - handte the FW resulta packet
+ *
+ * Description:
+ *      Retrieve the command result and handle the data
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+void SkHandleResultPacket(
+SK_AC   *pAC,				/* Adapter context */
+SK_U32  *pMsgBuff,			/* Message buffer */
+SK_U32  FrameLength)		/* Message size */
+{
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	FwCmdResult	*FwCommandResult;
+	SK_U16      CommandType;
+	SK_U16      CommandLength;
+	SK_U16      CommandResult;
+#endif
+
+	/*
+	 * THIS ROUTINE MUST COPY THE CONTENT OF pMsgBuff TO ANOTHER LOCATION!
+	 * pMsgBuff WILL BE FREED AFTER THIS ROUTINE HAS FINISHED!
+	 */
+
+	if (pAC->FwBufferLen > 0) {
+		/* Clear the old buffer */
+		kfree(pAC->pFwBuffer);
+	}
+
+	if ((pAC->pFwBuffer = (SK_U32 *) kmalloc(FrameLength, GFP_KERNEL)) != NULL ) {
+		/* Copy the data into a new buffer */
+		pAC->FwBufferLen = FrameLength;
+		memcpy(pAC->pFwBuffer, pMsgBuff, FrameLength);
+	} else {
+		printk("Alloc data ERROR\n");
+		return;
+	}
+
+	/* DEBUG CODE! */
+
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	FwCommandResult = (FwCmdResult *) pAC->pFwBuffer;
+	CommandType = FwCommandResult->Hdr.Cmd;
+	CommandLength = FwCommandResult->Hdr.Len;
+	CommandResult = FwCommandResult->Result;
+
+	printk("%s: SkHandleResultPacket => CommandType:   0x%x\n", DRV_NAME, CommandType);
+	printk("%s: SkHandleResultPacket => CommandLength: 0x%x\n", DRV_NAME, CommandLength);
+	printk("%s: SkHandleResultPacket => CommandResult: 0x%x\n", DRV_NAME, CommandResult);
+
+	/* Print output to see complete FW command result buffer */
+	PrintDataBuffer("SkHandleResultPacket => FIFO DATA", pMsgBuff, FrameLength);
+#endif
+}
+
+/******************************************************************************
+ *
+ *      SkHandleMsgCmdResponsePacket() - handte the FW resulta packet
+ *
+ * Description:
+ *      Store the received msg cmd response for later retrieval
+ *
+ * Returns:
+ *      - (void)
+ */
+void SkHandleMsgCmdResponsePacket(
+SK_AC   *pAC,				/* Adapter context */
+SK_U32  *pMsgBuff,			/* Message buffer */
+SK_U32  FrameLength)		/* Message size */
+{
+	if (pMsgBuff && FrameLength) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+		printk("%s-%s() FrameLength: 0x%x\n", DRV_NAME, __func__, FrameLength);
+		PrintDataBuffer("FIFO DATA", pMsgBuff, FrameLength);
+#endif
+
+		if (pAC->FwBufferLen > 0) {
+			kfree(pAC->pFwBuffer); /* Clear the old buffer */
+		}
+
+		if ((pAC->pFwBuffer = (SK_U32 *) kmalloc(FrameLength, GFP_KERNEL)) != NULL ) {
+			/* Copy the data into a new buffer */
+			pAC->FwBufferLen = FrameLength;
+			memcpy(pAC->pFwBuffer, pMsgBuff, FrameLength);
+		} else {
+			printk("%s-%s() Alloc data ERROR\n", DRV_NAME, __func__);
+		}
+	}
+}
+
+/******************************************************************************
+ *
+ *      SkGenDta() - Generate a test data packet
+ *
+ * Description:
+ *      Generate a test data packet
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+SK_U32 SkGenDta(
+SK_AC   *pAC,			/* Adapter context */
+SK_U32	*pMsg,			/* Datagram data */
+SK_U32  DgramId,		/* Datagram ID */
+SK_U16  DgramLen,		/* Datagram length */
+SK_U8   *ddata)			/* Payload data */
+{
+	FifoDgram     dgram;
+//        SK_U8         pad[8] = {0,0,0,0,0,0,0,0};
+        SK_U8         padlen = 0;
+
+	/* Generate the datagram */
+        /* fill header */
+        dgram.Id = DgramId;
+        dgram.DgramLen = DgramLen+sizeof(pMsg);
+        dgram.PayloadLen = DgramLen;
+
+        /* update DgramLen with padding */
+        if (dgram.DgramLen % 8)
+                padlen = 8 - ( dgram.DgramLen % 8 );
+        dgram.DgramLen += padlen;
+
+
+
+	printk("Data: 0x%x 0x%x 0x%x\n", dgram.DgramLen, dgram.PayloadLen, dgram.Id);
+	return 0;
+}
+
+
+/******************************************************************************
+ *
+ *      SkGenDta() - Initialize the download fifo
+ *
+ * Description:
+ *      Init the download fifo on board RAM
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+
+void SkInitDloadFifo (
+SK_AC   *pAC)                   /* Adapter context */
+{
+//	SK_U32	Addr;
+
+	/* Calculate the address and write the read pointer */
+
+
+
+	printk("QW: 0x%x Addr->0x%x\n", HOST_WRITE_QWORD, HOST_WRITE_ADDR);
+}
+
+/******************************************************************************
+ *
+ *      SkAccessRamBuf() - Handle a read request from the firmware
+ *
+ * Description:
+ *      Handle a read request from the firmware
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+
+SK_U8 SkAccessRamBuf(
+SK_AC  *pAC,            /* Adapter context */
+SK_U32 RamAddrOffset,   /* First RAM address (qword) */
+SK_U32 RamAddrMaxValue) /* Last RAM address (qword) */
+{
+	SK_U32  LowDword = 0x0;
+	SK_U32  HighDword = 0x0;
+	SK_U32  RPointer = 0x0;
+	SK_U32  WPointer = 0x0;
+	SK_U32  StartAddress = 0x0;
+	SK_U32  DPointer = 0x0;
+	SK_U32  CurrRamAddr = pAC->RamAddr;
+	SK_U32  RPointerRamAddr = pAC->RamAddr;
+	SK_U16  *pDataLow = (SK_U16 *) &LowDword;
+	SK_U32  *pMsgBuff = NULL;
+
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("RamOffset: 0x%x RamMaxVal: 0x%x\n", RamAddrOffset, RamAddrMaxValue);
+#endif
+
+	/* Read the fifo status */
+	(void) RamReadAddr(pAC, CurrRamAddr,
+				&LowDword, &HighDword, pAC->RamSelect);
+
+	/* Fifo not available... Return... */
+	if ((SK_U32) LowDword == 0) {
+		printk("sk98lin: Fifo not available\n");
+		return 0;
+	}
+
+	/* Set CurrRamAddr to beginning of FIFO write array! */
+	CurrRamAddr = RamAddrOffset;
+
+	/* Datagram handling */
+	(void) RamReadAddr(pAC, CurrRamAddr,
+				&StartAddress, &RPointer, pAC->RamSelect);
+	RPointerRamAddr = CurrRamAddr;
+	CurrRamAddr++;
+	(void) RamReadAddr(pAC, CurrRamAddr,
+				&DPointer, &WPointer, pAC->RamSelect);
+	RPointer = (RPointer - HOST_ROM_ADDR)/8;
+	WPointer = (WPointer - HOST_ROM_ADDR)/8;
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("Read pointer STA: RP: 0x%x WP: 0x%x\n", RPointer, WPointer);
+#endif
+
+	/*
+	**  exit if the read pointer == write pointer
+	*/
+	while (RPointer != WPointer) {
+		if (RPointer >= RamAddrMaxValue) {
+			RPointer = RamAddrOffset+2;
+		}
+		if (RPointer == WPointer)
+			goto pointer_save;
+
+		(void) RamReadAddr(pAC, RPointer,
+						&LowDword, &HighDword, pAC->RamSelect);
+
+		if ((SK_U32) LowDword == 0) {
+			printk("sk98lin: Fifo data not available\n");
+			return 0;
+		}
+
+		pMsgBuff = (SK_U32 *) kmalloc(pDataLow[0], GFP_KERNEL);
+		if (pMsgBuff == NULL) {
+			printk("sk98lin: Memory allocation failed!\n");
+
+			/* Set read pointer to beginning of next FIFO datagram */
+			RPointer = RPointer + (pDataLow[0]/8);
+			goto pointer_save;
+		}
+
+		RPointer++;
+		RPointer = SkReadDta(pAC, pMsgBuff, RamAddrOffset,
+						RamAddrMaxValue, RPointer, pDataLow[1]);
+
+		switch(HighDword) {
+			case SKGE_DGRAM_CMD:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle Command\n");
+#endif
+				break;
+			case SKGE_DGRAM_RESULT:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle Command result\n");
+#endif
+				SkHandleResultPacket(pAC, pMsgBuff, pDataLow[1]);
+				break;
+			case SKGE_DGRAM_PACKET:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle Packet\n");
+#endif
+				SkHandleDataPacket(pAC, pMsgBuff, pDataLow[1]);
+				break;
+			case SKGE_DGRAM_MSG2FW:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle Message to FW app\n");
+#endif
+				break;
+			case SKGE_DGRAM_MSGFW:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle Message from FW app\n");
+#endif
+				SkHandleMsgCmdResponsePacket(pAC, pMsgBuff, pDataLow[1]);
+				break;
+			case SKGE_DGRAM_STATUS:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle status message from FW\n");
+#endif
+				SkHandleStatusMsgFromFW(pAC, pMsgBuff, pDataLow[1]);
+				break;
+			case SKGE_DGRAM_APP_VERSION:
+				((SK_U8*)pMsgBuff)[pDataLow[1]-1]	= '\0';
+				printk("Firmware Application Code: %s\n", (SK_U8 *)(pMsgBuff+1));
+				break;
+			default:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("  +++ Handle default\n");
+#endif
+				break;
+		}
+
+		/* Done */
+		if (pMsgBuff != NULL) {
+			kfree(pMsgBuff);
+		}
+	}
+
+	pointer_save:
+	/* Set the read pointer address */
+	if (RPointer >= RamAddrMaxValue)
+		RPointer = RamAddrOffset+2;
+
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("Read pointer END: RP: 0x%x WP: 0x%x\n", RPointer, WPointer);
+#endif
+
+	RPointer = (RPointer*8)+HOST_ROM_ADDR;
+	RamWriteAddr(pAC, RPointerRamAddr, StartAddress, RPointer, pAC->RamSelect);
+
+	return 0;
+}
+
+
+/*****************************************************************************
+*
+* SkFwApiGet - Get the communication data
+*
+* Description:
+*
+* Returns:
+*
+*/
+
+int SkFwApiGet (
+    SK_AC *pAC,     /* Pointer to adapter context */
+    SK_IOC IoC)     /* IO context handle */
+{
+//	SK_U32  *pMsg = NULL;
+	unsigned long          Flags;
+
+	/* Datagram structure */
+	DgamMsg     ddata;
+        ddata.cmd = 1;
+        ddata.len = 5;
+        ddata.data = 1;
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("Handle SkFwApiGet\n");
+#endif
+	spin_lock_irqsave(&pAC->FwFifoLock, Flags);
+	SetRamAddr(pAC, SK_ST_FIFOTYPE, HOST_READ_QWORD, SK_ST_BUFADDR_HIGH);
+	SkAccessRamBuf(pAC, HOST_READ_DATA_QWORD, HOST_READ_PACKET_QWORD);
+	spin_unlock_irqrestore(&pAC->FwFifoLock, Flags);
+	return 0;
+}
+
+
+/******************************************************************************
+ *
+ *      SkWriteRamBuf() - Handle a write request from the upper layer
+ *
+ * Description:
+ *      Handle a write request to the firmware
+ *
+ * BE AWARE: SK_IN/SK_OUT macros will swap the following 32bit
+ *           variables in RamReadAddr() and RamWriteAddr():
+ *
+ *           - LowDword
+ *           - HighDword
+ *           - RPointer
+ *           - WPointer
+ *           - DPointer
+ *           - CurrRamAddr
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+SK_U8 SkWriteRamBuf(
+SK_AC   *pAC,			/* Adapter context */
+SK_U32  *pMsgBuff,
+SK_U32  FrameLength,
+SK_U32  DatagramType)
+{
+	SK_U32 LowDword = 0x0;
+	SK_U32 HighDword = 0x0;
+	SK_U32 RPointer = 0x0;
+	SK_U32 WPointer = 0x0;
+	SK_U32 Size = 0x0;
+	SK_U32 DPointer = 0x0;
+	SK_U32 CurrRamAddr = pAC->RamAddr;
+	SK_U32 WPointerRamAddr;
+	SK_U16 *pDataLow = (SK_U16 *) &LowDword;
+	SK_U16 DatagramLength;
+
+	/* Read the FIFO status */
+	(void) RamReadAddr(pAC, CurrRamAddr,
+					   &LowDword, &HighDword, pAC->RamSelect);
+
+	/* FIFO not available => Return! */
+	if ((SK_U32) LowDword == 0) {
+		printk("%s: SkWriteRamBuf => Fifo not available!\n", DRV_NAME);
+		return 1;
+	}
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("SkWriteRamBuf => Fifo available: 0x%x\n", LowDword);
+#endif
+
+	/* Set CurrRamAddr to beginning of FIFO write array! */
+	CurrRamAddr = HOST_WRITE_QWORD;
+
+	/* Retrieve read pointer */
+	(void) RamReadAddr(pAC, CurrRamAddr,
+					   &DPointer, &RPointer, pAC->RamSelect);
+
+	/* Retrieve write pointer */
+	CurrRamAddr++;
+	(void) RamReadAddr(pAC, CurrRamAddr,
+					   &Size, &WPointer, pAC->RamSelect);
+	WPointerRamAddr = CurrRamAddr;
+
+	/* Convert pointer addresses to quadword addresses */
+	RPointer = (RPointer - HOST_ROM_ADDR)/8;
+	WPointer = (WPointer - HOST_ROM_ADDR)/8;
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("SkWriteRamBuf START => RPointer: 0x%x\n", RPointer);
+	printk("SkWriteRamBuf START => WPointer: 0x%x\n", WPointer);
+#endif
+	/*
+	 * Fill LowDword and HighDword with FIFO datagram information:
+	 * LowDword: Datagram and payload length, HighDword: Transaction ID
+	 */
+	DatagramLength = 8;
+	DatagramLength += (FrameLength/8) * 8;
+	if (FrameLength % 8) {
+		DatagramLength += 8;
+	}
+
+	/* ENDIANESS */
+#ifdef SK_LITTLE_ENDIAN
+	pDataLow[0] = DatagramLength;
+	pDataLow[1] = FrameLength;
+#else
+	pDataLow[1] = DatagramLength;
+	pDataLow[0] = FrameLength;
+#endif
+	HighDword = DatagramType;
+
+	/* Write FIFO datagram information into RAM */
+	(void) RamWriteAddr(pAC, WPointer,
+						LowDword, HighDword, pAC->RamSelect);
+	WPointer++;
+
+	/* TEST */
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	PrintDataBuffer("SkWriteRamBuf => FIFO DATA", (char *) pMsgBuff, FrameLength);
+#endif
+
+	/* Write payload data into FIFO RAM */
+	WPointer = SkWriteData(pAC, pMsgBuff,
+							WPointer, FrameLength);
+
+	/* Set the write pointer address */
+	if (WPointer > HOST_WRITE_LAST_QWORD) {
+		WPointer = HOST_WRITE_QWORD+2;
+	}
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("SkWriteRamBuf END => RPointer:   0x%x\n", RPointer);
+	printk("SkWriteRamBuf END => WPointer:   0x%x\n", WPointer);
+#endif
+	WPointer = (WPointer*8)+HOST_ROM_ADDR;
+	(void) RamWriteAddr(pAC, WPointerRamAddr,
+						Size, WPointer, pAC->RamSelect);
+	return 0;
+
+} /* SkWriteRamBuf */
+
+/******************************************************************************
+ *
+ *      SkWriteData() - Write data to board RAM
+ *
+ * Description:
+ *      Write a data block to board RAM.
+ *
+ * Returns:
+ *      0 on success, 1 on error
+ */
+static SK_U32 SkWriteData(
+SK_AC   *pAC,			/* Adapter context */
+SK_U32  *pMsgBuff,		/* Message buffer */
+SK_U32  WPointer,		/* Write pointer */
+SK_U32  MsgSize)		/* Message size */
+{
+	SK_U32 LowDword = 0x0;
+	SK_U32 HighDword = 0x0;
+	SK_U32 *pWriteDword = NULL;
+	SK_U32 i = 0;
+
+	pWriteDword = pMsgBuff;
+
+	/* Write the payload */
+	for (i=0; i<MsgSize; i+=8) {
+
+		/* Overflow check */
+		if (WPointer > HOST_WRITE_LAST_QWORD) {
+			WPointer = HOST_WRITE_QWORD+2;
+		}
+
+		LowDword = *pWriteDword;
+		pWriteDword++;
+		HighDword = *pWriteDword;
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+		printk("SkWriteData   => LowDword:    0x%08x\n", LowDword);
+		printk("SkWriteData   => HighDword:   0x%08x\n", HighDword);
+#endif
+		(void) RamWriteAddr(pAC, WPointer,
+						   LowDword, HighDword, pAC->RamSelect);
+		pWriteDword++;
+		WPointer++;
+	}
+
+	return WPointer;
+
+} /* SkWriteData */
+
+
+/*****************************************************************************
+*
+* SkFwIsr - Handle an ISR from the firmware
+*
+* Description:
+*
+* Returns:
+*
+*/
+
+void SkFwIsr (
+    SK_AC *pAC,     /* Pointer to adapter context */
+    SK_IOC IoC)     /* IO context handle */
+{
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+	printk("Handle SkFwIsr\n");
+#endif
+	SetRamAddr(pAC, SK_ST_FIFOTYPE, HOST_READ_QWORD, SK_ST_BUFADDR_HIGH);
+	SkAccessRamBuf(pAC, HOST_READ_DATA_QWORD, HOST_READ_PACKET_QWORD);
+	if (!pAC->SdkQH) {
+		if ((netif_running(pAC->dev[0])) &&
+			(pAC->dev[0]->flags & IFF_RUNNING)) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+			printk("Handle SkFwIsr packet\n");
+#endif
+			SkAccessRamBuf(pAC, HOST_READ_PACKET_QWORD, HOST_WRITE_DATA_QWORD);
+		}
+	}
+	FwHciStateMachine(pAC, IoC, 0);
+
+	return;
+}
+
+
+/*****************************************************************************
+ *
+ * HandleDrvCommand - Handle a FW command
+ *
+ * Description:
+ *
+ * Returns:
+ *
+ */
+SK_U32 HandleDrvCommand (
+	SK_AC          *pAC,		/* Pointer to adapter context */
+	SK_GE_CMDIOCTL *pFwCommand,	/* FW data buffer from OS application layer/driver */
+	SK_U32         FrameLength)	/* Length of FW data buffer in bytes */
+{
+
+	switch(pFwCommand->Command) {
+		case SK_COMMAND_SLEEP:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+			printk("  +++ Handle sleep command\n");
+#endif
+			FwHciSendCommand(pAC, pAC->IoBase, YASF_HOSTCMD_SYS_WILL_SLEEP, 0, 0, 0, ASF_HCI_WAIT, 0);
+			if (pAC->SdkQH)
+				netif_stop_queue(pAC->dev[0]);
+			break;
+		case SK_COMMAND_SA_UPDATE:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+			printk("  +++ Handle sa update command\n");
+#endif
+			FwHciSendCommand(pAC, pAC->IoBase, YASF_HOSTCMD_SYS_SA_UPDATE_COMPLETE, 0, 0, 0, ASF_HCI_WAIT, 0);
+			if (pAC->SdkQH) {
+				netif_wake_queue(pAC->dev[0]);
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+				printk("Handle HandleDrvCommand packet\n");
+#endif
+				SetRamAddr(pAC, SK_ST_FIFOTYPE, HOST_READ_QWORD, SK_ST_BUFADDR_HIGH);
+				SkAccessRamBuf(pAC, HOST_READ_PACKET_QWORD, HOST_WRITE_DATA_QWORD);
+			}
+			break;
+		default:
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+			printk("  +++ Handle default\n");
+#endif
+			break;
+	}
+
+	printk("Handle DrvCommand -> 0x%x\n", pFwCommand->Command);
+
+	return 0;
+}
+
+
+/*****************************************************************************
+ *
+ * SendFwCommand - Handle a FW command
+ *
+ * Description:
+ *
+ * Returns:
+ *
+ */
+SK_U32 SendFwCommand (
+	SK_AC 		*pAC,			/* Pointer to adapter context */
+	SK_U32		DatagramType,	/* Datagram type */
+	char		*pFwDataBuff,	/* FW data buffer from OS application layer/driver */
+	SK_U32		FrameLength)	/* Length of FW data buffer in bytes */
+{
+	unsigned long          Flags;
+
+	spin_lock_irqsave(&pAC->FwFifoLock, Flags);
+	SetRamAddr(pAC, SK_ST_FIFOTYPE, HOST_READ_QWORD, SK_ST_BUFADDR_HIGH);
+
+	if (SkWriteRamBuf(pAC, (SK_U32 *) pFwDataBuff, FrameLength, DatagramType)) {
+		spin_unlock_irqrestore(&pAC->FwFifoLock, Flags);
+		return -1;
+	}
+	spin_unlock_irqrestore(&pAC->FwFifoLock, Flags);
+	return 0;
+
+} /* SendFwCommand */
+
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+/*****************************************************************************
+ *
+ * PrintDataBuffer - Do exactly what the name states  => ONLY FOR TESTING!
+ *
+ * Description:
+ *
+ * Returns:
+ *
+ */
+void PrintDataBuffer(char *pInfo, char *pData, SK_U32 Framelength)
+{
+	int currByte = 0;
+	int numBytes = 0;
+	int offset = 0;
+
+	printk("%s: Framelength: %d\n\n", pInfo, Framelength);
+
+	for (currByte = 0; currByte < Framelength; currByte=currByte+8) {
+		if ((currByte + 8) < Framelength) {
+#ifndef SK_PRINT_CHAR
+			printk("0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
+#else
+			printk("%c %c %c %c %c %c %c %c\n",
+#endif
+				(pData[currByte + 0] & 0xff),
+				(pData[currByte + 1] & 0xff),
+				(pData[currByte + 2] & 0xff),
+				(pData[currByte + 3] & 0xff),
+				(pData[currByte + 4] & 0xff),
+				(pData[currByte + 5] & 0xff),
+				(pData[currByte + 6] & 0xff),
+				(pData[currByte + 7] & 0xff));
+		} else {
+			numBytes = Framelength - currByte;
+			offset = currByte;
+			for (currByte = 0; currByte < numBytes; currByte++ ) {
+#ifndef SK_PRINT_CHAR
+				printk("0x%02x ", (pData[offset + currByte] & 0xff));
+#else
+				printk("%c ", (pData[offset + currByte] & 0xff));
+#endif
+			}
+			printk("\n\n");
+			break;
+		}
+	}
+	return;
+
+} /* PrintDataBuffer */
+#endif
diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c
--- linux/drivers/net/sk98lin/skge.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skge.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,7243 @@
+/******************************************************************************
+ *
+ * Name:        skge.c
+ * Project:     Gigabit Ethernet Adapter
+ * Purpose:     The main driver source module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	    (C)Copyright 1998-2002 SysKonnect GmbH.
+ *	    (C)Copyright 2002-2011 Marvell.
+ *
+ *	    Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	    Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *
+ *	All source files in this sk98lin directory except of the sk98lin
+ *	Linux specific files
+ *
+ *		- skdim.c
+ *		- skethtool.c
+ *		- skge.c
+ *		- skproc.c
+ *		- sky2.c
+ *		- Makefile
+ *		- h/skdrv1st.h
+ *		- h/skdrv2nd.h
+ *		- h/sktypes.h
+ *		- h/skversion.h
+ *
+ *	are part of SysKonnect's common modules for the SK-9xxx adapters.
+ *
+ *	Those common module files which are not Linux specific are used to
+ *	build drivers on different OS' (e.g. Windows, MAC OS) so that those
+ *	drivers are based on the same set of files
+ *
+ *	At a first glance, this seems to complicate things unnescessarily on
+ *	Linux, but please do not try to 'clean up' them without VERY good
+ *	reasons, because this will make it more difficult to keep the sk98lin
+ *	driver for Linux in synchronisation with the other drivers running on
+ *	other operating systems.
+ *
+ ******************************************************************************/
+
+#include	"h/skversion.h"
+
+#include	<linux/module.h>
+#include	<linux/init.h>
+#include	<linux/ethtool.h>
+#include    <linux/netdevice.h>
+#include    <linux/inetdevice.h>
+
+#ifdef CONFIG_PROC_FS
+#include 	<linux/proc_fs.h>
+#endif
+
+#include	"h/skdrv1st.h"
+#include	"h/skdrv2nd.h"
+#include	"h/skpcidevid.h"
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
+#include	<linux/moduleparam.h>
+#endif
+
+/*******************************************************************************
+ *
+ * Defines
+ *
+ ******************************************************************************/
+
+/* for debuging on x86 only */
+/* #define BREAKPOINT() asm(" int $3"); */
+
+#define NOT_EC_CHIP (pAC->FwCommon.ChipID == CHIP_ID_YUKON_EX) || \
+                (pAC->FwCommon.ChipID == CHIP_ID_YUKON_SUPR)
+
+
+/* Set blink mode*/
+#define OEM_CONFIG_VALUE (	SK_ACT_LED_BLINK | \
+				SK_DUP_LED_NORMAL | \
+				SK_LED_LINK100_ON)
+
+#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
+#define START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START)
+#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
+
+/*******************************************************************************
+ *
+ * Local Function Prototypes
+ *
+ ******************************************************************************/
+
+static int 	__devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
+static void 	sk98lin_remove_device(struct pci_dev *pdev);
+#ifdef CONFIG_PM
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,10)
+static int	sk98lin_suspend(struct pci_dev *pdev, pm_message_t state);
+#else
+static int	sk98lin_suspend(struct pci_dev *pdev, SK_U32 state);
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)
+static void	sk98lin_shutdown(struct pci_dev *pdev);
+#endif
+static int	sk98lin_resume(struct pci_dev *pdev);
+static void	SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
+static void	SkCheckWOParam(SK_AC *pAC, SK_U16*, SK_U16*);
+#ifndef MV_INCLUDE_SDK_SUPPORT
+static void	SetDynamicClockGating(SK_AC *pAC, SK_IOC IoC);
+#endif
+#endif
+#ifdef Y2_RECOVERY
+static void	SkGeHandleKernelTimer(unsigned long ptr);
+void		SkGeCheckTimer(DEV_NET *pNet);
+static SK_BOOL  CheckRXCounters(DEV_NET *pNet);
+static void	CheckRxPath(DEV_NET *pNet);
+#endif
+static void	FreeResources(struct SK_NET_DEVICE *dev);
+static int	SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
+static SK_BOOL	BoardAllocMem(SK_AC *pAC);
+static void	BoardFreeMem(SK_AC *pAC);
+static void	BoardInitMem(SK_AC *pAC);
+static void	SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+static SkIsrRetVar	SkGeIsr(int irq, void *dev_id);
+#else
+static SkIsrRetVar	SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs);
+#endif
+
+static void	GetConfiguration(SK_AC*);
+static void	GetConTypeConfiguration(SK_AC*);
+static void	GetWolTypeConfiguration(SK_AC*);
+static void	GetSpeedConfiguration(SK_AC*, SK_I32, char *, char *);
+static void	GetLinkModeCapabilities(SK_AC*, SK_I32, char *, char *, char *, char *);
+static void	GetFlowControlConfiguration(SK_AC*, SK_I32, char *, char *);
+static void	GetRoleConfiguration(SK_AC*, SK_I32, char *, char *);
+static void	GetInterruptModConfiguration(SK_AC*);
+static void	GetMiscConfiguration(SK_AC*);
+static void	SetConfiguration(SK_AC*);
+static void	ProductStr(SK_AC*);
+
+static int	SkGeOpen(struct SK_NET_DEVICE *dev);
+static int	SkGeClose(struct SK_NET_DEVICE *dev);
+static int	SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev);
+static int	SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p);
+static void	SkGeSetRxMode(struct SK_NET_DEVICE *dev);
+static struct	net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
+static int	SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
+static int	XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
+static void	FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
+static void	FillRxRing(SK_AC*, RX_PORT*);
+static SK_BOOL	FillRxDescriptor(SK_AC*, RX_PORT*);
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+extern int      SkY2Poll(struct napi_struct *napi, int work_limit);
+static int      SkGePoll(struct napi_struct *napi, int work_limit);
+#else
+extern int	SkY2Poll(struct net_device *dev, int *budget);
+static int	SkGePoll(struct net_device *dev, int *budget);
+#endif
+static void	ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
+#else
+static void	ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
+#endif
+#ifdef SK_POLL_CONTROLLER
+static void	SkGeNetPoll(struct SK_NET_DEVICE *dev);
+#endif
+static void	ClearRxRing(SK_AC*, RX_PORT*);
+static void	ClearTxRing(SK_AC*, TX_PORT*);
+static int	SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
+static void	PortReInitBmu(SK_AC*, int);
+static int	SkGeIocMib(DEV_NET*, unsigned int, int);
+static int	SkGeInitPCI(SK_AC *pAC);
+static SK_U32   ParseDeviceNbrFromSlotName(const char *SlotName);
+static int      SkDrvInitAdapter(SK_AC *pAC, int devNbr);
+static int      SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
+static int	XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
+extern void	SkLocalEventQueue(SK_AC *pAC,
+					SK_U32 Class,
+					SK_U32 Event,
+					SK_U32 Param1,
+					SK_U32 Param2,
+					SK_BOOL Flag);
+extern void	SkLocalEventQueue64(SK_AC *pAC,
+					SK_U32 Class,
+					SK_U32 Event,
+					SK_U64 Param,
+					SK_BOOL Flag);
+static void SkGeReleaseIrq(struct SK_NET_DEVICE *dev);
+static int SK_DEVINIT SkGeRequestIrq(struct SK_NET_DEVICE *dev);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+static int SK_DEVINIT SkGeTestIsr(int irq, void *dev_id);
+#else
+static int SK_DEVINIT SkGeTestIsr(int irq, void *dev_id, struct pt_regs *ptregs);
+#endif
+static int SK_DEVINIT SkGeTestMsi(struct SK_NET_DEVICE *dev, SK_AC *pAC);
+
+#ifdef USE_SK_RSS_SUPPORT
+static void SkSetRssSupport(SK_AC *pAC, int Port);
+#endif
+
+/*******************************************************************************
+ *
+ * Extern Function Prototypes
+ *
+ ******************************************************************************/
+#ifdef MV_INCLUDE_SDK_SUPPORT
+extern int SetFwIpAddr(SK_AC *pAC, SK_U32 , SK_U32 , SK_U32 );
+extern SK_U32 SendFwCommand (SK_AC *pAC, SK_U32 DatagramType, char *pFwDataBuff, SK_U32 FrameLength);
+extern SK_U32 HandleDrvCommand (SK_AC *pAC, SK_GE_CMDIOCTL *pFwCommand, SK_U32 FrameLength);
+#endif
+extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
+extern void SkY2FreeResources(SK_AC *pAC);
+extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
+extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
+extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+extern SkIsrRetVar SkY2Isr(int irq,void *dev_id);
+#else
+extern SkIsrRetVar SkY2Isr(int irq,void *dev_id,struct pt_regs *ptregs);
+#endif
+extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
+extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
+extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
+extern void SkY2RestartStatusUnit(SK_AC *pAC);
+extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
+
+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
+extern void SkDimStartModerationTimer(SK_AC *pAC);
+extern void SkDimModerate(SK_AC *pAC);
+
+/* Ethtool functions */
+extern int SkGeGetSettings(struct net_device *dev, struct ethtool_cmd *ecmd);
+extern void SkGeGetDrvInfo(struct net_device *dev, struct ethtool_drvinfo *ecmd);
+extern void SkGeGetWolSettings(struct net_device *dev, struct ethtool_wolinfo *ecmd);
+extern void SkGeGetPauseParam(struct net_device *dev, struct ethtool_pauseparam *ecmd);
+extern int SkGeGetCoalesce(struct net_device *dev, struct ethtool_coalesce *ecmd);
+extern SK_U32 SkGeGetRxCsum(struct net_device *dev);
+extern void SkGeGetStrings(struct net_device *dev, u32 stringset, u8 *strings);
+extern int SkGeGetStatsLen(struct net_device *dev);
+extern int SkGeGetSsetCount(struct net_device *dev, int sset);
+extern void SkGeGetEthStats(struct net_device *dev, struct ethtool_stats *stats, u64 *data);
+extern int SkGeSetSettings(struct net_device *dev, struct ethtool_cmd *ecmd);
+extern int SkGeSetWolSettings(struct net_device *dev, struct ethtool_wolinfo *ewol);
+extern int SkGeSetPauseParam(struct net_device *dev, struct ethtool_pauseparam *ecmd);
+extern int SkGeSetCoalesce(struct net_device *dev, struct ethtool_coalesce *ecmd);
+extern int SkGeSetSG(struct net_device *dev, u32 data);
+extern int SkGeSetTxCsum(struct net_device *dev, u32 data);
+extern int SkGeSetRxCsum(struct net_device *dev, u32 data);
+extern int SkGePhysId(struct net_device *dev, u32 data);
+
+#ifdef NETIF_F_TSO
+extern int SkGeSetTSO(struct net_device *netdev, u32 data);
+#endif
+
+#ifdef CONFIG_PROC_FS
+static const char 	SK_Root_Dir_entry[] = "sk98lin";
+static struct	proc_dir_entry *pSkRootDir;
+extern struct	file_operations sk_proc_fops;
+#endif
+
+#ifdef DEBUG
+static void	DumpMsg(struct sk_buff*, char*);
+static void	DumpData(char*, int);
+static void	DumpLong(char*, int);
+#endif
+
+/* global variables *********************************************************/
+static const char *BootString = BOOT_STRING;
+struct SK_NET_DEVICE *SkGeRootDev = NULL;
+static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
+
+/* local variables **********************************************************/
+static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
+static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
+static int sk98lin_max_boards_found = 0;
+
+#ifdef CONFIG_PROC_FS
+static struct proc_dir_entry	*pSkRootDir;
+#endif
+
+static struct ethtool_ops sk98lin_ethtool_ops = {
+	.get_sg			= ethtool_op_get_sg,
+	.get_link		= ethtool_op_get_link,
+	.get_tx_csum		= ethtool_op_get_tx_csum,
+/*	.get_perm_addr		= ethtool_op_get_perm_addr, */
+	.get_settings		= SkGeGetSettings,
+	.get_drvinfo		= SkGeGetDrvInfo,
+	.get_wol		= SkGeGetWolSettings,
+	.get_pauseparam		= SkGeGetPauseParam,
+	.get_coalesce		= SkGeGetCoalesce,
+	.get_rx_csum		= SkGeGetRxCsum,
+	.get_strings		= SkGeGetStrings,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
+	.get_stats_count	= SkGeGetStatsLen,
+#else
+	.get_sset_count		= SkGeGetSsetCount,
+#endif
+	.get_ethtool_stats	= SkGeGetEthStats,
+
+	.set_settings		= SkGeSetSettings,
+	.set_wol		= SkGeSetWolSettings,
+	.set_pauseparam		= SkGeSetPauseParam,
+	.set_coalesce		= SkGeSetCoalesce,
+	.set_sg			= SkGeSetSG,
+	.set_tx_csum		= SkGeSetTxCsum,
+	.set_rx_csum		= SkGeSetRxCsum,
+
+	.phys_id		= SkGePhysId,
+
+#ifdef NETIF_F_TSO
+	.get_tso		= ethtool_op_get_tso,
+	.set_tso		= SkGeSetTSO,
+#endif
+
+/*	.get_regs_len	= */
+/*	.get_regs	= */
+/*	.get_msglevel	= */
+/*	.nway_reset	= */
+/*	.get_ringparam	= */
+/*	.set_msglevel	= */
+/*	.set_ringparam	= */
+};
+
+
+MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
+
+static struct pci_driver sk98lin_driver = {
+	.name		= DRIVER_FILE_NAME,
+	.id_table	= sk98lin_pci_tbl,
+	.probe		= sk98lin_init_device,
+	.remove		= __devexit_p(sk98lin_remove_device),
+#ifdef CONFIG_PM
+	.suspend	= sk98lin_suspend,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)
+	.shutdown	= sk98lin_shutdown,
+#endif
+	.resume		= sk98lin_resume
+#endif
+};
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+/* conversion of netdev_ops */
+static const struct net_device_ops sky2_netdev_ops = {
+	.ndo_open               = SkGeOpen,
+	.ndo_stop               = SkGeClose,
+	.ndo_start_xmit         = SkY2Xmit,
+	.ndo_get_stats          = SkGeStats,
+	.ndo_do_ioctl           = SkGeIoctl,
+	.ndo_set_mac_address    = SkGeSetMacAddr,
+	.ndo_set_multicast_list = SkGeSetRxMode,
+	.ndo_change_mtu         = SkGeChangeMtu,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller    = SkGeNetPoll,
+#endif
+};
+
+static const struct net_device_ops skge_netdev_ops = {
+	.ndo_open               = SkGeOpen,
+	.ndo_stop               = SkGeClose,
+	.ndo_start_xmit         = SkGeXmit,
+	.ndo_get_stats          = SkGeStats,
+	.ndo_do_ioctl           = SkGeIoctl,
+	.ndo_set_mac_address    = SkGeSetMacAddr,
+	.ndo_set_multicast_list = SkGeSetRxMode,
+	.ndo_change_mtu         = SkGeChangeMtu,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller    = SkGeNetPoll,
+#endif
+};
+#endif
+
+/*****************************************************************************
+ *
+ * 	sk98lin_init_device - initialize the adapter
+ *
+ * Description:
+ *	This function initializes the adapter. Resources for
+ *	the adapter are allocated and the adapter is brought into Init 1
+ *	state.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static int __devinit sk98lin_init_device(struct pci_dev *pdev,
+				  const struct pci_device_id *ent)
+
+{
+	static SK_BOOL 		sk98lin_boot_string = SK_FALSE;
+#ifdef CONFIG_PROC_FS
+	static SK_BOOL 		sk98lin_proc_entry = SK_FALSE;
+#endif
+	static int		sk98lin_boards_found = 0;
+	SK_AC			*pAC;
+	DEV_NET			*pNet = NULL;
+	struct SK_NET_DEVICE	*dev = NULL;
+	int			retval;
+	int			pci_using_dac;
+
+	retval = pci_enable_device(pdev);
+	if (retval) {
+		printk(KERN_ERR "Cannot enable PCI device, "
+			"aborting.\n");
+		return retval;
+	}
+
+	dev = NULL;
+	pNet = NULL;
+
+	/* INSERT * We have to find the power-management capabilities */
+	/* Find power-management capability. */
+
+	pci_using_dac = 0;		/* Set 32 bit DMA per default */
+
+	/* Configure DMA attributes. */
+	retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
+	if (!retval) {
+		pci_using_dac = 1;
+	} else {
+		retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
+		if (retval) {
+			printk(KERN_ERR "No usable DMA configuration, "
+			       "aborting.\n");
+			return retval;
+		}
+	}
+
+	if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
+		printk(KERN_ERR "Unable to allocate etherdev "
+			"structure!\n");
+		return -ENODEV;
+	}
+
+	pNet = PRIV;
+
+	pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
+	if (pNet->pAC == NULL){
+		free_netdev(dev);
+		printk(KERN_ERR "Unable to allocate adapter "
+			"structure!\n");
+		return -ENODEV;
+	}
+
+	/* Print message */
+	if (!sk98lin_boot_string) {
+		/* set display flag to TRUE so that */
+		/* we only display this string ONCE */
+		sk98lin_boot_string = SK_TRUE;
+		printk("%s\n", BootString);
+	}
+
+	memset(pNet->pAC, 0, sizeof(SK_AC));
+	pAC = pNet->pAC;
+	pAC->PciDev = pdev;
+	pAC->PciDevId = pdev->device;
+	pAC->dev[0] = dev;
+	pAC->dev[1] = dev;
+	sprintf(pAC->Name, "SysKonnect SK-98xx");
+	pAC->CheckQueue = SK_FALSE;
+	pAC->InterfaceUp[0] = 0;
+	pAC->InterfaceUp[1] = 0;
+	dev->irq = pdev->irq;
+	retval = SkGeInitPCI(pAC);
+	if (retval) {
+		printk("SKGE: PCI setup failed: %i\n", retval);
+		free_netdev(dev);
+		return -ENODEV;
+	}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+	SET_MODULE_OWNER(dev);
+#endif
+	SET_ETHTOOL_OPS(dev, &sk98lin_ethtool_ops);
+
+	pAC->Index = sk98lin_boards_found;
+
+	if (SkGeBoardInit(dev, pAC)) {
+		free_netdev(dev);
+		return -ENODEV;
+	} else {
+		ProductStr(pAC);
+	}
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+	if (CHIP_ID_YUKON_2(pAC)) {
+		dev->netdev_ops		=  &sky2_netdev_ops;
+	} else {
+		dev->netdev_ops		=  &skge_netdev_ops;
+	}
+#else
+	dev->open		=  &SkGeOpen;
+	dev->stop		=  &SkGeClose;
+	dev->get_stats		=  &SkGeStats;
+	dev->set_multicast_list	=  &SkGeSetRxMode;
+	dev->set_mac_address	=  &SkGeSetMacAddr;
+	dev->do_ioctl		=  &SkGeIoctl;
+	dev->change_mtu		=  &SkGeChangeMtu;
+#ifdef SK_POLL_CONTROLLER
+	dev->poll_controller	=  SkGeNetPoll;
+#endif
+#endif
+	dev->flags		&= ~IFF_RUNNING;
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	if (pci_using_dac)
+		dev->features |= NETIF_F_HIGHDMA;
+
+	/* shifter to later moment in time... */
+	if (CHIP_ID_YUKON_2(pAC)) {
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+		dev->hard_start_xmit =	&SkY2Xmit;
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+		netif_napi_add(dev, &pNet->napi, SkY2Poll, 64);
+#else
+		dev->poll =  &SkY2Poll;
+		dev->weight = 64;
+#endif
+#endif
+	} else {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+		dev->hard_start_xmit =	&SkGeXmit;
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+		netif_napi_add(dev, &pNet->napi, SkGePoll, 64);
+#else
+		dev->poll =  &SkGePoll;
+		dev->weight = 64;
+#endif
+#endif
+	}
+
+#ifdef NETIF_F_TSO
+#ifdef USE_SK_TSO_FEATURE
+	if (CHIP_ID_YUKON_2(pAC)) {
+		dev->features |= NETIF_F_TSO;
+#ifdef USE_SK_RSS_SUPPORT
+	if (pAC->LinkInfo[0].RSS)
+		dev->features |= NETIF_F_RXHASH;
+#endif
+	}
+#endif
+#endif
+
+#ifdef CONFIG_SK98LIN_ZEROCOPY
+	dev->features |= NETIF_F_SG;
+#endif
+#ifdef USE_SK_TX_CHECKSUM
+	dev->features |= NETIF_F_IP_CSUM;
+#endif
+#ifdef USE_SK_RX_CHECKSUM
+	pAC->RxPort[0].UseRxCsum = SK_TRUE;
+	if (pAC->GIni.GIMacsFound == 2 ) {
+		pAC->RxPort[1].UseRxCsum = SK_TRUE;
+	}
+#endif
+
+	/* Save the hardware revision */
+	pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
+		(pAC->GIni.GIPciHwRev & 0x0F);
+
+	/* Set driver globals */
+	pAC->Pnmi.pDriverFileName    = DRIVER_FILE_NAME;
+	pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
+
+	SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
+	SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
+			sizeof(SK_PNMI_STRUCT_DATA));
+
+	/* Register net device */
+	retval = register_netdev(dev);
+	if (retval) {
+		printk(KERN_ERR "SKGE: Could not register device.\n");
+		FreeResources(dev);
+		free_netdev(dev);
+		return retval;
+	}
+
+	/* Save initial device name */
+	strcpy(pNet->InitialDevName, dev->name);
+
+	/* Set network to off */
+	netif_stop_queue(dev);
+	netif_carrier_off(dev);
+
+	/* Print adapter specific string from vpd and config settings */
+	printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
+
+	SkGeYellowLED(pAC, pAC->IoBase, 1);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
+	memcpy((caddr_t) &dev->dev_addr,
+#else
+	memcpy((caddr_t) dev->dev_addr,
+#endif
+		(caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
+
+	/* First adapter... Create proc and print message */
+#ifdef CONFIG_PROC_FS
+	if (!sk98lin_proc_entry) {
+		sk98lin_proc_entry = SK_TRUE;
+		SK_MEMCPY(&SK_Root_Dir_entry, BootString,
+			sizeof(SK_Root_Dir_entry) - 1);
+
+		/*Create proc (directory)*/
+		if(!pSkRootDir) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+			pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
+#else
+			pSkRootDir = proc_mkdir(SK_Root_Dir_entry, init_net.proc_net);
+#endif
+			if (!pSkRootDir) {
+				printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
+					dev->name, SK_Root_Dir_entry);
+			} else {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
+				pSkRootDir->owner = THIS_MODULE;
+#endif
+			}
+		}
+	}
+
+#endif
+
+	pNet->PortNr = 0;
+	pNet->NetNr  = 0;
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	napi_enable(&pNet->napi);
+#endif
+#endif
+
+	pci_set_drvdata(pdev, dev);
+
+	/* More then one port found */
+	if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
+		dev = alloc_etherdev(sizeof(DEV_NET));
+		if (!dev) {
+			printk(KERN_ERR "Unable to allocate etherdev "
+				"structure!\n");
+			return -ENODEV;
+		}
+
+		pAC->dev[1]   = dev;
+		pNet = PRIV;
+		pNet->PortNr  = 1;
+		pNet->NetNr   = 1;
+		pNet->pAC     = pAC;
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			dev->hard_start_xmit = &SkY2Xmit;
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+			dev->poll =  &SkY2Poll;
+			dev->weight = 64;
+#endif
+#endif
+		} else {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			dev->hard_start_xmit = &SkGeXmit;
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+			dev->poll =  &SkGePoll;
+			dev->weight = 64;
+#endif
+#endif
+		}
+
+		SET_ETHTOOL_OPS(dev, &sk98lin_ethtool_ops);
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+		if (CHIP_ID_YUKON_2(pAC)) {
+			dev->netdev_ops		=  &sky2_netdev_ops;
+		} else {
+			dev->netdev_ops		=  &skge_netdev_ops;
+		}
+#else
+		dev->open		=  &SkGeOpen;
+		dev->stop		=  &SkGeClose;
+		dev->get_stats		=  &SkGeStats;
+		dev->set_multicast_list	=  &SkGeSetRxMode;
+		dev->set_mac_address	=  &SkGeSetMacAddr;
+		dev->do_ioctl		=  &SkGeIoctl;
+		dev->change_mtu		=  &SkGeChangeMtu;
+#ifdef SK_POLL_CONTROLLER
+		dev->poll_controller	=  SkGeNetPoll;
+#endif
+#endif
+		dev->flags		&= ~IFF_RUNNING;
+		SET_NETDEV_DEV(dev, &pdev->dev);
+
+#ifdef NETIF_F_TSO
+#ifdef USE_SK_TSO_FEATURE
+		if (CHIP_ID_YUKON_2(pAC)) {
+			dev->features |= NETIF_F_TSO;
+#ifdef USE_SK_RSS_SUPPORT
+	if (pAC->LinkInfo[0].RSS)
+			dev->features |= NETIF_F_RXHASH;
+#endif
+		}
+#endif
+#endif
+#ifdef CONFIG_SK98LIN_ZEROCOPY
+		dev->features |= NETIF_F_SG;
+#endif
+#ifdef USE_SK_TX_CHECKSUM
+		dev->features |= NETIF_F_IP_CSUM;
+#endif
+
+		if (register_netdev(dev)) {
+			printk(KERN_ERR "SKGE: Could not register device.\n");
+			free_netdev(dev);
+			pAC->dev[1] = pAC->dev[0];
+		} else {
+
+			/* Save initial device name */
+			strcpy(pNet->InitialDevName, dev->name);
+
+			/* Set network to off */
+			netif_stop_queue(dev);
+			netif_carrier_off(dev);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
+			memcpy((caddr_t) &dev->dev_addr,
+#else
+			memcpy((caddr_t) dev->dev_addr,
+#endif
+				(caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
+
+			printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
+		}
+	}
+
+	pAC->Index = sk98lin_boards_found;
+	sk98lin_boards_found++;
+	sk98lin_max_boards_found = sk98lin_boards_found;
+	return 0;
+}
+
+
+
+/*****************************************************************************
+ *
+ * 	SkGeInitPCI - Init the PCI resources
+ *
+ * Description:
+ *	This function initialize the PCI resources and IO
+ *
+ * Returns: N/A
+ *
+ */
+static int SkGeInitPCI(SK_AC *pAC)
+{
+	struct SK_NET_DEVICE *dev = pAC->dev[0];
+	struct pci_dev *pdev = pAC->PciDev;
+	int retval;
+
+	if (pci_enable_device(pdev) != 0) {
+		return 1;
+	}
+
+	dev->mem_start = pci_resource_start (pdev, 0);
+	pci_set_master(pdev);
+
+	if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
+		retval = 2;
+		goto out_disable;
+	}
+
+#ifdef SK_BIG_ENDIAN
+	/*
+	 * On big endian machines, we use the adapter's aibility of
+	 * reading the descriptors as big endian.
+	 */
+	{
+		SK_U32		our2;
+		SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2);
+		our2 |= PCI_REV_DESC;
+		SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2);
+	}
+#endif
+
+	/*
+	 * Remap the regs into kernel space.
+	 */
+	pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
+
+	if (!pAC->IoBase){
+		retval = 3;
+		goto out_release;
+	}
+
+	return 0;
+
+out_release:
+	pci_release_regions(pdev);
+out_disable:
+	pci_disable_device(pdev);
+	return retval;
+}
+
+#ifdef CONFIG_PROC_FS
+/*****************************************************************************
+ *
+ * 	SkGeHandleProcfsTimer - Handle the procfs timer requests
+ *
+ * Description:
+ *      Checks, if the device's name changed. If this is the case
+ *      it deletes the old profs entry and creates a new one with
+ *      the new name.
+ *
+ * Returns:	N/A
+ *
+ */
+static void SkGeHandleProcfsTimer(unsigned long ptr)
+{
+	DEV_NET         *pNet = (DEV_NET*) ptr;
+	struct proc_dir_entry *pProcFile;
+
+	/*
+	 * If the current name and the last saved name of the device differ
+	 * we need to update our procfs entry.
+	 */
+	if ( (pSkRootDir) &&
+	     (strcmp(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name) != 0) ) {
+
+	  if (pNet->pAC->InterfaceUp[pNet->NetNr] == 1)
+	    remove_proc_entry(pNet->CurrentName, pSkRootDir);
+
+	  /*
+	   * InterfaceUp only holds 1 if both the network interface is up and
+	   * the corresponding procfs entry is done. Otherwise it is set to 0.
+	   */
+	  pNet->pAC->InterfaceUp[pNet->NetNr] = 0;
+
+	  pProcFile = create_proc_entry(pNet->pAC->dev[pNet->NetNr]->name, S_IRUGO, pSkRootDir);
+	  pProcFile->proc_fops = &sk_proc_fops;
+	  pProcFile->data      = pNet->pAC->dev[pNet->NetNr];
+
+	  /*
+	   * Remember, interface dev nr pNet->NetNr is up and procfs entry is created.
+	   */
+	  pNet->pAC->InterfaceUp[pNet->NetNr] = 1;
+
+	  strcpy(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name);
+	}
+
+	/*
+	 * Restart Procfs Timer
+	 */
+	pNet->ProcfsTimer.expires	= jiffies + HZ*5; /* 5 secs */
+	add_timer(&pNet->ProcfsTimer);
+}
+#endif
+
+
+#ifdef Y2_RECOVERY
+/*****************************************************************************
+ *
+ * 	SkGeHandleKernelTimer - Handle the kernel timer requests
+ *
+ * Description:
+ *	If the requested time interval for the timer has elapsed,
+ *	this function checks the link state.
+ *
+ * Returns:	N/A
+ *
+ */
+static void SkGeHandleKernelTimer(
+unsigned long ptr)  /* holds the pointer to adapter control context */
+{
+	DEV_NET         *pNet = (DEV_NET*) ptr;
+	SkGeCheckTimer(pNet);
+}
+
+/*****************************************************************************
+ *
+ * 	sk98lin_check_timer - Resume the the card
+ *
+ * Description:
+ *	This function checks the kernel timer
+ *
+ * Returns: N/A
+ *
+ */
+void SkGeCheckTimer(
+DEV_NET *pNet)  /* holds the pointer to adapter control context */
+{
+	SK_AC           *pAC = pNet->pAC;
+	SK_BOOL		StartTimer = SK_TRUE;
+	SK_U32          StatSpeed, StatDuplex, NewTimerInterval;
+
+#ifdef SK_EXTREME
+	if (HW_IS_EXT_LE_FORMAT(pAC)) {
+		/* Disable checks for Yukon Extreme */
+		return;
+	}
+#endif
+
+	StatSpeed = pAC->GIni.GP[pNet->NetNr].PLinkSpeedUsed;
+	if (StatSpeed == SK_LSPEED_STAT_10MBPS) {
+		StatDuplex = pAC->GIni.GP[pNet->NetNr].PLinkModeStatus;
+		if ((StatDuplex == SK_LMODE_STAT_AUTOHALF) ||
+			(StatDuplex == SK_LMODE_STAT_HALF)) {
+				NewTimerInterval = (HZ*2);
+		} else {
+			NewTimerInterval = (HZ);
+		}
+	} else if (StatSpeed == SK_LSPEED_STAT_100MBPS) {
+		NewTimerInterval = (HZ/2);
+	} else if (StatSpeed == SK_LSPEED_STAT_1000MBPS) {
+		NewTimerInterval = (HZ/4);
+	} else {
+		NewTimerInterval = (HZ*2);
+	}
+
+	if (pNet->InRecover) {
+		pNet->KernelTimer.expires = jiffies + NewTimerInterval;
+		add_timer(&pNet->KernelTimer);
+
+		return;
+	}
+
+	if (pNet->TimerExpired)
+		return;
+	pNet->TimerExpired = SK_TRUE;
+
+#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
+#define RXPORT pAC->RxPort[pNet->PortNr]
+
+	if ((CHIP_ID_YUKON_2(pAC)) &&
+		(!netif_queue_stopped(pAC->dev[pNet->PortNr]))) {
+
+#ifdef Y2_RX_CHECK
+		if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
+		/* Checks the RX path */
+			CheckRxPath(pNet);
+		}
+#endif
+
+		/* Check the transmitter */
+		if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
+			if (TXPORT.LastDone != TXPORT.TxALET.Done) {
+				TXPORT.LastDone = TXPORT.TxALET.Done;
+				pNet->TransmitTimeoutTimer = 0;
+			} else {
+				pNet->TransmitTimeoutTimer++;
+				if (pNet->TransmitTimeoutTimer >= 10) {
+					pNet->TransmitTimeoutTimer = 0;
+#ifdef CHECK_TRANSMIT_TIMEOUT
+					StartTimer =  SK_FALSE;
+					SkLocalEventQueue(pAC, SKGE_DRV,
+						SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
+#endif
+				}
+			}
+		}
+
+#ifdef CHECK_TRANSMIT_TIMEOUT
+		if (!timer_pending(&pNet->KernelTimer)) {
+			pNet->KernelTimer.expires = jiffies + NewTimerInterval;
+			add_timer(&pNet->KernelTimer);
+			pNet->TimerExpired = SK_FALSE;
+		}
+#endif
+	}
+}
+
+
+/*****************************************************************************
+*
+* CheckRXCounters - Checks the the statistics for RX path hang
+*
+* Description:
+*	This function is called periodical by a timer.
+*
+* Notes:
+*
+* Function Parameters:
+*
+* Returns:
+*	Traffic status
+*
+*/
+static SK_BOOL CheckRXCounters(
+DEV_NET *pNet)  /* holds the pointer to adapter control context */
+{
+	SK_AC           	*pAC = pNet->pAC;
+	SK_BOOL bStatus 	= SK_FALSE;
+
+	/* Variable used to store the MAC RX FIFO RP, RPLev*/
+	SK_U32			MACFifoRP = 0;
+	SK_U32			MACFifoRLev = 0;
+
+	/* Variable used to store the PCI RX FIFO RP, RPLev*/
+	SK_U32			RXFifoRP = 0;
+	SK_U8			RXFifoRLev = 0;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> CheckRXCounters()\n"));
+
+	/*Check if statistic counters hangs*/
+	if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
+		/* Now read the values of read pointer/level from MAC RX FIFO again */
+		SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
+		SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
+
+		/* Now read the values of read pointer/level from RX FIFO again */
+		SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
+		SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
+
+		/* Check if the MAC RX hang */
+		if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
+			(MACFifoRLev != 0) &&
+			(MACFifoRLev >= pNet->PreviousMACFifoRLev)){
+			bStatus = SK_TRUE;
+		}
+
+		/* Check if the PCI RX hang */
+		if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
+			(RXFifoRLev != 0) &&
+			(RXFifoRLev >= pNet->PreviousRXFifoRLev)){
+			/*Set the flag to indicate that the RX FIFO hangs*/
+			bStatus = SK_TRUE;
+		}
+	}
+
+	/* Store now the values of counters for next check */
+	pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
+
+	/* Store the values of  read pointer/level from MAC RX FIFO for next test */
+	pNet->PreviousMACFifoRP = MACFifoRP;
+	pNet->PreviousMACFifoRLev = MACFifoRLev;
+
+	/* Store the values of  read pointer/level from RX FIFO for next test */
+	pNet->PreviousRXFifoRP = RXFifoRP;
+	pNet->PreviousRXFifoRLev = RXFifoRLev;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== CheckRXCounters()\n"));
+
+	return bStatus;
+}
+
+/*****************************************************************************
+*
+* CheckRxPath - Checks if the RX path
+*
+* Description:
+*	This function is called periodical by a timer.
+*
+* Notes:
+*
+* Function Parameters:
+*
+* Returns:
+*	None.
+*
+*/
+static void  CheckRxPath(
+DEV_NET *pNet)  /* holds the pointer to adapter control context */
+{
+	unsigned long		Flags;    /* for the spin locks    */
+	/* Initialize the pAC structure.*/
+	SK_AC           	*pAC = pNet->pAC;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> CheckRxPath()\n"));
+
+	/*If the statistics are not changed then could be an RX problem */
+	if (CheckRXCounters(pNet)){
+		/*
+		 * First we try the simple solution by resetting the Level Timer
+		 */
+
+		/* Stop Level Timer of Status BMU */
+		SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
+
+		/* Start Level Timer of Status BMU */
+		SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
+
+		if (!CheckRXCounters(pNet)) {
+			return;
+		}
+
+		spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+		SkLocalEventQueue(pAC, SKGE_DRV,
+			SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
+
+		/* Reset the fifo counters */
+		pNet->PreviousMACFifoRP = 0;
+		pNet->PreviousMACFifoRLev = 0;
+		pNet->PreviousRXFifoRP = 0;
+		pNet->PreviousRXFifoRLev = 0;
+
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== CheckRxPath()\n"));
+}
+
+
+
+#endif
+
+
+#ifdef CONFIG_PM
+/*****************************************************************************
+ *
+ * 	sk98lin_resume - Resume the the card
+ *
+ * Description:
+ *	This function resumes the card into the D0 state
+ *
+ * Returns: N/A
+ *
+ */
+static int sk98lin_resume(
+struct pci_dev *pdev)   /* the device that is to resume */
+{
+	struct net_device   *dev  = pci_get_drvdata(pdev);
+	DEV_NET		    *pNet = PPRIV;
+	SK_AC		    *pAC  = pNet->pAC;
+	SK_U16		     PmCtlSts;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+	int                  rCode;
+#endif
+
+	/* Set the power state to D0 */
+	pci_set_power_state(pdev, 0);
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
+	pci_restore_state(pdev);
+#else
+	pci_restore_state(pdev, pAC->PciState);
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+	rCode = pci_enable_device(pdev);
+	if (rCode)
+		return rCode;
+#else
+	pci_enable_device(pdev);
+#endif
+	pci_set_master(pdev);
+
+	pci_enable_wake(pdev, 3, 0);
+	pci_enable_wake(pdev, 4, 0);
+
+	/* Set the adapter power state to D0 */
+	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
+	PmCtlSts &= ~(PCI_PM_STATE_D3);	/* reset all DState bits */
+	PmCtlSts |= PCI_PM_STATE_D0;
+	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
+
+	/* Reinit the adapter and start the port again */
+	pAC->BoardLevel = SK_INIT_DATA;
+	SkDrvLeaveDiagMode(pAC);
+
+	if (((pAC->WasIfUp[0] == SK_TRUE) || (pAC->WasIfUp[1] == SK_TRUE)) &&
+		(pAC->Suspended == SK_TRUE)) {
+
+		/* Enable interrupts */
+		SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SK_OUT32(pAC->IoBase, B0_HWE_IMSK, Y2_IRQ_HWE_MASK);
+		}
+		else {
+			SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+		}
+	}
+	pAC->Suspended = SK_FALSE;
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	if (pAC->GIni.GIDontInitPhy == SK_TRUE) {
+
+		/*
+		 * Start queue and carrier, set interface to running,
+		 * but don't enable the queue if SDK queue handling
+		 * is active
+		 */
+		if (!pAC->SdkQH) {
+			netif_wake_queue(pAC->dev[pNet->PortNr]);
+		}
+		netif_carrier_on(dev);
+		dev->flags |= IFF_RUNNING;
+	}
+
+	/* Map any waiting RX buffers to HW */
+#ifdef USE_SK_RSS_SUPPORT
+	SkSetRssSupport(pAC, pNet->PortNr);
+#endif
+	FillReceiveTableYukon2(pAC, pAC->IoBase, pNet->PortNr);
+	pAC->GIni.GIDontInitPhy = SK_FALSE;
+#endif
+	printk("sk98lin: resume complete\n");
+#endif
+
+	return 0;
+
+}
+
+
+/*****************************************************************************
+ *
+ * 	sk98lin_suspend - Suspend the card
+ *
+ * Description:
+ *	This function suspends the card into a defined state
+ *
+ * Returns: N/A
+ *
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,10)
+static int sk98lin_suspend(
+struct pci_dev	*pdev,   /* pointer to the device that is to suspend */
+pm_message_t	state)  /* what power state is desired by Linux?    */
+#else
+static int sk98lin_suspend(
+struct pci_dev	*pdev,   /* pointer to the device that is to suspend */
+SK_U32	state)  /* what power state is desired by Linux?    */
+#endif
+{
+	struct net_device   *dev  = pci_get_drvdata(pdev);
+	DEV_NET		    *pNet = PPRIV;
+	SK_AC		    *pAC  = pNet->pAC;
+	SK_U16		     PciPMControlStatus;
+	SK_U16		     PciPMCapabilities;
+	SK_MAC_ADDR	     MacAddr;
+	int		     i;
+
+	/* First Yukon revs do not support power management */
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
+		if (pAC->GIni.GIChipRev == 0) {
+			return 0; /* power management not supported */
+		}
+	}
+
+#if 0
+	if (pAC->WolInfo.ConfiguredWolOptions == 0) {
+		return 0; /* WOL possible, but disabled via ethtool */
+	}
+#endif
+
+	if(netif_running(dev)) {
+		netif_stop_queue(dev); /* stop device if running */
+	}
+
+	/* Read the PM control/status register from the PCI config space */
+	SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
+
+	/* Read the power management capabilities from the PCI config space */
+	SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
+
+	/* Enable WakeUp with Magic Packet - get MAC address from adapter */
+	for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
+		/* virtual address: will be used for data */
+		SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
+	}
+
+	pAC->Suspended = SK_TRUE;
+
+	SkDrvEnterDiagMode(pAC);
+	SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
+
+#ifndef MV_INCLUDE_SDK_SUPPORT
+	SetDynamicClockGating(pAC, pAC->IoBase);
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,15)
+	device_set_wakeup_enable(&pdev->dev, 1);
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
+	pci_save_state(pdev);
+#else
+	pci_save_state(pdev, pAC->PciState);
+#endif
+	/* Possibly we need to evaluate the return values */
+	pci_enable_wake(pdev, 3, 1);	/* D3 hot */
+	pci_enable_wake(pdev, 4, 1);	/* D3 cold */
+
+	pci_disable_device(pdev);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,10)
+	pci_set_power_state(pdev, pci_choose_state(pdev, state)); /* set the state */
+#else
+	pci_set_power_state(pdev, state); /* set the state */
+#endif
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	printk("sk98lin: suspend complete\n");
+#endif
+
+	return 0;
+}
+
+
+/******************************************************************************
+ *
+ *	SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
+ *
+ * Context:
+ *	init, pageable
+ *	the adapter should be de-initialized before calling this function
+ *
+ * Returns:
+ *	nothing
+ */
+
+static void SkEnableWOMagicPacket(
+SK_AC         *pAC,      /* Adapter Control Context          */
+SK_IOC         IoC,      /* I/O control context              */
+SK_MAC_ADDR    MacAddr)  /* MacAddr expected in magic packet */
+{
+	SK_U16	Word;
+	SK_U32	DWord;
+	SK_U16  AutoNegAdv;
+	SK_U16  PhyCtrl;
+	int 	Port;
+	int 	i;
+
+	/* Use port 0 as long as we do not have any dual port cards which support WOL */
+	Port = 0;
+	DWord = 0;
+
+	SK_OUT8(IoC, B0_POWER_CTRL, 0xa9);		/* enable VAUX */
+
+	if (pAC->WolInfo.ConfiguredWolOptions == 0) {
+		return; /* WOL possible, but disabled via ethtool */
+	}
+
+	SK_OUT16(IoC, B0_CTST, 0x0002);			/* clear S/W Reset */
+	SK_OUT16(IoC, GMAC_LINK_CTRL, 0x0002);	/* clear Link Reset */
+
+	/*
+	 * PHY Configuration:
+	 * Autonegotiation is enabled, advertise 10 HD, 10 FD,
+	 * 100 HD, and 100 FD.
+	 */
+	if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC)   ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_UL_2) ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR) ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_XL)   ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_EX)   ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_OPT)   ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON)      ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
+
+		SK_OUT8(IoC, B0_POWER_CTRL, 0xa9);		/* enable VAUX */
+
+		/* WA code for COMA mode */
+		/* Only for yukon plus based chipsets rev A3 */
+		if  ( (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) &&
+		      (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ) {
+			SK_IN32(IoC, B2_GP_IO, &DWord);
+			DWord |= GP_DIR_9;				/* set to output */
+			DWord &= ~GP_IO_9;				/* clear PHY reset (active high) */
+			SK_OUT32(IoC, B2_GP_IO, DWord);	/* clear PHY reset */
+		}
+
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
+			SK_OUT32(IoC, GPHY_CTRL, 0x01f04001);	/* set PHY reset */
+			SK_OUT32(IoC, GPHY_CTRL, 0x01f04002);	/* clear PHY reset */
+		} else {
+#ifndef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+			SK_OUT8(IoC, GPHY_CTRL, 0x02);		/* clear PHY reset */
+#endif
+		}
+#ifndef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+		SK_OUT8(IoC, GMAC_CTRL, 0x02);			/* clear MAC reset */
+
+		SkCheckWOParam(pAC, &AutoNegAdv, &PhyCtrl);
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv); /* Advertise 10/100 HD/FD */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, 0); /* Do not advertise 1000 HD/FD */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl); /* 100 MBps, Autoneg, FD */
+
+		GM_OUT16(IoC, Port, GM_GP_CTRL, 0x383a);
+#endif
+	} else if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
+			   (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P)) {
+		SK_OUT8(IoC, B0_POWER_CTRL, 0xa9);		/* enable VAUX */
+		SK_OUT8(IoC, GPHY_CTRL, 0x02);			/* clear PHY reset */
+		SK_OUT8(IoC, GMAC_CTRL, 0x02);			/* clear MAC reset */
+		SkCheckWOParam(pAC, &AutoNegAdv, &PhyCtrl);
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);     /* 100 MBit, disable Autoneg */
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P) {
+			/* Enable Link Partner Next Page */
+			/* Disable Energy Detect and enable Scrambler */
+			Word = 0x1130;
+		} else {
+			/* Enable Automatic Crossover */
+			Word = 0x0130;
+		}
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);     /* Write Parameters */
+
+		/*
+		 * MAC Configuration:
+		 * Set the MAC to 100 HD and enable the auto update
+		 * features for Speed and Duplex Mode.
+		 * If autonegotiation completes successfully, the
+		 * MAC takes the link parameters from the PHY.
+		 * If the link partner doesn't support autonegotiation,
+		 * the MAC can receive magic packets if the link partner
+		 * uses 100 HD.
+		 */
+		GM_OUT16(IoC, Port, GM_GP_CTRL, 0x383a);
+	}
+
+	/*
+	 * Set Up Magic Packet parameters
+	 */
+#ifndef MV_INCLUDE_SDK_SUPPORT
+	for (i = 0; i < 6; i+=2) {				/* Set up magic packet MAC address */
+		SK_IN16(IoC, B2_MAC_1 + i, &Word);
+		SK_OUT16(IoC, WOL_MAC_ADDR_LO + i, Word);
+	}
+
+	Word = 0x0;
+	Word |= WOL_CTL_ENA_PME_ON_MAGIC_PKT;   /* Enable PME on magic packet */
+	Word |= WOL_CTL_ENA_MAGIC_PKT_UNIT;     /* Enable magic packet unit */
+	SK_OUT16(IoC, WOL_CTRL_STAT, Word);
+#else
+	for (i = 0; i < 6; i+=2) {				/* Delete magic packet MAC address */
+		SK_OUT16(IoC, WOL_MAC_ADDR_LO + i, 0x0);
+	}
+
+	Word = 0x0;
+	Word |= WOL_CTL_DIS_PME_ON_MAGIC_PKT;   /* Disable PME on magic packet */
+	Word |= WOL_CTL_DIS_MAGIC_PKT_UNIT;     /* Disable magic packet unit */
+	Word |= WOL_CTL_DIS_PME_ON_LINK_CHG;    /* Disable PME on link change */
+	Word |= WOL_CTL_DIS_LINK_CHG_UNIT;      /* Disable link change unit */
+	SK_OUT16(IoC, WOL_CTRL_STAT, Word);
+
+	/* Hand over control to firmware */
+	if (pAC->FwRun && pAC->FwState) {
+		FwDriverGoodbye(pAC, pAC->IoBase);
+	}
+#endif
+
+	SK_OUT16(IoC, B0_CTST, Y2_HW_WOL_OFF);
+
+} /* SkEnableWOMagicPacket */
+
+
+/*****************************************************************************
+ *
+ *      SkCheckWOParam - Check the WOM param
+ *
+ * Description:
+ *
+ * Returns:     N/A
+ */
+static void SkCheckWOParam (
+SK_AC    *pAC,          /* pointer to adapter context          */
+SK_U16   *AutoNegAdv,
+SK_U16   *PhyCtrl)
+{
+
+	*AutoNegAdv = PHY_SEL_TYPE;
+	*PhyCtrl = 0;	/* PHY_MARV_CTRL */
+
+	/* set Auto-negotiation advertisement */
+	if (pAC->GIni.GICopperType) {
+		/* set Speed capabilities */
+		switch (pAC->WolSpeedType) {
+		case SK_LSPEED_AUTO:
+			*AutoNegAdv |= PHY_M_AN_100_FD_HD | PHY_M_AN_10_FD_HD;
+			*PhyCtrl |= PHY_CT_SP100; /* Default: 100MBPS */
+			break;
+		case SK_LSPEED_100MBPS:
+			*AutoNegAdv |= PHY_M_AN_100_FD_HD;
+			*PhyCtrl |= PHY_CT_SP100; /* Default: 100MBPS */
+			break;
+		case SK_LSPEED_10MBPS:
+			*AutoNegAdv |= PHY_M_AN_10_FD_HD;
+			*PhyCtrl |= PHY_CT_SP10;
+			break;
+		default:
+			*AutoNegAdv |= PHY_M_AN_100_FD_HD | PHY_M_AN_10_FD_HD;
+			*PhyCtrl |= PHY_CT_SP100; /* Default: 100MBPS */
+		}
+	}
+
+	/* Set the duplex mode */
+	if (pAC->WolDuplexType) {
+		*PhyCtrl = PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
+				PHY_CT_DUP_MD |  PHY_CT_COL_TST | PHY_CT_SPS_MSB |
+				PHY_CT_RE_CFG;
+	} else {
+		*PhyCtrl = PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
+				PHY_CT_COL_TST | PHY_CT_SPS_MSB | PHY_CT_RE_CFG;
+	}
+}
+
+#ifndef MV_INCLUDE_SDK_SUPPORT
+/******************************************************************************
+ *
+ *	SetDynamicClockGating - Enable dynamic clock gating
+ *
+ * Context:
+ *
+ * Returns:
+ *	nothing
+ */
+
+static void SetDynamicClockGating(
+SK_AC         *pAC,      /* Adapter Control Context          */
+SK_IOC         IoC)      /* I/O control context              */
+{
+	SK_U32 TmpVal32;
+	SK_U32 DCMask32;
+	SK_U8  TmpVal8;
+	SK_U16 SWord;
+
+	/* Enable Config write (Reg 0x158) */
+	SK_IN8(pAC->IoBase, B2_TST_CTRL1, &TmpVal8 );
+	TmpVal8 &= ~TST_CFG_WRITE_OFF;
+	TmpVal8 |= TST_CFG_WRITE_ON;
+	SK_OUT8(pAC->IoBase, B2_TST_CTRL1, TmpVal8 );
+
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PCI_OUR_REG_3, 0);
+
+	SK_IN32(pAC->IoBase, Y2_CFG_SPC + PCI_OUR_REG_4, &TmpVal32);
+	DCMask32 = PCIE_OUR4_DYN_CLK_GATE_SET | P_ASPM_FORCE_CLKREQ_ENA;
+	DCMask32 &= ~P_TIMER_VALUE_MSK; /* 0x68003015 */
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PCI_OUR_REG_4, TmpVal32 | DCMask32);
+
+#if 0
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PCI_OUR_REG_5,
+		PCIE_OUR5_EVENT_CLK_D3_SET |
+		PCIE_OUR5_EPROM_LDR_FIN |
+		PCIE_OUR5_EPROM_LDR_NOT_FIN |
+		P_GAT_CPU_TO_SLEEP |
+		P_REL_CPU_TO_SLEEP); /* 0x034a8b4a */
+#else
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PCI_OUR_REG_5, 0x034a8b4a);
+#endif
+
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PCI_CFG_REG_1,
+		PCIE_CFG1_EVENT_CLK_D3_SET); /* 0x01f60103 */
+
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + CONFIG_REG0, CONFIG_REG0_CLK_RUN_ASF |
+			CONFIG_REG0_CLK_RUN_FLASH);
+
+	SK_IN32(pAC->IoBase, Y2_CFG_SPC + PSM_CONFIG_REG1, &TmpVal32);
+	TmpVal32 |= PSM_CONFIG_REG1_CLK_RUN_ASF;
+	SK_OUT32(pAC->IoBase, Y2_CFG_SPC + PSM_CONFIG_REG1, TmpVal32);
+
+	SkGmPhyWrite(pAC, pAC->IoBase, 0, PHY_MARV_EXT_ADR, 0);
+	SkGmPhyRead(pAC, pAC->IoBase, 0, PHY_MARV_EXT_CTRL_2, &SWord);
+	SkGmPhyWrite(pAC, pAC->IoBase, 0, PHY_MARV_EXT_CTRL_2, SWord | BIT_0S);
+}
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)
+/*****************************************************************************
+ *
+ * 	sk98lin_shutdown
+ *
+ * Description:
+ *	This function suspends the card into a defined state
+ *
+ * Returns: N/A
+ *
+ */
+static void sk98lin_shutdown(struct pci_dev *pdev) {
+	sk98lin_suspend(pdev, PMSG_SUSPEND);
+}
+#endif
+
+#endif
+
+
+/*****************************************************************************
+ *
+ * 	FreeResources - release resources allocated for adapter
+ *
+ * Description:
+ *	This function releases the IRQ, unmaps the IO and
+ *	frees the desriptor ring.
+ *
+ * Returns: N/A
+ *
+ */
+static void FreeResources(struct SK_NET_DEVICE *dev)
+{
+DEV_NET		*pNet;
+SK_AC		*pAC;
+
+	if (PRIV) {
+		pNet = PPRIV;
+		pAC = pNet->pAC;
+
+		if (pAC->PciDev) {
+			pci_release_regions(pAC->PciDev);
+		}
+		if (pAC->IoBase) {
+			iounmap(pAC->IoBase);
+		}
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2FreeResources(pAC);
+		} else {
+			BoardFreeMem(pAC);
+		}
+	}
+
+} /* FreeResources */
+
+MODULE_AUTHOR("Mirko Lindner <support@marvell.com>");
+MODULE_DESCRIPTION("Marvell/SysKonnect Yukon Ethernet Network Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+#ifdef LINK_SPEED_A
+static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
+#else
+static char *Speed_A[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef LINK_SPEED_B
+static char *Speed_B[SK_MAX_CARD_PARAM] = LINK_SPEED;
+#else
+static char *Speed_B[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef AUTO_NEG_A
+static char *AutoNeg_A[SK_MAX_CARD_PARAM] = AUTO_NEG_A;
+#else
+static char *AutoNeg_A[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef DUP_CAP_A
+static char *DupCap_A[SK_MAX_CARD_PARAM] = DUP_CAP_A;
+#else
+static char *DupCap_A[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef FLOW_CTRL_A
+static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = FLOW_CTRL_A;
+#else
+static char *FlowCtrl_A[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef ROLE_A
+static char *Role_A[SK_MAX_CARD_PARAM] = ROLE_A;
+#else
+static char *Role_A[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef AUTO_NEG_B
+static char *AutoNeg_B[SK_MAX_CARD_PARAM] = AUTO_NEG_B;
+#else
+static char *AutoNeg_B[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef DUP_CAP_B
+static char *DupCap_B[SK_MAX_CARD_PARAM] = DUP_CAP_B;
+#else
+static char *DupCap_B[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef FLOW_CTRL_B
+static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = FLOW_CTRL_B;
+#else
+static char *FlowCtrl_B[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef ROLE_B
+static char *Role_B[SK_MAX_CARD_PARAM] = ROLE_B;
+#else
+static char *Role_B[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef CON_TYPE
+static char *ConType[SK_MAX_CARD_PARAM] = CON_TYPE;
+#else
+static char *ConType[SK_MAX_CARD_PARAM];
+#endif
+
+#ifdef WOL_TYPE
+static char *WolType[SK_MAX_CARD_PARAM] = WOL_TYPE;
+#else
+static char *WolType[SK_MAX_CARD_PARAM];
+#endif
+
+static int  IntsPerSec[SK_MAX_CARD_PARAM];
+static char *Moderation[SK_MAX_CARD_PARAM];
+static char *ModerationMask[SK_MAX_CARD_PARAM];
+static int  TxModeration[SK_MAX_CARD_PARAM];
+static char *LowLatency[SK_MAX_CARD_PARAM];
+static char *MsiIrq[SK_MAX_CARD_PARAM];
+static char *RSS[SK_MAX_CARD_PARAM];
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+static char *LinkMaintenance[SK_MAX_CARD_PARAM];
+#endif
+#ifdef MV_INCLUDE_SDK_SUPPORT
+static char *SdkQH[SK_MAX_CARD_PARAM];
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
+module_param_array(Speed_A, charp, NULL, 0);
+module_param_array(Speed_B, charp, NULL, 0);
+module_param_array(AutoNeg_A, charp, NULL, 0);
+module_param_array(AutoNeg_B, charp, NULL, 0);
+module_param_array(DupCap_A, charp, NULL, 0);
+module_param_array(DupCap_B, charp, NULL, 0);
+module_param_array(FlowCtrl_A, charp, NULL, 0);
+module_param_array(FlowCtrl_B, charp, NULL, 0);
+module_param_array(Role_A, charp, NULL, 0);
+module_param_array(Role_B, charp, NULL, 0);
+module_param_array(ConType, charp, NULL, 0);
+module_param_array(WolType, charp, NULL, 0);
+module_param_array(IntsPerSec, int, NULL, 0);
+module_param_array(Moderation, charp, NULL, 0);
+module_param_array(ModerationMask, charp, NULL, 0);
+module_param_array(LowLatency, charp, NULL, 0);
+module_param_array(TxModeration, int, NULL, 0);
+module_param_array(MsiIrq, charp, NULL, 0);
+module_param_array(RSS, charp, NULL, 0);
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+module_param_array(LinkMaintenance, charp, NULL, 0);
+#endif
+#ifdef MV_INCLUDE_SDK_SUPPORT
+module_param_array(SdkQH, charp, NULL, 0);
+#endif
+#else
+MODULE_PARM(Speed_A,          "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(Speed_B,          "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(AutoNeg_A,        "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(AutoNeg_B,        "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(DupCap_A,         "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(DupCap_B,         "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(FlowCtrl_A,       "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(FlowCtrl_B,       "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(Role_A,           "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(Role_B,           "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(ConType,	      "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(WolType,	      "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(IntsPerSec,       "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
+MODULE_PARM(Moderation,       "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(ModerationMask,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(LowLatency,       "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(TxModeration,     "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
+MODULE_PARM(MsiIrq,           "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+MODULE_PARM(RSS,              "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+MODULE_PARM(LinkMaintenance,  "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+#endif
+MODULE_PARM(SdkQH,            "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
+#endif
+#endif
+
+
+/*****************************************************************************
+ *
+ * 	sk98lin_remove_device - device deinit function
+ *
+ * Description:
+ *	Disable adapter if it is still running, free resources,
+ *	free device struct.
+ *
+ * Returns: N/A
+ */
+
+static void sk98lin_remove_device(struct pci_dev *pdev)
+{
+DEV_NET		*pNet;
+SK_AC		*pAC;
+struct SK_NET_DEVICE *next;
+unsigned long Flags;
+struct net_device *dev = pci_get_drvdata(pdev);
+
+	/* Device not available. Return. */
+	if (!dev)
+		return;
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+	next = pAC->Next;
+
+	netif_stop_queue(dev);
+
+	SkAddrMcUpdate(pAC,pAC->IoBase, 0); /* Mac update */
+	SkGeYellowLED(pAC, pAC->IoBase, 0);
+
+	if(pAC->BoardLevel == SK_INIT_RUN) {
+		/* board is still alive */
+		spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+		SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+					0, -1, SK_FALSE);
+		SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+					1, -1, SK_TRUE);
+
+		/* Disable interrupts */
+		SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+		SkGeDeInit(pAC, pAC->IoBase);
+
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+		pAC->BoardLevel = SK_INIT_DATA;
+		/* We do NOT check here, if IRQ was pending, of course*/
+	}
+
+	if(pAC->BoardLevel == SK_INIT_IO) {
+		/* board is still alive */
+		SkGeDeInit(pAC, pAC->IoBase);
+		pAC->BoardLevel = SK_INIT_DATA;
+	}
+
+#ifdef CONFIG_PROC_FS
+	/* Remove the sk98lin procfs device entries */
+	if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
+		if (pAC->InterfaceUp[1] == 1) {
+			remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
+		}
+	}
+	if (pAC->InterfaceUp[0] == 1) {
+		remove_proc_entry(pAC->dev[0]->name, pSkRootDir);
+	}
+#endif
+	if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
+		unregister_netdev(pAC->dev[1]);
+		free_netdev(pAC->dev[1]);
+	}
+
+	FreeResources(dev);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
+	dev->get_stats = NULL;
+#endif
+
+	/*
+	 * otherwise unregister_netdev calls get_stats with
+	 * invalid IO ...  :-(
+	 */
+	unregister_netdev(dev);
+	free_netdev(dev);
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	if (pAC->FwBufferLen > 0) {
+		/* Clear the old buffer */
+		kfree(pAC->pFwBuffer);
+	}
+#endif
+
+	kfree(pAC);
+	sk98lin_max_boards_found--;
+
+#ifdef CONFIG_PROC_FS
+	/* Remove all Proc entries if last device */
+	if (sk98lin_max_boards_found == 0) {
+		/* clear proc-dir */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+#ifndef SK_DISABLE_PROC_UNLOAD
+		remove_proc_entry(pSkRootDir->name, proc_net);
+#endif
+#else
+		remove_proc_entry(pSkRootDir->name, init_net.proc_net);
+#endif
+	}
+#endif
+
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeRequestIrq
+ *
+ * Description:
+ *	Handle software interrupt used during MSI test
+ * Returns:
+ *	IRQ_HANDLED if everything is ok
+ *      IRQ_NONE on error
+ */
+static int SK_DEVINIT SkGeRequestIrq(struct SK_NET_DEVICE *dev)
+{
+	DEV_NET *pNet = PPRIV;
+	SK_AC   *pAC  = pNet->pAC;
+	int	Ret;
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
+		Ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, dev->name, dev);
+#else
+		Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev);
+#endif
+	} else {
+		if ((pAC->GIni.GIPciBus == SK_PEX_BUS) &&
+			(pAC->MsiIrq) && (pci_enable_msi(pAC->PciDev) == 0)) {
+			Ret = SkGeTestMsi(dev, pAC);
+			if (Ret) {
+				/* Error */
+				printk("sk98lin: MSI enable error\n");
+				pci_disable_msi(pAC->PciDev);
+				pAC->AllocFlag &= ~SK_ALLOC_MSI;
+			} else {
+				dev->irq = pAC->PciDev->irq;
+			}
+		}
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
+		Ret = request_irq(dev->irq, SkY2Isr,
+			(pAC->AllocFlag & SK_ALLOC_MSI) ? 0 : IRQF_SHARED,
+			dev->name, dev);
+#else
+		Ret = request_irq(dev->irq, SkY2Isr,
+			(pAC->AllocFlag & SK_ALLOC_MSI) ? 0 : SA_SHIRQ,
+			dev->name, dev);
+#endif
+	}
+
+	if (Ret) {
+		printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
+			dev->irq);
+		return -EAGAIN;
+	} else if ((pAC->AllocFlag & SK_ALLOC_MSI) == 0) {
+		pAC->AllocFlag |= SK_ALLOC_IRQ;
+	}
+	pAC->IrqDev = dev;
+	return 0;
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeReleaseIrq
+ *
+ * Description:
+ *	Handle software interrupt used during MSI test
+ * Returns:
+ *	IRQ_HANDLED if everything is ok
+ *      IRQ_NONE on error
+ */
+static void SkGeReleaseIrq(struct SK_NET_DEVICE *dev)
+{
+	DEV_NET *pNet;
+	SK_AC   *pAC;
+
+	if (PRIV) {
+		pNet = PPRIV;
+		pAC = pNet->pAC;
+
+		if (pAC->AllocFlag & SK_ALLOC_MSI) {
+			free_irq(dev->irq, dev);
+			pci_disable_msi(pAC->PciDev);
+		}
+		if (pAC->AllocFlag & SK_ALLOC_IRQ) {
+			free_irq(dev->irq, dev);
+		}
+	}
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeTestIntr - SW interrupt test
+ *
+ * Description:
+ *	Handle software interrupt used during MSI test
+ * Returns:
+ *	IRQ_HANDLED if everything is ok
+ *      IRQ_NONE on error
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+static int SK_DEVINIT SkGeTestIsr(int irq, void *dev_id)
+#else
+static int SK_DEVINIT SkGeTestIsr(int irq, void *dev_id, struct pt_regs *ptregs)
+#endif
+{
+	struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
+	DEV_NET         *pNet;
+	SK_AC           *pAC;
+	SK_U32		status;
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+
+	SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &status);
+
+	if (status == 0)
+		return IRQ_NONE;
+
+	if (status & Y2_IS_IRQ_SW) {
+		pAC->AllocFlag |= SK_ALLOC_MSI;
+		wake_up(&pAC->msi_wait);
+		SK_OUT32(pAC->IoBase, B0_CTST, CS_CL_SW_IRQ);
+	}
+
+	SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
+	return IRQ_HANDLED;
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeTestMsi - Test interrupt path
+ *
+ * Description:
+ *
+ * Returns:
+ *	0, if everything is ok
+ *      !=0, on error
+ */
+static int SK_DEVINIT SkGeTestMsi(struct SK_NET_DEVICE *dev, SK_AC *pAC)
+{
+	struct pci_dev *pdev = pAC->PciDev;
+	int		Ret;
+	SK_U32		test32;
+	SK_U8		test8;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
+	Ret = request_irq(pdev->irq, SkGeTestIsr, 0, dev->name, dev);
+#else
+	Ret = request_irq(pdev->irq, (irq_handler_t) SkGeTestIsr, 0, dev->name, dev);
+#endif
+
+	if (Ret) {
+		dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
+		return Ret;
+	}
+
+	init_waitqueue_head (&pAC->msi_wait);
+
+	/* Enable SW IRQ */
+	SK_OUT32(pAC->IoBase, B0_IMSK, Y2_IS_IRQ_SW);
+
+	SK_OUT8(pAC->IoBase, B0_CTST, CS_ST_SW_IRQ);
+	SK_IN8(pAC->IoBase, B0_CTST, &test8);
+
+	wait_event_timeout(pAC->msi_wait, (pAC->AllocFlag & SK_ALLOC_MSI), HZ/10);
+
+	if (!(pAC->AllocFlag & SK_ALLOC_MSI)) {
+		/* MSI test failed, go back to INTx mode */
+		dev_info(&pdev->dev, "No interrupt generated using MSI, "
+			"switching to INTx mode.\n");
+		Ret = -EOPNOTSUPP;
+		SK_OUT8(pAC->IoBase, B0_CTST, CS_CL_SW_IRQ);
+	}
+
+	/* Disable the interrupts */
+	SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+	SK_IN32(pAC->IoBase, B0_IMSK, &test32);
+	free_irq(pdev->irq, dev);
+
+	return Ret;
+}
+
+#ifdef USE_SK_RSS_SUPPORT
+/*****************************************************************************
+ *
+ * 	SkSetRssSupport - Set the RSS support in the hardware
+ *
+ * Description:
+ *
+ * Returns:
+ *	N/A
+ */
+static void SkSetRssSupport(SK_AC *pAC, int Port)
+{
+	SK_U32 i;
+	SK_U32 nkeys = 4;
+	nkeys = pAC->GIni.GINumOfRssKeys;
+
+	if (!nkeys) {
+	/* Don't handle RSS */
+		return;
+	}
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_4229)) {
+		SK_OUT32(pAC->IoBase, 0x434, BIT_13);
+	}
+
+	/*
+	 * Starting with Extreme B0 we can configure the RSS based on HashType.
+	 * Supports IPv6 and other modes
+	 */
+	if(HW_IS_EXT_LE_FORMAT(pAC)) {
+		SK_OUT32(pAC->IoBase, RSS_CFG, 0x3f);	/* Hash all */
+	}
+
+	/* Program RSS initial values */
+	if (pAC->dev[Port]->features & NETIF_F_RXHASH) {
+		SK_U32 key[nkeys];
+
+		get_random_bytes(key, nkeys * sizeof(u32));
+
+		for (i = 0; i < nkeys; i++) {
+			SK_OUT32(pAC->IoBase, RSS_KEY_ADDR(Port, (i*4)), key[i]);
+		}
+
+		SkGeRxRss(pAC, pAC->IoBase, Port, SK_TRUE);
+	} else {
+	/* Disable hashing */
+		SK_OUT32(pAC->IoBase, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
+			     BMU_DIS_RX_RSS_HASH);
+	}
+}
+#endif
+
+/*****************************************************************************
+ *
+ * 	SkGeBoardInit - do level 0 and 1 initialization
+ *
+ * Description:
+ *	This function prepares the board hardware for running. The desriptor
+ *	ring is set up, the IRQ is allocated and the configuration settings
+ *	are examined.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static int __devinit SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
+{
+	short	i;
+	char	*DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */
+	char	*VerStr	= VER_STRING;
+#ifndef MV_INCLUDE_SDK_SUPPORT
+	unsigned long   Flags;    	/* for the spin locks	*/
+	SK_U32		TmpVal32;
+#endif
+
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("IoBase: %08lX\n", (unsigned long)pAC->IoBase));
+	for (i=0; i<SK_MAX_MACS; i++) {
+		pAC->TxPort[i][0].HwAddr = pAC->IoBase + TxQueueAddr[i][0];
+		pAC->TxPort[i][0].PortIndex = i;
+		pAC->RxPort[i].HwAddr = pAC->IoBase + RxQueueAddr[i];
+		pAC->RxPort[i].PortIndex = i;
+	}
+
+	/* Initialize the mutexes */
+	for (i=0; i<SK_MAX_MACS; i++) {
+		spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
+		spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
+	}
+
+	spin_lock_init(&pAC->InitLock);		/* Init lock */
+	spin_lock_init(&pAC->SlowPathLock);
+	spin_lock_init(&pAC->TxQueueLock);	/* for Yukon2 chipsets */
+	spin_lock_init(&pAC->SetPutIndexLock);	/* for Yukon2 chipsets */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	spin_lock_init(&pAC->FwFifoLock);	/* For Yukon2 SDK */
+#endif
+
+	/* level 0 init common modules here */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	spin_lock(&pAC->SlowPathLock);
+#else
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+#endif
+
+	/* Does a RESET on board ...*/
+	if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
+		printk("HWInit (0) failed.\n");
+#ifdef MV_INCLUDE_SDK_SUPPORT
+		spin_unlock(&pAC->SlowPathLock);
+#else
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+#endif
+		return(-EAGAIN);
+	}
+	SkI2cInit(  pAC, pAC->IoBase, SK_INIT_DATA);
+	SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
+	SkPnmiInit( pAC, pAC->IoBase, SK_INIT_DATA);
+	SkAddrInit( pAC, pAC->IoBase, SK_INIT_DATA);
+	SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	if (FwInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
+		printk("FwInit(SK_INIT_DATA) failed!\n");
+		spin_unlock(&pAC->SlowPathLock);
+		return(-EAGAIN);
+	}
+#else
+	/* Stop the firmware */
+	if (( pAC->GIni.GIChipId  == CHIP_ID_YUKON_EX ) ||
+		( pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR ))  {
+		if( pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR )
+			SK_OUT32(pAC->IoBase, CPU_WDOG, 0); /* stop the watch dog */
+
+		SK_IN32( pAC->IoBase, HCU_CCSR, &TmpVal32 );
+		TmpVal32 &= ~(BIT_0 | BIT_1);
+		SK_OUT32( pAC->IoBase, HCU_CCSR, TmpVal32 );
+	}
+	else  {
+		SK_IN32( pAC->IoBase, HCU_CCSR, &TmpVal32 );
+		TmpVal32 &= ~(BIT_2 | BIT_3);
+		TmpVal32 |= BIT_3;
+		SK_OUT32( pAC->IoBase, HCU_CCSR, TmpVal32 );
+	}
+#endif
+
+	pAC->BoardLevel = SK_INIT_DATA;
+	pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
+	pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
+
+	SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
+	SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
+
+	/* level 1 init common modules here (HW init) */
+	if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
+		printk("sk98lin: HWInit (1) failed.\n");
+#ifdef MV_INCLUDE_SDK_SUPPORT
+		spin_unlock(&pAC->SlowPathLock);
+#else
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+#endif
+		return(-EAGAIN);
+	}
+	SkI2cInit(  pAC, pAC->IoBase, SK_INIT_IO);
+	SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
+	SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
+	SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
+	SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	if (FwInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
+		printk("sk98lin: SDK support for this device disabled!\n");
+		pAC->FwRun = SK_FALSE;
+	} else {
+		pAC->FwRun = SK_TRUE;
+	}
+
+#endif
+
+#ifdef Y2_RECOVERY
+	/* mark entries invalid */
+	pAC->LastPort = 3;
+	pAC->LastOpc = 0xFF;
+#endif
+
+	/* Set chipset type support */
+	if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
+		(pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
+		pAC->ChipsetType = 1;	/* Yukon chipset (descriptor logic) */
+	} else if (CHIP_ID_YUKON_2(pAC)) {
+		pAC->ChipsetType = 2;	/* Yukon2 chipset (list logic) */
+	}
+
+	/* wake on lan support */
+	pAC->WolInfo.SupportedWolOptions = 0;
+#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
+	pAC->WolInfo.SupportedWolOptions  = WAKE_MAGIC;
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
+		if (pAC->GIni.GIChipRev == 0) {
+			pAC->WolInfo.SupportedWolOptions = 0;
+		}
+	}
+#endif
+	pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	pAC->GIni.GIDontInitPhy = SK_FALSE;
+	pAC->LinkInfo[0].LinkMaintenance = SK_TRUE;
+#endif
+
+	GetConfiguration(pAC);
+	SetConfiguration(pAC);
+
+	if (pAC->RlmtNets == 2) {
+		pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
+		pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
+	}
+
+	/* Set the tx moderation parameter */
+	if (pAC->TxModeration) {
+		pAC->GIni.GITxIdxRepThres = pAC->TxModeration;
+	}
+
+	pAC->BoardLevel = SK_INIT_IO;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	spin_unlock(&pAC->SlowPathLock);
+#else
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+#endif
+
+	/*
+	** Alloc descriptor/LETable memory for this board (both RxD/TxD)
+	*/
+	if (CHIP_ID_YUKON_2(pAC)) {
+		if (!SkY2AllocateResources(pAC)) {
+			printk("No memory for Yukon2 settings\n");
+			return(-EAGAIN);
+		}
+	} else {
+		if(!BoardAllocMem(pAC)) {
+			printk("No memory for descriptor rings.\n");
+			return(-EAGAIN);
+		}
+	}
+
+#ifdef SK_USE_CSUM
+	SkCsSetReceiveFlags(pAC,
+		SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
+		&pAC->CsOfs1, &pAC->CsOfs2, 0);
+	pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
+#endif
+
+	/*
+	** Function BoardInitMem() for Yukon dependent settings...
+	*/
+	BoardInitMem(pAC);
+
+	/*
+	 * Register the device here
+	 */
+	pAC->Next = SkGeRootDev;
+	SkGeRootDev = dev;
+
+	return (0);
+} /* SkGeBoardInit */
+
+
+/*****************************************************************************
+ *
+ * 	BoardAllocMem - allocate the memory for the descriptor rings
+ *
+ * Description:
+ *	This function allocates the memory for all descriptor rings.
+ *	Each ring is aligned for the desriptor alignment and no ring
+ *	has a 4 GByte boundary in it (because the upper 32 bit must
+ *	be constant for all descriptiors in one rings).
+ *
+ * Returns:
+ *	SK_TRUE, if all memory could be allocated
+ *	SK_FALSE, if not
+ */
+static SK_BOOL BoardAllocMem(
+SK_AC	*pAC)
+{
+caddr_t		pDescrMem;	/* pointer to descriptor memory area */
+size_t		AllocLength;	/* length of complete descriptor area */
+int		i;		/* loop counter */
+unsigned long	BusAddr;
+
+
+	/* rings plus one for alignment (do not cross 4 GB boundary) */
+	/* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */
+#if (BITS_PER_LONG == 32)
+	AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
+#else
+	AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
+		+ RX_RING_SIZE + 8;
+#endif
+
+	pDescrMem = pci_alloc_consistent(pAC->PciDev, AllocLength,
+					 &pAC->pDescrMemDMA);
+
+	if (pDescrMem == NULL)
+		return (SK_FALSE);
+
+	pAC->pDescrMem = pDescrMem;
+	BusAddr = (unsigned long) pAC->pDescrMemDMA;
+
+	/* Descriptors need 8 byte alignment, and this is ensured
+	 * by pci_alloc_consistent.
+	 */
+	for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("TX%d/A: pDescrMem: %lX,   PhysDescrMem: %lX\n",
+			i, (unsigned long) pDescrMem,
+			BusAddr));
+		pAC->TxPort[i][0].pTxDescrRing = pDescrMem;
+		pAC->TxPort[i][0].VTxDescrRing = BusAddr;
+		pDescrMem += TX_RING_SIZE;
+		BusAddr += TX_RING_SIZE;
+
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("RX%d: pDescrMem: %lX,   PhysDescrMem: %lX\n",
+			i, (unsigned long) pDescrMem,
+			(unsigned long)BusAddr));
+		pAC->RxPort[i].pRxDescrRing = pDescrMem;
+		pAC->RxPort[i].VRxDescrRing = BusAddr;
+		pDescrMem += RX_RING_SIZE;
+		BusAddr += RX_RING_SIZE;
+	} /* for */
+
+	return (SK_TRUE);
+} /* BoardAllocMem */
+
+
+/****************************************************************************
+ *
+ *	BoardFreeMem - reverse of BoardAllocMem
+ *
+ * Description:
+ *	Free all memory allocated in BoardAllocMem: adapter context,
+ *	descriptor rings, locks.
+ *
+ * Returns:	N/A
+ */
+static void BoardFreeMem(
+SK_AC		*pAC)
+{
+size_t		AllocLength;	/* length of complete descriptor area */
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("BoardFreeMem\n"));
+
+	if (pAC->pDescrMem) {
+
+#if (BITS_PER_LONG == 32)
+		AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
+#else
+		AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
+			+ RX_RING_SIZE + 8;
+#endif
+
+		pci_free_consistent(pAC->PciDev, AllocLength,
+			    pAC->pDescrMem, pAC->pDescrMemDMA);
+		pAC->pDescrMem = NULL;
+	}
+} /* BoardFreeMem */
+
+
+/*****************************************************************************
+ *
+ * 	BoardInitMem - initiate the descriptor rings
+ *
+ * Description:
+ *	This function sets the descriptor rings or LETables up in memory.
+ *	The adapter is initialized with the descriptor start addresses.
+ *
+ * Returns:	N/A
+ */
+static void BoardInitMem(
+SK_AC	*pAC)	/* pointer to adapter context */
+{
+int	i;		/* loop counter */
+int	RxDescrSize;	/* the size of a rx descriptor rounded up to alignment*/
+int	TxDescrSize;	/* the size of a tx descriptor rounded up to alignment*/
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("BoardInitMem\n"));
+
+	if (!pAC->GIni.GIYukon2) {
+		RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
+		pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
+		TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
+		pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
+
+		for (i=0; i<pAC->GIni.GIMacsFound; i++) {
+			SetupRing(
+				pAC,
+				pAC->TxPort[i][0].pTxDescrRing,
+				pAC->TxPort[i][0].VTxDescrRing,
+				(RXD**)&pAC->TxPort[i][0].pTxdRingHead,
+				(RXD**)&pAC->TxPort[i][0].pTxdRingTail,
+				(RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
+				&pAC->TxPort[i][0].TxdRingFree,
+				&pAC->TxPort[i][0].TxdRingPrevFree,
+				SK_TRUE);
+			SetupRing(
+				pAC,
+				pAC->RxPort[i].pRxDescrRing,
+				pAC->RxPort[i].VRxDescrRing,
+				&pAC->RxPort[i].pRxdRingHead,
+				&pAC->RxPort[i].pRxdRingTail,
+				&pAC->RxPort[i].pRxdRingPrev,
+				&pAC->RxPort[i].RxdRingFree,
+				&pAC->RxPort[i].RxdRingFree,
+				SK_FALSE);
+		}
+	}
+} /* BoardInitMem */
+
+/*****************************************************************************
+ *
+ * 	SetupRing - create one descriptor ring
+ *
+ * Description:
+ *	This function creates one descriptor ring in the given memory area.
+ *	The head, tail and number of free descriptors in the ring are set.
+ *
+ * Returns:
+ *	none
+ */
+static void SetupRing(
+SK_AC		*pAC,
+void		*pMemArea,	/* a pointer to the memory area for the ring */
+uintptr_t	VMemArea,	/* the virtual bus address of the memory area */
+RXD		**ppRingHead,	/* address where the head should be written */
+RXD		**ppRingTail,	/* address where the tail should be written */
+RXD		**ppRingPrev,	/* address where the tail should be written */
+int		*pRingFree,	/* address where the # of free descr. goes */
+int		*pRingPrevFree,	/* address where the # of free descr. goes */
+SK_BOOL		IsTx)		/* flag: is this a tx ring */
+{
+int	i;		/* loop counter */
+int	DescrSize;	/* the size of a descriptor rounded up to alignment*/
+int	DescrNum;	/* number of descriptors per ring */
+RXD	*pDescr;	/* pointer to a descriptor (receive or transmit) */
+RXD	*pNextDescr;	/* pointer to the next descriptor */
+RXD	*pPrevDescr;	/* pointer to the previous descriptor */
+uintptr_t VNextDescr;	/* the virtual bus address of the next descriptor */
+
+	if (IsTx == SK_TRUE) {
+		DescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) *
+			DESCR_ALIGN;
+		DescrNum = TX_RING_SIZE / DescrSize;
+	} else {
+		DescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) *
+			DESCR_ALIGN;
+		DescrNum = RX_RING_SIZE / DescrSize;
+	}
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("Descriptor size: %d   Descriptor Number: %d\n",
+		DescrSize,DescrNum));
+
+	pDescr = (RXD*) pMemArea;
+	pPrevDescr = NULL;
+	pNextDescr = (RXD*) (((char*)pDescr) + DescrSize);
+	VNextDescr = VMemArea + DescrSize;
+	for(i=0; i<DescrNum; i++) {
+		/* set the pointers right */
+		pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
+		pDescr->pNextRxd = pNextDescr;
+		pDescr->TcpSumStarts = pAC->CsOfs;
+
+		/* advance one step */
+		pPrevDescr = pDescr;
+		pDescr = pNextDescr;
+		pNextDescr = (RXD*) (((char*)pDescr) + DescrSize);
+		VNextDescr += DescrSize;
+	}
+	pPrevDescr->pNextRxd = (RXD*) pMemArea;
+	pPrevDescr->VNextRxd = VMemArea;
+	pDescr               = (RXD*) pMemArea;
+	*ppRingHead          = (RXD*) pMemArea;
+	*ppRingTail          = *ppRingHead;
+	*ppRingPrev          = pPrevDescr;
+	*pRingFree           = DescrNum;
+	*pRingPrevFree       = DescrNum;
+} /* SetupRing */
+
+
+/*****************************************************************************
+ *
+ * 	PortReInitBmu - re-initiate the descriptor rings for one port
+ *
+ * Description:
+ *	This function reinitializes the descriptor rings of one port
+ *	in memory. The port must be stopped before.
+ *	The HW is initialized with the descriptor start addresses.
+ *
+ * Returns:
+ *	none
+ */
+static void PortReInitBmu(
+SK_AC	*pAC,		/* pointer to adapter context */
+int	PortIndex)	/* index of the port for which to re-init */
+{
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("PortReInitBmu "));
+
+	/* set address of first descriptor of ring in BMU */
+	SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ Q_DA_L,
+		(uint32_t)(((caddr_t)
+		(pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) -
+		pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing +
+		pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) &
+		0xFFFFFFFF));
+	SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ Q_DA_H,
+		(uint32_t)(((caddr_t)
+		(pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) -
+		pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing +
+		pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) >> 32));
+	SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+Q_DA_L,
+		(uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) -
+		pAC->RxPort[PortIndex].pRxDescrRing +
+		pAC->RxPort[PortIndex].VRxDescrRing) & 0xFFFFFFFF));
+	SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+Q_DA_H,
+		(uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) -
+		pAC->RxPort[PortIndex].pRxDescrRing +
+		pAC->RxPort[PortIndex].VRxDescrRing) >> 32));
+} /* PortReInitBmu */
+
+
+/****************************************************************************
+ *
+ *	SkGeIsr - handle adapter interrupts for single port adapter
+ *
+ * Description:
+ *	The interrupt routine is called when the network adapter
+ *	generates an interrupt. It may also be called if another device
+ *	shares this interrupt vector with the driver.
+ *	This is the same as above, but handles only one port.
+ *
+ * Returns: N/A
+ *
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+static SkIsrRetVar SkGeIsr(int irq, void *dev_id)
+#else
+static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs)
+#endif
+{
+struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
+DEV_NET		*pNet;
+SK_AC		*pAC;
+SK_U32		IntSrc;		/* interrupts source register contents */
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+
+	/*
+	 * Check and process if its our interrupt
+	 */
+	SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
+	if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
+		return SkIsrRetNone;
+	}
+
+#ifdef CONFIG_SK98LIN_NAPI
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+	if (napi_schedule_prep(&pNet->napi)) {
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	if (netif_rx_schedule_prep(dev, &pNet->napi)) {
+#else
+	if (netif_rx_schedule_prep(dev)) {
+#endif
+		CLEAR_AND_START_RX(0);
+		CLEAR_TX_IRQ(0, TX_PRIO_LOW);
+		pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
+		SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+		__napi_schedule(&pNet->napi);
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+		__netif_rx_schedule(dev, &pNet->napi);
+#else
+		__netif_rx_schedule(dev);
+#endif
+	}
+
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+	if (IntSrc & IS_XA1_F) {
+		CLEAR_TX_IRQ(0, TX_PRIO_LOW);
+	}
+#endif
+#else
+	while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
+#if 0 /* software irq currently not used */
+		if (IntSrc & IS_IRQ_SW) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_INT_SRC,
+				("Software IRQ\n"));
+		}
+#endif
+		if (IntSrc & IS_R1_F) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_INT_SRC,
+				("EOF RX1 IRQ\n"));
+			ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
+			CLEAR_AND_START_RX(0);
+			SK_PNMI_CNT_RX_INTR(pAC, 0);
+		}
+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
+		if (IntSrc & IS_XA1_F) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_INT_SRC,
+				("EOF AS TX1 IRQ\n"));
+			CLEAR_TX_IRQ(0, TX_PRIO_LOW);
+			SK_PNMI_CNT_TX_INTR(pAC, 0);
+			spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+			FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+			spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+		}
+#if 0 /* only if sync. queues used */
+		if (IntSrc & IS_XS1_F) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_INT_SRC,
+				("EOF SY TX1 IRQ\n"));
+			CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
+			SK_PNMI_CNT_TX_INTR(pAC, 0);
+			spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+			FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
+			spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
+		}
+#endif
+#endif
+
+		SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
+	} /* while (IntSrc & IRQ_MASK != 0) */
+#endif
+
+#ifndef CONFIG_SK98LIN_NAPI
+	spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+	FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+	spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+	ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
+	START_RX(0);
+#endif
+
+	IntSrc &= pAC->GIni.GIValIrqMask;
+	if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+			("SPECIAL IRQ SP-Cards => %x\n", IntSrc));
+		pAC->CheckQueue = SK_FALSE;
+		spin_lock(&pAC->SlowPathLock);
+		if (IntSrc & SPECIAL_IRQS)
+			SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
+
+		SkEventDispatcher(pAC, pAC->IoBase);
+		spin_unlock(&pAC->SlowPathLock);
+		START_RX(0);
+	}
+
+	/* IRQ is processed - Enable IRQs again*/
+	SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+
+	return SkIsrRetHandled;
+} /* SkGeIsr */
+
+
+/****************************************************************************
+ *
+ *	SkGeOpen - handle start of initialized adapter
+ *
+ * Description:
+ *	This function starts the initialized adapter.
+ *	The board level variable is set and the adapter is
+ *	brought to full functionality.
+ *	The device flags are set for operation.
+ *	Do all necessary level 2 initialization, enable interrupts and
+ *	give start command to RLMT.
+ *
+ * Returns:
+ *	0 on success
+ *	!= 0 on error
+ */
+static int SkGeOpen(
+struct SK_NET_DEVICE *dev)  /* the device that is to be opened */
+{
+	DEV_NET        *pNet = PPRIV;
+	SK_AC          *pAC  = pNet->pAC;
+	unsigned long   Flags;    	/* for the spin locks */
+	SK_BOOL         DualNet;
+	int             CurrMac;	/* loop ctr for ports */
+	unsigned long   InitFlags;
+#ifdef Y2_RECOVERY
+	SK_U8           StatSpeed, StatDuplex;
+	SK_U32          NewTimerInterval;
+#endif
+	SK_BOOL         ModuleCount = SK_FALSE;
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_SET_FW_IP_DRIVER
+	struct		in_device *pindev;
+	SK_U32		ip_address;
+	SK_U32		ip_netmask;
+#endif
+#endif
+#ifdef CONFIG_PROC_FS
+	struct proc_dir_entry *pProcFile;
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
+
+	spin_lock_irqsave(&pAC->InitLock, InitFlags);
+	pAC->MaxPorts++;
+	if (pAC->DiagModeActive == DIAG_ACTIVE) {
+		if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING)
+			goto open_failed;
+	}
+
+	if (!try_module_get(THIS_MODULE)) {
+		/* increase of usage count not possible */
+		goto open_failed;
+	}
+	ModuleCount = SK_TRUE;
+	SetConfiguration(pAC);
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	if ((pAC->FwRun) && (pAC->FwState) && ((pAC->BoardLevel == SK_INIT_RUN) ||
+		(pAC->Suspended == SK_TRUE))) {
+		FwDriverHello(pAC, pAC->IoBase);
+	}
+
+	if (pAC->FwRun && ((pAC->BoardLevel == SK_INIT_RUN) ||
+		(pAC->Suspended == SK_TRUE)) &&
+		(pAC->FwState == SK_FALSE)) {
+
+		/* Communication DRV <=> FW is broken. Try to recover... */
+		printk("%s: SkGeOpen: FW not running => Restart CPU!\n",
+			pAC->dev[pNet->PortNr]->name);
+
+		FwAppInit2(pAC, pAC->IoBase);
+		FwDriverHello(pAC, pAC->IoBase);
+	}
+#endif
+
+	/* Set blink mode */
+	if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
+		pAC->GIni.GILedBlinkCtrl = OEM_CONFIG_VALUE;
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	pAC->FwOs.pFilePathName = FW_FILE_PATHNAME;
+	pAC->FwOs.FileSize = ASF_FLASH_SIZE_384K;
+#endif
+
+	if (pAC->BoardLevel == SK_INIT_DATA) {
+#ifdef MV_INCLUDE_SDK_SUPPORT
+		if (pAC->FwRun && pAC->Suspended == SK_TRUE) {
+			FwCheckLinkMode(pAC, pAC->IoBase, pNet->PortNr);
+		}
+#endif
+		/* Level 1 init common modules here */
+		if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
+			module_put(THIS_MODULE); /* decrease usage count */
+			printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
+			goto open_failed;
+		}
+		SkI2cInit	(pAC, pAC->IoBase, SK_INIT_IO);
+		SkEventInit	(pAC, pAC->IoBase, SK_INIT_IO);
+		SkPnmiInit	(pAC, pAC->IoBase, SK_INIT_IO);
+		SkAddrInit	(pAC, pAC->IoBase, SK_INIT_IO);
+		SkTimerInit	(pAC, pAC->IoBase, SK_INIT_IO);
+#ifdef MV_INCLUDE_SDK_SUPPORT
+		/* Nothing to do here if card returns from suspend... */
+		if (pAC->Suspended == SK_FALSE) {
+			if (FwInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
+				printk("sk98lin: SDK support for this device disabled!\n");
+				pAC->FwState = SK_FALSE;
+			}
+		}
+#endif
+		pAC->BoardLevel = SK_INIT_IO;
+#ifdef Y2_RECOVERY
+		/* mark entries invalid */
+		pAC->LastPort = 3;
+		pAC->LastOpc = 0xFF;
+#endif
+	}
+
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+	printk("SkGeOpen: pAC->Suspended:                   %d\n",
+		pAC->Suspended);
+	printk("SkGeOpen: pAC->LinkInfo[0].LinkMaintenance: %d\n",
+		pAC->LinkInfo[0].LinkMaintenance);
+	printk("SkGeOpen: pAC->GIni.GIDontInitPhy:          %d\n",
+		pAC->GIni.GIDontInitPhy);
+#endif
+
+	/* Transformerless mode */
+	if ((pAC->PciDev->vendor == 0x11ab ) &&
+		(pAC->PciDev->device == 0x4365) &&
+		(pAC->PciDev->subsystem_vendor == 0x10b7) &&
+		(pAC->PciDev->subsystem_device == 0x1700)) {
+
+		/* Enable transformerless mode */
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_TRAFO_LESS_ENABLE;
+
+		/* Set manual slave and MDX */
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_PHY_SET_SLAVE_MDIX;
+	}
+
+	if (pAC->BoardLevel != SK_INIT_RUN) {
+		if (pAC->Suspended) {
+		/* Set the configuration after suspend */
+			SetConfiguration(pAC);
+		}
+
+		/* Level 2 init modules here, check return value. */
+		if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
+			module_put(THIS_MODULE); /* decrease usage count */
+			printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
+			goto open_failed;
+		}
+
+		SkI2cInit	(pAC, pAC->IoBase, SK_INIT_RUN);
+		SkEventInit	(pAC, pAC->IoBase, SK_INIT_RUN);
+		SkPnmiInit	(pAC, pAC->IoBase, SK_INIT_RUN);
+		SkAddrInit	(pAC, pAC->IoBase, SK_INIT_RUN);
+		SkTimerInit	(pAC, pAC->IoBase, SK_INIT_RUN);
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+		/* Nothing to do here if card returns from suspend... */
+		if (pAC->FwRun && pAC->Suspended == SK_FALSE) {
+			spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
+			if (FwInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
+				module_put(THIS_MODULE); /* decrease usage count */
+				printk("%s: SkGeOpen: FwInit(SK_INIT_RUN) failed!\n",
+					pAC->dev[pNet->PortNr]->name);
+				spin_lock_irqsave(&pAC->InitLock, InitFlags);
+				goto open_failed;
+			}
+			spin_lock_irqsave(&pAC->InitLock, InitFlags);
+
+			if (pAC->FwState) {
+				FwDriverHello(pAC, pAC->IoBase);
+			}
+		}
+#endif
+		pAC->BoardLevel = SK_INIT_RUN;
+	}
+
+	DualNet = SK_FALSE;
+	if (pAC->RlmtNets == 2) {
+		DualNet = SK_TRUE;
+	}
+
+	if (SkGeInitAssignRamToQueues(
+		pAC,
+		pAC->ActivePort,
+		DualNet)) {
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2FreeResources(pAC);
+		} else {
+			BoardFreeMem(pAC);
+		}
+		module_put(THIS_MODULE); /* decrease usage count */
+		printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
+		goto open_failed;
+	}
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
+			/* Enable transmit descriptor polling. */
+			SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
+			FillRxRing(pAC, &pAC->RxPort[CurrMac]);
+			SkMacRxTxEnable(pAC, pAC->IoBase, CurrMac);
+		}
+
+		/*
+		** Has been setup already at SkGeInit(SK_INIT_IO),
+		** but additional masking added for Yukon
+		** chipsets -> modify it...
+		*/
+		pAC->GIni.GIValIrqMask &= IRQ_MASK;
+#ifndef USE_TX_COMPLETE
+		pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
+#endif
+	}
+
+	SkGeYellowLED(pAC, pAC->IoBase, 1);
+	SkDimEnableModerationIfNeeded(pAC);
+
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+	if (pAC->MaxPorts == 1) {
+		/* Clear all LE tables */
+		SK_MEMSET(pAC->pVirtMemAddr, 0, pAC->SizeOfAlignedLETables);
+	}
+
+	/* Send event to set the number of nets in PNMI */
+	SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS,
+		pAC->RlmtNets, -1, SK_TRUE);
+
+	/* Send event to start the ports (RX/TX) */
+	SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START,
+		pNet->PortNr, -1, SK_TRUE);
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+#ifdef Y2_RECOVERY
+	pNet->TimerExpired = SK_FALSE;
+	pNet->InRecover = SK_FALSE;
+	pNet->NetConsoleMode = SK_FALSE;
+
+	StatSpeed = pAC->GIni.GP[pNet->NetNr].PLinkSpeedUsed;
+	if (StatSpeed == SK_LSPEED_STAT_10MBPS) {
+		StatDuplex = pAC->GIni.GP[pNet->NetNr].PLinkModeStatus;
+		if ((StatDuplex == SK_LMODE_STAT_AUTOHALF) ||
+			(StatDuplex == SK_LMODE_STAT_HALF)) {
+				NewTimerInterval = (HZ*2);
+		} else {
+			NewTimerInterval = (HZ);
+		}
+	} else if (StatSpeed == SK_LSPEED_STAT_100MBPS) {
+		NewTimerInterval = (HZ/2);
+	} else if (StatSpeed == SK_LSPEED_STAT_1000MBPS) {
+		NewTimerInterval = (HZ/4);
+	} else {
+		NewTimerInterval = (HZ*2);
+	}
+
+	/* Initialize the kernel timer */
+	init_timer(&pNet->KernelTimer);
+	pNet->KernelTimer.function	= SkGeHandleKernelTimer;
+	pNet->KernelTimer.data		= (unsigned long) pNet;
+	pNet->KernelTimer.expires	= jiffies + NewTimerInterval;
+#endif
+
+	/* Map any waiting RX buffers to HW */
+	for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
+#ifdef USE_SK_RSS_SUPPORT
+		SkSetRssSupport(pAC, CurrMac);
+#endif
+		FillReceiveTableYukon2(pAC,pAC->IoBase, CurrMac);
+	}
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	if (pAC->GIni.GIDontInitPhy == SK_TRUE) {
+		SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
+		SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
+	}
+#endif
+
+	spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
+	if (pAC->RequestedIrq == SK_FALSE) {
+		if ((SkGeRequestIrq(pAC->dev[0])) == 0) {
+			pAC->RequestedIrq = SK_TRUE;
+
+			if (pAC->Suspended == SK_FALSE) {
+
+				/* Enable interrupts */
+				SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+				if (CHIP_ID_YUKON_2(pAC)) {
+					SK_OUT32(pAC->IoBase, B0_HWE_IMSK, Y2_IRQ_HWE_MASK);
+				}
+				else {
+				SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+				}
+			}
+		}
+		else {
+			printk("SkGeRequestIrq() failed => Interrupts not enabled!\n");
+			spin_lock_irqsave(&pAC->InitLock, InitFlags);
+			goto open_failed;
+		}
+	}
+	spin_lock_irqsave(&pAC->InitLock, InitFlags);
+
+#ifdef CONFIG_PROC_FS
+	/* Initialize the procfs timer */
+	init_timer(&pNet->ProcfsTimer);
+	pNet->ProcfsTimer.function	= SkGeHandleProcfsTimer;
+	pNet->ProcfsTimer.data		= (unsigned long) pNet;
+	pNet->ProcfsTimer.expires	= jiffies + HZ*5; /* initially 5 secs */
+	add_timer(&pNet->ProcfsTimer);
+#endif
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
+		SK_OUT8(pAC->IoBase, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
+			PC_VAUX_OFF | PC_VCC_ON));
+	}
+
+	spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
+
+#ifdef CONFIG_PROC_FS
+	if ((!pAC->InterfaceUp[pNet->NetNr]) && (pSkRootDir)) {
+		pProcFile = create_proc_entry(pAC->dev[pNet->NetNr]->name, S_IRUGO, pSkRootDir);
+		pProcFile->proc_fops = &sk_proc_fops;
+		pProcFile->data      = dev;
+
+		/*
+		 * Remember, interface dev nr pNet->NetNr is up
+		 */
+		pAC->InterfaceUp[pNet->NetNr] = 1;
+
+		strcpy(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name);
+	}
+#endif
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		pAC->StatusLETable.Done  = 0;
+		pAC->StatusLETable.Put   = 0;
+		pAC->StatusLETable.HwPut = 0;
+		SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
+	}
+#ifdef MV_SET_FW_IP_DRIVER
+	/* Set the IP address */
+	if (dev->ip_ptr != NULL) {
+		pindev = (struct in_device*) dev->ip_ptr;
+		ip_address = htonl(pindev->ifa_list->ifa_address);
+		ip_netmask = htonl(pindev->ifa_list->ifa_mask);
+		SetFwIpAddr(pAC, ip_address, ip_netmask, ip_address);
+	}
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeOpen suceeded\n"));
+
+	return (0);
+
+	/* SkGeOpen error handling*/
+open_failed:
+	if (ModuleCount) {
+		module_put(THIS_MODULE);
+	}
+	pAC->MaxPorts--;
+	spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
+	return (-1);
+} /* SkGeOpen */
+
+/****************************************************************************
+ *
+ *	SkGeClose - Stop initialized adapter
+ *
+ * Description:
+ *	Close initialized adapter.
+ *
+ * Returns:
+ *	0 - on success
+ *	error code - on error
+ */
+static int SkGeClose(
+struct SK_NET_DEVICE *dev)  /* the device that is to be closed */
+{
+	DEV_NET    	    *pNet = PPRIV;
+	SK_AC           *pAC  = pNet->pAC;
+	DEV_NET         *newPtrNet;
+	unsigned long   Flags;		/* for the spin locks		*/
+	int             CurrMac;	/* loop ctr for the current MAC	*/
+	int             PortIdx;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_SET_FW_IP_DRIVER
+	struct		in_device *pindev;
+	SK_U32		ip_address;
+	SK_U32		ip_netmask;
+#endif
+#endif
+	int			RstMode;
+#ifdef CONFIG_SK98LIN_NAPI
+	int			WorkToDo = 1; /* min(*budget, dev->quota);    */
+	int			WorkDone = 0;
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
+	spin_lock_irqsave(&pAC->InitLock, Flags);
+	if (pAC->MaxPorts == 1) {
+		/* Disable interrupts */
+		SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+	}
+	netif_stop_queue(dev);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	synchronize_irq(dev->irq);
+	napi_synchronize(&pNet->napi);
+#endif
+
+#ifdef CONFIG_PROC_FS
+	del_timer(&pNet->ProcfsTimer);
+#endif
+
+#ifdef Y2_RECOVERY
+	pNet->InRecover = SK_TRUE;
+	del_timer(&pNet->KernelTimer);
+#endif
+
+	if (pAC->DiagModeActive == DIAG_ACTIVE) {
+		if (pAC->DiagFlowCtrl == SK_FALSE) {
+			module_put(THIS_MODULE);
+			/*
+			** notify that the interface which has been closed
+			** by operator interaction must not be started up
+			** again when the DIAG has finished.
+			*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
+#else
+			newPtrNet = netdev_priv(pAC->dev[0]);
+#endif
+			if (newPtrNet == pNet) {
+				pAC->WasIfUp[0] = SK_FALSE;
+			} else {
+				pAC->WasIfUp[1] = SK_FALSE;
+			}
+			spin_unlock_irqrestore(&pAC->InitLock, Flags);
+			return 0; /* return to system everything is fine... */
+		} else {
+			pAC->DiagFlowCtrl = SK_FALSE;
+		}
+	}
+
+	PortIdx = pNet->PortNr;
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_SET_FW_IP_DRIVER
+	/* Set the IP address */
+	if (pAC->FwRun && dev->ip_ptr != NULL) {
+		pindev = (struct in_device*) dev->ip_ptr;
+		ip_address = htonl(pindev->ifa_list->ifa_address);
+		ip_netmask = htonl(pindev->ifa_list->ifa_mask);
+		SetFwIpAddr(pAC, ip_address, ip_netmask, ip_address);
+	}
+#endif
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	if (pAC->FwRun && pAC->Suspended == SK_TRUE) {
+		FwCheckLinkMode(pAC, pAC->IoBase, PortIdx);
+	}
+#ifdef MV_FW_SDK_LINK_MAINTENANCE_DEBUG
+	printk("SkGeClose: pAC->Suspended:                   %d\n",
+		pAC->Suspended);
+	printk("SkGeClose: pAC->LinkInfo[0].LinkMaintenance: %d\n",
+		pAC->LinkInfo[0].LinkMaintenance);
+	printk("SkGeClose: pAC->GIni.GIDontInitPhy:          %d\n",
+		pAC->GIni.GIDontInitPhy);
+#endif
+#endif
+#endif
+
+	if (pAC->MaxPorts == 1) {
+		spin_lock(&pAC->SlowPathLock);
+
+		/* Disable the status unit */
+		SK_OUT8(pAC->IoBase, STAT_CTRL, SC_STAT_RST_SET);
+
+		spin_unlock(&pAC->SlowPathLock);
+		if (pAC->RequestedIrq == SK_TRUE) {
+			pAC->RequestedIrq = SK_FALSE;
+			SkGeReleaseIrq(pAC->IrqDev);
+		}
+		spin_lock(&pAC->SlowPathLock);
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+		if (pAC->Suspended == SK_FALSE) {
+
+			/* Send event to stop the ports (RX/TX) */
+			SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+				PortIdx, -1, SK_TRUE);
+		}
+		else {
+
+			/* Stop queue and carrier, set interface to not running */
+			netif_stop_queue(dev);
+			netif_carrier_off(dev);
+			dev->flags &= ~IFF_RUNNING;
+		}
+#else
+		/* Send event to stop the ports (RX/TX) */
+		SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+			PortIdx, -1, SK_TRUE);
+#endif
+		if (CHIP_ID_YUKON_2(pAC)) {
+#ifdef MV_INCLUDE_SDK_SUPPORT
+			if (pAC->FwRun &&
+				pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR) {
+				SK_OUT32(pAC->IoBase, MR_ADDR(PortIdx, RX_GMF_CTRL_T),
+					RXMF_TCTL_MACSEC_FLSH_ENA);
+			}
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+			RstMode = SK_SOFT_RST;
+#endif
+#else
+			RstMode = SK_HARD_RST;
+#endif
+			SkY2PortStop(pAC,
+					pAC->IoBase,
+					PortIdx,
+					SK_STOP_ALL,
+					RstMode);
+		} else {
+			SkGeStopPort(pAC,
+					pAC->IoBase,
+					PortIdx,
+					SK_STOP_ALL,
+					SK_HARD_RST);
+		}
+		spin_unlock(&pAC->SlowPathLock);
+	} else {
+		spin_lock(&pAC->SlowPathLock);
+
+		/* Send event to stop the ports (RX/TX) */
+		SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+			PortIdx, -1, SK_TRUE);
+
+		SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
+				PortIdx, -1, SK_TRUE);
+		spin_unlock(&pAC->SlowPathLock);
+
+		/* Stop ports */
+		spin_lock(&pAC->TxPort[PortIdx][TX_PRIO_LOW].TxDesRingLock);
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2PortStop(pAC, pAC->IoBase, PortIdx,
+				SK_STOP_ALL, SK_HARD_RST);
+		}
+		else {
+			SkGeStopPort(pAC, pAC->IoBase, PortIdx,
+				SK_STOP_ALL, SK_HARD_RST);
+		}
+		spin_unlock(&pAC->TxPort[PortIdx][TX_PRIO_LOW].TxDesRingLock);
+	}
+
+	if (pAC->RlmtNets == 1) {
+		/* Clear all descriptor rings */
+		for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
+			if (!CHIP_ID_YUKON_2(pAC)) {
+#ifdef CONFIG_SK98LIN_NAPI
+				WorkToDo = 1;
+				ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
+						SK_TRUE,&WorkDone,WorkToDo);
+#else
+				ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
+#endif
+				ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
+				ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
+			} else {
+				SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
+				SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
+			}
+		}
+	} else {
+		/* Clear port descriptor rings */
+		if (!CHIP_ID_YUKON_2(pAC)) {
+#ifdef CONFIG_SK98LIN_NAPI
+			WorkToDo = 1;
+			ReceiveIrq(pAC, &pAC->RxPort[PortIdx], SK_TRUE, &WorkDone, WorkToDo);
+#else
+			ReceiveIrq(pAC, &pAC->RxPort[PortIdx], SK_TRUE);
+#endif
+			ClearRxRing(pAC, &pAC->RxPort[PortIdx]);
+			ClearTxRing(pAC, &pAC->TxPort[PortIdx][TX_PRIO_LOW]);
+		}
+		else {
+			SkY2FreeRxBuffers(pAC, pAC->IoBase, PortIdx);
+			SkY2FreeTxBuffers(pAC, pAC->IoBase, PortIdx);
+		}
+	}
+
+	SK_OUT8(pAC->IoBase, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
+		PC_VAUX_ON | PC_VCC_OFF));
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	if ((pAC->FwRun) && (pAC->FwState) && (pAC->Suspended == SK_FALSE)) {
+		FwDriverGoodbye(pAC, pAC->IoBase);
+	}
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeClose: done "));
+
+	SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
+	SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
+			sizeof(SK_PNMI_STRUCT_DATA));
+
+	pAC->MaxPorts--;
+	module_put(THIS_MODULE);
+
+#ifdef Y2_RECOVERY
+	pNet->InRecover = SK_FALSE;
+#endif
+	spin_unlock_irqrestore(&pAC->InitLock, Flags);
+
+	return (0);
+} /* SkGeClose */
+
+
+/*****************************************************************************
+ *
+ * 	SkGeXmit - Linux frame transmit function
+ *
+ * Description:
+ *	The system calls this function to send frames onto the wire.
+ *	It puts the frame in the tx descriptor ring. If the ring is
+ *	full then, the 'tbusy' flag is set.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ * WARNING: returning 1 in 'tbusy' case caused system crashes (double
+ *	allocated skb's) !!!
+ */
+static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev)
+{
+DEV_NET		*pNet;
+SK_AC		*pAC;
+int			Rc;	/* return code of XmitFrame */
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+
+	if ((!skb_shinfo(skb)->nr_frags) ||
+		(pAC->GIni.GIChipId == CHIP_ID_GENESIS)) {
+		/* Don't activate scatter-gather and hardware checksum */
+
+		if (pAC->RlmtNets == 2)
+			Rc = XmitFrame(
+				pAC,
+				&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW],
+				skb);
+		else
+			Rc = XmitFrame(
+				pAC,
+				&pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW],
+				skb);
+	} else {
+		/* scatter-gather and hardware TCP checksumming anabled*/
+		if (pAC->RlmtNets == 2)
+			Rc = XmitFrameSG(
+				pAC,
+				&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW],
+				skb);
+		else
+			Rc = XmitFrameSG(
+				pAC,
+				&pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW],
+				skb);
+	}
+
+	/* Transmitter out of resources? */
+	if (Rc <= 0) {
+		netif_stop_queue(dev);
+	}
+
+	/* If not taken, give buffer ownership back to the
+	 * queueing layer.
+	 */
+
+	if (Rc < 0) {
+		return NETDEV_TX_BUSY;
+	}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
+	dev->trans_start = jiffies;
+#endif
+	return NETDEV_TX_OK;
+
+} /* SkGeXmit */
+
+#ifdef CONFIG_SK98LIN_NAPI
+/*****************************************************************************
+ *
+ * 	SkGePoll - NAPI Rx polling callback for Yukon chipsets
+ *
+ * Description:
+ *	Called by the Linux system in case NAPI polling is activated
+ *
+ * Returns:
+ *	The number of work data still to be handled
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+static int SkGePoll(struct napi_struct *napi, int WorkToDo) {
+#else
+static int SkGePoll(struct net_device *dev, int *budget) {
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+	DEV_NET		*pNet    = container_of(napi, DEV_NET, napi);
+	SK_AC		*pAC     = pNet->pAC;
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	DEV_NET		*pNet    = container_of(napi, DEV_NET, napi);
+	SK_AC		*pAC     = pNet->pAC;
+	struct		SK_NET_DEVICE *dev = pAC->dev[0];
+#else
+	SK_AC		*pAC = ((DEV_NET*)dev->priv)->pAC;
+	int		WorkToDo = min(*budget, dev->quota);
+#endif
+
+	int		WorkDone = 0;
+	unsigned long	Flags;
+
+	spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+	FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
+	spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
+
+	ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
+	CLEAR_AND_START_RX(0);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+	*budget -= WorkDone;
+	dev->quota -= WorkDone;
+#endif
+
+	if(WorkDone < WorkToDo) {
+		spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
+		__napi_complete(napi);
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+		__netif_rx_complete(dev, napi);
+#else
+		netif_rx_complete(dev);
+#endif
+		pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
+#ifndef USE_TX_COMPLETE
+		pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
+#endif
+		/* enable interrupts again */
+		SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+	}
+	return (WorkDone >= WorkToDo);
+} /* SkGePoll */
+#endif
+
+#ifdef SK_POLL_CONTROLLER
+/*****************************************************************************
+ *
+ * 	SkGeNetPoll - Polling "interrupt"
+ *
+ * Description:
+ *	Polling 'interrupt' - used by things like netconsole and netdump
+ *	to send skbs without having to re-enable interrupts.
+ *	It's not called while the interrupt routine is executing.
+ */
+static void SkGeNetPoll(
+struct SK_NET_DEVICE *dev)
+{
+DEV_NET		*pNet;
+SK_AC		*pAC;
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+	pNet->NetConsoleMode = SK_TRUE;
+
+	/*  Prevent any reconfiguration while handling
+	    the 'interrupt' */
+	SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+	/* Handle the Yukon Isr */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+		SkGeIsr(dev->irq, dev);
+#else
+		SkGeIsr(dev->irq, dev, NULL);
+#endif
+	} else {
+		/* Handle the Yukon2 Isr */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+		SkY2Isr(dev->irq, dev);
+#else
+		SkY2Isr(dev->irq, dev, NULL);
+#endif
+	}
+
+}
+#endif
+
+
+/*****************************************************************************
+ *
+ * 	XmitFrame - fill one socket buffer into the transmit ring
+ *
+ * Description:
+ *	This function puts a message into the transmit descriptor ring
+ *	if there is a descriptors left.
+ *	Linux skb's consist of only one continuous buffer.
+ *	The first step locks the ring. It is held locked
+ *	all time to avoid problems with SWITCH_../PORT_RESET.
+ *	Then the descriptoris allocated.
+ *	The second part is linking the buffer to the descriptor.
+ *	At the very last, the Control field of the descriptor
+ *	is made valid for the BMU and a start TX command is given
+ *	if necessary.
+ *
+ * Returns:
+ *	> 0 - on succes: the number of bytes in the message
+ *	= 0 - on resource shortage: this frame sent or dropped, now
+ *		the ring is full ( -> set tbusy)
+ *	< 0 - on failure: other problems ( -> return failure to upper layers)
+ */
+static int XmitFrame(
+SK_AC 		*pAC,		/* pointer to adapter context	        */
+TX_PORT		*pTxPort,	/* pointer to struct of port to send to */
+struct sk_buff	*pMessage)	/* pointer to send-message              */
+{
+	TXD		*pTxd;		/* the rxd to fill */
+	TXD		*pOldTxd;
+	unsigned long	 Flags;
+	SK_U64		 PhysAddr;
+	int	 	 Protocol;
+	int		 IpHeaderLength;
+	int		 BytesSend = pMessage->len;
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
+
+	spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
+#ifndef USE_TX_COMPLETE
+	if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6)  {
+		FreeTxDescriptors(pAC, pTxPort);
+		pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
+	}
+#endif
+	if (pTxPort->TxdRingFree == 0) {
+		/*
+		** not enough free descriptors in ring at the moment.
+		** Maybe free'ing some old one help?
+		*/
+		FreeTxDescriptors(pAC, pTxPort);
+		if (pTxPort->TxdRingFree == 0) {
+			spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+			SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex);
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_TX_PROGRESS,
+				("XmitFrame failed\n"));
+			/*
+			** the desired message can not be sent
+			** Because tbusy seems to be set, the message
+			** should not be freed here. It will be used
+			** by the scheduler of the ethernet handler
+			*/
+				return (-1);
+		}
+	}
+
+	/*
+	** If the passed socket buffer is of smaller MTU-size than 60,
+	** copy everything into new buffer and fill all bytes between
+	** the original packet end and the new packet end of 60 with 0x00.
+	** This is to resolve faulty padding by the HW with 0xaa bytes.
+	*/
+	if (BytesSend < C_LEN_ETHERNET_MINSIZE) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+		if ((pMessage = skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) == NULL) {
+#else
+		if (skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) {
+#endif
+			spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+			return (0);
+		}
+		pMessage->len = C_LEN_ETHERNET_MINSIZE;
+	}
+
+	/*
+	** advance head counter behind descriptor needed for this frame,
+	** so that needed descriptor is reserved from that on. The next
+	** action will be to add the passed buffer to the TX-descriptor
+	*/
+	pTxd = pTxPort->pTxdRingHead;
+	pTxPort->pTxdRingHead = pTxd->pNextTxd;
+	pTxPort->TxdRingFree--;
+
+#ifdef SK_DUMP_TX
+	DumpMsg(pMessage, "XmitFrame");
+#endif
+
+	/*
+	** First step is to map the data to be sent via the adapter onto
+	** the DMA memory. Kernel 2.2 uses virt_to_bus(), but kernels 2.4
+	** and 2.6 need to use pci_map_page() for that mapping.
+	*/
+	PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+					virt_to_page(pMessage->data),
+					((unsigned long) pMessage->data & ~PAGE_MASK),
+					pMessage->len,
+					PCI_DMA_TODEVICE);
+	pTxd->VDataLow  = (SK_U32) (PhysAddr & 0xffffffff);
+	pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+	pTxd->pMBuf     = pMessage;
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+	if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
+#else
+	if (pMessage->ip_summed == CHECKSUM_HW) {
+#endif
+		Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
+		if ((Protocol == C_PROTO_ID_UDP) &&
+			(pAC->GIni.GIChipRev == 0) &&
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
+			pTxd->TBControl = BMU_TCP_CHECK;
+		} else {
+			pTxd->TBControl = BMU_UDP_CHECK;
+		}
+
+		IpHeaderLength  = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
+		IpHeaderLength  = (IpHeaderLength & 0xf) * 4;
+		pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
+		pTxd->TcpSumWr  = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
+							(Protocol == C_PROTO_ID_UDP ?
+							C_OFFSET_UDPHEADER_UDPCS :
+							C_OFFSET_TCPHEADER_TCPCS);
+		pTxd->TcpSumSt  = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
+
+		pTxd->TBControl |= BMU_OWN | BMU_STF |
+				   BMU_SW  | BMU_EOF |
+#ifdef USE_TX_COMPLETE
+				   BMU_IRQ_EOF |
+#endif
+				   pMessage->len;
+	} else {
+		pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
+				  BMU_SW  | BMU_EOF |
+#ifdef USE_TX_COMPLETE
+				   BMU_IRQ_EOF |
+#endif
+			pMessage->len;
+	}
+
+	/*
+	** If previous descriptor already done, give TX start cmd
+	*/
+	pOldTxd = xchg(&pTxPort->pTxdRingPrev, pTxd);
+	if ((pOldTxd->TBControl & BMU_OWN) == 0) {
+		SK_OUT8(pTxPort->HwAddr, Q_CSR, CSR_START);
+	}
+
+	/*
+	** after releasing the lock, the skb may immediately be free'd
+	*/
+	spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+	if (pTxPort->TxdRingFree != 0) {
+		return (BytesSend);
+	} else {
+		return (0);
+	}
+
+} /* XmitFrame */
+
+/*****************************************************************************
+ *
+ * 	XmitFrameSG - fill one socket buffer into the transmit ring
+ *                (use SG and TCP/UDP hardware checksumming)
+ *
+ * Description:
+ *	This function puts a message into the transmit descriptor ring
+ *	if there is a descriptors left.
+ *
+ * Returns:
+ *	> 0 - on succes: the number of bytes in the message
+ *	= 0 - on resource shortage: this frame sent or dropped, now
+ *		the ring is full ( -> set tbusy)
+ *	< 0 - on failure: other problems ( -> return failure to upper layers)
+ */
+static int XmitFrameSG(
+SK_AC 		*pAC,		/* pointer to adapter context           */
+TX_PORT		*pTxPort,	/* pointer to struct of port to send to */
+struct sk_buff	*pMessage)	/* pointer to send-message              */
+{
+
+	TXD		*pTxd;
+	TXD		*pTxdFst;
+	TXD		*pTxdLst;
+	int 	 	 CurrFrag;
+	int		 BytesSend;
+	int		 IpHeaderLength;
+	int		 Protocol;
+	skb_frag_t	*sk_frag;
+	SK_U64		 PhysAddr;
+	unsigned long	 Flags;
+
+	spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
+#ifndef USE_TX_COMPLETE
+	FreeTxDescriptors(pAC, pTxPort);
+#endif
+	if ((skb_shinfo(pMessage)->nr_frags +1) > pTxPort->TxdRingFree) {
+		FreeTxDescriptors(pAC, pTxPort);
+		if ((skb_shinfo(pMessage)->nr_frags + 1) > pTxPort->TxdRingFree) {
+			spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+			SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex);
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_TX_PROGRESS,
+				("XmitFrameSG failed - Ring full\n"));
+				/* this message can not be sent now */
+				return(-1);
+		}
+	}
+
+	pTxd      = pTxPort->pTxdRingHead;
+	pTxdFst   = pTxd;
+	pTxdLst   = pTxd;
+	BytesSend = 0;
+	Protocol  = 0;
+
+	/*
+	** Map the first fragment (header) into the DMA-space
+	*/
+	PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+			virt_to_page(pMessage->data),
+			((unsigned long) pMessage->data & ~PAGE_MASK),
+			skb_headlen(pMessage),
+			PCI_DMA_TODEVICE);
+
+	pTxd->VDataLow  = (SK_U32) (PhysAddr & 0xffffffff);
+	pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+
+	/*
+	** Does the HW need to evaluate checksum for TCP or UDP packets?
+	*/
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+	if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
+#else
+	if (pMessage->ip_summed == CHECKSUM_HW) {
+#endif
+		pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
+		/*
+		** We have to use the opcode for tcp here,  because the
+		** opcode for udp is not working in the hardware yet
+		** (Revision 2.0)
+		*/
+		Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
+		if ((Protocol == C_PROTO_ID_UDP) &&
+			(pAC->GIni.GIChipRev == 0) &&
+			(pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
+			pTxd->TBControl |= BMU_TCP_CHECK;
+		} else {
+			pTxd->TBControl |= BMU_UDP_CHECK;
+		}
+
+		IpHeaderLength  = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
+		pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
+		pTxd->TcpSumWr  = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
+							(Protocol == C_PROTO_ID_UDP ?
+							C_OFFSET_UDPHEADER_UDPCS :
+							C_OFFSET_TCPHEADER_TCPCS);
+		pTxd->TcpSumSt  = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
+	} else {
+		pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
+					skb_headlen(pMessage);
+	}
+
+	pTxd = pTxd->pNextTxd;
+	pTxPort->TxdRingFree--;
+	BytesSend += skb_headlen(pMessage);
+
+	/*
+	** Browse over all SG fragments and map each of them into the DMA space
+	*/
+	for (CurrFrag = 0; CurrFrag < skb_shinfo(pMessage)->nr_frags; CurrFrag++) {
+		sk_frag = &skb_shinfo(pMessage)->frags[CurrFrag];
+		/*
+		** we already have the proper value in entry
+		*/
+		PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+						 sk_frag->page,
+						 sk_frag->page_offset,
+						 sk_frag->size,
+						 PCI_DMA_TODEVICE);
+
+		pTxd->VDataLow  = (SK_U32) (PhysAddr & 0xffffffff);
+		pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+		pTxd->pMBuf     = pMessage;
+
+		/*
+		** Does the HW need to evaluate checksum for TCP or UDP packets?
+		*/
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+		if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
+#else
+		if (pMessage->ip_summed == CHECKSUM_HW) {
+#endif
+			pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
+			/*
+			** We have to use the opcode for tcp here because the
+			** opcode for udp is not working in the hardware yet
+			** (revision 2.0)
+			*/
+			if ((Protocol == C_PROTO_ID_UDP) &&
+				(pAC->GIni.GIChipRev == 0) &&
+				(pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
+				pTxd->TBControl |= BMU_TCP_CHECK;
+			} else {
+				pTxd->TBControl |= BMU_UDP_CHECK;
+			}
+		} else {
+			pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
+		}
+
+		/*
+		** Do we have the last fragment?
+		*/
+		if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags )  {
+#ifdef USE_TX_COMPLETE
+			pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
+#else
+			pTxd->TBControl |= BMU_EOF | sk_frag->size;
+#endif
+			pTxdFst->TBControl |= BMU_OWN | BMU_SW;
+
+		} else {
+			pTxd->TBControl |= sk_frag->size;
+		}
+		pTxdLst = pTxd;
+		pTxd    = pTxd->pNextTxd;
+		pTxPort->TxdRingFree--;
+		BytesSend += sk_frag->size;
+	}
+
+	/*
+	** If previous descriptor already done, give TX start cmd
+	*/
+	if ((pTxPort->pTxdRingPrev->TBControl & BMU_OWN) == 0) {
+		SK_OUT8(pTxPort->HwAddr, Q_CSR, CSR_START);
+	}
+
+	pTxPort->pTxdRingPrev = pTxdLst;
+	pTxPort->pTxdRingHead = pTxd;
+
+	spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+
+	if (pTxPort->TxdRingFree > 0) {
+		return (BytesSend);
+	} else {
+		return (0);
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	FreeTxDescriptors - release descriptors from the descriptor ring
+ *
+ * Description:
+ *	This function releases descriptors from a transmit ring if they
+ *	have been sent by the BMU.
+ *	If a descriptors is sent, it can be freed and the message can
+ *	be freed, too.
+ *	The SOFTWARE controllable bit is used to prevent running around a
+ *	completely free ring for ever. If this bit is no set in the
+ *	frame (by XmitFrame), this frame has never been sent or is
+ *	already freed.
+ *	The Tx descriptor ring lock must be held while calling this function !!!
+ *
+ * Returns:
+ *	none
+ */
+static void FreeTxDescriptors(
+SK_AC	*pAC,		/* pointer to the adapter context */
+TX_PORT	*pTxPort)	/* pointer to destination port structure */
+{
+TXD	*pTxd;		/* pointer to the checked descriptor */
+TXD	*pNewTail;	/* pointer to 'end' of the ring */
+SK_U32	Control;	/* TBControl field of descriptor */
+SK_U64	PhysAddr;	/* address of DMA mapping */
+
+	pNewTail = pTxPort->pTxdRingTail;
+	pTxd     = pNewTail;
+	/*
+	** loop forever; exits if BMU_SW bit not set in start frame
+	** or BMU_OWN bit set in any frame
+	*/
+	while (1) {
+		Control = pTxd->TBControl;
+		if ((Control & BMU_SW) == 0) {
+			/*
+			** software controllable bit is set in first
+			** fragment when given to BMU. Not set means that
+			** this fragment was never sent or is already
+			** freed ( -> ring completely free now).
+			*/
+			pTxPort->pTxdRingTail = pTxd;
+			netif_wake_queue(pAC->dev[pTxPort->PortIndex]);
+			return;
+		}
+		if (Control & BMU_OWN) {
+			pTxPort->pTxdRingTail = pTxd;
+			if (pTxPort->TxdRingFree > 0) {
+				netif_wake_queue(pAC->dev[pTxPort->PortIndex]);
+			}
+			return;
+		}
+
+		/*
+		** release the DMA mapping, because until not unmapped
+		** this buffer is considered being under control of the
+		** adapter card!
+		*/
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
+		if (pTxd->pMBuf != NULL) {
+#endif
+		/* Release the page and free the message */
+			PhysAddr = ((SK_U64) pTxd->VDataHigh) << (SK_U64) 32;
+			PhysAddr |= (SK_U64) pTxd->VDataLow;
+			pci_unmap_page(pAC->PciDev, PhysAddr,
+				 pTxd->pMBuf->len,
+				 PCI_DMA_TODEVICE);
+
+			if (Control & BMU_EOF)
+				DEV_KFREE_SKB_ANY(pTxd->pMBuf);	/* free message */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
+		}
+#endif
+
+		pTxPort->TxdRingFree++;
+		pTxd->TBControl &= ~BMU_SW;
+		pTxd = pTxd->pNextTxd; /* point behind fragment with EOF */
+	} /* while(forever) */
+} /* FreeTxDescriptors */
+
+/*****************************************************************************
+ *
+ * 	FillRxRing - fill the receive ring with valid descriptors
+ *
+ * Description:
+ *	This function fills the receive ring descriptors with data
+ *	segments and makes them valid for the BMU.
+ *	The active ring is filled completely, if possible.
+ *	The non-active ring is filled only partial to save memory.
+ *
+ * Description of rx ring structure:
+ *	head - points to the descriptor which will be used next by the BMU
+ *	tail - points to the next descriptor to give to the BMU
+ *
+ * Returns:	N/A
+ */
+static void FillRxRing(
+SK_AC		*pAC,		/* pointer to the adapter context */
+RX_PORT		*pRxPort)	/* ptr to port struct for which the ring
+				   should be filled */
+{
+unsigned long	Flags;
+
+	spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags);
+	while (pRxPort->RxdRingFree > pRxPort->RxFillLimit) {
+		if(!FillRxDescriptor(pAC, pRxPort))
+			break;
+	}
+	spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags);
+} /* FillRxRing */
+
+
+/*****************************************************************************
+ *
+ * 	FillRxDescriptor - fill one buffer into the receive ring
+ *
+ * Description:
+ *	The function allocates a new receive buffer and
+ *	puts it into the next descriptor.
+ *
+ * Returns:
+ *	SK_TRUE - a buffer was added to the ring
+ *	SK_FALSE - a buffer could not be added
+ */
+static SK_BOOL FillRxDescriptor(
+SK_AC		*pAC,		/* pointer to the adapter context struct */
+RX_PORT		*pRxPort)	/* ptr to port struct of ring to fill */
+{
+struct sk_buff	*pMsgBlock;	/* pointer to a new message block */
+RXD		*pRxd;		/* the rxd to fill */
+SK_U16		Length;		/* data fragment length */
+SK_U64		PhysAddr;	/* physical address of a rx buffer */
+
+	pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
+	if (pMsgBlock == NULL) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_ENTRY,
+			("%s: Allocation of rx buffer failed !\n",
+			pAC->dev[pRxPort->PortIndex]->name));
+		SK_PNMI_CNT_NO_RX_BUF(pAC, pRxPort->PortIndex);
+		return(SK_FALSE);
+	}
+	skb_reserve(pMsgBlock, 2); /* to align IP frames */
+	/* skb allocated ok, so add buffer */
+	pRxd = pRxPort->pRxdRingTail;
+	pRxPort->pRxdRingTail = pRxd->pNextRxd;
+	pRxPort->RxdRingFree--;
+	Length = pRxPort->RxBufSize;
+	PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+		virt_to_page(pMsgBlock->data),
+		((unsigned long) pMsgBlock->data &
+		~PAGE_MASK),
+		pRxPort->RxBufSize - 2,
+		PCI_DMA_FROMDEVICE);
+
+	pRxd->VDataLow  = (SK_U32) (PhysAddr & 0xffffffff);
+	pRxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
+	pRxd->pMBuf     = pMsgBlock;
+	pRxd->RBControl = BMU_OWN       |
+			  BMU_STF       |
+			  BMU_IRQ_EOF   |
+			  BMU_TCP_CHECK |
+			  Length;
+	return (SK_TRUE);
+
+} /* FillRxDescriptor */
+
+
+/*****************************************************************************
+ *
+ * 	ReQueueRxBuffer - fill one buffer back into the receive ring
+ *
+ * Description:
+ *	Fill a given buffer back into the rx ring. The buffer
+ *	has been previously allocated and aligned, and its phys.
+ *	address calculated, so this is no more necessary.
+ *
+ * Returns: N/A
+ */
+static void ReQueueRxBuffer(
+SK_AC		*pAC,		/* pointer to the adapter context struct */
+RX_PORT		*pRxPort,	/* ptr to port struct of ring to fill */
+struct sk_buff	*pMsg,		/* pointer to the buffer */
+SK_U32		PhysHigh,	/* phys address high dword */
+SK_U32		PhysLow)	/* phys address low dword */
+{
+RXD		*pRxd;		/* the rxd to fill */
+SK_U16		Length;		/* data fragment length */
+
+	pRxd = pRxPort->pRxdRingTail;
+	pRxPort->pRxdRingTail = pRxd->pNextRxd;
+	pRxPort->RxdRingFree--;
+	Length = pRxPort->RxBufSize;
+
+	pRxd->VDataLow  = PhysLow;
+	pRxd->VDataHigh = PhysHigh;
+	pRxd->pMBuf     = pMsg;
+	pRxd->RBControl = BMU_OWN       |
+			  BMU_STF       |
+			  BMU_IRQ_EOF   |
+			  BMU_TCP_CHECK |
+			  Length;
+	return;
+} /* ReQueueRxBuffer */
+
+/*****************************************************************************
+ *
+ * 	ReceiveIrq - handle a receive IRQ
+ *
+ * Description:
+ *	This function is called when a receive IRQ is set.
+ *	It walks the receive descriptor ring and sends up all
+ *	frames that are complete.
+ *
+ * Returns:	N/A
+ */
+static void ReceiveIrq(
+#ifdef CONFIG_SK98LIN_NAPI
+SK_AC    *pAC,          /* pointer to adapter context          */
+RX_PORT  *pRxPort,      /* pointer to receive port struct      */
+SK_BOOL   SlowPathLock, /* indicates if SlowPathLock is needed */
+int      *WorkDone,
+int       WorkToDo)
+#else
+SK_AC    *pAC,          /* pointer to adapter context          */
+RX_PORT  *pRxPort,      /* pointer to receive port struct      */
+SK_BOOL   SlowPathLock) /* indicates if SlowPathLock is needed */
+#endif
+{
+	RXD             *pRxd;          /* pointer to receive descriptors         */
+	struct sk_buff  *pMsg;          /* pointer to message holding frame       */
+	struct sk_buff  *pNewMsg;       /* pointer to new message for frame copy  */
+	SK_U32           Control;       /* control field of descriptor     */
+	int              PortIndex = pRxPort->PortIndex;
+	int              FrameLength;   /* total length of received frame  */
+	int              IpFrameLength; /* IP length of the received frame */
+	SK_BOOL          IsBadFrame;    /* the frame received is bad!      */
+	SK_U32           FrameStat;
+	unsigned short   Csum1;
+	unsigned short   Csum2;
+	unsigned short   Type;
+	int              Result;
+	SK_U64           PhysAddr;
+
+rx_start:
+	/* do forever; exit if BMU_OWN found */
+	for ( pRxd = pRxPort->pRxdRingHead ;
+		  pRxPort->RxdRingFree < pAC->RxDescrPerRing ;
+		  pRxd = pRxd->pNextRxd,
+		  pRxPort->pRxdRingHead = pRxd,
+		  pRxPort->RxdRingFree ++) {
+
+		/*
+		 * For a better understanding of this loop
+		 * Go through every descriptor beginning at the head
+		 * Please note: the ring might be completely received so the OWN bit
+		 * set is not a good crirteria to leave that loop.
+		 * Therefore the RingFree counter is used.
+		 * On entry of this loop pRxd is a pointer to the Rxd that needs
+		 * to be checked next.
+		 */
+
+		Control = pRxd->RBControl;
+
+#ifdef CONFIG_SK98LIN_NAPI
+		if (*WorkDone >= WorkToDo) {
+			break;
+		}
+		(*WorkDone)++;
+#endif
+
+		/* check if this descriptor is ready */
+		if ((Control & BMU_OWN) != 0) {
+			/* this descriptor is not yet ready */
+			/* This is the usual end of the loop */
+			/* We don't need to start the ring again */
+			FillRxRing(pAC, pRxPort);
+			return;
+		}
+
+		/* get length of frame and check it */
+		FrameLength = Control & BMU_BBC;
+		if (FrameLength > pRxPort->RxBufSize) {
+			goto rx_failed;
+		}
+
+		/* check for STF and EOF */
+		if ((Control & (BMU_STF | BMU_EOF)) != (BMU_STF | BMU_EOF)) {
+			goto rx_failed;
+		}
+
+		/* here we have a complete frame in the ring */
+		pMsg = pRxd->pMBuf;
+
+		FrameStat = pRxd->FrameStat;
+
+		/* check for frame length mismatch */
+#define XMR_FS_LEN_SHIFT	18
+#define GMR_FS_LEN_SHIFT	16
+		if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
+			if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
+				SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+					SK_DBGCAT_DRV_RX_PROGRESS,
+					("skge: Frame length mismatch (%u/%u).\n",
+					FrameLength,
+					(SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
+				goto rx_failed;
+			}
+		} else {
+			if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
+				SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+					SK_DBGCAT_DRV_RX_PROGRESS,
+					("skge: Frame length mismatch (%u/%u).\n",
+					FrameLength,
+					(SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
+				goto rx_failed;
+			}
+		}
+
+		/* Set Rx Status */
+		if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
+			IsBadFrame = (FrameStat &
+				(XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0;
+		} else {
+			IsBadFrame = (((FrameStat & GMR_FS_ANY_ERR) != 0) ||
+							((FrameStat & GMR_FS_RX_OK) == 0));
+		}
+
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0,
+			("Received frame of length %d on port %d\n",
+			FrameLength, PortIndex));
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0,
+			("Number of free rx descriptors: %d\n",
+			pRxPort->RxdRingFree));
+		/* DumpMsg(pMsg, "Rx");	*/
+
+		if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
+			/* there is a receive error in this frame */
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS,
+				("skge: Error in received frame, dropped!\n"
+				"Control: %x\nRxStat: %x\n",
+				Control, FrameStat));
+
+			PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
+			PhysAddr |= (SK_U64) pRxd->VDataLow;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
+			pci_dma_sync_single(pAC->PciDev,
+						(dma_addr_t) PhysAddr,
+						FrameLength,
+						PCI_DMA_FROMDEVICE);
+#else
+			pci_dma_sync_single_for_cpu(pAC->PciDev,
+						(dma_addr_t) PhysAddr,
+						FrameLength,
+						PCI_DMA_FROMDEVICE);
+#endif
+			ReQueueRxBuffer(pAC, pRxPort, pMsg,
+				pRxd->VDataHigh, pRxd->VDataLow);
+
+			continue;
+		}
+
+		/*
+		 * if short frame then copy data to reduce memory waste
+		 */
+		if ((FrameLength < SK_COPY_THRESHOLD) &&
+			((pNewMsg = alloc_skb(FrameLength+2, GFP_ATOMIC)) != NULL)) {
+			/*
+			 * Short frame detected and allocation successfull
+			 */
+			/* use new skb and copy data */
+			skb_reserve(pNewMsg, 2);
+			skb_put(pNewMsg, FrameLength);
+			PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
+			PhysAddr |= (SK_U64) pRxd->VDataLow;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
+			pci_dma_sync_single(pAC->PciDev,
+						(dma_addr_t) PhysAddr,
+						FrameLength,
+						PCI_DMA_FROMDEVICE);
+#else
+			pci_dma_sync_single_for_device(pAC->PciDev,
+						(dma_addr_t) PhysAddr,
+						FrameLength,
+						PCI_DMA_FROMDEVICE);
+#endif
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
+			skb_copy_to_linear_data(pNewMsg, pMsg->data,
+				FrameLength);
+#else
+			eth_copy_and_sum(pNewMsg, pMsg->data,
+				FrameLength, 0);
+#endif
+			ReQueueRxBuffer(pAC, pRxPort, pMsg,
+				pRxd->VDataHigh, pRxd->VDataLow);
+
+			pMsg = pNewMsg;
+
+		} else {
+			/*
+			 * if large frame, or SKB allocation failed, pass
+			 * the SKB directly to the networking
+			 */
+			PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
+			PhysAddr |= (SK_U64) pRxd->VDataLow;
+
+			/* release the DMA mapping */
+			pci_unmap_single(pAC->PciDev,
+					 PhysAddr,
+					 pRxPort->RxBufSize - 2,
+					 PCI_DMA_FROMDEVICE);
+			skb_put(pMsg, FrameLength); /* set message len */
+			pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
+
+			if (pRxPort->UseRxCsum) {
+				Type = ntohs(*((short*)&pMsg->data[12]));
+				if (Type == 0x800) {
+					IpFrameLength = (int) ntohs((unsigned short)
+							((unsigned short *) pMsg->data)[8]);
+					if ((FrameLength - IpFrameLength) == 0xe) {
+						Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
+						Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
+						if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
+							(pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
+							(pAC->ChipsetType)) {
+							Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
+								Csum1, Csum2, PortIndex, IpFrameLength);
+							if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
+							    (Result == SKCS_STATUS_IP_CSUM_OK)  ||
+							    (Result == SKCS_STATUS_TCP_CSUM_OK) ||
+							    (Result == SKCS_STATUS_UDP_CSUM_OK)) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+								pMsg->ip_summed = CHECKSUM_COMPLETE;
+								pMsg->csum = Csum1 & 0xffff;
+#else
+								pMsg->ip_summed = CHECKSUM_UNNECESSARY;
+#endif
+							} else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR)    ||
+							           (Result == SKCS_STATUS_UDP_CSUM_ERROR)    ||
+							           (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
+							           (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
+							           (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
+								/* HW Checksum error */
+								SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+								SK_DBGCAT_DRV_RX_PROGRESS,
+								("skge: CRC error. Frame dropped!\n"));
+								goto rx_failed;
+							} else {
+								pMsg->ip_summed = CHECKSUM_NONE;
+							}
+						}/* checksumControl calculation valid */
+					} /* Frame length check */
+				} /* IP frame */
+			} /* pRxPort->UseRxCsum */
+		} /* frame > SK_COPY_TRESHOLD */
+
+		/* Send up only frames from active port */
+		if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
+#ifdef xDEBUG
+			DumpMsg(pMsg, "Rx");
+#endif
+			SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
+			pMsg->dev = pAC->dev[PortIndex];
+			pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
+
+			netif_rx(pMsg); /* frame for upper layer */
+			pAC->dev[PortIndex]->last_rx = jiffies;
+		} else {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS,("D"));
+			DEV_KFREE_SKB(pMsg); /* drop frame */
+		}
+	} /* for ... scanning the RXD ring */
+
+	/* RXD ring is empty -> fill and restart */
+	FillRxRing(pAC, pRxPort);
+	return;
+
+rx_failed:
+	/* remove error frame */
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
+		("Schrottdescriptor, length: 0x%x\n", FrameLength));
+
+	/* release the DMA mapping */
+
+	PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
+	PhysAddr |= (SK_U64) pRxd->VDataLow;
+	pci_unmap_page(pAC->PciDev,
+			 PhysAddr,
+			 pRxPort->RxBufSize - 2,
+			 PCI_DMA_FROMDEVICE);
+	DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
+	pRxd->pMBuf = NULL;
+	pRxPort->RxdRingFree++;
+	pRxPort->pRxdRingHead = pRxd->pNextRxd;
+	goto rx_start;
+
+} /* ReceiveIrq */
+
+/*****************************************************************************
+ *
+ * 	ClearRxRing - remove all buffers from the receive ring
+ *
+ * Description:
+ *	This function removes all receive buffers from the ring.
+ *	The receive BMU must be stopped before calling this function.
+ *
+ * Returns: N/A
+ */
+static void ClearRxRing(
+SK_AC	*pAC,		/* pointer to adapter context */
+RX_PORT	*pRxPort)	/* pointer to rx port struct */
+{
+RXD		*pRxd;	/* pointer to the current descriptor */
+unsigned long	Flags;
+SK_U64		PhysAddr;
+
+	if (pRxPort->RxdRingFree == pAC->RxDescrPerRing) {
+		return;
+	}
+	spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags);
+	pRxd = pRxPort->pRxdRingHead;
+	do {
+		if (pRxd->pMBuf != NULL) {
+
+			PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
+			PhysAddr |= (SK_U64) pRxd->VDataLow;
+			pci_unmap_page(pAC->PciDev,
+					 PhysAddr,
+					 pRxPort->RxBufSize - 2,
+					 PCI_DMA_FROMDEVICE);
+			DEV_KFREE_SKB(pRxd->pMBuf);
+			pRxd->pMBuf = NULL;
+		}
+		pRxd->RBControl &= BMU_OWN;
+		pRxd = pRxd->pNextRxd;
+		pRxPort->RxdRingFree++;
+	} while (pRxd != pRxPort->pRxdRingTail);
+	pRxPort->pRxdRingTail = pRxPort->pRxdRingHead;
+	spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags);
+} /* ClearRxRing */
+
+/*****************************************************************************
+ *
+ *	ClearTxRing - remove all buffers from the transmit ring
+ *
+ * Description:
+ *	This function removes all transmit buffers from the ring.
+ *	The transmit BMU must be stopped before calling this function
+ *	and transmitting at the upper level must be disabled.
+ *	The BMU own bit of all descriptors is cleared, the rest is
+ *	done by calling FreeTxDescriptors.
+ *
+ * Returns: N/A
+ */
+static void ClearTxRing(
+SK_AC	*pAC,		/* pointer to adapter context */
+TX_PORT	*pTxPort)	/* pointer to tx prt struct */
+{
+TXD		*pTxd;		/* pointer to the current descriptor */
+int		i;
+unsigned long	Flags;
+
+	spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
+	pTxd = pTxPort->pTxdRingHead;
+	for (i=0; i<pAC->TxDescrPerRing; i++) {
+		pTxd->TBControl &= ~BMU_OWN;
+		pTxd = pTxd->pNextTxd;
+	}
+	FreeTxDescriptors(pAC, pTxPort);
+	spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
+} /* ClearTxRing */
+
+/*****************************************************************************
+ *
+ * 	SkGeSetMacAddr - Set the hardware MAC address
+ *
+ * Description:
+ *	This function sets the MAC address used by the adapter.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
+{
+
+DEV_NET *pNet = PPRIV;
+SK_AC	*pAC = pNet->pAC;
+int	Ret;
+
+struct sockaddr	*addr = p;
+unsigned long	Flags;
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeSetMacAddr starts now...\n"));
+
+	memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
+
+	if (addr->sa_data == NULL) {
+		printk(KERN_ERR "Null pointer from the upper layer\n");
+		return -EBUSY;
+	}
+
+	if (dev->dev_addr == NULL) {
+		printk(KERN_ERR "Device not available - NULL pointer\n");
+		return -EBUSY;
+	}
+
+	if (pAC->BoardLevel == SK_INIT_DATA) {
+		printk(KERN_ERR "Device already down - Don't handle event\n");
+		return -EBUSY;
+	}
+
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+
+	if (pAC->RlmtNets == 2)
+		Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
+		      (SK_MAC_ADDR*) dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
+	else
+		Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
+		      (SK_MAC_ADDR*) dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+	if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
+		return -EBUSY;
+
+	return 0;
+} /* SkGeSetMacAddr */
+
+
+/*****************************************************************************
+ *
+ * 	SkGeSetRxMode - set receive mode
+ *
+ * Description:
+ *	This function sets the receive mode of an adapter. The adapter
+ *	supports promiscuous mode, allmulticast mode and a number of
+ *	multicast addresses. If more multicast addresses the available
+ *	are selected, a hash function in the hardware is used.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static void SkGeSetRxMode(struct SK_NET_DEVICE *dev)
+{
+
+DEV_NET		*pNet;
+SK_AC		*pAC;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
+struct netdev_hw_addr   *ha;
+#else
+struct dev_mc_list      *pMcList;
+int                     i;
+#endif
+int			PortIdx;
+unsigned long		Flags;
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeSetRxMode starts now... "));
+
+	pNet = PPRIV;
+	pAC = pNet->pAC;
+	if (pAC->RlmtNets == 1)
+		PortIdx = pAC->ActivePort;
+	else
+		PortIdx = pNet->NetNr;
+
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+	if (dev->flags & IFF_PROMISC) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+			("PROMISCUOUS mode\n"));
+		SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx,
+			SK_PROM_MODE_LLC);
+	} else if (dev->flags & IFF_ALLMULTI) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+			("ALLMULTI mode\n"));
+		SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx,
+			SK_PROM_MODE_ALL_MC);
+	} else {
+		SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx,
+			SK_PROM_MODE_NONE);
+		SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0);
+
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+			("Number of MC entries: %d ", dev->mc_count));
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
+		netdev_for_each_mc_addr(ha,dev) {
+			SkAddrMcAdd(pAC, pAC->IoBase, PortIdx,
+			(SK_MAC_ADDR*)ha->addr, 0);
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MCA,
+				("%02x:%02x:%02x:%02x:%02x:%02x\n",
+				ha->addr[0],
+				ha->addr[1],
+				ha->addr[2],
+				ha->addr[3],
+				ha->addr[4],
+				ha->addr[5]));
+		}
+#else
+		pMcList = dev->mc_list;
+		for (i=0; i<dev->mc_count; i++, pMcList = pMcList->next) {
+			SkAddrMcAdd(pAC, pAC->IoBase, PortIdx,
+				(SK_MAC_ADDR*)pMcList->dmi_addr, 0);
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MCA,
+				("%02x:%02x:%02x:%02x:%02x:%02x\n",
+				pMcList->dmi_addr[0],
+				pMcList->dmi_addr[1],
+				pMcList->dmi_addr[2],
+				pMcList->dmi_addr[3],
+				pMcList->dmi_addr[4],
+				pMcList->dmi_addr[5]));
+		}
+#endif
+		SkAddrMcUpdate(pAC, pAC->IoBase, PortIdx);
+	}
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+	return;
+} /* SkGeSetRxMode */
+
+
+/*****************************************************************************
+ *
+ * 	SkSetMtuBufferSize - set the MTU buffer to another value
+ *
+ * Description:
+ *	This function sets the new buffers and is called whenever the MTU
+ *      size is changed
+ *
+ * Returns:
+ *	N/A
+ */
+
+static void SkSetMtuBufferSize(
+SK_AC	*pAC,		/* pointer to adapter context */
+int	PortNr,		/* Port number */
+int	Mtu)		/* pointer to tx prt struct */
+{
+	pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
+
+	/* RxBufSize must be a multiple of 8 */
+	while (pAC->RxPort[PortNr].RxBufSize % 8) {
+		pAC->RxPort[PortNr].RxBufSize =
+			pAC->RxPort[PortNr].RxBufSize + 1;
+	}
+
+	if (Mtu > ETH_MAX_MTU) {
+		pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
+	} else {
+		if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
+			pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
+		} else {
+			pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
+		}
+	}
+
+	return;
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeChangeMtu - set the MTU to another value
+ *
+ * Description:
+ *	This function sets is called whenever the MTU size is changed
+ *	(ifconfig mtu xxx dev ethX). If the MTU is bigger than standard
+ *	ethernet MTU size, long frame support is activated.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
+{
+DEV_NET			*pNet;
+SK_AC			*pAC;
+unsigned long		Flags;
+#ifdef CONFIG_SK98LIN_NAPI
+int			WorkToDo = 1; // min(*budget, dev->quota);
+int			WorkDone = 0;
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeChangeMtu starts now...\n"));
+
+	pNet = PPRIV;
+	pAC  = pNet->pAC;
+
+	/* MTU size outside the spec */
+	if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
+		return -EINVAL;
+	}
+
+	/* MTU > 1500 on yukon FE and FE+ not allowed */
+	if (((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
+		 (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P))
+		&& (NewMtu > ETH_MAX_MTU)) {
+		return -EINVAL;
+	}
+
+	/* Diag access active */
+	if (pAC->DiagModeActive == DIAG_ACTIVE) {
+		if (pAC->DiagFlowCtrl == SK_FALSE) {
+			return -1; /* still in use, deny any actions of MTU */
+		} else {
+			pAC->DiagFlowCtrl = SK_FALSE;
+		}
+	}
+
+	/* TSO on Yukon Ultra and MTU > 1500 not supported */
+#ifdef NETIF_F_TSO
+#ifdef USE_SK_TSO_FEATURE
+	if (CHIP_ID_YUKON_2(pAC)) {
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) && (NewMtu > ETH_MAX_MTU)) {
+			dev->features &= ~NETIF_F_TSO;
+		} else {
+			dev->features |= NETIF_F_TSO;
+		}
+	}
+#endif
+#endif
+	dev->mtu = NewMtu;
+
+	if (NewMtu < 1500) {
+		return 0;
+	}
+
+	SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
+
+	if (!netif_running(dev)) {
+		/* Preset MTU size if device not ready/running */
+		return 0;
+	}
+
+	/*  Prevent any reconfiguration while changing the MTU
+	    by disabling any interrupts */
+	SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+
+	netif_stop_queue(dev);
+	SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP,
+				pNet->PortNr, -1, SK_TRUE);
+	spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
+
+
+	/* Change RxFillLimit to 1 */
+	if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
+		pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
+	} else {
+		pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
+		pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
+					(pAC->RxDescrPerRing / 4);
+	}
+
+	/* clear and reinit the rx rings here, because of new MTU size */
+	if (CHIP_ID_YUKON_2(pAC)) {
+		SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
+		SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
+		SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
+	} else {
+#ifdef CONFIG_SK98LIN_NAPI
+		WorkToDo = 1;
+		ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
+#else
+		ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
+#endif
+		ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
+		FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
+
+		/* Enable transmit descriptor polling */
+		SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
+		FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
+	}
+
+	netif_start_queue(pAC->dev[pNet->PortNr]);
+	spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
+	SkLocalEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START,
+				pNet->PortNr, -1, SK_TRUE);
+
+	/* Enable Interrupts again */
+	SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+	if (CHIP_ID_YUKON_2(pAC)) {
+		SK_OUT32(pAC->IoBase, B0_HWE_IMSK, Y2_IRQ_HWE_MASK);
+	}
+	else {
+		SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+	}
+
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+	return 0;
+
+}
+
+
+/*****************************************************************************
+ *
+ * 	SkGeStats - return ethernet device statistics
+ *
+ * Description:
+ *	This function return statistic data about the ethernet device
+ *	to the operating system.
+ *
+ * Returns:
+ *	pointer to the statistic structure.
+ */
+static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
+{
+	DEV_NET		*pNet = PPRIV;
+	SK_AC		*pAC = pNet->pAC;
+	unsigned long	LateCollisions, ExcessiveCollisions, RxTooLong, RxTooShort;
+	unsigned long	Flags; /* for spin lock */
+    	SK_U32		MaxNumOidEntries, Oid, Len;
+	char		Buf[8];
+	struct {
+		SK_U32         Oid;
+		unsigned long *pVar;
+	} Vars[] = {
+		{ OID_SKGE_STAT_TX_LATE_COL,   &LateCollisions               },
+		{ OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions          },
+		{ OID_SKGE_STAT_RX_TOO_LONG,   &RxTooLong                    },
+		{ OID_SKGE_STAT_RX_SHORTS,     &RxTooShort                   },
+		{ OID_SKGE_STAT_RX,            &pAC->stats.rx_packets        },
+		{ OID_SKGE_STAT_TX,            &pAC->stats.tx_packets        },
+		{ OID_SKGE_STAT_RX_OCTETS,     &pAC->stats.rx_bytes          },
+		{ OID_SKGE_STAT_TX_OCTETS,     &pAC->stats.tx_bytes          },
+		{ OID_SKGE_RX_NO_BUF_CTS,      &pAC->stats.rx_dropped        },
+		{ OID_SKGE_TX_NO_BUF_CTS,      &pAC->stats.tx_dropped        },
+		{ OID_SKGE_STAT_RX_MULTICAST,  &pAC->stats.multicast         },
+		{ OID_SKGE_STAT_RX_RUNT,       &pAC->stats.rx_length_errors  },
+		{ OID_SKGE_STAT_RX_FCS,        &pAC->stats.rx_crc_errors     },
+		{ OID_SKGE_STAT_RX_FRAMING,    &pAC->stats.rx_frame_errors   },
+		{ OID_SKGE_STAT_RX_OVERFLOW,   &pAC->stats.rx_over_errors    },
+		{ OID_SKGE_STAT_RX_MISSED,     &pAC->stats.rx_missed_errors  },
+		{ OID_SKGE_STAT_TX_CARRIER,    &pAC->stats.tx_carrier_errors },
+		{ OID_SKGE_STAT_TX_UNDERRUN,   &pAC->stats.tx_fifo_errors    },
+	};
+
+	if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
+	    (pAC->BoardLevel     == SK_INIT_RUN)) {
+		memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
+		spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+
+    		MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
+    		for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
+			if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
+				&Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
+				memset(Buf, 0x00, sizeof(Buf));
+			}
+			*Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
+		}
+		spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+
+		pAC->stats.rx_frame_errors = pAC->stats.rx_frame_errors +
+					RxTooShort + RxTooLong;
+		pAC->stats.collisions =	LateCollisions + ExcessiveCollisions;
+		pAC->stats.tx_errors =	pAC->stats.tx_carrier_errors +
+					pAC->stats.tx_fifo_errors;
+		pAC->stats.rx_errors = 	pAC->stats.rx_length_errors +
+					pAC->stats.rx_crc_errors +
+					pAC->stats.rx_frame_errors +
+					pAC->stats.rx_over_errors +
+					pAC->stats.rx_missed_errors;
+
+		if (dev->mtu > ETH_MAX_MTU) {
+			pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
+		}
+	}
+
+	return(&pAC->stats);
+} /* SkGeStats */
+
+/*****************************************************************************
+ *
+ * 	SkGeIoctl - IO-control function
+ *
+ * Description:
+ *	This function is called if an ioctl is issued on the device.
+ *	There are three subfunction for reading, writing and test-writing
+ *	the private MIB data structure (usefull for SysKonnect-internal tools).
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ */
+static int SkGeIoctl(
+struct SK_NET_DEVICE *dev,  /* the device the IOCTL is to be performed on   */
+struct ifreq         *rq,   /* additional request structure containing data */
+int                   cmd)  /* requested IOCTL command number               */
+{
+	DEV_NET          *pNet = PPRIV;
+	SK_AC            *pAC  = pNet->pAC;
+	struct pci_dev   *pdev = NULL;
+	void             *pMemBuf;
+	SK_GE_IOCTL       Ioctl;
+	SK_GE_FWIOCTL     FwIoctl;
+	unsigned long     Flags; /* for spin lock */
+	unsigned int      Err = 0;
+	unsigned int      Length = 0;
+	int               HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
+	int               Size = 0;
+	int               Ret = 0;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	SK_U8             LinkData[256];
+	SK_U16            LinkCap;
+#endif
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeIoctl starts now...\n"));
+
+	if(copy_from_user(&FwIoctl, rq->ifr_data, sizeof(SK_GE_FWIOCTL))) {
+		return -EFAULT;
+	}
+
+	switch(cmd) {
+	case SK_IOCTL_SETMIB:     /* FALL THRU */
+	case SK_IOCTL_PRESETMIB:  /* FALL THRU (if capable!) */
+		if (!capable(CAP_NET_ADMIN)) return -EPERM;
+ 	case SK_IOCTL_GETMIB:
+		if(!copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
+			Ioctl.Len<sizeof(pAC->PnmiStruct)?
+			Ioctl.Len : sizeof(pAC->PnmiStruct))) {
+			Size = SkGeIocMib(pNet, Ioctl.Len, cmd);
+			if(!copy_to_user(Ioctl.pData,&pAC->PnmiStruct,Ioctl.Len<Size? Ioctl.Len:Size)) {
+				Ioctl.Len = Size;
+				if(!copy_to_user(rq->ifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) {
+					return 0;
+				}
+			}
+		}
+		return -EFAULT;
+		break;
+	case SK_IOCTL_GEN:
+		Length = sizeof(pAC->PnmiStruct) + HeaderLength;
+		if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
+			Length = Ioctl.Len;
+		}
+		if ((pMemBuf = kmalloc(Length, GFP_KERNEL)) != NULL) {
+			if(!copy_from_user(pMemBuf, Ioctl.pData, Length)) {
+				spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+				Ret = SkPnmiGenIoctl(pAC,pAC->IoBase,pMemBuf,&Length,0);
+				spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+				if (Ret >= 0) {
+					if(!copy_to_user(Ioctl.pData, pMemBuf, Length) ) {
+						Ioctl.Len = Length;
+						if(!copy_to_user(rq->ifr_data,&Ioctl,sizeof(SK_GE_IOCTL))) {
+							return 0; /* copy to userland OK! */
+						}
+					}
+				}
+			}
+			kfree(pMemBuf);
+		}
+		return -EFAULT;
+		break;
+	case SK_IOCTL_DIAG:
+		if (!capable(CAP_NET_ADMIN)) return -EPERM;
+		Length = sizeof(pAC->PnmiStruct) + HeaderLength;
+		if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
+			Length = Ioctl.Len;
+		}
+		if ((pMemBuf = kmalloc(Length, GFP_KERNEL)) != NULL) {
+			if(!copy_from_user(pMemBuf, Ioctl.pData, Length)) {
+				pdev = pAC->PciDev;
+				Length = 3 * sizeof(SK_U32);  /* Error, Bus and Device */
+				* ((SK_U32 *)pMemBuf) = 0;
+				* ((SK_U32 *)pMemBuf + 1) = pdev->bus->number;
+				* ((SK_U32 *)pMemBuf + 2) = ParseDeviceNbrFromSlotName(pci_name(pdev));
+
+				if(!copy_to_user(Ioctl.pData, pMemBuf, Length) ) {
+					Ioctl.Len = Length;
+					if(!copy_to_user(rq->ifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) {
+						return 0; /* copy to userland OK! */
+					}
+				}
+			}
+			kfree(pMemBuf);
+		}
+		return -EFAULT;
+		break;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	case SK_IOCTL_APPTOFW:
+		if(!netif_running(dev))  return -EPERM;
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+		printk("Receive command from App layer. Command: 0x%x\n", FwIoctl.Command);
+#endif
+		if ((pMemBuf = kmalloc(FwIoctl.Len, GFP_KERNEL)) != NULL) {
+			unsigned long Flags;  /* for spin lock */
+			spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+			if(!copy_from_user(pMemBuf, FwIoctl.pData, FwIoctl.Len)) {
+				if ( FwIoctl.Command == SK_IOCTL_FW_SEND) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+					printk("Receive data from App layer. Len: 0x%x\n", FwIoctl.Len);
+#endif
+					SendFwCommand(pAC, SKGE_DGRAM_MSG2FW, pMemBuf, FwIoctl.Len);
+				} else if (FwIoctl.Command == SK_IOCTL_COMMAND) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+					printk("Receive command from App layer. Len: 0x%x\n", FwIoctl.Len);
+#endif
+					HandleDrvCommand(pAC, pMemBuf, FwIoctl.Len);
+				} else if (FwIoctl.Command == SK_IOCTL_FW_RECEIVE) {
+					if ((pAC->FwBufferLen) && (pAC->FwBufferLen)) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+						printk("Send data to the App layer. Len: 0x%x\n", pAC->FwBufferLen);
+#endif
+						if(!copy_to_user(FwIoctl.pData, pAC->pFwBuffer, pAC->FwBufferLen) ) {
+							FwIoctl.Len = pAC->FwBufferLen;
+							if(!copy_to_user(rq->ifr_data, &FwIoctl, sizeof(SK_GE_FWIOCTL))) {
+								pAC->FwBufferLen = 0;
+								kfree(pAC->pFwBuffer);
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+								printk("SEND DONE!!!!\n");
+#endif
+							}
+						}
+					}
+				} else {
+					Err = -EPERM;
+				}
+			}
+			kfree(pMemBuf);
+			spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+		}
+		break;
+	case SK_IOCTL_GETLINKCAP:
+		if (netif_running(dev)) {
+			if (copy_from_user(&LinkData[0], rq->ifr_data, sizeof(LinkData))) {
+				return -EFAULT;
+			}
+
+			/* Get information about link partner capabilities. */
+			SkGmPhyRead(pAC, pAC->IoBase, pNet->PortNr, PHY_MARV_AUNE_LP, &LinkCap);
+			memcpy((char *) &LinkData[0], (char *) &LinkCap, sizeof(LinkCap));
+
+			if ((pAC->dev[pNet->PortNr]->flags & IFF_RUNNING) == 0) {
+
+				LinkData[2] = SK_AUTONEG_NOLINK; /* No link. */
+			}
+			else if ((pAC->GIni.GP[pNet->PortNr].PLinkModeConf == SK_LMODE_HALF) ||
+				(pAC->GIni.GP[pNet->PortNr].PLinkModeConf == SK_LMODE_FULL)) {
+
+				LinkData[2] = SK_AUTONEG_OFF; /* Autonegotiation not used. */
+			}
+			else {
+
+				/* Get information about autonegotiation status. */
+				LinkData[2] = pAC->GIni.GP[pNet->PortNr].PAutoNegFail;
+			}
+
+			if (copy_to_user(rq->ifr_data, &LinkData[0], sizeof(LinkData))) {
+				return -EFAULT;
+			}
+
+			rq->ifr_name[0] = 'A';
+			rq->ifr_name[1] = 'C';
+			rq->ifr_name[2] = 'K';
+		}
+		else {
+			rq->ifr_name[0] = 'D';
+			rq->ifr_name[1] = 'E';
+			rq->ifr_name[2] = 'C';
+		}
+
+		break;
+#endif
+	default:
+		Err = -EOPNOTSUPP;
+	}
+	return(Err);
+
+} /* SkGeIoctl */
+
+
+/*****************************************************************************
+ *
+ * 	SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message
+ *
+ * Description:
+ *	This function reads/writes the MIB data using PNMI (Private Network
+ *	Management Interface).
+ *	The destination for the data must be provided with the
+ *	ioctl call and is given to the driver in the form of
+ *	a user space address.
+ *	Copying from the user-provided data area into kernel messages
+ *	and back is done by copy_from_user and copy_to_user calls in
+ *	SkGeIoctl.
+ *
+ * Returns:
+ *	returned size from PNMI call
+ */
+static int SkGeIocMib(
+DEV_NET		*pNet,	/* pointer to the adapter context */
+unsigned int	Size,	/* length of ioctl data */
+int		mode)	/* flag for set/preset */
+{
+	SK_AC		*pAC = pNet->pAC;
+	unsigned long	Flags;  /* for spin lock */
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("SkGeIocMib starts now...\n"));
+
+	/* access MIB */
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+	switch(mode) {
+	case SK_IOCTL_GETMIB:
+		SkPnmiGetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size,
+			pNet->NetNr);
+		break;
+	case SK_IOCTL_PRESETMIB:
+		SkPnmiPreSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size,
+			pNet->NetNr);
+		break;
+	case SK_IOCTL_SETMIB:
+		SkPnmiSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size,
+			pNet->NetNr);
+		break;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
+		("MIB data access succeeded\n"));
+	return (Size);
+} /* SkGeIocMib */
+
+/*****************************************************************************
+ *
+ * 	SetConfiguration - Get the configuration information
+ *
+ * Description:
+ *	This function sets the per-adapter configuration information from
+ *	the options provided on the command line and ethtool
+ *
+ * Returns:
+ *	none
+ */
+static void SetConfiguration(
+SK_AC	*pAC)	/* pointer to the adapter context structure */
+{
+	/* Set the link speed */
+	pAC->GIni.GP[0].PLinkSpeed = pAC->LinkInfo[0].PLinkSpeed;
+	pAC->GIni.GP[1].PLinkSpeed = pAC->LinkInfo[1].PLinkSpeed;
+
+	/* Set the desired link mode */
+	pAC->GIni.GP[0].PLinkModeConf = pAC->LinkInfo[0].PLinkModeConf;
+	pAC->GIni.GP[1].PLinkModeConf = pAC->LinkInfo[1].PLinkModeConf;
+
+	/* Set flow control */
+	pAC->GIni.GP[0].PFlowCtrlMode = pAC->LinkInfo[0].PFlowCtrlMode;
+	pAC->GIni.GP[1].PFlowCtrlMode = pAC->LinkInfo[1].PFlowCtrlMode;
+
+	/* Set the role parameter */
+	pAC->GIni.GP[0].PMSMode = pAC->LinkInfo[0].PMSMode;
+	pAC->GIni.GP[1].PMSMode = pAC->LinkInfo[1].PMSMode;
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	if (pAC->LinkInfo[0].PLinkSpeed == SK_LSPEED_AUTO) {
+	/* Autonegotiation enabled - disable Link Maintenance*/
+		pAC->LinkInfo[0].LinkMaintenance = SK_FALSE;
+	} else {
+		if (pAC->LinkInfo[0].PLinkMaintenance)
+			pAC->LinkInfo[0].LinkMaintenance = SK_TRUE;
+		else
+			pAC->LinkInfo[0].LinkMaintenance = SK_FALSE;
+	}
+
+	if (pAC->LinkInfo[1].PLinkSpeed == SK_LSPEED_AUTO) {
+	/* Autonegotiation enabled - disable Link Maintenance*/
+		pAC->LinkInfo[1].LinkMaintenance = SK_FALSE;
+	}
+#endif
+}
+
+
+/*****************************************************************************
+ *
+ * 	GetConfiguration - Get the configuration information
+ *
+ * Description:
+ *	This function reads per-adapter configuration information from
+ *	the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetConfiguration(
+SK_AC	*pAC)	/* pointer to the adapter context structure */
+{
+	/* Get the ConType parameters */
+	GetConTypeConfiguration(pAC);
+
+	/* Get the WolType parameters */
+	GetWolTypeConfiguration(pAC);
+
+	/* Get link parameters for port A */
+	if (!pAC->LinkInfo[0].PLinkSpeed) {
+		GetSpeedConfiguration(pAC, 0, "Speed_A", Speed_A[pAC->Index]);
+		GetLinkModeCapabilities(pAC, 0, "AutoNeg_A", AutoNeg_A[pAC->Index],
+				"DupCap_A", DupCap_A[pAC->Index]);
+		GetFlowControlConfiguration(pAC, 0, "FlowCtrl_A", FlowCtrl_A[pAC->Index]);
+		GetRoleConfiguration(pAC, 0, "Role_A", Role_A[pAC->Index]);
+	}
+
+	/* Get link parameters for port B */
+	if (!pAC->LinkInfo[1].PLinkSpeed) {
+		GetSpeedConfiguration(pAC, 1, "Speed_B", Speed_B[pAC->Index]);
+		GetLinkModeCapabilities(pAC, 1, "AutoNeg_B", AutoNeg_B[pAC->Index],
+				"DupCap_B", DupCap_A[pAC->Index]);
+		GetFlowControlConfiguration(pAC, 1, "FlowCtrl_B", FlowCtrl_B[pAC->Index]);
+		GetRoleConfiguration(pAC, 1, "Role_B", Role_B[pAC->Index]);
+	}
+
+	/* Get interrupt moderation parameters */
+	GetInterruptModConfiguration(pAC);
+
+	/* Get misc parameters */
+	GetMiscConfiguration(pAC);
+
+}
+
+/*****************************************************************************
+ *
+ * 	GetLinkCapabilities - Get the link Capabilities definition
+ *
+ * Description:
+ *
+ * Returns:
+ *	LinkMode
+ */
+static int GetLinkCapabilities (
+SK_U32	AutoNeg,
+SK_U32	Duplex) {
+	int Capabilities[3][3] = \
+		{ {                -1, SK_LMODE_FULL     , SK_LMODE_HALF     },
+		  {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
+		  {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
+	return(Capabilities[AutoNeg][Duplex]);
+}
+
+/*****************************************************************************
+ *
+ * 	GetConTypeConfiguration - read ConType configuration information
+ *
+ * Description:
+ *	This function reads per-adapter ConType configuration information from
+ *	the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetConTypeConfiguration(
+SK_AC	*pAC)	/* pointer to the adapter context structure */
+{
+SK_I32	Port;		/* preferred port */
+
+	/*
+	** Check merged parameter ConType. If it has not been used,
+	** verify any other parameter (e.g. AutoNeg) and use default values.
+	**
+	** Stating both ConType and other lowlevel link parameters is also
+	** possible. If this is the case, the passed ConType-parameter is
+	** overwritten by the lowlevel link parameter.
+	**
+	** The following settings are used for a merged ConType-parameter:
+	**
+	** ConType   DupCap   AutoNeg   FlowCtrl      Role      Speed
+	** -------   ------   -------   --------   ----------   -----
+	**  Auto      Both      On      SymOrRem      Auto       Auto
+	**  1000FD    Full      Off       None      <ignored>    1000
+	**  100FD     Full      Off       None      <ignored>    100
+	**  100HD     Half      Off       None      <ignored>    100
+	**  10FD      Full      Off       None      <ignored>    10
+	**  10HD      Half      Off       None      <ignored>    10
+	**
+	** This ConType parameter is used for all ports of the adapter!
+	*/
+
+	if ((ConType != NULL)                &&
+		(pAC->Index < SK_MAX_CARD_PARAM) &&
+		(ConType[pAC->Index] != NULL) ) {
+
+		/* Check chipset family */
+		if ((!pAC->ChipsetType) &&
+			(strcmp(ConType[pAC->Index],"Auto")!=0) &&
+			(strcmp(ConType[pAC->Index],"")!=0)) {
+			/* Set the speed parameter back */
+			printk("sk98lin: Illegal value \"%s\" "
+				"for ConType."
+				" Using Auto.\n",
+				ConType[pAC->Index]);
+
+			ConType[pAC->Index] = "Auto";
+		}
+
+		if ((pAC->ChipsetType) &&
+			(pAC->GIni.GICopperType != SK_TRUE) &&
+			(strcmp(ConType[pAC->Index],"") != 0) &&
+			(strcmp(ConType[pAC->Index],"1000FD") != 0)) {
+			/* Set the speed parameter back */
+			printk("sk98lin: Illegal value \"%s\" "
+				"for ConType."
+				" Using Auto.\n",
+				ConType[pAC->Index]);
+			ConType[pAC->Index] = "Auto";
+		}
+
+		if (strcmp(ConType[pAC->Index],"")==0) {
+			/* No ConType defined */
+		} else if (strcmp(ConType[pAC->Index],"Auto")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_ON, SKL_DC_BOTH);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_AUTO;
+			}
+		} else if (strcmp(ConType[pAC->Index],"1000FD")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_OFF, SKL_DC_FULL);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_1000MBPS;
+			}
+		} else if (strcmp(ConType[pAC->Index],"100FD")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_OFF, SKL_DC_FULL);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_100MBPS;
+			}
+		} else if (strcmp(ConType[pAC->Index],"100HD")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_OFF, SKL_DC_HALF);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_100MBPS;
+			}
+		} else if (strcmp(ConType[pAC->Index],"10FD")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_OFF, SKL_DC_FULL);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_10MBPS;
+			}
+		} else if (strcmp(ConType[pAC->Index],"10HD")==0) {
+			for (Port = 0; Port < SK_MAX_MACS; Port++) {
+			pAC->LinkInfo[Port].PLinkModeConf =
+					GetLinkCapabilities(SKL_AN_OFF, SKL_DC_HALF);
+			pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_NONE;
+			pAC->LinkInfo[Port].PMSMode       = SK_MS_MODE_AUTO;
+			pAC->LinkInfo[Port].PLinkSpeed    = SK_LSPEED_10MBPS;
+			}
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for ConType\n",
+				ConType[pAC->Index]);
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetWolTypeConfiguration - read WolType configuration information
+ *
+ * Description:
+ *	This function reads per-adapter WolType configuration information from
+ *	the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetWolTypeConfiguration(
+SK_AC	*pAC)	/* pointer to the adapter context structure */
+{
+
+	/*
+	** Check merged parameter WolType.
+	**
+	** The following settings are used for a merged ConType-parameter:
+	**
+	** WolType   DupCap   AutoNeg   FlowCtrl      Role      Speed
+	** -------   ------   -------   --------   ----------   -----
+	**  Auto      Both      On      SymOrRem      Auto       Auto
+	**  100FD     Full      Off       None      <ignored>    100
+	**  100HD     Half      Off       None      <ignored>    100
+	**  10FD      Full      Off       None      <ignored>    10
+	**  10HD      Half      Off       None      <ignored>    10
+	**
+	*/
+
+	if ((WolType != NULL)                &&
+		(pAC->Index < SK_MAX_CARD_PARAM) &&
+		(WolType[pAC->Index] != NULL) ) {
+
+		/* Set the WOL parameter */
+		if (strcmp(WolType[pAC->Index],"")==0) {
+			pAC->WolSpeedType = SK_LSPEED_AUTO;
+			pAC->WolDuplexType = SK_TRUE;
+		} else if (strcmp(WolType[pAC->Index],"Auto")==0) {
+			pAC->WolSpeedType = SK_LSPEED_AUTO;
+			pAC->WolDuplexType = SK_TRUE;
+		} else if (strcmp(WolType[pAC->Index],"100FD")==0) {
+			pAC->WolSpeedType = SK_LSPEED_100MBPS;
+			pAC->WolDuplexType = SK_TRUE;
+		} else if (strcmp(WolType[pAC->Index],"100HD")==0) {
+			pAC->WolSpeedType = SK_LSPEED_100MBPS;
+			pAC->WolDuplexType = SK_FALSE;
+		} else if (strcmp(WolType[pAC->Index],"10FD")==0) {
+			pAC->WolSpeedType = SK_LSPEED_10MBPS;
+			pAC->WolDuplexType = SK_TRUE;
+		} else if (strcmp(WolType[pAC->Index],"10HD")==0) {
+			pAC->WolSpeedType = SK_LSPEED_10MBPS;
+			pAC->WolDuplexType = SK_FALSE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for WolType\n",
+				WolType[pAC->Index]);
+			pAC->WolSpeedType = SK_LSPEED_AUTO;
+			pAC->WolDuplexType = SK_TRUE;
+
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetSpeedConfiguration - read Speed configuration information
+ *
+ * Description:
+ *	This function reads per-adapter speed configuration information from
+ *	the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetSpeedConfiguration (
+SK_AC	*pAC,		/* pointer to the adapter context structure */
+SK_I32	Port,		/* Port number */
+char	*ParamName,	/* Parameter name */
+char	*ParamValue)	/* Parameter value */
+{
+
+	/*
+	** Parse any parameter settings for port
+	** a) any LinkSpeed stated?
+	*/
+	pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_AUTO;
+	if (ParamValue != NULL && pAC->Index<SK_MAX_CARD_PARAM) {
+		if (strcmp(ParamValue,"")==0) {
+			/* Not defined */
+		} else if (strcmp(ParamValue,"Auto")==0) {
+			pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_AUTO;
+		} else if (strcmp(ParamValue,"10")==0) {
+			pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_10MBPS;
+		} else if (strcmp(ParamValue,"100")==0) {
+			pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_100MBPS;
+		} else if (strcmp(ParamValue,"1000")==0) {
+			if ((pAC->PciDev->vendor == 0x11ab ) &&
+				((pAC->PciDev->device == 0x4350) ||
+				 (pAC->PciDev->device == 0x4354))) {
+				pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_100MBPS;
+				printk("sk98lin: Illegal value \"%s\" for %s.\n"
+					"Gigabit speed not possible with this chip revision!",
+					ParamValue, ParamName);
+			} else {
+				pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_1000MBPS;
+			}
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for %s\n",
+			ParamValue, ParamName);
+		}
+	} else {
+		if ((pAC->PciDev->vendor == 0x11ab ) &&
+			((pAC->PciDev->device == 0x4350) ||
+			 (pAC->PciDev->device == 0x4354))) {
+			/* Gigabit speed not supported
+			 * Swith to speed 100
+			 */
+			pAC->LinkInfo[Port].PLinkSpeed = SK_LSPEED_100MBPS;
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetLinkModeCapabilities - read link mode capabilities
+ *
+ * Description:
+ *	This function reads per-adapter link capabilities information from
+ *	the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetLinkModeCapabilities (
+SK_AC	*pAC,			/* pointer to the adapter context structure */
+SK_I32	Port,			/* Port number */
+char	*AutoNegParamName,	/* AutoNeg Parameter name */
+char	*AutoNegParamValue,	/* AutoNeg Parameter value */
+char	*DupCapParamName,	/* DupCap Parameter name */
+char	*DupCapParamValue)	/* DupCap Parameter value */
+{
+	SK_BOOL		AutoSet;
+	SK_BOOL		DupSet;
+	int		AutoNeg	= 1;	/* autoneg off (0) or on (1) */
+	int		DuplexCap = 0;	/* 0=both,1=full,2=half */
+
+/*
+ *	The two parameters AutoNeg. and DuplexCap. map to one configuration
+ *	parameter. The mapping is described by this table:
+ *	DuplexCap ->	|	both	|	full	|	half	|
+ *	AutoNeg		|		|		|		|
+ *	-----------------------------------------------------------------
+ *	Off		|    illegal	|	Full	|	Half	|
+ *	-----------------------------------------------------------------
+ *	On		|   AutoBoth	|   AutoFull	|   AutoHalf	|
+ *	-----------------------------------------------------------------
+ *	Sense		|   AutoSense	|   AutoSense	|   AutoSense	|
+ */
+
+
+	/* Set the default value */
+	pAC->LinkInfo[Port].PLinkModeConf =
+		GetLinkCapabilities(SKL_AN_ON, SKL_DC_BOTH);
+
+	/*
+	** Any Autonegotiation and DuplexCapabilities set?
+	** Please note that both belong together...
+	*/
+	AutoNeg = SKL_AN_ON;
+	AutoSet = SK_FALSE;
+	if (AutoNegParamValue != NULL && pAC->Index<SK_MAX_CARD_PARAM) {
+		AutoSet = SK_TRUE;
+		if (strcmp(AutoNegParamValue,"")==0) {
+			AutoSet = SK_FALSE;
+		} else if (strcmp(AutoNegParamValue,"On")==0) {
+			AutoNeg = SKL_AN_ON;
+		} else if (strcmp(AutoNegParamValue,"Off")==0) {
+			AutoNeg = SKL_AN_OFF;
+		} else if (strcmp(AutoNegParamValue,"Sense")==0) {
+			AutoNeg = SKL_AN_SENS;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for %s\n",
+			AutoNegParamValue, AutoNegParamName);
+		}
+	}
+
+	DuplexCap = SKL_DC_BOTH;
+	DupSet    = SK_FALSE;
+	if (DupCapParamValue != NULL && pAC->Index<SK_MAX_CARD_PARAM) {
+		DupSet = SK_TRUE;
+		if (strcmp(DupCapParamValue,"")==0) {
+			DupSet = SK_FALSE;
+		} else if (strcmp(DupCapParamValue,"Both")==0) {
+			DuplexCap = SKL_DC_BOTH;
+		} else if (strcmp(DupCapParamValue,"Full")==0) {
+			DuplexCap = SKL_DC_FULL;
+		} else if (strcmp(DupCapParamValue,"Half")==0) {
+			DuplexCap = SKL_DC_HALF;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for %s\n",
+			DupCapParamValue, DupCapParamName);
+		}
+	}
+
+	/*
+	** Check for illegal combinations
+	*/
+	if ((pAC->LinkInfo[Port].PLinkSpeed == SK_LSPEED_1000MBPS) &&
+		((DuplexCap == SK_LMODE_STAT_AUTOHALF) ||
+		(DuplexCap == SK_LMODE_STAT_HALF)) &&
+		(pAC->ChipsetType)) {
+			printk("sk98lin: Half Duplex not possible with Gigabit speed!\n"
+					"    Using Full Duplex.\n");
+				DuplexCap = SKL_DC_FULL;
+	}
+
+	if ( AutoSet && AutoNeg==SKL_AN_SENS && DupSet) {
+		printk("sk98lin, Port A: DuplexCapabilities"
+			" ignored using Sense mode\n");
+	}
+
+	if (AutoSet && AutoNeg==SKL_AN_OFF &&
+		DupSet && DuplexCap==SKL_DC_BOTH){
+		printk("sk98lin: Port A: Illegal combination"
+			" of values AutoNeg. and DuplexCap.\n    Using "
+			"Full Duplex\n");
+		DuplexCap = SKL_DC_FULL;
+	}
+
+	if (AutoSet && AutoNeg==SKL_AN_OFF && !DupSet) {
+		DuplexCap = SKL_DC_FULL;
+	}
+
+	if (!AutoSet && DupSet) {
+		AutoNeg = SKL_AN_ON;
+	}
+
+
+	pAC->LinkInfo[Port].PAutoNeg = AutoNeg;
+	pAC->LinkInfo[Port].PDuplexCap = DuplexCap;
+
+	/*
+	** set the desired mode
+	*/
+	if (AutoSet || DupSet) {
+		pAC->LinkInfo[Port].PLinkModeConf =
+				GetLinkCapabilities(AutoNeg, DuplexCap);
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetFlowControlConfiguration - read the flow control configuration
+ *
+ * Description:
+ *	This function reads per-adapter flow control configuration information
+ *	from the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetFlowControlConfiguration (
+SK_AC	*pAC,		/* pointer to the adapter context structure */
+SK_I32	Port,		/* Port number */
+char	*ParamName,	/* Parameter name */
+char	*ParamValue)	/* Parameter value */
+{
+	int	FlowCtrl = SK_FLOW_MODE_SYM_OR_REM;	/* FlowControl  */
+	SK_BOOL IsFlowCtrlDefined	= SK_TRUE;
+
+	/* Set the default value */
+	pAC->LinkInfo[Port].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
+
+	/*
+	** Any Flowcontrol-parameter set?
+	*/
+	if (ParamValue != NULL && pAC->Index<SK_MAX_CARD_PARAM) {
+		if (strcmp(ParamValue,"") == 0) {
+			/* Not defined */
+			IsFlowCtrlDefined = SK_FALSE;
+		} else if (strcmp(ParamValue,"SymOrRem") == 0) {
+			FlowCtrl = SK_FLOW_MODE_SYM_OR_REM;
+		} else if (strcmp(ParamValue,"Sym")==0) {
+			FlowCtrl = SK_FLOW_MODE_SYMMETRIC;
+		} else if (strcmp(ParamValue,"LocSend")==0) {
+			FlowCtrl = SK_FLOW_MODE_LOC_SEND;
+		} else if (strcmp(ParamValue,"None")==0) {
+			FlowCtrl = SK_FLOW_MODE_NONE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for %s\n",
+			ParamValue, ParamName);
+			IsFlowCtrlDefined = SK_FALSE;
+		}
+	} else {
+			IsFlowCtrlDefined = SK_FALSE;
+	}
+
+	/* Check the values */
+	if (IsFlowCtrlDefined) {
+		if ((pAC->LinkInfo[Port].PAutoNeg == SKL_AN_OFF) &&
+		(FlowCtrl != SK_FLOW_MODE_NONE)) {
+		printk("sk98lin: %s: FlowControl"
+			" impossible without AutoNegotiation,"
+			" disabled\n", ParamName);
+		FlowCtrl = SK_FLOW_MODE_NONE;
+		}
+		pAC->LinkInfo[Port].PFlowCtrlMode = FlowCtrl;
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetRoleConfiguration - read the role configuration
+ *
+ * Description:
+ *	This function reads per-adapter role configuration information
+ *	from the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetRoleConfiguration (
+SK_AC	*pAC,		/* pointer to the adapter context structure */
+SK_I32	Port,		/* Port number */
+char	*ParamName,	/* Parameter name */
+char	*ParamValue)	/* Parameter value */
+{
+
+	/* Set the default value */
+	pAC->LinkInfo[Port].PMSMode = SK_MS_MODE_AUTO;
+
+	/*
+	** What is with the RoleParameter?
+	*/
+	if (ParamValue != NULL && pAC->Index<SK_MAX_CARD_PARAM) {
+		if (strcmp(ParamValue,"")==0) {
+		} else if (strcmp(ParamValue,"Auto")==0) {
+			pAC->LinkInfo[Port].PMSMode = SK_MS_MODE_AUTO;
+		} else if (strcmp(ParamValue,"Master")==0) {
+			pAC->LinkInfo[Port].PMSMode = SK_MS_MODE_MASTER;
+		} else if (strcmp(ParamValue,"Slave")==0) {
+			pAC->LinkInfo[Port].PMSMode = SK_MS_MODE_SLAVE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for %s\n",
+			ParamValue, ParamName);
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	GetInterruptModConfiguration - read the IntMod configuration
+ *
+ * Description:
+ *	This function reads per-adapter interrupt moderation configuration
+ *	information from the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetInterruptModConfiguration (
+SK_AC	*pAC)		/* pointer to the adapter context structure */
+{
+	int IrqModMaskOffset	= 6; /* all ints moderated=default */
+	SK_U32	IrqModMask[7][2] =
+		{ { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS  },
+		  { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS  },
+		  { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
+		  { IRQ_MASK_SP_RX   , Y2_IRQ_MASK     },
+		  { IRQ_MASK_TX_RX   , Y2_DRIVER_IRQS  },
+		  { IRQ_MASK_SP_TX   , Y2_IRQ_MASK     },
+		  { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK     } };
+
+	/*
+	** Check the interrupt moderation parameters
+	*/
+	pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
+	if (Moderation[pAC->Index] != NULL) {
+		if (strcmp(Moderation[pAC->Index], "") == 0) {
+			pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
+		} else if (strcmp(Moderation[pAC->Index], "Static") == 0) {
+			pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
+		} else if (strcmp(Moderation[pAC->Index], "Dynamic") == 0) {
+			pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_DYNAMIC;
+		} else if (strcmp(Moderation[pAC->Index], "None") == 0) {
+			pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
+				"      Disable interrupt moderation.\n",
+				Moderation[pAC->Index]);
+		}
+	} else {
+/* Set interrupt moderation if wished */
+#ifdef CONFIG_SK98LIN_STATINT
+		pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
+#endif
+	}
+
+	if (ModerationMask[pAC->Index] != NULL) {
+		if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
+			IrqModMaskOffset = 0;
+		} else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
+			IrqModMaskOffset = 1;
+		} else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
+			IrqModMaskOffset = 2;
+		} else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
+			IrqModMaskOffset = 3;
+		} else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
+			IrqModMaskOffset = 3;
+		} else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
+			IrqModMaskOffset = 4;
+		} else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
+			IrqModMaskOffset = 4;
+		} else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
+			IrqModMaskOffset = 5;
+		} else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
+			IrqModMaskOffset = 5;
+		} else { /* some rubbish stated */
+			// IrqModMaskOffset = 6; ->has been initialized
+			// already at the begin of this function...
+		}
+	}
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
+	} else {
+		pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
+	}
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
+	} else {
+		pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
+	}
+	if (IntsPerSec[pAC->Index] != 0) {
+		if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
+			(IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
+			printk("sk98lin: Illegal value \"%d\" for IntsPerSec. (Range: %d - %d)\n"
+				"      Using default value of %i.\n",
+				IntsPerSec[pAC->Index],
+				C_INT_MOD_IPS_LOWER_RANGE,
+				C_INT_MOD_IPS_UPPER_RANGE,
+				pAC->DynIrqModInfo.MaxModIntsPerSec);
+		} else {
+			pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
+		}
+	}
+
+	/*
+	** Evaluate upper and lower moderation threshold
+	*/
+	pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
+		pAC->DynIrqModInfo.MaxModIntsPerSec +
+		(pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
+
+	pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
+		pAC->DynIrqModInfo.MaxModIntsPerSec -
+		(pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
+
+	pAC->DynIrqModInfo.DynIrqModSampleInterval =
+		SK_DRV_MODERATION_TIMER_LENGTH;
+}
+
+/*****************************************************************************
+ *
+ * 	GetMiscConfiguration - read the misc configuration
+ *
+ * Description:
+ *	This function reads per-adapter misc configuration information
+ *	from the options provided on the command line.
+ *
+ * Returns:
+ *	none
+ */
+static void GetMiscConfiguration (
+SK_AC	*pAC)		/* pointer to the adapter context structure */
+{
+	pAC->LinkInfo[0].RSS = SK_FALSE;
+	pAC->LinkInfo[1].RSS = SK_FALSE;
+
+#ifdef USE_SK_RSS_SUPPORT
+	/*
+	 * Check the RSS parameter configuration
+	 */
+	if (RSS[pAC->Index] != NULL) {
+		if (strcmp(RSS[pAC->Index], "On") == 0) {
+			pAC->LinkInfo[0].RSS = SK_TRUE;
+			pAC->LinkInfo[1].RSS = SK_TRUE;
+		} else if (strcmp(RSS[pAC->Index], "Off") == 0) {
+			pAC->LinkInfo[0].RSS = SK_FALSE;
+			pAC->LinkInfo[1].RSS = SK_FALSE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for RSS.\n"
+				"      Disable Receive-Side Scaling.\n",
+				RSS[pAC->Index]);
+		}
+	}
+#endif
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	/*
+	 * Check the SDK queue handling
+	 */
+	pAC->SdkQH = 0;
+	if (SdkQH[pAC->Index] != NULL) {
+		if (strcmp(SdkQH[pAC->Index], "On") == 0) {
+			pAC->SdkQH = 1;
+		} else if (strcmp(SdkQH[pAC->Index], "Off") == 0) {
+			pAC->SdkQH = 0;
+		} else if (strcmp(SdkQH[pAC->Index], "1") == 0) {
+			pAC->SdkQH = 1;
+		} else if (strcmp(SdkQH[pAC->Index], "0") == 0) {
+			pAC->SdkQH = 0;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for SdkQH.\n"
+				"      Disable SDK queue handling.\n",
+				SdkQH[pAC->Index]);
+		}
+	}
+#endif
+
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+	/*
+	** Check the LinkMaintenance parameter
+	*/
+	pAC->LinkInfo[0].PLinkMaintenance = SK_TRUE;
+	pAC->LinkInfo[1].PLinkMaintenance = SK_FALSE;
+
+	if (LinkMaintenance[pAC->Index] != NULL) {
+		if (strcmp(LinkMaintenance[pAC->Index], "On") == 0) {
+			pAC->LinkInfo[0].PLinkMaintenance = SK_TRUE;
+		} else if (strcmp(LinkMaintenance[pAC->Index], "Off") == 0) {
+			pAC->LinkInfo[0].PLinkMaintenance = SK_FALSE;
+		} else {
+			printk("sk98lin: Illegal value \"%s\" for LinkMaintenance.\n"
+				"      Enable LinkMaintenance.\n",
+				LinkMaintenance[pAC->Index]);
+		}
+	}
+#endif
+
+	/* Evaluate settings for both ports */
+	pAC->ActivePort = 0;
+	pAC->RlmtNets = 1;
+
+	if (pAC->GIni.GIMacsFound == 2) {
+		pAC->RlmtNets = 2;
+	}
+
+	/*
+	** Check the TxModeration parameters
+	*/
+	pAC->TxModeration = 0;
+	if (TxModeration[pAC->Index] != 0) {
+		if (!HW_IS_EXT_LE_FORMAT(pAC)) {
+			printk("sk98lin: Illegal value for TxModeration. "
+				"Not a Yukon 2 card\n    Disable tx moderation.\n");
+
+		} else if ((TxModeration[pAC->Index] < 1) ||
+			(TxModeration[pAC->Index] > C_TX_INT_MOD_UPPER_RANGE)) {
+			printk("sk98lin: Illegal value \"%d\" for TxModeration. (Range: 1 - %d)\n"
+				"      Disable tx moderation.\n",
+				TxModeration[pAC->Index],
+				C_TX_INT_MOD_UPPER_RANGE);
+		} else {
+			pAC->TxModeration = TxModeration[pAC->Index];
+		}
+	}
+
+	/*
+	** Check the LowLatency parameters
+	*/
+	pAC->LowLatency = SK_FALSE;
+	if (LowLatency[pAC->Index] != NULL) {
+		if (strcmp(LowLatency[pAC->Index], "On") == 0) {
+			pAC->LowLatency = SK_TRUE;
+		}
+	}
+
+	/*
+	** Check the MsiIrq parameters
+	*/
+	pAC->MsiIrq = SK_TRUE;
+	if (MsiIrq[pAC->Index] != NULL) {
+		if (strcmp(MsiIrq[pAC->Index], "Off") == 0) {
+			pAC->MsiIrq = SK_FALSE;
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * 	ProductStr - return a adapter identification string from vpd
+ *
+ * Description:
+ *	This function reads the product name string from the vpd area
+ *	and puts it the field pAC->DeviceString.
+ *
+ * Returns: N/A
+ */
+static void ProductStr(SK_AC *pAC)
+{
+	char Default[] = "Generic Marvell Yukon chipset Ethernet device";
+	char Key[] = VPD_NAME; /* VPD productname key */
+	int StrLen = 80;       /* stringlen           */
+	unsigned long Flags;
+	int ReturnCode = 0;
+
+	spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+	if ((ReturnCode = VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) != 0) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
+			("Error reading VPD data: %d\n", ReturnCode));
+		strcpy(pAC->DeviceStr, Default);
+	}
+	spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+} /* ProductStr */
+
+/****************************************************************************/
+/* functions for common modules *********************************************/
+/****************************************************************************/
+
+/*****************************************************************************
+ *
+ *	SkOsGetTime - provide a time value
+ *
+ * Description:
+ *	This routine provides a time value. The unit is 1/HZ (defined by Linux).
+ *	It is not used for absolute time, but only for time differences.
+ *
+ *
+ * Returns:
+ *	Time value
+ */
+SK_U64 SkOsGetTime(SK_AC *pAC)
+{
+	SK_U64	PrivateJiffies;
+
+	SkOsGetTimeCurrent(pAC, &PrivateJiffies);
+
+	return PrivateJiffies;
+} /* SkOsGetTime */
+
+
+/*****************************************************************************
+ *
+ *	SkPciReadCfgDWord - read a 32 bit value from pci config space
+ *
+ * Description:
+ *	This routine reads a 32 bit value from the pci configuration
+ *	space.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciReadCfgDWord(
+SK_AC *pAC,		/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U32 *pVal)		/* pointer to store the read value */
+{
+	pci_read_config_dword(pAC->PciDev, PciAddr, pVal);
+	return(0);
+} /* SkPciReadCfgDWord */
+
+
+/*****************************************************************************
+ *
+ *	SkPciReadCfgWord - read a 16 bit value from pci config space
+ *
+ * Description:
+ *	This routine reads a 16 bit value from the pci configuration
+ *	space.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciReadCfgWord(
+SK_AC *pAC,	/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U16 *pVal)		/* pointer to store the read value */
+{
+	pci_read_config_word(pAC->PciDev, PciAddr, pVal);
+	return(0);
+} /* SkPciReadCfgWord */
+
+
+/*****************************************************************************
+ *
+ *	SkPciReadCfgByte - read a 8 bit value from pci config space
+ *
+ * Description:
+ *	This routine reads a 8 bit value from the pci configuration
+ *	space.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciReadCfgByte(
+SK_AC *pAC,	/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U8 *pVal)		/* pointer to store the read value */
+{
+	pci_read_config_byte(pAC->PciDev, PciAddr, pVal);
+	return(0);
+} /* SkPciReadCfgByte */
+
+
+/*****************************************************************************
+ *
+ *	SkPciWriteCfgDWord - write a 32 bit value to pci config space
+ *
+ * Description:
+ *	This routine writes a 32 bit value to the pci configuration
+ *	space.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciWriteCfgDWord(
+SK_AC *pAC,	/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U32 Val)		/* pointer to store the read value */
+{
+	pci_write_config_dword(pAC->PciDev, PciAddr, Val);
+	return(0);
+} /* SkPciWriteCfgDWord */
+
+
+/*****************************************************************************
+ *
+ *	SkPciWriteCfgWord - write a 16 bit value to pci config space
+ *
+ * Description:
+ *	This routine writes a 16 bit value to the pci configuration
+ *	space. The flag PciConfigUp indicates whether the config space
+ *	is accesible or must be set up first.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciWriteCfgWord(
+SK_AC *pAC,	/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U16 Val)		/* pointer to store the read value */
+{
+	pci_write_config_word(pAC->PciDev, PciAddr, Val);
+	return(0);
+} /* SkPciWriteCfgWord */
+
+
+/*****************************************************************************
+ *
+ *	SkPciWriteCfgWord - write a 8 bit value to pci config space
+ *
+ * Description:
+ *	This routine writes a 8 bit value to the pci configuration
+ *	space. The flag PciConfigUp indicates whether the config space
+ *	is accesible or must be set up first.
+ *
+ * Returns:
+ *	0 - indicate everything worked ok.
+ *	!= 0 - error indication
+ */
+int SkPciWriteCfgByte(
+SK_AC *pAC,	/* Adapter Control structure pointer */
+int PciAddr,		/* PCI register address */
+SK_U8 Val)		/* pointer to store the read value */
+{
+	pci_write_config_byte(pAC->PciDev, PciAddr, Val);
+	return(0);
+} /* SkPciWriteCfgByte */
+
+
+/*****************************************************************************
+ *
+ *	SkDrvEvent - handle driver events
+ *
+ * Description:
+ *	This function handles events from all modules directed to the driver
+ *
+ * Context:
+ *	Is called under protection of slow path lock.
+ *
+ * Returns:
+ *	0 if everything ok
+ *	< 0  on error
+ *
+ */
+int SkDrvEvent(
+SK_AC     *pAC,    /* pointer to adapter context */
+SK_IOC     IoC,    /* IO control context         */
+SK_U32     Event,  /* event-id                   */
+SK_EVPARA  Param)  /* event-parameter            */
+{
+	unsigned long    Flags;
+	int              FromPort;    /* the port from which we switch away */
+	int              Stat = 0;
+	DEV_NET          *pNet = NULL;
+#ifdef CONFIG_SK98LIN_NAPI
+	int              WorkToDo = 1; /* min(*budget, dev->quota); */
+	int              WorkDone = 0;
+#endif
+	SK_EVPARA        Para;
+
+	switch (Event) {
+	case SK_DRV_PORT_FAIL:
+		FromPort = Param.Para32[0];
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("PORT FAIL EVENT, Port: %d\n", FromPort));
+		if (FromPort == 0) {
+			printk("%s: Port A failed.\n", pAC->dev[0]->name);
+		} else {
+			printk("%s: Port B failed.\n", pAC->dev[1]->name);
+		}
+		break;
+	case SK_DRV_PORT_RESET:
+		FromPort = Param.Para32[0];
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("PORT RESET EVENT, Port: %d ", FromPort));
+		SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
+					FromPort, SK_FALSE);
+		spin_lock_irqsave(
+			&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+			Flags);
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
+		} else {
+			SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
+		}
+		pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
+		spin_unlock_irqrestore(
+			&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+			Flags);
+
+		if (!CHIP_ID_YUKON_2(pAC)) {
+#ifdef CONFIG_SK98LIN_NAPI
+			WorkToDo = 1;
+			ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
+#else
+			ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
+#endif
+			ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
+		}
+		spin_lock_irqsave(
+			&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+			Flags);
+
+#ifdef USE_TIST_FOR_RESET
+		if (!HW_IS_EXT_LE_FORMAT(pAC) && pAC->GIni.GIYukon2) {
+#ifdef Y2_RECOVERY
+			/* for Yukon II we want to have tist enabled all the time */
+			if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
+				SK_Y2_TIST_LE_ENA(pAC->IoBase);
+			}
+#else
+			/* make sure that we do not accept any status LEs from now on */
+			if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
+#endif
+				/* port already waiting for tist */
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+					("Port %c is now waiting for specific Tist\n",
+					'A' +  FromPort));
+				SK_SET_WAIT_BIT_FOR_PORT(
+					pAC,
+					SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
+					FromPort);
+				/* get current timestamp */
+				Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
+				pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
+#ifndef Y2_RECOVERY
+			} else {
+				/* nobody is waiting yet */
+				SK_SET_WAIT_BIT_FOR_PORT(
+					pAC,
+					SK_PSTATE_WAITING_FOR_ANY_TIST,
+					FromPort);
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+					("Port %c is now waiting for any Tist (0x%X)\n",
+					'A' +  FromPort, pAC->AdapterResetState));
+				/* start tist */
+				SK_Y2_TIST_LE_ENA(pAC-IoBase);
+			}
+#endif
+		}
+#endif
+
+#ifdef Y2_LE_CHECK
+		/* mark entries invalid */
+		pAC->LastPort = 3;
+		pAC->LastOpc = 0xFF;
+#endif
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2PortStart(pAC, IoC, FromPort);
+		} else {
+			if (SkGeInitPort(pAC, IoC, FromPort)) {
+				if (FromPort == 0) {
+					printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
+				} else {
+					printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
+				}
+			}
+			SkAddrMcUpdate(pAC,IoC, FromPort);
+			PortReInitBmu(pAC, FromPort);
+			SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
+			CLEAR_AND_START_RX(FromPort);
+		}
+		spin_unlock_irqrestore(
+			&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+			Flags);
+		break;
+	case SK_DRV_LINK_UP:	/* From SIRQ. */
+		spin_lock_irqsave(&pAC->InitLock, Flags);
+		FromPort = Param.Para32[0];
+
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("LINK UP EVENT, Port: %d ", FromPort));
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+#ifdef MV_INCLUDE_FW_SDK_LINK_MAINTENANCE
+		FwCheckLinkState(pAC, pAC->IoBase, FromPort, &(pAC->DriverLinkStat));
+#endif
+#endif
+		/* MAC update */
+		SkAddrMcUpdate(pAC, IoC, FromPort);
+		if (pAC->dev[FromPort]->flags & IFF_PROMISC) {
+			SkAddrPromiscuousChange(pAC, IoC, FromPort,
+				SK_PROM_MODE_LLC);
+		} else if (pAC->dev[FromPort]->flags & IFF_ALLMULTI) {
+			SkAddrPromiscuousChange(pAC, IoC, FromPort,
+				SK_PROM_MODE_ALL_MC);
+		}
+
+		Para.Para32[0] = FromPort;
+		Para.Para32[1] = 0;
+		SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_RLMT_ACTIVE_UP, Para);
+
+		if (DoPrintInterfaceChange) {
+			printk("%s: network connection up using port %c\n",
+				pAC->dev[FromPort]->name, 'A'+FromPort);
+
+			if (pAC->AllocFlag & SK_ALLOC_MSI) {
+				printk("    interrupt src:   MSI\n");
+			} else {
+				printk("    interrupt src:   INTx\n");
+			}
+
+			Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
+			if (Stat == SK_LSPEED_STAT_10MBPS) {
+				printk("    speed:           10\n");
+			} else if (Stat == SK_LSPEED_STAT_100MBPS) {
+				printk("    speed:           100\n");
+			} else if (Stat == SK_LSPEED_STAT_1000MBPS) {
+				printk("    speed:           1000\n");
+			} else {
+				printk("    speed:           unknown\n");
+			}
+
+			Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
+			if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
+			    (Stat == SK_LMODE_STAT_AUTOFULL)) {
+				printk("    autonegotiation: yes\n");
+			} else {
+				printk("    autonegotiation: no\n");
+			}
+
+			if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
+			    (Stat == SK_LMODE_STAT_HALF)) {
+				printk("    duplex mode:     half\n");
+			} else {
+				printk("    duplex mode:     full\n");
+			}
+
+			Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
+			if (Stat == SK_FLOW_STAT_REM_SEND ) {
+				printk("    flowctrl:        remote send\n");
+			} else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
+				printk("    flowctrl:        local send\n");
+			} else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
+				printk("    flowctrl:        symmetric\n");
+			} else {
+				printk("    flowctrl:        none\n");
+			}
+
+			if ((pAC->GIni.GICopperType == SK_TRUE) &&
+				(pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
+				SK_LSPEED_STAT_1000MBPS)) {
+				Stat = pAC->GIni.GP[FromPort].PMSStatus;
+				if (Stat == SK_MS_STAT_MASTER ) {
+					printk("    role:            master\n");
+				} else if (Stat == SK_MS_STAT_SLAVE ) {
+					printk("    role:            slave\n");
+				} else {
+					printk("    role:            ???\n");
+				}
+			}
+
+			/* Display interrupt moderation informations */
+			if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
+				printk("    irq moderation:  static (%d ints/sec)\n",
+					pAC->DynIrqModInfo.MaxModIntsPerSec);
+			} else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
+				printk("    irq moderation:  dynamic (%d ints/sec)\n",
+					pAC->DynIrqModInfo.MaxModIntsPerSec);
+			}
+
+#ifdef NETIF_F_TSO
+			if (CHIP_ID_YUKON_2(pAC)) {
+				if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
+					printk("    tcp offload:     enabled\n");
+				} else {
+					printk("    tcp offload:     disabled\n");
+				}
+			}
+#endif
+
+			if (pAC->dev[FromPort]->features & NETIF_F_SG) {
+				printk("    scatter-gather:  enabled\n");
+			} else {
+				printk("    scatter-gather:  disabled\n");
+			}
+
+			if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
+				printk("    tx-checksum:     enabled\n");
+			} else {
+				printk("    tx-checksum:     disabled\n");
+			}
+
+			if (pAC->RxPort[FromPort].UseRxCsum) {
+				printk("    rx-checksum:     enabled\n");
+			} else {
+				printk("    rx-checksum:     disabled\n");
+			}
+#ifdef CONFIG_SK98LIN_NAPI
+				printk("    rx-polling:      enabled\n");
+#endif
+			if (pAC->TxModeration) {
+				printk("    tx moderation:   %d\n",
+					pAC->TxModeration);
+			}
+
+			if (pAC->LowLatency) {
+				printk("    low latency:     enabled\n");
+			}
+#ifdef MV_INCLUDE_SDK_SUPPORT
+			if (pAC->FwRun) {
+				printk("    SDK:             enabled\n");
+				if (pAC->SdkQH) {
+					printk("    SDK queue  :     enabled\n");
+				}
+			}
+#endif
+
+#ifdef USE_SK_RSS_SUPPORT
+			if (pAC->dev[FromPort]->features & NETIF_F_RXHASH) {
+				printk("    RSS:             enabled\n");
+			}
+#endif
+		} else {
+			DoPrintInterfaceChange = SK_TRUE;
+		}
+
+		/* Inform the world that link protocol is up. */
+		Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
+		if ( (Stat == SK_LSPEED_STAT_10MBPS) ||
+		     (Stat == SK_LSPEED_STAT_100MBPS) ||
+		     (Stat == SK_LSPEED_STAT_1000MBPS) ) {
+
+			/* Don't enable the queue if SDK queue handling */
+#ifdef MV_INCLUDE_SDK_SUPPORT
+			if (!pAC->SdkQH) {
+				netif_wake_queue(pAC->dev[FromPort]);
+			}
+#else
+			netif_wake_queue(pAC->dev[FromPort]);
+#endif
+			netif_carrier_on(pAC->dev[FromPort]);
+
+			pAC->dev[FromPort]->flags |= IFF_RUNNING;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			pNet = (DEV_NET *) pAC->dev[FromPort]->priv;
+#else
+			pNet = netdev_priv(pAC->dev[FromPort]);
+#endif
+#ifdef Y2_RECOVERY
+			if (!timer_pending(&pNet->KernelTimer)) {
+				pNet->TimerExpired = SK_FALSE;
+				SkGeCheckTimer(pNet);
+			}
+#endif
+		}
+
+		/* Map any waiting RX buffers to HW */
+		FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
+
+		spin_unlock_irqrestore(&pAC->InitLock, Flags);
+		break;
+	case SK_DRV_LINK_DOWN:	/* From SIRQ. */
+		if (pAC->RlmtNets == 2) {
+			FromPort = Param.Para32[0];
+		}
+		else {
+			FromPort = pAC->ActivePort;
+		}
+
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("LINK DOWN EVENT "));
+
+		/* Stop queue and carrier */
+		netif_stop_queue(pAC->dev[FromPort]);
+		netif_carrier_off(pAC->dev[FromPort]);
+
+		Para.Para32[0] = FromPort;
+		Para.Para32[1] = 0;
+		SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Para);
+
+		/* Print link change */
+		if (DoPrintInterfaceChange) {
+			if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
+				printk("%s: network connection down\n",
+					pAC->dev[FromPort]->name);
+			}
+		} else {
+			DoPrintInterfaceChange = SK_TRUE;
+		}
+		pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
+		break;
+	case SK_DRV_TIMER:
+		if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
+			/* check what IRQs are to be moderated */
+			SkDimStartModerationTimer(pAC);
+			SkDimModerate(pAC);
+		} else {
+			printk("Expiration of unknown timer\n");
+		}
+		break;
+	case SK_DRV_ADAP_FAIL:
+#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("ADAPTER FAIL EVENT\n"));
+		printk("%s: Adapter failed.\n", pAC->dev[0]->name);
+		SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
+		break;
+#endif
+
+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
+	case SK_DRV_RECOVER:
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+		pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
+#else
+		pNet = netdev_priv(pAC->dev[Param.Para32[0]]);
+#endif
+
+#ifdef Y2_RECOVERY
+		/* Recover already in progress */
+		if (pNet->InRecover) {
+			break;
+		}
+#endif
+		spin_lock_irqsave(&pAC->InitLock, Flags);
+
+		netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
+#ifdef Y2_RECOVERY
+		pNet->InRecover = SK_TRUE;
+#endif
+		FromPort = Param.Para32[0];
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+			("DRV RECOVER EVENT, Port: %d ", FromPort));
+
+		/* Disable interrupts */
+		SK_OUT32(pAC->IoBase, B0_IMSK, 0);
+		SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
+
+		SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
+					FromPort, SK_FALSE);
+		spin_lock(&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock);
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
+		} else {
+			SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
+		}
+		pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
+		spin_unlock(&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock);
+
+		if (!CHIP_ID_YUKON_2(pAC)) {
+#ifdef CONFIG_SK98LIN_NAPI
+			WorkToDo = 1;
+			ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
+#else
+			ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
+#endif
+			ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
+		}
+		spin_lock(&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock);
+
+#ifdef USE_TIST_FOR_RESET
+		if (!HW_IS_EXT_LE_FORMAT(pAC) && pAC->GIni.GIYukon2) {
+#if 0
+			/* make sure that we do not accept any status LEs from now on */
+			SK_Y2_TIST_LE_ENA(pAC->IoBase);
+
+			/* get current timestamp */
+			Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
+			pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
+
+			SK_SET_WAIT_BIT_FOR_PORT(
+				pAC,
+				SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
+				FromPort);
+#endif
+			SK_SET_WAIT_BIT_FOR_PORT(
+				pAC,
+				SK_PSTATE_WAITING_FOR_ANY_TIST,
+				FromPort);
+
+			/* start tist */
+			SK_Y2_TIST_LE_ENA(pAC->IoBase);
+		}
+#endif
+
+		/* Restart Receive BMU on Yukon-2 */
+		if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
+			SkYuk2RestartRxBmu(pAC, IoC, FromPort);
+		}
+
+#ifdef Y2_LE_CHECK
+		/* mark entries invalid */
+		pAC->LastPort = 3;
+		pAC->LastOpc = 0xFF;
+#endif
+
+#endif
+		/* Restart ports but do not initialize PHY. */
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SkY2PortStart(pAC, IoC, FromPort);
+		} else {
+			if (SkGeInitPort(pAC, IoC, FromPort)) {
+				if (FromPort == 0) {
+					printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
+				} else {
+					printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
+				}
+			}
+			SkAddrMcUpdate(pAC,IoC, FromPort);
+			PortReInitBmu(pAC, FromPort);
+			SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
+			CLEAR_AND_START_RX(FromPort);
+		}
+		spin_unlock(&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock);
+
+		/* Map any waiting RX buffers to HW */
+#ifdef USE_SK_RSS_SUPPORT
+		SkSetRssSupport(pAC, FromPort);
+#endif
+		FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
+
+#ifdef Y2_RECOVERY
+		pNet->InRecover = SK_FALSE;
+#endif
+
+		/* Enable Interrupts */
+		SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
+		if (CHIP_ID_YUKON_2(pAC)) {
+			SK_OUT32(pAC->IoBase, B0_HWE_IMSK, Y2_IRQ_HWE_MASK);
+		}
+		else {
+			SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
+		}
+		netif_wake_queue(pAC->dev[FromPort]);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+		pNet = (DEV_NET *) pAC->dev[FromPort]->priv;
+#else
+		pNet = netdev_priv(pAC->dev[FromPort]);
+#endif
+#ifdef Y2_RECOVERY
+		if (!timer_pending(&pNet->KernelTimer)) {
+			pNet->TimerExpired = SK_FALSE;
+			SkGeCheckTimer(pNet);
+		}
+#endif
+		spin_unlock_irqrestore(&pAC->InitLock, Flags);
+		break;
+	default:
+		break;
+	}
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
+		("END EVENT "));
+
+	return (0);
+} /* SkDrvEvent */
+
+
+/******************************************************************************
+ *
+ *	SkLocalEventQueue()	-	add event to queue
+ *
+ * Description:
+ *	This function adds an event to the event queue and run the
+ *	SkEventDispatcher. At least Init Level 1 is required to queue events,
+ *	but will be scheduled add Init Level 2.
+ *
+ * returns:
+ *	nothing
+ */
+void SkLocalEventQueue(
+SK_AC *pAC,		/* Adapters context */
+SK_U32 Class,		/* Event Class */
+SK_U32 Event,		/* Event to be queued */
+SK_U32 Param1,		/* Event parameter 1 */
+SK_U32 Param2,		/* Event parameter 2 */
+SK_BOOL Dispatcher)	/* Dispatcher flag:
+			 *	TRUE == Call SkEventDispatcher
+			 *	FALSE == Don't execute SkEventDispatcher
+			 */
+{
+	SK_EVPARA 	EvPara;
+	EvPara.Para32[0] = Param1;
+	EvPara.Para32[1] = Param2;
+
+	/* Don't queue events if the device is not activated */
+	if(pAC->BoardLevel != SK_INIT_RUN) {
+		return;
+	}
+
+	if (Class == SKGE_PNMI) {
+		SkPnmiEvent(	pAC,
+				pAC->IoBase,
+				Event,
+				EvPara);
+	} else {
+		SkEventQueue(	pAC,
+				Class,
+				Event,
+				EvPara);
+	}
+
+	/* Run the dispatcher */
+	if (Dispatcher) {
+		SkEventDispatcher(pAC, pAC->IoBase);
+	}
+
+}
+
+/******************************************************************************
+ *
+ *	SkLocalEventQueue64()	-	add event to queue (64bit version)
+ *
+ * Description:
+ *	This function adds an event to the event queue and run the
+ *	SkEventDispatcher. At least Init Level 1 is required to queue events,
+ *	but will be scheduled add Init Level 2.
+ *
+ * returns:
+ *	nothing
+ */
+void SkLocalEventQueue64(
+SK_AC *pAC,		/* Adapters context */
+SK_U32 Class,		/* Event Class */
+SK_U32 Event,		/* Event to be queued */
+SK_U64 Param,		/* Event parameter */
+SK_BOOL Dispatcher)	/* Dispatcher flag:
+			 *	TRUE == Call SkEventDispatcher
+			 *	FALSE == Don't execute SkEventDispatcher
+			 */
+{
+	SK_EVPARA 	EvPara;
+	EvPara.Para64 = Param;
+
+	/* Don't queue events if the device is not activated */
+	if(pAC->BoardLevel != SK_INIT_RUN) {
+		return;
+	}
+
+	if (Class == SKGE_PNMI) {
+		SkPnmiEvent(	pAC,
+				pAC->IoBase,
+				Event,
+				EvPara);
+	} else {
+		SkEventQueue(	pAC,
+				Class,
+				Event,
+				EvPara);
+	}
+
+	/* Run the dispatcher */
+	if (Dispatcher) {
+		SkEventDispatcher(pAC, pAC->IoBase);
+	}
+
+}
+
+
+/*****************************************************************************
+ *
+ *	SkErrorLog - log errors
+ *
+ * Description:
+ *	This function logs errors to the system buffer and to the console
+ *
+ * Returns:
+ *	0 if everything ok
+ *	< 0  on error
+ *
+ */
+void SkErrorLog(
+SK_AC	*pAC,
+int	ErrClass,
+int	ErrNum,
+char	*pErrorMsg)
+{
+char	ClassStr[80];
+
+	switch (ErrClass) {
+	case SK_ERRCL_OTHER:
+		strcpy(ClassStr, "Other error");
+		break;
+	case SK_ERRCL_CONFIG:
+		strcpy(ClassStr, "Configuration error");
+		break;
+	case SK_ERRCL_INIT:
+		strcpy(ClassStr, "Initialization error");
+		break;
+	case SK_ERRCL_NORES:
+		strcpy(ClassStr, "Out of resources error");
+		break;
+	case SK_ERRCL_SW:
+		strcpy(ClassStr, "internal Software error");
+		break;
+	case SK_ERRCL_HW:
+		strcpy(ClassStr, "Hardware failure");
+		break;
+	case SK_ERRCL_COMM:
+		strcpy(ClassStr, "Communication error");
+		break;
+	case SK_ERRCL_INFO:
+		strcpy(ClassStr, "Information");
+		break;
+	}
+
+	if (ErrClass == SK_ERRCL_INFO) {
+		printk(KERN_INFO "%s: -- INFORMATION --\n"
+			"        Msg:  %s\n", pAC->dev[0]->name,
+			pErrorMsg);
+	} else {
+		printk(KERN_INFO "%s: -- ERROR --\n        Class:  %s\n"
+			"        Nr:  0x%x\n        Msg:  %s\n", pAC->dev[0]->name,
+			ClassStr, ErrNum, pErrorMsg);
+	}
+
+} /* SkErrorLog */
+
+/*****************************************************************************
+ *
+ *	SkDrvEnterDiagMode - handles DIAG attach request
+ *
+ * Description:
+ *	Notify the kernel to NOT access the card any longer due to DIAG
+ *	Deinitialize the Card
+ *
+ * Returns:
+ *	int
+ */
+int SkDrvEnterDiagMode(
+SK_AC   *pAc)   /* pointer to adapter context */
+{
+	SK_AC   *pAC  = NULL;
+	DEV_NET *pNet = NULL;
+
+	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+		pNet = (DEV_NET *) pAc->dev[0]->priv;
+	#else
+		pNet = netdev_priv(pAc->dev[0]);
+#endif
+	pAC = pNet->pAC;
+
+	SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
+			sizeof(SK_PNMI_STRUCT_DATA));
+
+	pAC->DiagModeActive = DIAG_ACTIVE;
+	if (pAC->BoardLevel > SK_INIT_DATA) {
+		if (netif_running(pAC->dev[0])) {
+			pAC->WasIfUp[0] = SK_TRUE;
+			pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose      */
+			DoPrintInterfaceChange = SK_FALSE;
+			SkDrvDeInitAdapter(pAC, 0);  /* performs SkGeClose */
+		} else {
+			pAC->WasIfUp[0] = SK_FALSE;
+		}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
+				pNet = (DEV_NET *) pAc->dev[1]->priv;
+#else
+			if (pNet != netdev_priv(pAc->dev[1])) {
+				pNet = netdev_priv(pAc->dev[1]);
+#endif
+			if (netif_running(pAC->dev[1])) {
+				pAC->WasIfUp[1] = SK_TRUE;
+				pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
+				DoPrintInterfaceChange = SK_FALSE;
+				SkDrvDeInitAdapter(pAC, 1);  /* do SkGeClose  */
+			} else {
+				pAC->WasIfUp[1] = SK_FALSE;
+			}
+		}
+		pAC->BoardLevel = SK_INIT_DATA;
+	}
+	return(0);
+}
+
+/*****************************************************************************
+ *
+ *	SkDrvLeaveDiagMode - handles DIAG detach request
+ *
+ * Description:
+ *	Notify the kernel to may access the card again after use by DIAG
+ *	Initialize the Card
+ *
+ * Returns:
+ * 	int
+ */
+int SkDrvLeaveDiagMode(
+SK_AC   *pAc)   /* pointer to adapter control context */
+{
+	SK_MEMCPY(&(pAc->PnmiStruct), &(pAc->PnmiBackup),
+			sizeof(SK_PNMI_STRUCT_DATA));
+	pAc->DiagModeActive    = DIAG_NOTACTIVE;
+	pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
+	if (pAc->WasIfUp[0] == SK_TRUE) {
+		pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
+		DoPrintInterfaceChange = SK_FALSE;
+		SkDrvInitAdapter(pAc, 0);    /* first device  */
+	}
+	if (pAc->WasIfUp[1] == SK_TRUE) {
+		pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
+		DoPrintInterfaceChange = SK_FALSE;
+		SkDrvInitAdapter(pAc, 1);    /* second device */
+	}
+	return(0);
+}
+
+/*****************************************************************************
+ *
+ *	ParseDeviceNbrFromSlotName - Evaluate PCI device number
+ *
+ * Description:
+ * 	This function parses the PCI slot name information string and will
+ *	retrieve the devcie number out of it. The slot_name maintianed by
+ *	linux is in the form of '02:0a.0', whereas the first two characters
+ *	represent the bus number in hex (in the sample above this is
+ *	pci bus 0x02) and the next two characters the device number (0x0a).
+ *
+ * Returns:
+ *	SK_U32: The device number from the PCI slot name
+ */
+
+static SK_U32 ParseDeviceNbrFromSlotName(
+const char *SlotName)   /* pointer to pci slot name eg. '02:0a.0' */
+{
+	char	*CurrCharPos	= (char *) SlotName;
+	int	FirstNibble	= -1;
+	int	SecondNibble	= -1;
+	SK_U32	Result		=  0;
+
+	while (*CurrCharPos != '\0') {
+		if (*CurrCharPos == ':') {
+			while (*CurrCharPos != '.') {
+				CurrCharPos++;
+				if (	(*CurrCharPos >= '0') &&
+					(*CurrCharPos <= '9')) {
+					if (FirstNibble == -1) {
+						/* dec. value for '0' */
+						FirstNibble = *CurrCharPos - 48;
+					} else {
+						SecondNibble = *CurrCharPos - 48;
+					}
+				} else if (	(*CurrCharPos >= 'a') &&
+						(*CurrCharPos <= 'f')  ) {
+					if (FirstNibble == -1) {
+						FirstNibble = *CurrCharPos - 87;
+					} else {
+						SecondNibble = *CurrCharPos - 87;
+					}
+				} else {
+					Result = 0;
+				}
+			}
+
+			Result = FirstNibble;
+			Result = Result << 4; /* first nibble is higher one */
+			Result = Result | SecondNibble;
+		}
+		CurrCharPos++;   /* next character */
+	}
+	return (Result);
+}
+
+/****************************************************************************
+ *
+ *	SkDrvDeInitAdapter - deinitialize adapter (this function is only
+ *				called if Diag attaches to that card)
+ *
+ * Description:
+ *	Close initialized adapter.
+ *
+ * Returns:
+ *	0 - on success
+ *	error code - on error
+ */
+static int SkDrvDeInitAdapter(
+SK_AC   *pAC,		/* pointer to adapter context   */
+int      devNbr)	/* what device is to be handled */
+{
+	struct SK_NET_DEVICE *dev;
+
+	dev = pAC->dev[devNbr];
+
+	/*
+	** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
+	** or module_put() (2.6) to decrease the number of users for
+	** a device, but if a device is to be put under control of
+	** the DIAG, that count is OK already and does not need to
+	** be adapted! Hence the opposite MOD_INC_USE_COUNT or
+	** try_module_get() needs to be used again to correct that.
+	*/
+	if (!try_module_get(THIS_MODULE)) {
+		return (-1);
+	}
+
+	if (SkGeClose(dev) != 0) {
+		module_put(THIS_MODULE);
+		return (-1);
+	}
+	return (0);
+
+} /* SkDrvDeInitAdapter() */
+
+/****************************************************************************
+ *
+ *	SkDrvInitAdapter - Initialize adapter (this function is only
+ *				called if Diag deattaches from that card)
+ *
+ * Description:
+ *	Close initialized adapter.
+ *
+ * Returns:
+ *	0 - on success
+ *	error code - on error
+ */
+static int SkDrvInitAdapter(
+SK_AC   *pAC,		/* pointer to adapter context   */
+int      devNbr)	/* what device is to be handled */
+{
+	struct SK_NET_DEVICE *dev;
+
+	dev = pAC->dev[devNbr];
+
+	if (SkGeOpen(dev) != 0) {
+		return (-1);
+	} else {
+		/*
+		** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
+		** or try_module_get() (2.6) to increase the number of
+		** users for a device, but if a device was just under
+		** control of the DIAG, that count is OK already and
+		** does not need to be adapted! Hence the opposite
+		** MOD_DEC_USE_COUNT or module_put() needs to be used
+		** again to correct that.
+		*/
+		module_put(THIS_MODULE);
+	}
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	/*
+	** Use correct MTU size and indicate to kernel TX queue can be started
+	*/
+	if (pAC->FwRun && pAC->Suspended == SK_FALSE) {
+		if (SkGeChangeMtu(dev, dev->mtu) != 0) {
+			return (-1);
+		}
+	}
+#endif
+	return (0);
+
+} /* SkDrvInitAdapter */
+
+static int __init sk98lin_init(void)
+{
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
+	return pci_register_driver(&sk98lin_driver);
+#else
+	return pci_module_init(&sk98lin_driver);
+#endif
+}
+
+static void __exit sk98lin_cleanup(void)
+{
+	pci_unregister_driver(&sk98lin_driver);
+}
+
+module_init(sk98lin_init);
+module_exit(sk98lin_cleanup);
+
+
+#ifdef DEBUG
+/****************************************************************************/
+/* "debug only" section *****************************************************/
+/****************************************************************************/
+
+/*****************************************************************************
+ *
+ *	DumpMsg - print a frame
+ *
+ * Description:
+ *	This function prints frames to the system logfile/to the console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpMsg(
+struct sk_buff *skb,  /* linux' socket buffer  */
+char           *str)  /* additional msg string */
+{
+	int msglen = (skb->len > 64) ? 64 : skb->len;
+
+	if (skb == NULL) {
+		printk("DumpMsg(): NULL-Message\n");
+		return;
+	}
+
+	if (skb->data == NULL) {
+		printk("DumpMsg(): Message empty\n");
+		return;
+	}
+
+	printk("DumpMsg: PhysPage: %p\n",
+		page_address(virt_to_page(skb->data)));
+	printk("--- Begin of message from %s , len %d (from %d) ----\n",
+		str, msglen, skb->len);
+	DumpData((char *)skb->data, msglen);
+	printk("------- End of message ---------\n");
+} /* DumpMsg */
+
+/*****************************************************************************
+ *
+ *	DumpData - print a data area
+ *
+ * Description:
+ *	This function prints a area of data to the system logfile/to the
+ *	console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpData(
+char  *p,     /* pointer to area containing the data */
+int    size)  /* the size of that data area in bytes */
+{
+	register int  i;
+	int           haddr = 0, addr = 0;
+	char          hex_buffer[180] = { '\0' };
+	char          asc_buffer[180] = { '\0' };
+	char          HEXCHAR[] = "0123456789ABCDEF";
+
+	for (i=0; i < size; ) {
+		if (*p >= '0' && *p <='z') {
+			asc_buffer[addr] = *p;
+		} else {
+			asc_buffer[addr] = '.';
+		}
+		addr++;
+		asc_buffer[addr] = 0;
+		hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[*p & 0x0f];
+		haddr++;
+		hex_buffer[haddr] = ' ';
+		haddr++;
+		hex_buffer[haddr] = 0;
+		p++;
+		i++;
+		if (i%16 == 0) {
+			printk("%s  %s\n", hex_buffer, asc_buffer);
+			addr = 0;
+			haddr = 0;
+		}
+	}
+} /* DumpData */
+
+
+/*****************************************************************************
+ *
+ *	DumpLong - print a data area as long values
+ *
+ * Description:
+ *	This function prints a long variable to the system logfile/to the
+ *	console.
+ *
+ * Returns: N/A
+ *
+ */
+static void DumpLong(
+char  *pc,    /* location of the variable to print */
+int    size)  /* how large is the variable?        */
+{
+	register int   i;
+	int            haddr = 0;
+	char           hex_buffer[180] = { '\0' };
+	char           HEXCHAR[] = "0123456789ABCDEF";
+	long          *p = (long*) pc;
+	int            l;
+
+	for (i=0; i < size; ) {
+		l = (long) *p;
+		hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 24) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 20) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 16) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 12) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 8) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[(l >> 4) & 0xf];
+		haddr++;
+		hex_buffer[haddr] = HEXCHAR[l & 0x0f];
+		haddr++;
+		hex_buffer[haddr] = ' ';
+		haddr++;
+		hex_buffer[haddr] = 0;
+		p++;
+		i++;
+		if (i%8 == 0) {
+			printk("%4x %s\n", (i-8)*4, hex_buffer);
+			haddr = 0;
+		}
+	}
+	printk("------------------------\n");
+} /* DumpLong */
+
+#endif
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
+
diff -ruN linux/drivers/net/sk98lin/skgehwt.c linux-new/drivers/net/sk98lin/skgehwt.c
--- linux/drivers/net/sk98lin/skgehwt.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgehwt.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,240 @@
+/******************************************************************************
+ *
+ * Name:	skgehwt.c
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Hardware Timer
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgehwt.c,v $
+ *	Revision 2.4  2007/07/31 13:22:14  rschmidt
+ *	Editorial changes.
+ *	
+ *	Revision 2.3  2005/12/14 16:11:02  ibrueder
+ *	Added copyright header flags.
+ *
+ *	Revision 2.2  2004/05/28 13:39:04  rschmidt
+ *	Corrected define SK_HWT_MAX, all HW-timer events were reduced to 1 sec.
+ *	Changed para Time in SkHwtStart() to units of  1 uS (16 uS before).
+ *	Adapted for Yukon-2 timer IRQ in SkHwtRead().
+ *	Editorial changes.
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1.
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch.
+ *
+ *	Revision 1.15  2003/09/16 13:41:23  rschmidt
+ *	Added (C) Marvell to SysKonnectFileId
+ *	Editorial changes.
+ *
+ *	Revision 1.14  2003/05/13 18:01:58  mkarl
+ *	Editorial changes.
+ *
+ *	Revision 1.13  1999/11/22 13:31:12  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.12  1998/10/15 15:11:34  gklug
+ *	fix: ID_sccs to SysKonnectFileId
+ *
+ *	Revision 1.11  1998/10/08 15:27:51  gklug
+ *	chg: correction factor is host clock dependent
+ *
+ *	Revision 1.10  1998/09/15 14:18:31  cgoos
+ *	Changed more BOOLEANs to SK_xxx
+ *
+ *	Revision 1.9  1998/09/15 14:16:06  cgoos
+ *	Changed line 107: FALSE to SK_FALSE
+ *
+ *	Revision 1.8  1998/08/24 13:04:44  gklug
+ *	fix: typo
+ *
+ *	Revision 1.7  1998/08/19 09:50:49  gklug
+ *	fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ *	Revision 1.6  1998/08/17 09:59:02  gklug
+ *	fix: typos
+ *
+ *	Revision 1.5  1998/08/14 07:09:10  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.4  1998/08/10 14:14:52  gklug
+ *	rmv: unnecessary SK_ADDR macro
+ *
+ *	Revision 1.3  1998/08/07 12:53:44  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.2  1998/08/07 09:19:29  gklug
+ *	adapt functions to the C coding conventions
+ *	rmv unnecessary functions.
+ *
+ *	Revision 1.1  1998/08/05 11:28:36  gklug
+ *	first version: adapted from SMT/FDDI
+ *
+ ******************************************************************************/
+
+/*
+ *	Event queue and dispatcher
+ */
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/schedule/V3/skgehwt.c#5 $ (C) Marvell.";
+#endif
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#include "h/skdrv2nd.h"		/* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+ *   Hardware Timer function queue management.
+ */
+intro()
+{}
+#endif
+
+/*
+ * Prototypes of local functions.
+ */
+#define SK_HWT_MAX	65000UL * 160		/* ca. 10 sec. */
+
+/* correction factor (62.5/100 = 5/8) */
+#define SK_HWT_FAC	(5 * (SK_U32)pAC->GIni.GIHstClkFact / 8)
+
+/*
+ * Initialize hardware timer.
+ *
+ * Must be called during init level 1.
+ */
+void SkHwtInit(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	pAC->Hwt.TStart = 0 ;
+	pAC->Hwt.TStop = 0;
+	pAC->Hwt.TActive = SK_FALSE;
+
+	SkHwtStop(pAC, IoC);
+}
+
+/*
+ *
+ * Start hardware timer (clock ticks are HW-dependent).
+ *
+ */
+void SkHwtStart(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+SK_U32	Time)	/* Time in usec to load the timer */
+{
+	if (Time > SK_HWT_MAX) {
+		Time = SK_HWT_MAX;
+	}
+
+	pAC->Hwt.TStart = Time;
+	pAC->Hwt.TStop = 0L;
+
+	if (!Time) {
+		Time = 1L;
+	}
+
+	SK_OUT32(IoC, B2_TI_INI, Time * SK_HWT_FAC);
+
+	SK_OUT16(IoC, B2_TI_CTRL, TIM_START);	/* Start timer */
+
+	pAC->Hwt.TActive = SK_TRUE;
+}
+
+/*
+ * Stop hardware timer.
+ * and clear the timer IRQ
+ */
+void SkHwtStop(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SK_OUT16(IoC, B2_TI_CTRL, TIM_STOP);
+
+	SK_OUT16(IoC, B2_TI_CTRL, TIM_CLR_IRQ);
+
+	pAC->Hwt.TActive = SK_FALSE;
+}
+
+/*
+ *	Stop hardware timer and read time elapsed since last start.
+ *
+ * returns
+ *	The elapsed time since last start in units of 1 us.
+ *
+ */
+SK_U32 SkHwtRead(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SK_U32	TRead;
+	SK_U32	IStatus;
+	SK_U32	TimerInt;
+
+	TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT;
+
+	if (pAC->Hwt.TActive) {
+
+		SkHwtStop(pAC, IoC);
+
+		SK_IN32(IoC, B2_TI_VAL, &TRead);
+
+		TRead /= SK_HWT_FAC;
+
+		SK_IN32(IoC, B0_ISRC, &IStatus);
+
+		/* Check if timer expired (or wrapped around) */
+		if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) {
+
+			SkHwtStop(pAC, IoC);
+
+			pAC->Hwt.TStop = pAC->Hwt.TStart;
+		}
+		else {
+
+			pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
+		}
+	}
+	return(pAC->Hwt.TStop);
+}
+
+/*
+ * interrupt source= timer
+ */
+void SkHwtIsr(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SkHwtStop(pAC, IoC);
+
+	pAC->Hwt.TStop = pAC->Hwt.TStart;
+
+	SkTimerDone(pAC, IoC);
+}
+
+/* End of file */
diff -ruN linux/drivers/net/sk98lin/skgeinit.c linux-new/drivers/net/sk98lin/skgeinit.c
--- linux/drivers/net/sk98lin/skgeinit.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgeinit.c	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,4689 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/skgeinit.c#15 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #15 $, $Change: 6261 $
+ * Date:	$DateTime: 2011/05/11 11:41:14 $
+ * Purpose:	Contains functions to initialize the adapter
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* global variables ***********************************************************/
+
+/* local variables ************************************************************/
+
+struct s_QOffTab {
+	int	RxQOff;				/* Receive Queue Address Offset */
+	int	XsQOff;				/* Sync Tx Queue Address Offset */
+	int	XaQOff;				/* Async Tx Queue Address Offset */
+#ifdef SK_AVB
+	int AvbQOff[AVB_LE_Q_CNT];		/* AVB Tx Queues Addresses Offsets */
+	int AvbMacQOff[AVB_MAC_Q_CNT];	/* AVB MAC Tx Queues Addresses Offsets */
+	int AvbClsQOff[AVB_CLS_CNT];	/* AVB Classes Offsets */
+#endif /* SK_AVB */
+};
+
+static struct s_QOffTab QOffTab[] = {
+	{
+		Q_R1, Q_XS1, Q_XA1,
+#ifdef SK_AVB
+		{
+			Q_AVB_TX_1, Q_AVB_TX_2, Q_AVB_TX_3, Q_AVB_TX_4,
+			Q_AVB_TX_5, Q_AVB_TX_6, Q_AVB_TX_7, Q_AVB_TX_8
+		},
+		{
+			TXMF_TCTL, TXMF_TCTL2, TXMF_TCTL3, TXMF_TCTL4, TXMF_TCTL5
+		},
+		{
+			CLASS_A_RATE_INT, CLASS_B_RATE_INT
+		}
+#endif /* SK_AVB */
+	},
+	{
+		Q_R2, Q_XS2, Q_XA2,
+#ifdef SK_AVB
+		{
+			Q_AVB_TX_1, Q_AVB_TX_2, Q_AVB_TX_3, Q_AVB_TX_4,
+			Q_AVB_TX_5, Q_AVB_TX_6, Q_AVB_TX_7, Q_AVB_TX_8
+		},
+		{
+			TXMF_TCTL, TXMF_TCTL2, TXMF_TCTL3, TXMF_TCTL4, TXMF_TCTL5
+		},
+		{
+			CLASS_A_RATE_INT, CLASS_B_RATE_INT
+		}
+#endif /* SK_AVB */
+	}
+};
+
+struct s_Config {
+	char	ScanString[8];
+	SK_U32	Value;
+};
+
+static struct s_Config OemConfig = {
+	{'O','E','M','_','C','o','n','f'},
+#ifdef SK_OEM_CONFIG
+	OEM_CONFIG_VALUE,
+#else
+	0,
+#endif
+};
+
+/******************************************************************************
+ *
+ *	SkHwGetTimeDelta() - Get time delta from timestamp timer
+ *
+ * Description:
+ *	Get time delta relativ to parameter 'Start'
+ *
+ * Returns:
+ *	nothing
+ */
+SK_U32 SkHwGetTimeDelta(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+SK_U32	Start)	/* Start time */
+{
+	SK_U32	Delta;
+
+	/* get current value of timestamp timer */
+	SK_IN32(IoC, GMAC_TI_ST_VAL, &Delta);
+
+	if (Delta >= Start) {
+		Delta -= Start;
+	}
+	else {
+		Delta += (~Start + 1);
+	}
+
+	return(Delta);
+
+}	/* SkHwGetTimeDelta */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGePortVlan() - Enable / Disable VLAN support
+ *
+ * Description:
+ *	Enable or disable the VLAN support of the selected port.
+ *	The new configuration is *not* saved over any SkGeStopPort() and
+ *	SkGeInitPort() calls.
+ *	Currently this function is only supported on Yukon-2/EC adapters.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGePortVlan(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port number */
+SK_BOOL	Enable)	/* Flag */
+{
+	SK_U32	RxCtrl;
+	SK_U32	TxCtrl;
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		if (Enable) {
+			RxCtrl = RX_VLAN_STRIP_ON;
+			TxCtrl = TX_VLAN_TAG_ON;
+		}
+		else {
+			RxCtrl = RX_VLAN_STRIP_OFF;
+			TxCtrl = TX_VLAN_TAG_OFF;
+		}
+
+		SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl);
+
+		SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl);
+	}
+}	/* SkGePortVlan */
+
+
+/******************************************************************************
+ *
+ *	SkGeMacSecLE() - Enable / Disable MACsec LE (Yukon-Ext.)
+ *
+ * Description:
+ *	Enable or disable generation of MACsec status list elements.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeMacSecLE(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port number */
+SK_BOOL	Enable)	/* Flag */
+{
+	if (HW_SUP_MACSEC(pAC)) {
+		SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
+			Enable ? RBMU_CSR_MACSEC_LE_ENA : RBMU_CSR_MACSEC_LE_DIS);
+	}
+}	/* SkGeMacSecLE */
+
+
+/******************************************************************************
+ *
+ *	SkGeRxRss() - Enable / Disable RSS Hash Calculation
+ *
+ * Description:
+ *	Enable or disable the RSS hash calculation of the selected port.
+ *	The new configuration is *not* saved over any SkGeStopPort() and
+ *	SkGeInitPort() calls.
+ *	Currently this function is only supported on Yukon-2/EC adapters.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeRxRss(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port number */
+SK_BOOL	Enable)	/* Flag */
+{
+	if (CHIP_ID_YUKON_2(pAC)) {
+		SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
+			Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH);
+	}
+}	/* SkGeRxRss */
+
+
+/******************************************************************************
+ *
+ *	SkGeRxCsum() - Enable / Disable Receive Checksum
+ *
+ * Description:
+ *	Enable or disable the Rx TCP/IP Checksum Check of the selected port.
+ *	The new configuration is *not* saved over any SkGeStopPort() and
+ *	SkGeInitPort() calls.
+ *	Currently this function is only supported on Yukon-2/EC adapters.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeRxCsum(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port number */
+SK_BOOL	Enable)	/* Flag */
+{
+	if (CHIP_ID_YUKON_2(pAC)) {
+		SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
+			Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
+	}
+}	/* SkGeRxCsum */
+#endif /* !SK_SLIM */
+
+#ifndef DISABLE_YUKON_I
+/******************************************************************************
+ *
+ *	SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
+ *
+ * Description:
+ *	Enable or disable the descriptor polling of the receive descriptor
+ *	ring (RxD) for port 'Port'.
+ *	The new configuration is *not* saved over any SkGeStopPort() and
+ *	SkGeInitPort() calls.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGePollRxD(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL PollRxD)	/* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
+{
+	SK_GEPORT	*pPrt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ?
+		CSR_ENA_POL : CSR_DIS_POL));
+}	/* SkGePollRxD */
+
+
+/******************************************************************************
+ *
+ *	SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
+ *
+ * Description:
+ *	Enable or disable the descriptor polling of the transmit descriptor
+ *	ring(s) (TxD) for port 'Port'.
+ *	The new configuration is *not* saved over any SkGeStopPort() and
+ *	SkGeInitPort() calls.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGePollTxD(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL PollTxD)	/* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
+{
+	SK_GEPORT	*pPrt;
+	SK_U32		DWord;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	DWord = (SK_U32)(PollTxD ? CSR_ENA_POL : CSR_DIS_POL);
+
+	if (pPrt->PXSQSize != 0) {
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
+	}
+
+	if (pPrt->PXAQSize != 0) {
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
+	}
+}	/* SkGePollTxD */
+#endif /* !DISABLE_YUKON_I */
+
+
+#ifdef SK_AVB
+/******************************************************************************
+ *
+ *  SkYuk2AVBControl() - Control AVB feature of Yukon-Optima
+ *
+ * Description:
+ *  This function enables or disables the AVB feature of Yukon-Optima.
+ *
+ * return:
+ *  nothing
+ */
+void SkYuk2AVBControl(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index 0 or 1 */
+SK_BOOL	Enable)		/* Enable / disable AVB feature */
+{
+	SK_GEPORT	*pPrt;
+	int			q;
+
+	if (!HW_SUP_AVB(pAC)) {
+		return;
+	}
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* Disable all prefetch units first */
+	for (q = 0; q < AVB_LE_Q_CNT; q++) {
+		SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PAvbQOffs[q], PREF_UNIT_CTRL_REG),
+			(SK_U8)PREF_UNIT_RST_SET);
+	}
+
+	for (q = 0; q < AVB_MAC_Q_CNT; q++) {
+		SK_OUT8(IoC, Y2_AVB_MAC_Q_ADDR(pPrt->PAvbMacQOffs[q], TXMF_TCTL),
+			(SK_U8)TXMF_TCTL_RST_SET);
+	}
+
+	SK_OUT16(IoC, GMAC_LINK_CTRL, Enable ?
+			MAC_CTRL_AVB_MODE_ON : MAC_CTRL_AVB_MODE_OFF);
+
+	if (Enable) {
+		/* Start the MAC Queues */
+		for (q = 0; q < AVB_MAC_Q_CNT; q++) {
+			SK_OUT8(IoC, Y2_AVB_MAC_Q_ADDR(pPrt->PAvbMacQOffs[q], TXMF_TCTL),
+				(SK_U8)(TXMF_TCTL_RST_CLR | TXMF_TCTL_OP_ON));
+
+			RegisterSelectiveSetReset(pAC, IoC,
+				Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[q], TX1_RATE_MISC),
+				TX_RATE_MISC_RATE_SHAPE_DIS, 0);
+		}
+
+		SK_OUT32(IoC, Y2_AVB_CLS_ADDR(CLASS_A_RATE_INT, CLASS_A_RATE_INT),
+			TX_RATE_INT_K_FACTOR_EN);
+		SK_OUT32(IoC, Y2_AVB_CLS_ADDR(CLASS_B_RATE_INT, CLASS_A_RATE_INT),
+			TX_RATE_INT_K_FACTOR_EN);
+	}
+}
+
+/******************************************************************************
+ *
+ *  SkYuk2AVBModeEnabled() - Get AVB feature state of Yukon-Optima
+ *
+ * Description:
+ *  This function returns the state of the AVB feature of Yukon-Optima (ena/dis).
+ *
+ * returns:
+ *  SK_FALSE - AVB Mode is disabled
+ *  SK_TRUE  - AVB Mode is enabled
+ */
+SK_BOOL SkYuk2AVBModeEnabled(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index 0 or 1 */
+{
+	SK_U8	Byte;
+
+	if (!HW_SUP_AVB(pAC)) {
+		return(SK_FALSE);
+	}
+
+	/* Since the bit definitions for AVB Mode and MACSEC Tx bypass
+	 * are overlapping in a chip containing both of the features the
+	 * AVB bits will certainly reside on a different location so this
+	 * function must be updated accordingly and the driver should always
+	 * use this function to get the AVB bits.
+	*/
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_OPT &&
+		pAC->GIni.GIChipId <= CHIP_ID_YUKON_OP_2) {
+
+		SK_IN8(IoC, GMAC_LINK_CTRL, &Byte);
+
+		return((Byte & MAC_CTRL_AVB_MODE_ON) != 0);
+	}
+
+	return(SK_FALSE);
+}
+
+/******************************************************************************
+ *
+ *  SkYuk2SetQueueDataRate() - Set data rate of the specified MAC FIFO
+ *
+ * Description:
+ *  This function sets the the queue registers to guarantee the requested
+ *  data rate.
+ *
+ * returns:
+ *  nothing
+ */
+void SkYuk2SetQueueDataRate(
+SK_AC	*pAC,			/* Adapter Context					*/
+SK_IOC	IoC,			/* I/O Context						*/
+int		Port,			/* Port Index 0 or 1				*/
+int		Queue,			/* MAC FIFO queue to setup (0-3)	*/
+SK_U32	DataRate)		/* Data Rate in Kbps (1000 bps)		*/
+{
+	SK_U32	DataRateReg;
+	SK_U32	DWord;
+
+	Queue--;
+
+	if (SkYuk2AVBModeEnabled(pAC, IoC, Port) &&
+		Queue >= 0 && Queue < AVB_MAC_Q_CNT) {
+
+		SK_IN32(IoC, Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[Queue],
+			TX1_RATE_INT), &DWord);
+
+		/*
+		 *	2^22 / 10^6 = 4,19....
+		 ****
+		 *	DataRate * 2^22 / 10^6 ==
+		 *	DataRate * 2^22 / (2^6 * 5^6) ==
+		 *	DataRate * 2^16 / 5^6 ==
+		 *	DataRate * (62500 / 5^6 + 3036 / 5^6) ==
+		 *	DataRate * (4 + 3036 / 5^6) ==
+		 *	DataRate * 4 + DataRate * 3036 / 5^6 ==
+		 ****
+		 *	DataRate * 4 + DataRate * (3000 + 36) / 5^6 ==
+		 *	DataRate * 4 + DataRate * 24 / 5^3 + DataRate * 36 / 5^6 ==
+		 *	DataRate * 4 + DataRate * 24 / 5^3 + (DataRate * 24 % 5^3) * 5^3 / 5^6 + DataRate * 36 / 5^6 ==
+		 *	DataRate * 4 + DataRate * 24 / 5^3 + ((DataRate * 24 % 5^3) * 5^3 + DataRate * 36) / 5^6 ==
+		 ****
+		 *	(every single expression is < 2^32 if DataRate < 2^20)
+		 */
+		if (DataRate >= 1000000) {
+			DataRateReg = BIT_22 - 1;
+		}
+		else {
+			DataRateReg = 4 * DataRate + ((3036 * DataRate + 15625 / 2) / 15625);
+		}
+
+		DWord = (DWord & ~(BIT_22 - 1)) | DataRateReg | TX_RATE_INT_K_FACTOR_EN;
+
+		/* Yukon-Optima has 5 MAC FIFO queues but only the first 4 have a rate shaper */
+
+		SK_OUT32(IoC, Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[Queue],
+			TX1_RATE_INT), DWord);
+
+		/* Enable rate shaping by clearing TX_RATE_MISC_RATE_SHAPE_DIS bit */
+		RegisterSelectiveSetReset(pAC, IoC, Y2_AVB_MAC_Q_ADDR(
+			pAC->GIni.GP[Port].PAvbMacQOffs[Queue], TX1_RATE_MISC),
+			0, TX_RATE_MISC_RATE_SHAPE_DIS);
+
+		SkYuk2SetClassDataRates(pAC, IoC, Port);
+	}
+}
+
+/****************************************************************************
+ *
+ * \brief Updates data rates for class A and class B
+ *
+ * \details Updates data rates for class A and class B
+ *
+ * \return nothing
+ *
+ *****************************************************************************/
+void SkYuk2SetClassDataRates(
+SK_AC	*pAC,			/*!< Adapter Context		*/
+SK_IOC	IoC,			/*!< I/O Context			*/
+int		Port)			/*!< Port Index 0 or 1		*/
+{
+	int		i;
+	int		QueuesClass;
+	SK_U32	DWord;
+	SK_U32	QueuesRate;
+	SK_U32	DataRateClassA = 0;
+	SK_U32	DataRateClassB = 0;
+
+	for (i = 0; i < AVB_MAC_Q_CNT; i++) {
+
+		SK_IN32(IoC, Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[i],
+			TX1_RATE_MISC),
+			&DWord);
+
+		QueuesClass = (int)(DWord & 0x3);
+
+		SK_IN32(IoC, Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[i],
+			TX1_RATE_INT),
+			&QueuesRate);
+
+		QueuesRate &= (BIT_22 - 1);
+
+		switch (QueuesClass) {
+		case 1:
+			DataRateClassA += QueuesRate;
+			break;
+		case 2:
+			DataRateClassB += QueuesRate;
+			break;
+		default:
+#ifndef SK_DIAG
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+				("Class %d doesn't support shaping\n", QueuesClass));
+#else /* !SK_DIAG */
+			c_print("Class %d doesn't support shaping\n", QueuesClass);
+#endif /* !SK_DIAG */
+		}
+	}
+
+	/* writing Class Rates */
+	SK_IN32(IoC, Y2_AVB_CLS_ADDR(CLASS_A_RATE_INT, CLASS_A_RATE_INT), &DWord);
+	DWord = (DWord & ~(BIT_22 - 1)) | TX_RATE_INT_K_FACTOR_EN | DataRateClassA;
+	SK_OUT32(IoC, Y2_AVB_CLS_ADDR(CLASS_A_RATE_INT, CLASS_A_RATE_INT), DWord);
+
+	SK_IN32(IoC, Y2_AVB_CLS_ADDR(CLASS_B_RATE_INT, CLASS_A_RATE_INT), &DWord);
+	DWord = (DWord & ~(BIT_22 - 1)) | TX_RATE_INT_K_FACTOR_EN | DataRateClassB;
+	SK_OUT32(IoC, Y2_AVB_CLS_ADDR(CLASS_B_RATE_INT, CLASS_A_RATE_INT), DWord);
+}
+
+/******************************************************************************
+ *
+ *  SkYuk2AvbSetQueueClass() - Set class for the specified MAC FIFO
+ *
+ * Description:
+ *  This function sets the class for the specified MAC FIFO queue.
+ *
+ * returns:
+ *  nothing
+ */
+void SkYuk2AvbSetQueueClass(
+SK_AC	*pAC,		/* Adapter Context			*/
+SK_IOC	IoC,		/* I/O Context				*/
+int		Port,		/* Port Index 0 or 1		*/
+int		Queue,		/* MAC FIFO queue (0-3)		*/
+SK_U32	Class)		/* New class for queue		*/
+{
+	Queue--;
+
+	if (SkYuk2AVBModeEnabled(pAC, IoC, Port) &&
+		Queue >= 0 && Queue < AVB_MAC_Q_CNT) {
+
+		RegisterSelectiveSetReset(pAC, IoC,
+			Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[Queue], TX1_RATE_MISC),
+				Class & TX_RATE_MISC_CLASS_MSK,
+				TX_RATE_MISC_CLASS_MSK);
+	}
+}
+
+/******************************************************************************
+ *
+ *  SkYuk2AvbSetQueuePriority() - Set class for the specified MAC FIFO
+ *
+ * Description:
+ *  This function sets the class for the specified MAC FIFO queue.
+ *
+ * returns:
+ *  nothing
+ */
+void SkYuk2AvbSetQueuePriority(
+SK_AC	*pAC,			/* Adapter Context 					*/
+SK_IOC	IoC,			/* I/O Context 						*/
+int		Port,			/* Port Index 0 or 1				*/
+int		Queue,			/* MAC FIFO queue to setup (0-3)	*/
+SK_U32	Priority)		/* New priority for queue			*/
+{
+	Queue--;
+
+	if (SkYuk2AVBModeEnabled(pAC, IoC, Port) &&
+		Queue >= 0 && Queue < AVB_MAC_Q_CNT) {
+
+		RegisterSelectiveSetReset(pAC, IoC,
+			Y2_AVB_MAC_Q_ADDR(pAC->GIni.GP[Port].PAvbMacQOffs[Queue], TX1_RATE_MISC),
+				(Priority << TX_RATE_MISC_PRI_BASE) & TX_RATE_MISC_PRI_MSK,
+				TX_RATE_MISC_PRI_MSK);
+	}
+}
+
+
+/******************************************************************************
+ *
+ * \brief Maps LE queue to Tx MAC FIFO queue in AVB mode
+ *
+ * \details Maps LE queue to Tx MAC FIFO queue in AVB mode
+ *
+  * \return nothing
+  *
+  *****************************************************************************/
+void SkYuk2AvbSetLeQueue(
+SK_AC *pAC,			/*!< Adapter Context > 		*/
+SK_IOC IoC,			/*!< I/ O Context > 			*/
+int Port,			/*!< Port Index 0 or 1 >		*/
+int Pfu,			/*!< PFU to map to queue > 	*/
+int Queue)			/*!< Queue PFU should be mapped to >	*/
+{
+	SK_U32	Addr;
+	SK_U32	Data;
+
+	if (SkYuk2AVBModeEnabled(pAC, IoC, Port) &&
+		Queue >= 1 && Queue <= AVB_MAC_Q_CNT &&
+		Pfu >= 6 && Pfu <= AVB_LE_Q_CNT) {
+
+		Addr = TPLE_ADDR(Pfu, REQ_TH);
+
+		SK_IN32(IoC, Addr, &Data);
+
+		Data = (Data & ~TPLE_REQ_TH_H_MAP_MSK) | ((Queue & 0x7) << 29);
+
+		SK_OUT32(IoC, Addr, Data);
+	}
+}
+
+
+/******************************************************************************
+  *
+  * \brief Maps LE queue to Tx MAC FIFO queue
+  *
+  * \details Maps LE queue to Tx MAC FIFO queue
+  *
+  * \return nothing
+  *
+  *****************************************************************************/
+void SkYuk2AvbSetLePriority(
+SK_AC	*pAC,			/*!< Adapter Context > 		*/
+SK_IOC	IoC,			/*!< I/ O Context > 		*/
+int		Port,			/*!< Port Index 0 or 1 >	*/
+int		Pfu,			/*!< PFU to map to queue > 	*/
+int		Priority)		/*!< PFU queue's priority > */
+{
+	SK_U32	Addr;
+	SK_U32	Data;
+
+	if (SkYuk2AVBModeEnabled(pAC, IoC, Port) &&
+		Priority >= 0 && Priority <= 3 && Pfu >= 1 && Pfu <= AVB_LE_Q_CNT) {
+
+		Addr = TPLE_ADDR(Pfu, REQ_CTRL);
+
+		SK_IN32(IoC, Addr, &Data);
+
+		Data = (Data & 0xfffffffc) | Priority;
+
+		SK_OUT32(IoC, Addr, Data);
+	}
+}
+#endif /* SK_AVB */
+
+/******************************************************************************
+ *
+ *  RegisterSelectiveSetReset() - Set/reset bits in specified register
+ *
+ * Description:
+ *  This function helps in modifying bits for registers where
+ *  read-modify-write scheme is needed.
+ *
+ * returns:
+ *  nothing
+ */
+void RegisterSelectiveSetReset(
+SK_AC	*pAC,			/* Adapter Context */
+SK_IOC	IoC,			/* I/O Context */
+SK_U32	Register,		/* Offset of register to modify			*/
+SK_U32	BitsToSet,		/* Bits to be set in the register		*/
+SK_U32	BitsToClear)	/* Bits to be cleared in the register	*/
+{
+	SK_U32 Val32;
+
+	SK_IN32(IoC, Register, &Val32);
+
+	Val32 &= ~BitsToClear;
+	Val32 |= BitsToSet;
+
+	SK_OUT32(IoC, Register, Val32);
+}
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGeYellowLED() - Switch the yellow LED on or off.
+ *
+ * Description:
+ *	Switch the yellow LED on or off.
+ *
+ * Note:
+ *	This function may be called any time after SkGeInit(Level 1).
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeYellowLED(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		State)		/* yellow LED state, 0 = OFF, 0 != ON */
+{
+	int	LedReg;
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		/* different mapping on Yukon-2 */
+		LedReg = B0_CTST + 1;
+	}
+	else {
+		LedReg = B0_LED;
+	}
+
+	if (State == 0) {
+		/* Switch state LED OFF */
+		SK_OUT8(IoC, LedReg, LED_STAT_OFF);
+	}
+	else {
+		/* Switch state LED ON */
+		SK_OUT8(IoC, LedReg, LED_STAT_ON);
+	}
+}	/* SkGeYellowLED */
+#endif /* !SK_SLIM */
+
+
+/******************************************************************************
+ *
+ *	DoCalcAddr() - Calculates the start and the end address of a queue.
+ *
+ * Description:
+ *	This function calculates the start and the end address of a queue.
+ *  Afterwards the 'StartVal' is incremented to the next start position.
+ *	If the port is already initialized the calculated values
+ *	will be checked against the configured values and an
+ *	error will be returned, if they are not equal.
+ *	If the port is not initialized the values will be written to
+ *	*StartAdr and *EndAddr.
+ *
+ * Returns:
+ *	0:	success
+ *	1:	configuration error
+ */
+static int DoCalcAddr(
+SK_AC		*pAC,				/* Adapter Context */
+SK_GEPORT	SK_FAR *pPrt,		/* port index */
+int			QuSize,				/* size of the queue to configure in kB */
+SK_U32		SK_FAR *StartVal,	/* start value for address calculation */
+SK_U32		SK_FAR *QuStartAddr,/* start address to calculate */
+SK_U32		SK_FAR *QuEndAddr)	/* end address to calculate */
+{
+	SK_U32	EndVal;
+	SK_U32	NextStart;
+	int		Rtv;
+
+	Rtv = 0;
+	if (QuSize == 0) {
+		EndVal = *StartVal;
+		NextStart = EndVal;
+	}
+	else {
+		EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
+		NextStart = EndVal + 1;
+	}
+
+	if (pPrt->PState >= SK_PRT_INIT) {
+		if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
+			Rtv = 1;
+		}
+	}
+	else {
+		*QuStartAddr = *StartVal;
+		*QuEndAddr = EndVal;
+	}
+
+	*StartVal = NextStart;
+	return(Rtv);
+}	/* DoCalcAddr */
+
+/******************************************************************************
+ *
+ *	SkGeRoundQueueSize() - Round the given queue size to the adapters QZ units
+ *
+ * Description:
+ *	This function rounds the given queue size in kBs to adapter specific
+ *	queue size units (Yukon-1: 8 kB, Yukon-2/EC: 1 kB).
+ *
+ * Returns:
+ *	the rounded queue size in kB
+ */
+static int SkGeRoundQueueSize(
+SK_AC	*pAC,		/* Adapter Context */
+int	QueueSizeKB)	/* Queue size in kB */
+{
+	int QueueSizeSteps;
+
+	QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP;
+
+	return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1));
+}	/* SkGeRoundQueueSize */
+
+
+/******************************************************************************
+ *
+ *	SkGeInitAssignRamToQueues() - Allocate default queue sizes
+ *
+ * Description:
+ *	This function assigns the memory to the different queues and ports.
+ *	When DualNet is set to SK_TRUE all ports get the same amount of memory.
+ *	Otherwise the first port gets most of the memory and all the
+ *	other ports just the required minimum.
+ *	This function can only be called when pAC->GIni.GIRamSize and
+ *	pAC->GIni.GIMacsFound have been initialized, usually this happens
+ *	at init level 1
+ *
+ * Returns:
+ *	0 - ok
+ *	1 - invalid input values
+ *	2 - not enough memory
+ */
+
+int SkGeInitAssignRamToQueues(
+SK_AC	*pAC,			/* Adapter Context */
+int		ActivePort,		/* Active Port in RLMT mode */
+SK_BOOL	DualNet)		/* Dual Net active */
+{
+	int	i;
+	int	UsedKilobytes;			/* memory already assigned */
+	int	ActivePortKilobytes;	/* memory available for active port */
+	int	MinQueueSize;			/* min. memory for queues */
+	int	TotalRamSize;			/* total memory for queues */
+	SK_BOOL	DualPortYukon2;
+	SK_GEPORT *pPrt;
+
+	if (ActivePort >= pAC->GIni.GIMacsFound) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+			("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
+			ActivePort));
+		return(1);
+	}
+
+	DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2);
+
+	TotalRamSize = pAC->GIni.GIRamSize;
+
+	if (DualPortYukon2) {
+		TotalRamSize *= 2;
+	}
+
+	MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE;
+
+	if (MinQueueSize > pAC->GIni.GIRamSize) {
+		MinQueueSize = pAC->GIni.GIRamSize;
+	}
+
+	if ((pAC->GIni.GIMacsFound * MinQueueSize +
+		 RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+			("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
+			TotalRamSize));
+		return(2);
+	}
+
+	if (DualNet) {
+		/* every port gets the same amount of memory */
+		ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound;
+
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+			pPrt = &pAC->GIni.GP[i];
+
+			if (DualPortYukon2) {
+				ActivePortKilobytes = pAC->GIni.GIRamSize;
+			}
+			/* take away the minimum memory for active queues */
+			ActivePortKilobytes -= MinQueueSize;
+
+			/* receive queue gets the minimum + 80% of the rest */
+			pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
+				(int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100) +
+				SK_MIN_RXQ_SIZE;
+
+			ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE);
+
+			/* synchronous transmit queue */
+			pPrt->PXSQSize = 0;
+
+			/* asynchronous transmit queue */
+			pPrt->PXAQSize = SkGeRoundQueueSize(pAC,
+				ActivePortKilobytes + SK_MIN_TXQ_SIZE);
+		}
+	}
+	else {	/* RLMT Mode or single link adapter */
+
+		UsedKilobytes = 0;
+
+		/* set standby queue size defaults for all standby ports */
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+			if (i != ActivePort) {
+				pPrt = &pAC->GIni.GP[i];
+
+				if (DualPortYukon2) {
+					pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
+						(int)((long)(pAC->GIni.GIRamSize - MinQueueSize) *
+						RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE;
+
+					pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize;
+				}
+				else {
+					pPrt->PRxQSize = SK_MIN_RXQ_SIZE;
+					pPrt->PXAQSize = SK_MIN_TXQ_SIZE;
+				}
+				pPrt->PXSQSize = 0;
+
+				/* Count used RAM */
+				UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize;
+			}
+		}
+		/* what's left? */
+		ActivePortKilobytes = TotalRamSize - UsedKilobytes;
+
+		/* assign it to the active port */
+		/* first take away the minimum memory */
+		ActivePortKilobytes -= MinQueueSize;
+		pPrt = &pAC->GIni.GP[ActivePort];
+
+		/* receive queue gets 80% of the rest */
+		pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
+			(int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100);
+
+		ActivePortKilobytes -= pPrt->PRxQSize;
+
+		/* add the minimum memory for Rx queue */
+		pPrt->PRxQSize += MinQueueSize/2;
+
+		/* synchronous transmit queue */
+		pPrt->PXSQSize = 0;
+
+		/* asynchronous transmit queue gets 20% of the rest */
+		pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) +
+			/* add the minimum memory for Tx queue */
+			MinQueueSize/2;
+	}
+
+#ifdef DEBUG
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+		pPrt = &pAC->GIni.GP[i];
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+			("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n",
+			i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize));
+	}
+#endif /* DEBUG */
+
+	return(0);
+}	/* SkGeInitAssignRamToQueues */
+
+
+/******************************************************************************
+ *
+ *	SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
+ *
+ * Description:
+ *	This function verifies the Queue Size Configuration specified
+ *	in the variables PRxQSize, PXSQSize, and PXAQSize of all
+ *	used ports.
+ *	This requirements must be fullfilled to have a valid configuration:
+ *		- The size of all queues must not exceed GIRamSize.
+ *		- The queue sizes must be specified in units of 8 kB.
+ *		- The size of Rx queues of available ports must not be
+ *		  smaller than 16 kB (Yukon-1) resp. 10 kB (Yukon-2).
+ *		- The size of at least one Tx queue (synch. or asynch.)
+ *		  of available ports must not be smaller than 16 kB,
+ *		  resp. 10 kB (Yukon-2) when Jumbo Frames are used.
+ *		- The RAM start and end addresses must not be changed
+ *		  for ports which are already initialized.
+ *	Furthermore SkGeCheckQSize() defines the Start and End Addresses
+ *  of all ports and stores them into the HWAC port structure.
+ *
+ * Returns:
+ *	0:	Queue Size Configuration valid
+ *	1:	Queue Size Configuration invalid
+ */
+static int SkGeCheckQSize(
+SK_AC	*pAC,		/* Adapter Context */
+int		Port)		/* port index */
+{
+	SK_GEPORT *pPrt;
+	int	i;
+	int	Rtv;
+	int	Rtv2;
+	SK_U32	StartAddr;
+#ifndef SK_SLIM
+	int	UsedMem;	/* total memory used (max. found ports) */
+#endif /* !SK_SLIM */
+
+	Rtv = 0;
+
+#ifndef SK_SLIM
+
+	UsedMem = 0;
+
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+		pPrt = &pAC->GIni.GP[i];
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			UsedMem = 0;
+		}
+		else if (((pPrt->PRxQSize & QZ_UNITS) != 0 ||
+				  (pPrt->PXSQSize & QZ_UNITS) != 0 ||
+				  (pPrt->PXAQSize & QZ_UNITS) != 0)) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
+			return(1);
+		}
+
+#ifndef SK_DIAG
+		if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE &&
+			pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
+			return(1);
+		}
+
+		/*
+		 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
+		 * if Jumbo Frames are used, this size has to be >= 16 kB.
+		 */
+		if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
+			(pPrt->PPortUsage == SK_JUMBO_LINK &&
+			((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
+			 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
+				return(1);
+		}
+#endif /* !SK_DIAG */
+
+		UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
+
+		if (UsedMem > pAC->GIni.GIRamSize) {
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
+			return(1);
+		}
+	}
+
+#endif /* !SK_SLIM */
+
+	/* Now start address calculation */
+	StartAddr = pAC->GIni.GIRamOffs;
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+		pPrt = &pAC->GIni.GP[i];
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			StartAddr = 0;
+		}
+
+		/* Calculate/Check values for the receive queue */
+		Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
+			&pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
+		Rtv |= Rtv2;
+
+		/* Calculate/Check values for the synchronous Tx queue */
+		Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
+			&pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
+		Rtv |= Rtv2;
+
+		/* Calculate/Check values for the asynchronous Tx queue */
+		Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
+			&pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
+		Rtv |= Rtv2;
+
+		if (Rtv) {
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
+			return(1);
+		}
+	}
+
+	return(0);
+}	/* SkGeCheckQSize */
+
+
+/******************************************************************************
+ *
+ *	SkGeInitMacFifo() - Initialize the MAC FIFOs
+ *
+ * Description:
+ *	Initialize all MAC FIFOs of the specified port
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeInitMacFifo(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_U16	Word;
+	/*
+	 * For each FIFO:
+	 *	- release local reset
+	 *	- use default value for MAC FIFO size
+	 *	- setup defaults for the control register
+	 *	- enable the FIFO
+	 */
+
+	Word = (SK_U16)GMF_RX_CTRL_DEF;
+
+#ifndef DISABLE_YUKON_I
+	/* disable Rx GMAC FIFO Flush for YUKON-Plus */
+	if (pAC->GIni.GIYukonLite) {
+
+		Word &= ~GMF_RX_F_FL_ON;
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	/* configure Rx GMAC FIFO */
+	SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
+
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
+
+	Word = RX_FF_FL_DEF_MSK;
+
+#ifndef SK_DIAG
+	if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) {
+		/*
+		 * Flushing must be enabled (needed for ASF see dev. #4.29),
+		 * but the flushing mask should be disabled (see dev. #4.115)
+		 */
+		Word = 0;
+	}
+#endif /* !SK_DIAG */
+
+	/* set Rx GMAC FIFO Flush Mask (after clearing reset) */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word);
+
+	/* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */
+	Word = (SK_U16)RX_GMF_FL_THR_DEF;
+
+	if (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIAsfEnabled) {
+		/* WA for dev. #4.30 & 4.89 (reduce to 0x08 -> 48 bytes) */
+		Word -= 2;
+	}
+	else if (HW_FEATURE(pAC, HWF_WA_DEV_521)) {
+		Word = 0x178;
+	}
+	else {
+		/*
+		* because Pause Packet Truncation in GMAC is not working
+		* we have to increase the Flush Threshold to 64 bytes
+		* in order to flush pause packets in Rx FIFO on Yukon-1
+		*/
+		Word++;
+	}
+
+	/* set Rx GMAC FIFO Flush Threshold (after clearing reset) */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word);
+
+	/* configure Tx GMAC FIFO */
+	SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
+
+	SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
+
+	/* set Rx Pause Threshold */
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||
+			pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P) {
+
+			Word = HW_FEATURE(pAC, HWF_WA_DEV_521) ?
+						SK_DEV521_ULPP : SK_ECU_ULPP;
+		}
+		else {
+			Word = SK_EXT_ULPP;
+		}
+
+		/* set Rx Pause Upper Threshold */
+		SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), Word);
+
+		/* set Rx Pause Lower Threshold */
+		SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
+
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EX &&
+			 pAC->GIni.GIChipRev != CHIP_REV_YU_EX_A0) ||
+			pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+			/* Yukon-Extreme B0 and further devices */
+			/* enable Store & Forward mode for TX */
+			SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
+		}
+		else {
+			if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
+				/* set Tx GMAC FIFO Almost Empty Threshold */
+				SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
+					(SK_ECU_JUMBO_WM << 16) | (SK_U16)SK_ECU_AE_THR);
+				/* disable Store & Forward mode for TX */
+				SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
+			}
+			else {
+				/* enable Store & Forward mode for TX */
+				SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
+			}
+		}
+	}
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_520)) {
+		/* disable dynamic watermark */
+		SK_IN16(IoC, MR_ADDR(Port, TX_GMF_EA), &Word);
+
+		SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_EA), Word & ~TX_DYN_WM_ENA);
+	}
+
+}	/* SkGeInitMacFifo */
+
+
+/******************************************************************************
+ *
+ *	DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
+ *
+ * Description:
+ *	If the queue is used, enable and initialize it.
+ *	Make sure the queue is still reset, if it is not used.
+ *
+ * Returns:
+ *	nothing
+ */
+void DoInitRamQueue(
+SK_AC	*pAC,			/* Adapter Context */
+SK_IOC	IoC,			/* I/O Context */
+int		QuIoOffs,		/* Queue I/O Address Offset */
+SK_U32	QuStartAddr,	/* Queue Start Address */
+SK_U32	QuEndAddr,		/* Queue End Address */
+int		QuType)			/* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
+{
+	SK_U32	RxUpThresVal;
+	SK_U32	RxLoThresVal;
+
+	if (QuStartAddr != QuEndAddr) {
+		/* calculate thresholds, assume we have a big Rx queue */
+		RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
+		RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
+
+		/* build HW address format */
+		QuStartAddr = QuStartAddr / 8;
+		QuEndAddr = QuEndAddr / 8;
+
+		/* release local reset */
+		SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
+
+		/* configure addresses */
+		SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
+		SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
+		SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
+		SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
+
+		switch (QuType) {
+		case SK_RX_SRAM_Q:
+			/* configure threshold for small Rx Queue */
+			RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
+
+			/* continue with SK_RX_BRAM_Q */
+		case SK_RX_BRAM_Q:
+			/* write threshold for Rx Queue (Pause packets) */
+			SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
+			SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
+
+			/* the high priority threshold not used */
+			break;
+		case SK_TX_RAM_Q:
+			/*
+			 * GMAC Tx FIFO is only 1 kB
+			 * enable Store & Forward Mode for the Tx Side
+			 */
+			SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
+			break;
+		}
+
+		/* set queue operational */
+		SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
+	}
+	else {
+		/* ensure the queue is still disabled */
+		SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
+	}
+}	/* DoInitRamQueue */
+
+
+/******************************************************************************
+ *
+ *	SkGeInitRamBufs() - Initialize the RAM Buffer Queues
+ *
+ * Description:
+ *	Initialize all RAM Buffer Queues of the specified port
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeInitRamBufs(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT *pPrt;
+	int RxQType;
+
+	if (!HW_IS_RAM_IF_AVAIL(pAC)) {
+		return;
+	}
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) {
+		RxQType = SK_RX_SRAM_Q;		/* small Rx Queue */
+	}
+	else {
+		RxQType = SK_RX_BRAM_Q;		/* big Rx Queue */
+	}
+
+	DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
+		pPrt->PRxQRamEnd, RxQType);
+
+	DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
+		pPrt->PXsQRamEnd, SK_TX_RAM_Q);
+
+	DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
+		pPrt->PXaQRamEnd, SK_TX_RAM_Q);
+
+}	/* SkGeInitRamBufs */
+
+
+/******************************************************************************
+ *
+ *	SkGeInitRamIface() - Initialize the RAM Interface
+ *
+ * Description:
+ *	This function initializes the Adapters RAM Interface.
+ *
+ * Note:
+ *	This function is used in the diagnostics.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeInitRamIface(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	int i;
+	int RamBuffers;
+
+	if (!HW_IS_RAM_IF_AVAIL(pAC)) {
+		return;
+	}
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		RamBuffers = pAC->GIni.GIMacsFound;
+	}
+	else {
+		RamBuffers = 1;
+	}
+
+	for (i = 0; i < RamBuffers; i++) {
+		/* release local reset */
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR);
+
+		/* configure timeout values */
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
+	}
+}	/* SkGeInitRamIface */
+
+
+/******************************************************************************
+ *
+ *	SkGeInitBmu() - Initialize the BMU state machines
+ *
+ * Description:
+ *	Initialize all BMU state machines of the specified port
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeInitBmu(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		RxWm;
+	SK_U16		TxWm;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	RxWm = SK_BMU_RX_WM;
+	TxWm = SK_BMU_TX_WM;
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+
+		if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
+			/* for better performance set it to 128 */
+			RxWm = SK_BMU_RX_WM_PEX;
+		}
+
+		/* Rx Queue: Release all local resets and set the watermark */
+		SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET);
+		SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT);
+		SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON);
+
+		SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm);
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+			pAC->GIni.GIChipRev > CHIP_REV_YU_EC_U_A0) {
+			/* MAC Rx RAM Read is controlled by hardware */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS);
+		}
+
+		/*
+		 * Tx Queue: Release all local resets if the queue is used !
+		 *		set watermark
+		 */
+		if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) {
+			/* Yukon-EC doesn't have a synchronous Tx queue */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON);
+
+			SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm);
+		}
+
+		if (pPrt->PXAQSize != 0) {
+
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
+
+#if (!defined(SK_SLIM) && !defined(SK_DIAG))
+			if (HW_FEATURE(pAC, HWF_TX_IP_ID_INCR_ON)) {
+				/* Enable Tx IP ID Increment */
+				SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_TX_IPIDINCR_ON);
+			}
+#endif /* !SK_SLIM && !SK_DIAG */
+
+			SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm);
+
+			if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+				pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
+				/* fix for Yukon-EC Ultra: set BMU FIFO level */
+				SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV);
+			}
+		}
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
+			/* for better performance */
+			RxWm /= 2;
+			TxWm /= 2;
+		}
+
+		/* Rx Queue: Release all local resets and set the watermark */
+		SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
+		SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
+
+		/*
+		 * Tx Queue: Release all local resets if the queue is used !
+		 *		set watermark
+		 */
+		if (pPrt->PXSQSize != 0) {
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
+		}
+
+		if (pPrt->PXAQSize != 0) {
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
+		}
+	}
+#endif /* !DISABLE_YUKON_I */
+	/*
+	 * Do NOT enable the descriptor poll timers here, because
+	 * the descriptor addresses are not specified yet.
+	 */
+}	/* SkGeInitBmu */
+
+
+/******************************************************************************
+ *
+ *	TestStopBit() - Test the stop bit of the queue
+ *
+ * Description:
+ *	Stopping a queue is not as simple as it seems to be.
+ *	If descriptor polling is enabled, it may happen
+ *	that RX/TX stop is done and SV idle is NOT set.
+ *	In this case we have to issue another stop command.
+ *
+ * Returns:
+ *	The queues control status register
+ */
+static SK_U32 TestStopBit(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		QuIoOffs)	/* Queue I/O Address Offset */
+{
+	SK_U32	QuCsr;	/* CSR contents */
+
+	SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) {
+			/* Stop Descriptor overridden by start command */
+			SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP);
+
+			SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
+		}
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
+			/* Stop Descriptor overridden by start command */
+			SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
+
+			SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
+		}
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	return(QuCsr);
+}	/* TestStopBit */
+
+
+/******************************************************************************
+ *
+ *	SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
+ *
+ * Description:
+ *	After calling this function the descriptor rings and Rx and Tx
+ *	queues of this port may be reconfigured.
+ *
+ *	It is possible to stop the receive and transmit path separate or
+ *	both together.
+ *
+ *	Dir =	SK_STOP_TX	Stops the transmit path only and resets the MAC.
+ *				The receive queue is still active and
+ *				the pending Rx frames may be still transferred
+ *				into the RxD.
+ *		SK_STOP_RX	Stop the receive path. The tansmit path
+ *				has to be stopped once before.
+ *		SK_STOP_ALL	SK_STOP_TX + SK_STOP_RX
+ *
+ *	RstMode =	SK_SOFT_RST	Resets the MAC, the PHY is still alive.
+ *				SK_HARD_RST	Resets the MAC and the PHY.
+ *
+ * Example:
+ *	1) A Link Down event was signaled for a port. Therefore the activity
+ *	of this port should be stopped and a hardware reset should be issued
+ *	to enable the workaround of XMAC Errata #2.
+ *	But the received frames should not be discarded.
+ *		...
+ *		SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
+ *		(transfer all pending Rx frames)
+ *		SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
+ *		...
+ *
+ *	2) An event was issued which request the driver to switch
+ *	the 'virtual active' link to an other already active port
+ *	as soon as possible. The frames in the receive queue of this
+ *	port may be lost. But the PHY must not be reset during this
+ *	event.
+ *		...
+ *		SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
+ *		...
+ *
+ * Extended Description:
+ *	If SK_STOP_TX is set,
+ *		o disable the MAC's receive and transmitter to prevent
+ *		  from sending incomplete frames
+ *		o stop the port's transmit queues before terminating the
+ *		  BMUs to prevent from performing incomplete PCI cycles
+ *		  on the PCI bus
+ *		- The network Rx and Tx activity and PCI Tx transfer is
+ *		  disabled now.
+ *		o reset the MAC depending on the RstMode
+ *		o Stop Interval Timer and Limit Counter of Tx Arbiter,
+ *		  also disable Force Sync bit and Enable Alloc bit.
+ *		o perform a local reset of the port's Tx path
+ *			- reset the PCI FIFO of the async Tx queue
+ *			- reset the PCI FIFO of the sync Tx queue
+ *			- reset the RAM Buffer async Tx queue
+ *			- reset the RAM Buffer sync Tx queue
+ *			- reset the MAC Tx FIFO
+ *		o switch Link and Tx LED off, stop the LED counters
+ *
+ *	If SK_STOP_RX is set,
+ *		o stop the port's receive queue
+ *		- The path data transfer activity is fully stopped now.
+ *		o perform a local reset of the port's Rx path
+ *			- reset the PCI FIFO of the Rx queue
+ *			- reset the RAM Buffer receive queue
+ *			- reset the MAC Rx FIFO
+ *		o switch Rx LED off, stop the LED counter
+ *
+ *	If all ports are stopped,
+ *		o reset the RAM Interface.
+ *
+ * Notes:
+ *	o This function may be called during the driver states RESET_PORT and
+ *	  SWITCH_PORT.
+ */
+void SkGeStopPort(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port to stop (MAC_1 + n) */
+int		Dir,		/* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
+int		RstMode)	/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
+{
+	SK_GEPORT *pPrt;
+#ifndef DISABLE_YUKON_I
+	SK_U32	RxCsr;
+#endif /* !DISABLE_YUKON_I */
+	SK_U32	XsCsr;
+	SK_U32	XaCsr;
+	SK_U32	CsrStart;
+	SK_U32	CsrStop;
+	SK_U32	CsrIdle;
+	SK_U32	CsrTest;
+	SK_U32	StartTime;
+	SK_U32	TimeOut;
+	SK_U8	FifoRdShLev;	/* FIFO read shadow level */
+	SK_U8	FifoRdLev;		/* FIFO read level */
+	int		i;
+	int		ToutCnt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGeStopPort: Port %d, Dir %d, RstMode %d\n",
+		 Port, Dir, RstMode));
+
+	/* set the proper values of Q_CSR register layout depending on the chip */
+	if (CHIP_ID_YUKON_2(pAC)) {
+		CsrStart = BMU_START;
+		CsrStop = BMU_STOP;
+		CsrIdle = BMU_IDLE;
+		CsrTest = BMU_IDLE;
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		CsrStart = CSR_START;
+		CsrStop = CSR_STOP;
+		CsrIdle = CSR_SV_IDLE;
+		CsrTest = CSR_SV_IDLE | CSR_STOP;
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	if ((Dir & SK_STOP_TX) != 0) {
+
+		if (!pAC->GIni.GIAsfEnabled) {
+			/* disable receiver and transmitter */
+			SkMacRxTxDisable(pAC, IoC, Port);
+		}
+		else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+				 pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR) {
+			/*
+			 * Enable flushing of non ASF packets;
+			 * required, because MAC is not disabled
+			 */
+			SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T),
+				RXMF_TCTL_MACSEC_FLSH_ENA);
+		}
+
+		/* stop both transmit queues */
+		if (pPrt->PXSQSize != 0) {
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop);
+		}
+
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop);
+
+		/* If the BMU is in reset, CSR_STOP will terminate immediately */
+
+		/* get current value of timestamp timer */
+		StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+		ToutCnt = 0;
+
+		TimeOut = HW_MS_TO_TICKS(pAC, SK_TICKS_PER_SEC / 18);
+
+		do {
+			XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
+
+			if (HW_SYNC_TX_SUPPORTED(pAC)) {
+				XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
+			}
+			else {
+				XsCsr = XaCsr;
+			}
+
+			if (SkHwGetTimeDelta(pAC, IoC, StartTime) > TimeOut) {
+				/*
+				 * Timeout of 1/18 second reached.
+				 * This needs to be checked at 1/18 sec only.
+				 */
+				ToutCnt++;
+				if (ToutCnt > 1) {
+					/*
+					 * If BMU stop doesn't terminate, we assume that
+					 * we have a stable state and can reset the BMU,
+					 * the Prefetch Unit, and RAM buffer now.
+					 */
+					break;			/* ===> leave do/while loop here */
+				}
+				/*
+				 * Cache incoherency workaround: assume a start command
+				 * has been lost while sending the frame.
+				 */
+
+				/* get current value of timestamp timer */
+				StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+				if (pPrt->PXSQSize != 0 && (XsCsr & CsrStop) != 0) {
+					SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
+				}
+
+				if ((XaCsr & CsrStop) != 0) {
+					SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
+				}
+
+				/*
+				 * After the previous operations the X(s|a)Csr does no
+				 * longer contain the proper values
+				 */
+				XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
+
+				if (HW_SYNC_TX_SUPPORTED(pAC)) {
+					XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
+				}
+				else {
+					XsCsr = XaCsr;
+				}
+			}
+		} while (((XsCsr & CsrTest) != CsrIdle ||
+				  (XaCsr & CsrTest) != CsrIdle));
+
+		if (pAC->GIni.GIAsfEnabled) {
+
+			pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
+				SK_PRT_RESET;
+		}
+		else {
+			/* Reset the MAC depending on the RstMode */
+			if (RstMode == SK_SOFT_RST || pAC->GIni.GIDontInitPhy) {
+
+				SkMacSoftRst(pAC, IoC, Port);
+			}
+			else {
+#ifdef SK_DIAG
+				if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
+					pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {
+
+					pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;
+
+					/* set GPHY Control reset */
+					SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
+				}
+				else {
+
+					SkMacHardRst(pAC, IoC, Port);
+				}
+#else /* !SK_DIAG */
+				SkMacHardRst(pAC, IoC, Port);
+#endif /* !SK_DIAG */
+			}
+		}
+
+		/* disable Force Sync bit and Enable Alloc bit */
+		SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
+			TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
+
+		/* Stop Interval Timer and Limit Counter of Tx Arbiter */
+		SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
+		SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
+
+		/* Perform a local reset of the port's Tx path */
+		if (CHIP_ID_YUKON_2(pAC)) {
+			/* Reset the PCI FIFO of the async Tx queue */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
+				BMU_FIFO_RST | BMU_RST_SET);
+
+			/* Reset the Tx prefetch units */
+			SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
+				PREF_UNIT_RST_SET);
+
+			if (pPrt->PXSQSize != 0) {
+				/* Reset the PCI FIFO of the sync Tx queue */
+				SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
+					BMU_FIFO_RST | BMU_RST_SET);
+
+				SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
+					PREF_UNIT_RST_SET);
+			}
+
+#ifdef SK_AVB
+			/* Reset the AVB prefetch units */
+			if (HW_SUP_AVB(pAC)) {
+				/* Resets the prefetch units before it sets the AVB mode */
+				SkYuk2AVBControl(pAC, IoC, Port,
+					SkYuk2AVBModeEnabled(pAC, IoC, Port));
+			}
+#endif /* SK_AVB */
+		}
+#ifndef DISABLE_YUKON_I
+		else {
+			/* Reset the PCI FIFO of the async Tx queue */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
+
+			if (pPrt->PXSQSize != 0) {
+				/* Reset the PCI FIFO of the sync Tx queue */
+				SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
+			}
+		}
+#endif /* !DISABLE_YUKON_I */
+
+		if (HW_IS_RAM_IF_AVAIL(pAC)) {
+			/* Reset the RAM Buffer async Tx queue */
+			SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
+
+			if (pPrt->PXSQSize != 0) {
+				/* Reset the RAM Buffer sync Tx queue */
+				SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
+			}
+		}
+
+		/* do the reset only if ASF is not enabled */
+		if (!pAC->GIni.GIAsfEnabled) {
+			/* Reset Tx MAC FIFO */
+			SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
+		}
+
+		/* set Pause Off */
+		SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
+	}
+
+	if ((Dir & SK_STOP_RX) != 0) {
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			/*
+			 * The RX Stop command will not work for Yukon-2 if the BMU does not
+			 * reach the end of packet and since we can't make sure that we have
+			 * incoming data, we must reset the BMU while it is not during a DMA
+			 * transfer. Since it is possible that the RX path is still active,
+			 * the RX RAM buffer will be stopped first, so any possible incoming
+			 * data will not trigger a DMA. After the RAM buffer is stopped, the
+			 * BMU is polled until any DMA in progress is ended and only then it
+			 * will be reset.
+			 */
+
+			if (HW_IS_RAM_IF_AVAIL(pAC)) {
+				/* disable the RAM Buffer receive queue */
+				SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);
+
+				i = 0xffff;
+				while (--i) {
+					SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &FifoRdShLev);
+					SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &FifoRdLev);
+
+					if (FifoRdShLev == FifoRdLev) {
+						break;
+					}
+				}
+			}
+
+			/*
+			 * If the Rx side is blocked, the above loop cannot terminate.
+			 * But, if there was any traffic it should be terminated, now.
+			 * However, stop the Rx BMU and the Prefetch Unit !
+			 */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
+				BMU_FIFO_RST | BMU_RST_SET);
+			/* reset the Rx prefetch unit */
+			SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
+				PREF_UNIT_RST_SET);
+		}
+#ifndef DISABLE_YUKON_I
+		else {
+			/*
+			 * The RX Stop Command will not terminate if no buffers
+			 * are queued in the RxD ring. But it will always reach
+			 * the Idle state. Therefore we can use this feature to
+			 * stop the transfer of received packets.
+			 */
+			/* stop the port's receive queue */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);
+
+			i = 100;
+			do {
+				RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);
+
+				/* timeout if i==0 (bug fix for #10748) */
+				if (--i == 0) {
+					SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
+						SKERR_HWI_E024MSG);
+					break;
+				}
+			} while ((RxCsr & CsrTest) != CsrIdle);
+			/* The path data transfer activity is fully stopped now */
+
+			/* Perform a local reset of the port's Rx path */
+			/* Reset the PCI FIFO of the Rx queue */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
+		}
+#endif /* !DISABLE_YUKON_I */
+
+		if (HW_IS_RAM_IF_AVAIL(pAC)) {
+			/* Reset the RAM Buffer receive queue */
+			SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
+		}
+
+		if (!pAC->GIni.GIAsfEnabled) {
+			/* Reset Rx MAC FIFO */
+			SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
+		}
+
+#ifndef NDIS_MINIPORT_DRIVER	/* temp. ifndef, remove after PM module rework*/
+#ifndef DISABLE_YUKON_I
+		/* WA for Dev. #4.169 */
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON ||
+			 pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) &&
+			RstMode == SK_HARD_RST) {
+			/* set Link Control reset */
+			SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
+
+			/* clear Link Control reset */
+			SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
+		}
+#endif /* !DISABLE_YUKON_I */
+#endif /* !NDIS_MINIPORT */
+	}
+}	/* SkGeStopPort */
+
+
+/******************************************************************************
+ *
+ *	SkGeInit0() - Level 0 Initialization
+ *
+ * Description:
+ *	- Initialize the BMU address offsets
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeInit0(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	SK_GEPORT *pPrt;
+	int i;
+#ifdef SK_AVB
+	int q;
+#endif /* SK_AVB */
+
+	for (i = 0; i < SK_MAX_MACS; i++) {
+		pPrt = &pAC->GIni.GP[i];
+
+		pPrt->PState = SK_PRT_RESET;
+		pPrt->PPortUsage = SK_RED_LINK;
+		pPrt->PRxQOff = QOffTab[i].RxQOff;
+		pPrt->PXsQOff = QOffTab[i].XsQOff;
+		pPrt->PXaQOff = QOffTab[i].XaQOff;
+
+#ifdef SK_AVB
+		for (q = 0; q < AVB_LE_Q_CNT; q++) {
+			pPrt->PAvbQOffs[q] = QOffTab[i].AvbQOff[q];
+		}
+		for (q = 0; q < AVB_MAC_Q_CNT; q++) {
+			pPrt->PAvbMacQOffs[q] = QOffTab[i].AvbMacQOff[q];
+		}
+		for (q = 0; q <AVB_CLS_CNT; q++) {
+			pPrt->PAvbClsQOffs[q] = QOffTab[i].AvbClsQOff[q];
+		}
+#endif /* SK_AVB */
+
+		pPrt->PCheckPar = SK_FALSE;
+		pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL;
+		pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS;
+		pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS;
+		pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN;
+		pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE;
+		pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
+#ifndef SK_SLIM
+		pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
+			SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
+		pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
+		pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
+		pPrt->PMSCap = 0;
+		pPrt->PLipaAbil = 0;
+#endif /* !SK_SLIM */
+		pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
+		pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO;
+		pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET;
+		pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
+		pPrt->PEnDetMode = SK_FALSE;
+		pPrt->PAutoNegFail = SK_FALSE;
+		pPrt->PHWLinkUp = SK_FALSE;
+		pPrt->PPhyQLink = SK_FALSE;
+		pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
+#ifndef SK_SLIM
+		pPrt->PMacColThres = TX_COL_DEF;
+		pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
+		pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
+		pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
+		pPrt->PMacJamLen = TX_JAM_LEN_DEF;
+		pPrt->PMacDataBlind = DATA_BLIND_DEF;
+		pPrt->PMacIpgData_1G = IPG_DATA_DEF_1000;
+		pPrt->PMacIpgData_FE = IPG_DATA_DEF_10_100;
+		pPrt->PMacLimit4 = SK_FALSE;
+#endif /* !SK_SLIM */
+	}
+
+	pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
+	pAC->GIni.GIChipCap = 0;
+	pAC->GIni.GIPexCapOffs = 0;
+	pAC->GIni.GIDontInitPhy = SK_FALSE;
+	pAC->GIni.GIExtLeFormat = SK_FALSE;
+	pAC->GIni.GIVMainAvail = SK_TRUE;
+#ifndef SK_SLIM
+#ifdef SK_PHY_LP_MODE
+	pAC->GIni.GIGotoD3Cold = SK_FALSE;
+#endif
+	pAC->GIni.GIJumTcpSegSup = SK_FALSE;
+	pAC->GIni.GITxIdxRepThres = 10;
+	pAC->GIni.GINumOfRssKeys = 0;
+#endif /* !SK_SLIM */
+	for (i = 0; i < 4; i++) {
+		pAC->GIni.HwF.Features[i] = 0x00000000;
+		pAC->GIni.HwF.OnMask[i]   = 0x00000000;
+		pAC->GIni.HwF.OffMask[i]  = 0x00000000;
+	}
+
+}	/* SkGeInit0*/
+
+#ifdef SK_PCI_RESET
+/******************************************************************************
+ *
+ *	SkGePciReset() - Reset PCI interface
+ *
+ * Description:
+ *	o Read PCI configuration.
+ *	o Change power state to 3.
+ *	o Change power state to 0.
+ *	o Restore PCI configuration.
+ *
+ * Returns:
+ *	0:	Success.
+ *	1:	Power state could not be changed to 3.
+ */
+static int SkGePciReset(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	int		i;
+	SK_U16	PmCtlSts;
+	SK_U32	Bp1;
+	SK_U32	Bp2;
+	SK_U16	PciCmd;
+	SK_U8	Cls;
+	SK_U8	Lat;
+	SK_U32	ConfigSpace[PCI_CFG_SIZE];
+
+	/*
+	 * Note: Switching to D3 state is like a software reset.
+	 *		 Switching from D3 to D0 is a hardware reset.
+	 *		 We have to save and restore the configuration space.
+	 */
+	for (i = 0; i < PCI_CFG_SIZE; i++) {
+		SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
+	}
+
+	/* the RAM Interface Arbiter is enabled */
+	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
+
+	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
+
+	if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
+		return(1);
+	}
+
+	/* Return to D0 state */
+	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
+
+	/* Check for D0 state */
+	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
+
+	if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
+		return(1);
+	}
+
+	/* Check PCI Config Registers */
+	SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
+	SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
+	SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
+
+	/*
+	 * Compute the location in PCI config space of BAR2
+	 * relativ to the location of BAR1
+	 */
+	if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
+		/* BAR1 is 64 bits wide */
+		i = 8;
+	}
+	else {
+		i = 4;
+	}
+
+	SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
+	SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
+
+	if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
+		Lat != 0) {
+		return(1);
+	}
+
+	/* Restore PCI Config Space */
+	for (i = 1; i < PCI_CFG_SIZE; i++) {
+		SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
+	}
+
+	return(0);
+}	/* SkGePciReset */
+#endif /* SK_PCI_RESET */
+
+
+/******************************************************************************
+ *
+ *	SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
+ *
+ * Description:
+ *	This function collects the available features and required deviation services
+ *	of the adapter and provides these information in the GIHwF struct.
+ *	This information is used as default value and may be overwritten by the driver
+ *	using the SET_HW_FEATURE_MASK() macro in its Init0 phase.
+ *
+ * Notice:
+ *	Using the On and Off Mask:
+ *	Never switch on the same bit in both masks simultaneously.
+ *	However, if doing the Off Mask will win.
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeSetUpSupFeatures(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	int		i;
+	int		LedCfg;
+	SK_U16	Word;
+#ifndef SK_SLIM
+	SK_APP_CONF		*pCfgVal;
+	SK_APP_CONFIG	*pCfgData;
+#endif
+
+	switch (pAC->GIni.GIChipId) {
+	case CHIP_ID_YUKON_EC:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 4;
+		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
+			/* A0/A1 */
+			pAC->GIni.HwF.Features[HW_DEV_LIST] =
+				HWF_WA_DEV_42  | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
+				HWF_WA_DEV_420 | HWF_WA_DEV_423;
+		}
+		/* A0 - A3 */
+		pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_424 |
+			HWF_WA_DEV_425 | HWF_WA_DEV_427 | HWF_WA_DEV_428 |
+			HWF_WA_DEV_463 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
+			HWF_WA_DEV_4152 | HWF_WA_DEV_4167 | HWF_WA_DEV_4222;
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
+		break;
+
+	case CHIP_ID_YUKON_FE:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 4;
+#endif
+		pAC->GIni.HwF.Features[HW_DEV_LIST] =
+			HWF_WA_DEV_427  | HWF_WA_DEV_463  | HWF_WA_DEV_4109 |
+			HWF_WA_DEV_4152 | HWF_WA_DEV_4167 | HWF_WA_DEV_4222;
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
+		break;
+
+	case CHIP_ID_YUKON_XL:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 4;
+		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		pAC->GIni.HwF.Features[HW_DEV_LIST] = HWF_WA_DEV_427 | HWF_WA_DEV_483;
+
+		switch (pAC->GIni.GIChipRev) {
+
+		case CHIP_REV_YU_XL_A0:		/* still needed for Diag */
+			pAC->GIni.HwF.Features[HW_DEV_LIST] |=
+				HWF_WA_DEV_463  | HWF_WA_DEV_472  | HWF_WA_DEV_479 |
+				HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
+			break;
+
+		case CHIP_REV_YU_XL_A1:
+			pAC->GIni.HwF.Features[HW_DEV_LIST] |=
+				HWF_WA_DEV_4109 | HWF_WA_DEV_4115 | HWF_WA_DEV_4152 |
+				HWF_WA_DEV_4167;
+			break;
+
+		case CHIP_REV_YU_XL_A2:
+			pAC->GIni.HwF.Features[HW_DEV_LIST] |=
+				HWF_WA_DEV_4109 | HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
+			break;
+
+		case CHIP_REV_YU_XL_A3:
+			pAC->GIni.HwF.Features[HW_DEV_LIST] |=
+				HWF_WA_DEV_4109 | HWF_WA_DEV_4115;
+			break;
+		}
+		if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_4222;
+		}
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
+		break;
+
+	case CHIP_ID_YUKON_EC_U:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 4;
+#endif
+		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST] =
+				HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
+				HWF_WA_DEV_4217;
+		}
+		else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST] =
+				HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185 |
+				HWF_WA_DEV_4217;
+
+			/* check for Rev. A1 */
+			SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);
+
+			if (Word == 0) {
+				pAC->GIni.HwF.Features[HW_DEV_LIST] |=
+					HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
+			}
+		}
+		else {	/* >= CHIP_REV_YU_EC_U_B0 */
+			pAC->GIni.HwF.Features[HW_DEV_LIST] =
+				HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4217;
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] = HWF_ENA_POW_SAV_W_WOL;
+
+			if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_B1) {
+				pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_NEW_FLOW_CONTROL;
+			}
+		}
+		pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_4222;
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_4216;
+		break;
+
+	case CHIP_ID_YUKON_EX:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 10;
+#endif
+		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EX_A0) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST] =
+				HWF_WA_DEV_4217 | HWF_WA_DEV_LIM_IPV6_RSS | HWF_WA_DEV_53 |
+				HWF_WA_DEV_54 | HWF_WA_DEV_56 | HWF_WA_DEV_4109 |
+				HWF_WA_DEV_4222;
+			pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
+				HWF_WA_DEV_51 | HWF_WA_DEV_4216 | HWF_WA_DEV_515 |
+				HWF_WA_DEV_517 | HWF_WA_DEV_519;
+		}
+		else {
+			if (pAC->GIni.GIChipRev == CHIP_REV_YU_EX_B0) {
+				pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
+					HWF_WA_DEV_510 | HWF_WA_DEV_511 | HWF_WA_DEV_515 |
+					HWF_WA_DEV_517 | HWF_WA_DEV_519;
+			}
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] =
+				HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED |
+				HWF_ENA_POW_SAV_W_WOL | HWF_NEW_FLOW_CONTROL;
+
+			pAC->GIni.HwF.Features[HW_DEV_LIST] = HWF_WA_DEV_4109;
+#ifndef SK_SLIM
+			pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		}
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |=
+			HWF_WA_DEV_4229 | HWF_WA_DEV_548;
+		break;
+
+	case CHIP_ID_YUKON_FE_P:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 10;
+#endif
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
+			HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
+		pAC->GIni.HwF.Features[HW_DEV_LIST] = HWF_WA_DEV_4109;
+
+		if (pAC->GIni.GIChipRev == CHIP_REV_YU_FE2_A0) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
+				HWF_WA_DEV_4229 | HWF_WA_DEV_520 | HWF_WA_DEV_521 |
+				HWF_WA_DEV_547;
+		}
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_548;
+		break;
+
+	case CHIP_ID_YUKON_SUPR:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 10;
+		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
+			HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
+		if (pAC->GIni.GIChipRev == CHIP_REV_YU_SU_A0) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
+				HWF_WA_DEV_4229 | HWF_WA_DEV_542 | HWF_WA_DEV_548 |
+				HWF_WA_DEV_563;
+		}
+		break;
+
+	case CHIP_ID_YUKON_UL_2:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 4;
+		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		pAC->GIni.HwF.Features[HW_DEV_LIST] =
+			HWF_WA_DEV_4109 | HWF_WA_DEV_4217 | HWF_WA_DEV_4222;
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
+			HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
+		break;
+
+	case CHIP_ID_YUKON_OPT:
+	case CHIP_ID_YUKON_PRM:
+	case CHIP_ID_YUKON_OP_2:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfRssKeys = 10;
+		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
+#endif
+		pAC->GIni.HwF.Features[HW_DEV_LIST] =
+			HWF_WA_DEV_4109 | HWF_WA_DEV_4217 | HWF_WA_DEV_4222;
+		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
+			HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
+		if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_PRM) {
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_DO_EEE_ENABLE;
+		}
+
+		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_OPT ||
+			pAC->GIni.GIChipId == CHIP_ID_YUKON_PRM) {
+			pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_563;
+		}
+		break;
+	}
+
+	/* legacy way for LED scheme */
+	LedCfg = CFG_LED_MODE(pAC->GIni.GIHwResInfo);
+
+#ifndef SK_SLIM
+	pCfgVal  = &pAC->GIni.CfgVal;
+	pCfgData = &pAC->GIni.CfgData;
+
+	/* get the Application Configuration Value */
+	SK_IN32(IoC, B2_MAC_3, &pCfgVal->ApplicConfigVal);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Application Configuration: %08lx\n",
+		 pCfgVal->ApplicConfigVal));
+
+	pCfgData->ValidConfiguration = (SK_BOOL)pCfgVal->fields.ValidConfig;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Application Config HI: %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u\n",
+		 pCfgVal->bits.D31, pCfgVal->bits.D30, pCfgVal->bits.D29, pCfgVal->bits.D28,
+		 pCfgVal->bits.D27, pCfgVal->bits.D26, pCfgVal->bits.D25, pCfgVal->bits.D24,
+		 pCfgVal->bits.D23, pCfgVal->bits.D22, pCfgVal->bits.D21, pCfgVal->bits.D20,
+		 pCfgVal->bits.D19, pCfgVal->bits.D18, pCfgVal->bits.D17, pCfgVal->bits.D16));
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Application Config LO: %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u\n",
+		 pCfgVal->bits.D15, pCfgVal->bits.D14, pCfgVal->bits.D13, pCfgVal->bits.D12,
+		 pCfgVal->bits.D11, pCfgVal->bits.D10, pCfgVal->bits.D09, pCfgVal->bits.D08,
+		 pCfgVal->bits.D07, pCfgVal->bits.D06, pCfgVal->bits.D05, pCfgVal->bits.D04,
+		 pCfgVal->bits.D03, pCfgVal->bits.D02, pCfgVal->bits.D01, pCfgVal->bits.D00));
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Application Configuration Valid: %u (LED #%u)\n",
+		 pCfgVal->fields.ValidConfig,
+		 pCfgVal->fields.LED_Scheme));
+
+	if (pCfgData->ValidConfiguration) {
+		/* set the Application Configuration structure */
+		pCfgData->WakeUpSpeedSel	= pCfgVal->fields.WakeUpSpeed;
+		pCfgData->EnergySaveScheme	= pCfgVal->fields.EnergyScheme;
+		pCfgData->LED_SchemeSel		= pCfgVal->fields.LED_Scheme;
+		pCfgData->AutoNegSchemeSel	= pCfgVal->fields.AutoNegScheme;
+
+		pCfgData->DynClockGatingEn	= (SK_BOOL)pCfgVal->fields.DynClockGating;
+		pCfgData->SmartSpeedDownEn	= (SK_BOOL)pCfgVal->fields.SmartSpeed;
+		pCfgData->MonitorSpeedStepEn	= (SK_BOOL)pCfgVal->fields.MonSpeedStep;
+		pCfgData->HW_WakeOnLAN_En		= (SK_BOOL)pCfgVal->fields.HW_WoLAN;
+		pCfgData->WakeFromShutdownEn	= (SK_BOOL)pCfgVal->fields.WakeFromS5;
+		pCfgData->MemoryTypeInternal	= (SK_BOOL)pCfgVal->fields.MemoryType;
+
+#ifndef SK_DIAG
+		/* configure HW-Features accordingly */
+		if (pCfgData->DynClockGatingEn &&
+			pAC->GIni.GIChipId != CHIP_ID_YUKON_FE_P) {
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_D0_CLK_GAT_ENABLE;
+		}
+
+		if (pCfgData->HW_WakeOnLAN_En) {
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_HW_WOL_ENABLE;
+		}
+
+		if (pCfgData->AutoNegSchemeSel > 0) {
+			pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_FORCE_AUTO_NEG;
+		}
+
+		/* set PHY Reverse Auto-negotiation flag for Yukon-Optima and above */
+		if (pCfgData->WakeUpSpeedSel > 1 &&
+			pAC->GIni.GIChipId >= CHIP_ID_YUKON_OPT) {
+			pAC->GIni.GP[MAC_1].PRevAutoNeg = SK_TRUE;
+		}
+#endif /* !SK_DIAG */
+
+		/* new configuration for LED scheme */
+		LedCfg = pCfgData->LED_SchemeSel;
+	}
+#endif /* !SK_SLIM */
+
+	if (LedCfg == CFG_LED_DUAL_ACT_LNK) {
+		/* Dual LED ACT/LNK */
+		pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
+	}
+	else if (LedCfg == CFG_LED_LINK_MUX_P60) {
+		/* LED pin 60 used differently */
+		pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60;
+	}
+	else if (LedCfg == CFG_LED_ACT_OFF_NOTR) {
+		/* Activity LED off if no traffic */
+		pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_NOTR_OFF;
+	}
+	else if (LedCfg == CFG_LED_COMB_ACT_LNK) {
+		/* Combined Activity/Link LED mode */
+		pAC->GIni.GILedBlinkCtrl |= SK_LED_COMB_ACT_LNK;
+	}
+	else if (LedCfg == CFG_LED_HP_SPC_4_LED) {
+		/* HP special 4 LED mode */
+		pAC->GIni.GILedBlinkCtrl |= SK_LED_COMB_ACT_LNK | SK_ACT_LED_NOTR_OFF;
+	}
+
+	/* filter the HW Features using the On and Off Mask */
+	for (i = 0; i < 4; i++) {
+		pAC->GIni.HwF.Features[i] =
+			(pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
+				~pAC->GIni.HwF.OffMask[i];
+	}
+}	/* SkGeSetUpSupFeatures */
+
+
+/******************************************************************************
+ *
+ *	SkGeInit1() - Level 1 Initialization
+ *
+ * Description:
+ *	o Do a software reset.
+ *	o Clear all reset bits.
+ *	o Verify that the detected hardware is present.
+ *	  Return an error if not.
+ *	o Get the hardware configuration
+ *		+ Read the number of MACs/Ports.
+ *		+ Read the RAM size.
+ *		+ Read the PCI Revision Id.
+ *		+ Find out the adapters host clock speed
+ *		+ Read and check the PHY type
+ *
+ * Returns:
+ *	0:	success
+ *	5:	Unexpected Chip Id detected
+ *	6:	HW self test failed
+ */
+static int SkGeInit1(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	SK_U8	Byte;
+	SK_U8	ChipId;
+	SK_U8	ChipRev;
+	SK_U8	MacCfg;
+	SK_U16	Word;
+	SK_U32	CtrlStat;
+#ifndef SK_SLIM
+	SK_U32	VauxAvail;
+#endif /* !SK_SLIM */
+	SK_U32	DWord;
+	SK_U32	Our1;
+#ifndef SK_DIAG
+	SK_U32	Our5;
+#endif /* !SK_DIAG */
+	SK_U32	PowerDownBit;
+	SK_BOOL	FiberType;
+	SK_GEPORT *pPrt;
+	int		RetVal;
+	int		i, j;
+	int		mem_mapped;
+
+	RetVal = 0;
+	ChipId = 0;
+
+#ifndef VCPU
+#if (defined(SK_SLIM) || (defined(SK_DIAG) && !defined(SK_MEM_MAPPED_IO)))
+	mem_mapped = 0;
+#else	/* !SK_SLIM && (!SK_DIAG || SK_MEM_MAPPED_IO) */
+	mem_mapped = 1;
+#endif	/* !SK_SLIM && (!SK_DIAG || SK_MEM_MAPPED_IO) */
+#else	/* VCPU */
+	mem_mapped = pAC->sw.mem_mapped;
+#endif	/* VCPU */
+
+	if (!mem_mapped) {
+#if !defined(SK_ASF) && !defined(MV_INCLUDE_SDK_SUPPORT)
+#ifdef XXX
+		/* disable static clock gating */
+#ifndef VCPU
+		fprintf(stderr, "Need to determine the chip type.\n");
+		exit(1);
+#else	/* VCPU */
+		SimPrintf("Need to determine the chip type.\n");
+#endif	/* VCPU */
+#endif /* XXX */
+		if (0) {
+			/* for Yukon-Optima 2 and later */
+			SkPciWriteCfgDWord(pAC, PCI_OUR_REG_3, 0);
+			/* for chips before Yukon-Optima 2 */
+			SkPciWriteCfgDWord(pAC, PCI_OUR_REG_3 % 0x300, 0);
+		}
+		else {
+			SkPciWriteCfgDWord(pAC, PCI_OUR_REG_3 % 0x300, 0);
+		}
+#endif /* !SK_ASF && !MV_INCLUDE_SDK_SUPPORT */
+	}
+	else {
+		/* get MAC Config. / Chip Ident. & Revision */
+		SK_IN16(IoC, B2_MAC_CFG, &Word);
+
+		ChipId = (SK_U8)(Word >> 8);
+
+		/* save Chip Identification */
+		pAC->GIni.GIChipId = ChipId;
+
+		if (ChipId >= CHIP_ID_YUKON_EC_U) {
+			/* Enable all clocks, otherwise the system will hang */
+			/* Do not use PCI_C here */
+			SK_OUT32(IoC, Y2_CFG_SPC + PCI_OUR_REG_3 % 0x300, 0);
+		}
+	}
+
+	/* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
+	SK_IN32(IoC, B0_CTST, &CtrlStat);
+
+#ifdef SK_PCI_RESET
+	(void)SkGePciReset(pAC, IoC);
+#endif /* SK_PCI_RESET */
+
+	/* release the SW-reset */
+	/* Important: SW-reset has to be cleared here, to ensure
+	 * the CHIP_ID can be read I/O-mapped based, too -
+	 * remember the RAP register can only be written if SW-reset is cleared.
+	 */
+	SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
+
+	if (!mem_mapped) {
+		/* get MAC Config. / Chip Ident. & Revision */
+		SK_IN16(IoC, B2_MAC_CFG, &Word);
+
+		ChipId = (SK_U8)(Word >> 8);
+
+		/* save Chip Identification */
+		pAC->GIni.GIChipId = ChipId;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("MAC_CFG: 0x%04X, B0_CTST: 0x%08lX\n", Word, CtrlStat));
+
+	pAC->GIni.GIAsfEnabled = SK_FALSE;
+
+	/* get MAC Configuration / Chip Revision Number */
+	MacCfg = (SK_U8)Word;
+
+	/* get Chip Revision Number */
+	ChipRev = (MacCfg & CFG_CHIP_R_MSK) >> 4;
+
+	/* save Chip Revision */
+	pAC->GIni.GIChipRev = ChipRev;
+
+
+	/* ASF support only for Yukon-2 */
+	if (ChipId >= CHIP_ID_YUKON_XL && ChipId <= CHIP_ID_YUKON_SUPR) {
+
+#if defined(SK_ASF) || defined(SK_SLIM) || defined(MV_INCLUDE_SDK_SUPPORT)
+		if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
+			/* do the SW-reset only if ASF is not enabled */
+			pAC->GIni.GIAsfEnabled = SK_TRUE;
+		}
+#else /* !SK_ASF && !SK_SLIM && !MV_INCLUDE_SDK_SUPPORT */
+
+		/* put ASF system in reset state */
+		if (ChipId == CHIP_ID_YUKON_EX || ChipId == CHIP_ID_YUKON_SUPR) {
+
+			/* stop the watchdog */
+			SK_OUT32(IoC, CPU_WDOG, 0);
+
+			/* Do not touch bit 5..3 */
+			SK_IN16(IoC, B28_Y2_ASF_STAT_CMD, &Word);
+
+			pAC->GIni.GIAsfRunning =
+				((Word & HCU_CCSR_UC_STATE_MSK) == HCU_CCSR_ASF_RUNNING);
+
+			Word &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
+				HCU_CCSR_UC_STATE_MSK);
+
+			/*
+			 * CPU clock divider shouldn't be used because
+			 * - ASF firmware may malfunction
+			 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
+			 */
+			if ((Word & HCU_CCSR_CPU_CLK_DIVIDE_MSK) != 0) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+					("CPU Clock Divider bits are set (0x%x), cleared now\n", Word));
+				Word &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
+			}
+
+			SK_OUT16(IoC, B28_Y2_ASF_STAT_CMD, Word);
+			/* stop the watchdog */
+			SK_OUT32(IoC, CPU_WDOG, 0);
+		}
+		else {	/* Yukon-EC / Yukon-2 */
+			SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
+
+			pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;
+
+			SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
+		}
+
+		/* disable ASF Unit */
+		SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
+#endif /* !SK_ASF && !SK_SLIM && !MV_INCLUDE_SDK_SUPPORT */
+	}
+
+	if (!pAC->GIni.GIAsfEnabled) {
+		/* Yukon-2: required for Diag and Power Management */
+		/* set the SW-reset */
+		SK_OUT8(IoC, B0_CTST, CS_RST_SET);
+
+		/* release the SW-reset */
+		SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
+	}
+
+	/* enable Config Write */
+	SK_TST_MODE_ON(IoC);
+
+	if (1) {
+		/* reset all error bits in the PCI STATUS register */
+		/*
+		 * Note: PCI Cfg cycles cannot be used, because they are not
+		 *		 available on some platforms after 'boot time'.
+		 */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), &Word);
+		SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
+	}
+	else {
+		SkPciReadCfgWord(pAC, PCI_STATUS, &Word);
+		SkPciWriteCfgWord(pAC, PCI_STATUS, Word | (SK_U16)PCI_ERRBITS);
+	}
+
+	/* release Master Reset */
+	SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
+
+#ifdef CLK_RUN
+	CtrlStat |= CS_CLK_RUN_ENA;
+
+	/* restore CLK_RUN bits */
+	SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
+		(CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
+#endif /* CLK_RUN */
+
+	if (ChipId >= CHIP_ID_YUKON_XL && ChipId <= CHIP_ID_YUKON_OP_2) {
+
+		pAC->GIni.GIYukon2 = SK_TRUE;
+		pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
+
+		pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;
+
+#ifndef SK_SLIM
+		VauxAvail = Y2_VAUX_AVAIL;
+
+		/* check if VMAIN is available */
+		if ((CtrlStat & Y2_VMAIN_AVAIL) == 0) {
+			pAC->GIni.GIVMainAvail = SK_FALSE;
+		}
+#endif /* !SK_SLIM */
+
+		/* needed before using PEX_CAP_REGS() macro */
+		if ((ChipId == CHIP_ID_YUKON_EX && ChipRev != CHIP_REV_YU_EX_A0) ||
+			ChipId >= CHIP_ID_YUKON_FE_P) {
+
+			pAC->GIni.GIPexCapOffs = PEX_CAP_REG_OFFS;
+		}
+
+		if (1) {
+			SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_STATUS), &DWord);
+		}
+		else {
+			SkPciReadCfgDWord(pAC, PCI_OUR_STATUS, &DWord);
+		}
+
+		if ((DWord & PCI_OS_PCI_X) != 0) {
+#ifndef SK_SLIM
+			/* this is a PCI / PCI-X bus */
+			if ((DWord & PCI_OS_PCIX) != 0) {
+				/* this is a PCI-X bus */
+				pAC->GIni.GIPciBus = SK_PCIX_BUS;
+
+				/* PCI-X is always 64-bit wide */
+				pAC->GIni.GIPciSlot64 = SK_TRUE;
+
+				pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
+			}
+			else {
+				/* this is a conventional PCI bus */
+				pAC->GIni.GIPciBus = SK_PCI_BUS;
+
+				SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_2), &Word);
+
+				/* check if 64-bit width is used */
+				pAC->GIni.GIPciSlot64 = (SK_BOOL)
+					(((DWord & PCI_OS_PCI64B) != 0) &&
+					((Word & PCI_USEDATA64) != 0));
+
+				/* check if 66 MHz PCI Clock is active */
+				pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
+			}
+#endif /* !SK_SLIM */
+		}
+		else {
+			/* this is a PEX bus */
+			pAC->GIni.GIPciBus = SK_PEX_BUS;
+
+			/* clear any PEX errors */
+			if (1) {
+				SK_OUT32(IoC, PCI_C2(pAC, IoC, PEX_UNC_ERR_STAT), ALL_32_BITS);
+				SK_IN32(IoC, PCI_C2(pAC, IoC, PEX_UNC_ERR_STAT), &DWord);
+			}
+			else {
+				SkPciWriteCfgDWord(pAC, PEX_UNC_ERR_STAT, ALL_32_BITS);
+				SkPciReadCfgDWord(pAC, PEX_UNC_ERR_STAT, &DWord);
+			}
+
+			if ((DWord & PEX_RX_OV) != 0) {
+				/* Dev. #4.205 occurred */
+				pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
+				pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
+			}
+
+			if (1) {
+				SK_IN16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_STAT)), &Word);
+			}
+			else {
+				SkPciReadCfgWord(pAC, PEX_CAP_REGS(PEX_LNK_STAT), &Word);
+			}
+
+			pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
+
+			/* read PEX Link Control */
+			if (1) {
+				SK_IN16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_CTRL)),
+					&pAC->GIni.GIPexLinkCtrl);
+			}
+			else {
+				SkPciReadCfgWord(pAC, PEX_CAP_REGS(PEX_LNK_CTRL),
+					&pAC->GIni.GIPexLinkCtrl);
+			}
+		}
+		/*
+		 * Yukon-2 chips family has a different way of providing
+		 * the number of MACs available
+		 */
+		pAC->GIni.GIMacsFound = 1;
+
+		/* get HW Resources */
+		SK_IN8(IoC, B2_Y2_HW_RES, &Byte);
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			/*
+			 * OEM config value is overwritten and should not
+			 * be used for Yukon-2
+			 */
+			pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;
+
+#ifndef SK_SLIM
+			if (ChipId == CHIP_ID_YUKON_EC_U ||
+				ChipId == CHIP_ID_YUKON_EX ||
+				ChipId >= CHIP_ID_YUKON_FE_P) {
+				/* LED Configuration is stored in GP_IO */
+				SK_IN8(IoC, B2_GP_IO, &Byte);
+			}
+#endif /* !SK_SLIM */
+		}
+
+		/* save HW Resources / Application Information */
+		pAC->GIni.GIHwResInfo = Byte;
+
+		if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
+
+			SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);
+
+			if (!(Byte & Y2_STATUS_LNK2_INAC)) {
+				/* Link 2 activ */
+				pAC->GIni.GIMacsFound++;
+			}
+		}
+
+#ifdef VCPU
+		if (ChipId == CHIP_ID_YUKON_XL) {
+			/* temporary WA for reported number of links */
+			pAC->GIni.GIMacsFound = 2;
+		}
+#endif /* VCPU */
+
+		if (pAC->GIni.GIMacsFound > 1) {
+			/* allow IRQ from Port 2 only on dual port adapters */
+			pAC->GIni.GIValIrqMask |= Y2_IS_L2_MASK;
+		}
+
+		pAC->GIni.GIChipCap = MacCfg & 0x0f;
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		pAC->GIni.GIYukon2 = SK_FALSE;
+		pAC->GIni.GIValIrqMask = IS_ALL_MSK;
+		pAC->GIni.GIValHwIrqMask = 0;	/* not activated */
+
+#ifndef SK_SLIM
+		VauxAvail = CS_VAUX_AVAIL;
+#endif /* !SK_SLIM */
+
+		pAC->GIni.GIMacsFound = (MacCfg & CFG_SNG_MAC) ? 1 : 2;
+	}
+#endif /* !DISABLE_YUKON_I */
+
+#ifndef SK_DIAG
+	if (ChipId == CHIP_ID_YUKON_XL && ChipRev == CHIP_REV_YU_XL_A0) {
+		/* Yukon-2 Chip Rev. A0 */
+		return(6);
+	}
+#endif /* !SK_DIAG */
+
+	/* read the adapters RAM size */
+	SK_IN8(IoC, B2_E_0, &Byte);
+
+	pAC->GIni.GIYukonLite = SK_FALSE;
+	pAC->GIni.GIVauxAvail = SK_FALSE;
+
+	if (ChipId < CHIP_ID_YUKON || ChipId > CHIP_ID_YUKON_OP_2) {
+		/* unexpected Chip Id */
+		return(5);
+	}
+
+	pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
+
+#ifndef SK_SLIM
+	pAC->GIni.GIRamOffs = 0;
+
+	/* WA for Yukon chip Rev. A0 */
+	pAC->GIni.GIWolOffs = (ChipId == CHIP_ID_YUKON && ChipRev == 0) ?
+		WOL_REG_OFFS : 0;
+
+	/* get PM Capabilities of PCI config space */
+	if (1) {
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_PM_CAP_REG), &Word);
+	}
+	else {
+		SkPciReadCfgWord(pAC, PCI_PM_CAP_REG, &Word);
+	}
+
+	/* check if VAUX is available */
+	if (((CtrlStat & VauxAvail) != 0) &&
+		/* check also if PME from D3cold is set */
+		((Word & PCI_PME_D3C_SUP) != 0)) {
+		/* set entry in GE init struct */
+		pAC->GIni.GIVauxAvail = SK_TRUE;
+	}
+#endif /* !SK_SLIM */
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+
+		if (ChipId == CHIP_ID_YUKON_LITE) {
+			/* this is Rev. A1 */
+			pAC->GIni.GIYukonLite = SK_TRUE;
+		}
+#ifndef SK_SLIM
+		else {
+			/* save Flash-Address Register */
+			SK_IN32(IoC, B2_FAR, &DWord);
+
+			/* test Flash-Address Register */
+			SK_OUT8(IoC, B2_FAR + 3, 0xff);
+			SK_IN8(IoC, B2_FAR + 3, &Byte);
+
+			if (Byte != 0) {
+				/* this is Rev. A0 */
+				pAC->GIni.GIYukonLite = SK_TRUE;
+
+				/* restore Flash-Address Register */
+				SK_OUT32(IoC, B2_FAR, DWord);
+			}
+		}
+#endif /* !SK_SLIM */
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		/* Check for CLS = 0 (dev. #4.55) */
+		if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
+			/* PCI and PCI-X */
+			SK_IN8(IoC, PCI_C2(pAC, IoC, PCI_CACHE_LSZ), &Byte);
+
+			if (Byte == 0) {
+				/* set CLS to 2 if configured to 0 */
+				SK_OUT8(IoC, PCI_C2(pAC, IoC, PCI_CACHE_LSZ), 2);
+			}
+
+			if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
+				/* set Cache Line Size opt. */
+				SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &DWord);
+				DWord |= PCI_CLS_OPT;
+				SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), DWord);
+			}
+		}
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	/* GeCommon also used in ASF firmware: VMain may not be available */
+	if (pAC->GIni.GIVMainAvail) {
+		/* switch power to VCC (WA for VAUX problem) */
+		SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
+			PC_VAUX_OFF | PC_VCC_ON));
+#ifdef DEBUG
+		SK_IN32(IoC, B0_CTST, &DWord);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Ctrl/Stat & Switch: 0x%08lX\n", DWord));
+#endif /* DEBUG */
+	}
+
+	Byte = 0;
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		switch (ChipId) {
+		/* PEX adapters work with different host clock */
+		case CHIP_ID_YUKON_EC:
+		case CHIP_ID_YUKON_EC_U:
+		case CHIP_ID_YUKON_EX:
+		case CHIP_ID_YUKON_SUPR:
+		case CHIP_ID_YUKON_UL_2:
+		case CHIP_ID_YUKON_OPT:
+		case CHIP_ID_YUKON_PRM:
+		case CHIP_ID_YUKON_OP_2:
+			/* Yukon-EC and later work with 125 MHz host clock */
+			pAC->GIni.GIHstClkFact = SK_FACT_125;
+			break;
+		case CHIP_ID_YUKON_FE:
+			/* Yukon-FE works with 100 MHz host clock */
+			pAC->GIni.GIHstClkFact = SK_FACT_100;
+			break;
+		case CHIP_ID_YUKON_FE_P:
+			/* Yukon-FE+ works with 50 MHz core clock */
+			pAC->GIni.GIHstClkFact = SK_FACT_50;
+			break;
+		case CHIP_ID_YUKON_XL:
+			/* all Yukon-2 adapters work with 156 MHz host clock */
+			pAC->GIni.GIHstClkFact = 2 * SK_FACT_78;
+
+			if (ChipRev > CHIP_REV_YU_XL_A1) {
+				/* enable bits are inverted */
+				Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+					Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+					Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
+			}
+			break;
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006,
+				SKERR_HWI_E006MSG);
+		}
+
+		pAC->GIni.GIPollTimerVal =
+			SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100;
+
+		/* set power down bit */
+		PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
+
+		/* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */
+		SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
+
+		/* enable MAC/PHY, PCI and Core Clock for both Links */
+		SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		/* YUKON adapters work with 78 MHz host clock */
+		pAC->GIni.GIHstClkFact = SK_FACT_78;
+
+		pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;	/* 215 ms */
+
+		/* read the Interrupt source */
+		SK_IN32(IoC, B0_ISRC, &DWord);
+
+		if ((DWord & IS_HW_ERR) != 0) {
+			/* read the HW Error Interrupt source */
+			SK_IN32(IoC, B0_HWE_ISRC, &DWord);
+
+			if ((DWord & IS_IRQ_SENSOR) != 0) {
+				/* disable HW Error IRQ */
+				pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
+			}
+		}
+		/* set power down bit */
+		PowerDownBit = PCI_PHY_COMA;
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	/* call before using first time HW_FEATURE macro */
+	SkGeSetUpSupFeatures(pAC, IoC);
+
+	if (1) {
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &Our1);
+	}
+	else {
+		SkPciReadCfgDWord(pAC, PCI_OUR_REG_1, &Our1);
+	}
+
+	Our1 &= ~PowerDownBit;
+
+	if (ChipId == CHIP_ID_YUKON_XL && ChipRev > CHIP_REV_YU_XL_A1) {
+		/* deassert Low Power for 1st PHY */
+		Our1 |= PCI_Y2_PHY1_COMA;
+
+		if (pAC->GIni.GIMacsFound > 1) {
+			/* deassert Low Power for 2nd PHY */
+			Our1 |= PCI_Y2_PHY2_COMA;
+		}
+	}
+	else if (ChipId == CHIP_ID_YUKON_EC_U ||
+			 ChipId == CHIP_ID_YUKON_EX ||
+			 ChipId >= CHIP_ID_YUKON_FE_P) {
+
+		/* enable all clocks */
+		/* PCI_OUR_REG_3 is set at the top of the function */
+
+#ifndef SK_DIAG
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5), &Our5);
+
+		if (HW_FEATURE(pAC, HWF_D0_CLK_GAT_ENABLE)) {
+			/* set also bit 13 as WA for dev.#5.60 */
+			Our5 |= P_REL_EN_RX_DV;
+		}
+		else {
+			/* disable clock gating */
+			SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &DWord);
+
+#ifdef SK_ASPM_DISABLED
+			DWord &= P_PIN63_LINK_LED_ENA;
+#else /* !SK_ASPM_DISABLED */
+			DWord &= P_ASPM_CONTROL_MSK;
+#endif /* !SK_ASPM_DISABLED */
+
+			/* set all bits to 0 except bits 15..12 and 8 */
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), DWord);
+
+			/* set all bits to 0 except bits 28 & 27 */
+			Our5 &= P_CTL_TIM_VMAIN_AV_MSK;
+		}
+
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5), Our5);
+#endif /* !SK_DIAG */
+
+		/* set all bits to 0 */
+		if (1) {
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_CFG_REG_1), 0);
+		}
+		else {
+			SkPciWriteCfgDWord(pAC, PCI_CFG_REG_1, 0);
+		}
+
+#if !defined(SK_SLIM) && !defined(SK_DIAG)
+		if (!pAC->GIni.GIAsfEnabled) {
+			/* enable HW WOL */
+			SK_OUT16(IoC, B0_CTST, Y2_HW_WOL_ON);
+		}
+#endif /* !SK_SLIM && !SK_DIAG */
+
+		/* Enable workaround for dev. #4.107 on Yukon-Ultra & Extreme */
+		SK_IN32(IoC, B2_GP_IO, &DWord);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("PCI_OUR_REG_1: 0x%08lX, GP_IO: 0x%08lX\n", Our1, DWord));
+
+		SK_OUT32(IoC, B2_GP_IO, DWord | GLB_GPIO_STAT_RACE_DIS);
+
+		if (ChipId == CHIP_ID_YUKON_UL_2 || ChipId == CHIP_ID_YUKON_OPT) {
+			/* set TWSI timeout value to maximum */
+			if (1) {
+				SK_IN16(IoC, PCI_C2(pAC, IoC, OTP_LDR_CTRL), &Word);
+				Word |= OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_MSK;
+				SK_OUT16(IoC, PCI_C2(pAC, IoC, OTP_LDR_CTRL), Word);
+			}
+			else {
+				SkPciReadCfgWord(pAC, OTP_LDR_CTRL, &Word);
+				Word |= OTP_LDR_CTRL_EEPROM_TIMEOUT_VAL_MSK;
+				SkPciWriteCfgWord(pAC, OTP_LDR_CTRL, Word);
+			}
+		}
+	}
+
+#ifdef DEBUG
+	/* check for link through GPHY Control */
+	SK_IN32(IoC, GPHY_CTRL, &DWord);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("GPHY_CTRL: 0x%08lX\n", DWord));
+
+	if ((DWord & GPC_RST_CLR) != 0 && (DWord & GPC_PHY_LINK_UP) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("PHY Link Up\n"));
+	}
+#endif /* DEBUG */
+
+	/* release PHY from PowerDown/COMA Mode */
+	if (1) {
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), Our1);
+	}
+	else {
+		SkPciWriteCfgDWord(pAC, PCI_OUR_REG_1, Our1);
+	}
+
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+		if (!pAC->GIni.GIAsfEnabled && !pAC->GIni.GIDontInitPhy) {
+			/* set Link Control reset */
+			SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
+		}
+
+		/* clear Link Control reset */
+		SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
+	}
+
+	/* disable Config Write */
+	SK_TST_MODE_OFF(IoC);
+
+	/* get the Connector & PMD type */
+	SK_IN16(IoC, B2_CONN_TYP, &Word);
+
+#ifndef SK_SLIM
+	/* save the Connector type */
+	pAC->GIni.GIConTyp = (SK_U8)Word;
+
+	if (!CHIP_ID_YUKON_2(pAC)) {
+		/* this is a conventional PCI bus */
+		pAC->GIni.GIPciBus = SK_PCI_BUS;
+
+		/* check if 64-bit PCI Slot is present */
+		pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
+
+		/* check if 66 MHz PCI Clock is active */
+		pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
+	}
+
+	/* read PCI HW Revision Id. */
+	if (1) {
+		SK_IN8(IoC, PCI_C2(pAC, IoC, PCI_REV_ID), &pAC->GIni.GIPciHwRev);
+	}
+	else {
+		SkPciReadCfgByte(pAC, PCI_REV_ID, &pAC->GIni.GIPciHwRev);
+	}
+#endif /* !SK_SLIM */
+
+	Byte = (SK_U8)(Word >> 8);
+
+	/* save the PMD type */
+	pAC->GIni.GIPmdTyp = Byte;
+
+	FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P');
+
+	pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' ||
+		(pAC->GIni.GIYukon2 && !FiberType));
+
+	/* read the PHY type */
+	SK_IN8(IoC, B2_E_1, &Byte);
+
+	Byte &= 0x0f;	/* the PHY type is stored in the lower nibble */
+
+	if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) &&
+		!FiberType) {
+		/* if this field is not initialized */
+		Byte = (SK_U8)SK_PHY_MARV_COPPER;
+
+		pAC->GIni.GICopperType = SK_TRUE;
+	}
+
+	if (!pAC->GIni.GICopperType) {
+		Byte = (SK_U8)SK_PHY_MARV_FIBER;
+	}
+
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+#ifdef VCPU
+		SK_U32	MacAddr1;
+		SK_U16	MacAddr2;
+
+		SK_IN32(IoC, B2_MAC_1 + 8 * i, &MacAddr1);
+		if (0 == MacAddr1) {
+			SK_IN16(IoC, B2_MAC_1 + 8 * i + 4, &MacAddr2);
+			if (0 == MacAddr2) {
+				/* Enable Config Write. */
+				SK_TST_MODE_ON(IoC);
+
+				SK_OUT32(IoC, B2_MAC_1 + 8 * i, 0x125A0000);
+				SK_OUT16(IoC, B2_MAC_1 + 8 * i + 4, 0x5634 + 0x0100 * i);
+
+				/* Disable Config Write. */
+				SK_TST_MODE_OFF(IoC);
+			}
+		}
+#endif /* VCPU */
+
+		pPrt = &pAC->GIni.GP[i];
+
+		pPrt->PhyType = (int)Byte;
+
+		pPrt->PhyAddr = PHY_ADDR_MARV;
+
+		/* get the MAC addresses */
+		for (j = 0; j < 3; j++) {
+			SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]);
+		}
+
+		if (pAC->GIni.GICopperType) {
+
+			if (ChipId == CHIP_ID_YUKON_FE ||
+				ChipId == CHIP_ID_YUKON_FE_P ||
+				(ChipId == CHIP_ID_YUKON_EC && pAC->GIni.GIChipCap == 2)) {
+
+				pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS |
+					SK_LSPEED_CAP_10MBPS);
+
+				pAC->GIni.GIRamSize = 4;
+			}
+			else {
+				pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS |
+					SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS |
+					SK_LSPEED_CAP_AUTO);
+			}
+
+			pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
+
+#ifndef SK_SLIM
+			pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
+				SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
+#endif
+		}
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+			("PHY type: %d  PHY addr: %04x\n",
+			 Byte, pPrt->PhyAddr));
+	}
+
+	if (ChipId <= CHIP_ID_YUKON_XL) {
+		/* clear TWSI IRQ */
+		SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
+	}
+
+	/* get MAC Type & set function pointers dependent on */
+#ifndef SK_SLIM
+	pAC->GIni.GINumOfPattern = SK_NUM_WOL_PATTERN;
+#endif
+	switch (ChipId) {
+	case CHIP_ID_YUKON_EX:
+	case CHIP_ID_YUKON_SUPR:
+		pAC->GIni.GIExtLeFormat = SK_TRUE;
+#ifndef SK_SLIM
+		if (ChipId == CHIP_ID_YUKON_EX) {
+			pAC->GIni.GINumOfPattern += 2;
+		}
+		else {
+			pAC->GIni.GINumOfPattern += 7;	/* Yukon-Supreme got 14 patterns */
+		}
+#endif /* !SK_SLIM */
+		/* bypass MACSec unit */
+		SK_OUT16(IoC, MAC_CTRL, MAC_CTRL_BYP_MACSECRX_ON |
+			MAC_CTRL_BYP_MACSECTX_ON | MAC_CTRL_BYP_RETR_ON);
+
+		if (ChipId == CHIP_ID_YUKON_SUPR && ChipRev > CHIP_REV_YU_SU_B0) {
+			/* enable MACSec clock gating */
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_3), P_CLK_MACSEC_DIS);
+		}
+		break;
+
+	case CHIP_ID_YUKON_FE_P:
+		pAC->GIni.GIExtLeFormat = SK_TRUE;
+	case CHIP_ID_YUKON_UL_2:
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfPattern -= 1;
+#endif
+		break;
+
+	case CHIP_ID_YUKON_OPT:
+	case CHIP_ID_YUKON_PRM:
+	case CHIP_ID_YUKON_OP_2:
+		pAC->GIni.GIExtLeFormat = SK_TRUE;
+#ifndef SK_SLIM
+		pAC->GIni.GINumOfPattern += 1;
+#endif
+
+		if (ChipId == CHIP_ID_YUKON_OPT && ChipRev == 0) {
+			/* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
+			SK_OUT32(IoC, Y2_PEX_PHY_DATA, (0x80UL << 16) | BIT_7);
+
+			/* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
+			Word = 10;
+
+			/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
+			SK_OUT32(IoC, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
+		}
+		else {
+			/* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
+			Word = 3;
+		}
+
+		Word <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
+
+		Word |= (SK_U16)PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
+
+		/* enable Config Write */
+		SK_TST_MODE_ON(IoC);
+
+		/* reset PHY Quick Link Detect */
+		if (1) {
+			SK_OUT16(IoC, PCI_C2(pAC, IoC, PSM_CONFIG_REG4), Word);
+		}
+		else {
+			SkPciWriteCfgWord(pAC, PSM_CONFIG_REG4, Word);
+		}
+
+#ifndef SK_DIAG
+		/* enable PHY Quick Link */
+		pAC->GIni.GIValIrqMask |= Y2_IS_PHY_QLNK;
+
+		/* check if PSMv2 was running before */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PSM_CONFIG_REG3), &Word);
+
+		if ((Word & PEX_LC_ASPM_LC_L1) != 0) {
+			/* restore the PCIe Link Control register */
+			SK_OUT16(IoC, PCI_C2(pAC, IoC, PCIE_LNKCTRL), Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Restored PCIE_LNKCTRL: 0x%04X\n", Word));
+		}
+#endif /* !SK_DIAG */
+
+		/* disable Config Write */
+		SK_TST_MODE_OFF(IoC);
+
+		break;
+	}
+
+#ifndef SK_SLIM
+	pAC->GIni.GIMacType = SK_MAC_GMAC;
+
+	pAC->GIni.GIFunc.pFnMacUpdateStats	= SkGmUpdateStats;
+	pAC->GIni.GIFunc.pFnMacStatistic	= SkGmMacStatistic;
+	pAC->GIni.GIFunc.pFnMacResetCounter	= SkGmResetCounter;
+	pAC->GIni.GIFunc.pFnMacOverflow		= SkGmOverflowStatus;
+#endif /* !SK_SLIM */
+
+#ifdef SK_DIAG
+	pAC->GIni.GIFunc.pFnMacPhyRead		= SkGmPhyRead;
+	pAC->GIni.GIFunc.pFnMacPhyWrite		= SkGmPhyWrite;
+#else /* SK_DIAG */
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+		pAC->GIni.GIFunc.pSkGeSirqIsr	= SkYuk2SirqIsr;
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		pAC->GIni.GIFunc.pSkGeSirqIsr	= SkGeYuSirqIsr;
+	}
+#endif /* !DISABLE_YUKON_I */
+#endif /* !SK_DIAG */
+
+#ifdef SPECIAL_HANDLING
+	if (ChipId == CHIP_ID_YUKON) {
+		/* check HW self test result */
+		SK_IN8(IoC, B2_E_3, &Byte);
+		if (Byte & B2_E3_RES_MASK) {
+			RetVal = 6;
+		}
+	}
+#endif
+
+	return(RetVal);
+}	/* SkGeInit1 */
+
+
+/******************************************************************************
+ *
+ *	SkGeInit2() - Level 2 Initialization
+ *
+ * Description:
+ *	- start the Blink Source Counter
+ *	- start the Descriptor Poll Timer
+ *	- configure the MAC-Arbiter
+ *	- configure the Packet-Arbiter
+ *	- enable the Tx Arbiters
+ *	- enable the RAM Interface Arbiter
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeInit2(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	SK_U16	Word;
+#if !defined(SK_SLIM) && !defined(SK_DIAG)
+	SK_EVPARA	Para;
+#endif /* !SK_SLIM && !SK_DIAG */
+	int		i;
+
+	/* start the Descriptor Poll Timer */
+	if (pAC->GIni.GIPollTimerVal != 0) {
+		if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
+			pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
+		}
+
+		SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
+
+		SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
+	}
+
+	/* start Time Stamp Timer with LE generation disabled */
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)(GMT_ST_LE_DIS | GMT_ST_START));
+
+	/* enable the Tx Arbiters */
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+		SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
+	}
+
+	/* enable the RAM Interface Arbiter */
+	SkGeInitRamIface(pAC, IoC);
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+
+		if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
+
+			/* enable Config Write */
+			SK_TST_MODE_ON(IoC);
+
+			/* get Max. Read Request Size */
+			if (1) {
+				SK_IN16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_DEV_CTRL)), &Word);
+			}
+			else {
+				SkPciReadCfgWord(pAC, PEX_CAP_REGS(PEX_DEV_CTRL), &Word);
+			}
+
+			/* check for HW-default value of 512 bytes */
+			if ((Word & PEX_DC_MAX_RRS_MSK) == PEX_DC_MAX_RD_RQ_SIZE(2)) {
+				/* change Max. Read Request Size to 2048 bytes */
+				Word &= ~PEX_DC_MAX_RRS_MSK;
+				Word |= PEX_DC_MAX_RD_RQ_SIZE(4);
+
+				if (1) {
+					SK_OUT16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_DEV_CTRL)), Word);
+				}
+				else {
+					SkPciWriteCfgWord(pAC, PEX_CAP_REGS(PEX_DEV_CTRL), Word);
+				}
+			}
+
+#ifdef REPLAY_TIMER
+			else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
+				/* PEX Ack Reply Timeout to 40 us */
+				SK_OUT16(IoC, PCI_C2(pAC, IoC, PEX_ACK_RPLY_TOX1), 0x2710);
+			}
+#endif
+			/* disable Config Write */
+			SK_TST_MODE_OFF(IoC);
+
+#if !defined(SK_SLIM) && !defined(SK_DIAG)
+			SK_IN16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_CAP)), &Word);
+
+			Word = (Word & PEX_CAP_MAX_WI_MSK) >> 4;
+
+			/* compare PEX Negotiated Link Width against max. capabil */
+			if (pAC->GIni.GIPexWidth != (SK_U8)Word) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("PEX negotiated Link width is: %d, exp.: %d\n",
+					 pAC->GIni.GIPexWidth, Word));
+
+#ifndef NDIS_MINIPORT_DRIVER
+				SK_ERR_LOG(pAC, SK_ERRCL_INFO, SKERR_HWI_E026,
+					SKERR_HWI_E026MSG);
+#endif
+				Para.Para64 = 0;
+				SkEventQueue(pAC, SKGE_DRV, SK_DRV_PEX_LINK_WIDTH, Para);
+			}
+#endif /* !SK_SLIM && !SK_DIAG */
+		}
+
+		/*
+		 * Writing the HW Error Mask Reg. will not generate an IRQ
+		 * as long as the B0_IMSK is not set by the driver.
+		 */
+		SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
+	}
+}	/* SkGeInit2 */
+
+
+/******************************************************************************
+ *
+ *	SkGeInit() - Initialize the GE Adapter with the specified level.
+ *
+ * Description:
+ *	Level	0:	Initialize the Module structures.
+ *	Level	1:	Generic Hardware Initialization. The IOP/MemBase pointer has
+ *				to be set before calling this level.
+ *
+ *			o Do a software reset.
+ *			o Clear all reset bits.
+ *			o Verify that the detected hardware is present.
+ *			  Return an error if not.
+ *			o Get the hardware configuration
+ *				+ Set GIMacsFound with the number of MACs.
+ *				+ Store the RAM size in GIRamSize.
+ *				+ Save the PCI Revision ID in GIPciHwRev.
+ *			o return an error
+ *				if Number of MACs > SK_MAX_MACS
+ *
+ *			After returning from Level 0 the adapter
+ *			may be accessed with I/O operations.
+ *
+ *	Level	2:	start the Blink Source Counter
+ *
+ * Returns:
+ *	0:	success
+ *	1:	Number of MACs exceeds SK_MAX_MACS (after level 1)
+ *	2:	Adapter not present or not accessible
+ *	3:	Illegal initialization level
+ *	4:	Initialization level 1 call missing
+ *	5:	Unexpected PHY type detected
+ *	6:	HW self test failed
+ */
+int	SkGeInit(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Level)		/* Initialization Level */
+{
+	int		RetVal;		/* return value */
+	SK_U32	DWord;
+
+	RetVal = 0;
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("SkGeInit(Level %d)\n", Level));
+
+	switch (Level) {
+	case SK_INIT_DATA:
+		/* Initialization Level 0 */
+		SkGeInit0(pAC, IoC);
+		pAC->GIni.GILevel = SK_INIT_DATA;
+		break;
+
+	case SK_INIT_IO:
+		/* Initialization Level 1 */
+		RetVal = SkGeInit1(pAC, IoC);
+		if (RetVal != 0) {
+			break;
+		}
+
+		/* check if the adapter seems to be accessible */
+		SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
+		SK_IN32(IoC, B2_IRQM_INI, &DWord);
+		SK_OUT32(IoC, B2_IRQM_INI, 0L);
+
+		if (DWord != SK_TEST_VAL) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Error accessing IRQM register, 0x%08lX\n", DWord));
+			RetVal = 2;
+			break;
+		}
+
+#ifdef DEBUG
+		/* check if the number of GIMacsFound matches SK_MAX_MACS */
+		if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
+			RetVal = 1;
+			break;
+		}
+#endif /* DEBUG */
+
+		/* Level 1 successfully passed */
+		pAC->GIni.GILevel = SK_INIT_IO;
+		break;
+
+	case SK_INIT_RUN:
+		/* Initialization Level 2 */
+		if (pAC->GIni.GILevel != SK_INIT_IO) {
+#ifndef SK_DIAG
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
+#endif /* !SK_DIAG */
+			RetVal = 4;
+			break;
+		}
+
+		SkGeInit2(pAC, IoC);
+
+		/* Level 2 successfully passed */
+		pAC->GIni.GILevel = SK_INIT_RUN;
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
+		RetVal = 3;
+		break;
+	}
+
+	return(RetVal);
+}	/* SkGeInit */
+
+/******************************************************************************
+ *
+ *	SkGeEnaDynClkGating() - Enable Dynamic Clock Gating
+ *
+ * Description:
+ *	Check whether the device supports dynamic clock gating.
+ *	If yes, enable it.
+ *
+ *	Returns:
+ *		nothing
+ */
+void SkGeEnaDynClkGating(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	SK_U32	DWord;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("SkGeEnaDynClkGating\n"));
+
+	if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EX &&
+		 pAC->GIni.GIChipRev != CHIP_REV_YU_EX_A0) ||
+		 pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Enable dynamic clock gating, Chip Rev.=%d\n",
+			 pAC->GIni.GIChipRev));
+
+		/* set events for gate / release core clock in D3 */
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5), PCIE_OUR5_EVENT_CLK_D3_SET);
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_CFG_REG_1), PCIE_CFG1_EVENT_CLK_D3_SET);
+
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &DWord);
+
+		/* save bit 8 for LED scheme #3 */
+		DWord &= P_PIN63_LINK_LED_ENA;
+		DWord |= PCIE_OUR4_DYN_CLK_GATE_SET;
+
+		if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_CLK_PM_ENA) == 0) {
+			/* Force CLKREQ Enable and CLKREQn pin low */
+			DWord |= P_ASPM_FORCE_CLKREQ_PIN | P_ASPM_FORCE_CLKREQ_ENA;
+		}
+
+		/* set dynamic core clock gating */
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), DWord);
+	}
+}
+
+/******************************************************************************
+ *
+ *	SkGeDeInit() - Deinitialize the adapter
+ *
+ * Description:
+ *	All ports of the adapter will be stopped if not already done.
+ *	Do a software reset and switch off all LEDs.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeDeInit(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	int		i;
+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
+	int		ChipId;
+	SK_U32	DWord;
+#else
+	SK_U16	Word;
+#endif /* SK_PHY_LP_MODE_DEEP_SLEEP */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGeDeInit:  GILevel = %d, PState = %d\n",
+		 pAC->GIni.GILevel, pAC->GIni.GP[MAC_1].PState));
+
+	/* check for static clock gating */
+	if (pAC->GIni.GILevel == SK_INIT_DATA) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("Adapter is already de-initialized\n"));
+
+		return;
+	}
+
+#if (!defined(SK_SLIM) && !defined(VCPU))
+	/* ensure I2C is ready */
+	SkI2cWaitIrq(pAC, IoC);
+#endif
+
+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
+	/*
+	 * for power saving purposes within mobile environments
+	 * we set the PHY to coma mode.
+	 */
+
+	if (CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIAsfEnabled
+#ifdef XXX
+		|| (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3)
+#endif /* XXX */
+		) {
+
+		/* flag for SkGmEnterLowPowerMode() that the call was from here */
+		pAC->GIni.GILevel = SK_INIT_IO;
+
+		/* for all ports switch PHY to coma mode */
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+			/* Reset Rx MAC FIFO */
+			SK_OUT8(IoC, MR_ADDR(i, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
+
+			(void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
+		}
+
+#ifndef SK_SLIM
+		if (pAC->GIni.GIVauxAvail) {
+			/* switch power to VAUX */
+			SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
+				PC_VAUX_ON | PC_VCC_OFF));
+#ifdef DEBUG
+			SK_IN32(IoC, B0_CTST, &DWord);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Ctrl/Stat & Switch: 0x%08lX\n", DWord));
+#endif /* DEBUG */
+		}
+#endif /* !SK_SLIM */
+
+		ChipId = pAC->GIni.GIChipId;
+
+		if (ChipId == CHIP_ID_YUKON_EC_U ||
+			ChipId == CHIP_ID_YUKON_EX ||
+			ChipId >= CHIP_ID_YUKON_FE_P) {
+
+			if (!HW_FEATURE(pAC, HWF_HW_WOL_ENABLE)) {
+				/* disable HW WOL */
+				SK_OUT16(IoC, B0_CTST, Y2_HW_WOL_OFF);
+			}
+
+			if (HW_FEATURE(pAC, HWF_ENA_POW_SAV_W_WOL)) {
+
+				SK_IN32(IoC, GPHY_CTRL, &DWord);
+
+				/* Enable Shutdown of 2.5V regulator when Vmain not present */
+				SK_OUT32(IoC, GPHY_CTRL, DWord | PHY_CFG_INT_REG_PD_ENA);
+
+				/* stop the watchdog */
+				SK_OUT32(IoC, CPU_WDOG, 0);
+
+				/* put CPU into reset state */
+				SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)HCU_CCSR_ASF_RESET);
+
+				if (!HW_FEATURE(pAC, HWF_WA_DEV_542)) {
+					/* put CPU into halt state */
+					SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)HCU_CCSR_ASF_HALTED);
+				}
+
+				/* stop the watchdog */
+				SK_OUT32(IoC, CPU_WDOG, 0);
+
+				/* check for Yukon-Ultra A3,B0 / Yukon-Extreme A0 */
+				if ((ChipId == CHIP_ID_YUKON_EC_U &&
+					 pAC->GIni.GIChipRev > CHIP_REV_YU_EC_U_A0 &&
+					 /* check for HW-Rev 2.0 or higher */
+					 (pAC->GIni.GIPciHwRev >> 4) > 1) ||
+					(ChipId == CHIP_ID_YUKON_EX &&
+					 pAC->GIni.GIChipRev == CHIP_REV_YU_EX_A0)) {
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+						("Enable static clock gating, Chip Rev.=%d\n",
+						pAC->GIni.GIChipRev));
+
+					/* Enable static clock gating */
+					SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_3),
+						PCIE_OUR3_WOL_D3_COLD_SET);
+				}
+				else {
+					SkGeEnaDynClkGating(pAC, IoC);
+				}
+			}
+		}
+	}
+#ifndef DISABLE_YUKON_I
+	else if (pAC->GIni.GIYukonLite) {
+		/* take the PHY out of reset (GP_IO) */
+		SkMacClearRst(pAC, IoC, MAC_1);
+
+		/* switch PHY to IEEE Power Down mode */
+		(void)SkGmEnterLowPowerMode(pAC, IoC, 0, PHY_PM_IEEE_POWER_DOWN);
+
+#ifndef SK_SLIM
+		if (pAC->GIni.GIVauxAvail) {
+			/* switch power to VAUX */
+			SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
+				PC_VAUX_ON | PC_VCC_OFF));
+		}
+#endif /* !SK_SLIM */
+	}
+#endif /* !DISABLE_YUKON_I */
+#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */
+
+	if (!pAC->GIni.GIAsfEnabled) {
+		/* stop all current transfer activity */
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
+				pAC->GIni.GP[i].PState != SK_PRT_RESET) {
+
+				SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
+			}
+		}
+	}
+
+	/* reset all bits in the PCI STATUS register */
+	/*
+	 * Note: PCI Cfg cycles cannot be used, because they are not
+	 *	 available on some platforms after 'boot time'.
+	 */
+	if (1) {
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), &Word);
+	}
+	else {
+		SkPciReadCfgWord(pAC, PCI_STATUS, &Word);
+	}
+
+	SK_TST_MODE_ON(IoC);
+
+	if (1) {
+		SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
+	}
+	else {
+		SkPciWriteCfgWord(pAC, PCI_STATUS, Word | (SK_U16)PCI_ERRBITS);
+	}
+
+	SK_TST_MODE_OFF(IoC);
+
+	if (!pAC->GIni.GIAsfEnabled) {
+		/* enable dynamic clock gating if supported */
+		SkGeEnaDynClkGating(pAC, IoC);
+
+		/* set the SW-reset */
+		SK_OUT8(IoC, B0_CTST, CS_RST_SET);
+	}
+#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */
+
+	pAC->GIni.GILevel = SK_INIT_DATA;
+
+}	/* SkGeDeInit */
+
+
+#ifdef XXX
+/******************************************************************************
+ *
+ *	SkGeByPassMacSec() - Startup initialization for MAC Security unit
+ *
+ * Description:
+ *	Set the MAC security unit into a state to bypass all data.
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGeByPassMacSec(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port to configure */
+{
+	if (HW_IS_EXT_LE_FORMAT(pAC)) {
+		/* Bypass all MACSec frames */
+		SK_OUT16(IoC, MR_ADDR(Port, MAC_CTRL), MAC_CTRL_BYP_MACSECRX_ON |
+			MAC_CTRL_BYP_MACSECTX_ON | MAC_CTRL_BYP_RETR_ON);
+	}
+}
+#endif /* XXX */
+
+/******************************************************************************
+ *
+ *	SkGeInitPort() - Initialize the specified port
+ *
+ * Description:
+ *	PRxQSize, PXSQSize and PXAQSize has to be configured for the specified port
+ *	before calling this function.
+ *	The descriptor rings has to be initialized too.
+ *
+ *	o (Re)configure queues of the specified port.
+ *	o configure the MAC of the specified port.
+ *	o put ASIC and MAC(s) in operational mode.
+ *	o initialize Rx/Tx and Sync LED
+ *	o initialize RAM Buffers and MAC FIFOs
+ *
+ *	The port is ready to connect when returning.
+ *
+ * Note:
+ *	The MAC's Rx and Tx state machine is still disabled when returning.
+ *
+ * Returns:
+ *	0:	success
+ *	1:	Queue size initialization error. The configured values
+ *		for PRxQSize, PXSQSize, or PXAQSize are invalid for one
+ *		or more queues. The specified port was NOT initialized.
+ *		An error log entry was generated.
+ *	2:	The port has to be stopped before it can be initialized again.
+ */
+int SkGeInitPort(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port to configure */
+{
+	SK_GEPORT *pPrt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (SkGeCheckQSize(pAC, Port) != 0) {
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
+		return(1);
+	}
+
+	if (pPrt->PState >= SK_PRT_INIT) {
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
+		return(2);
+	}
+
+	/* configuration ok, initialize the Port now */
+
+	if (pAC->GIni.GIDontInitPhy) {
+		/* change PState to avoid PHY rset */
+		pPrt->PState = SK_PRT_STOP;
+	}
+
+	SkGmInitMac(pAC, IoC, Port);
+
+	SkGeInitMacFifo(pAC, IoC, Port);
+
+	SkGeInitRamBufs(pAC, IoC, Port);
+
+	if (pPrt->PXSQSize != 0) {
+		/* enable Force Sync bit if synchronous queue available */
+		SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
+	}
+
+	SkGeInitBmu(pAC, IoC, Port);
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR) {
+		/*
+		 * Disable flushing of non ASF packets;
+		 * must be done after initializing the BMUs;
+		 * drivers without ASF support should do this too, otherwise
+		 * it may happen that they cannot run on ASF devices;
+		 * remember that the MAC FIFO isn't reset during initialization.
+		 */
+		SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RXMF_TCTL_MACSEC_FLSH_DIS);
+	}
+
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+		/* Enable RX Home Address & Routing Header checksum fix */
+		SK_OUT16(IoC, RX_GMF_FL_CTRL, RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
+
+		/* Routing Header checksum fix */
+		SK_OUT32(IoC, TBMU_TEST, TBMU_TEST_ROUTING_ADD_FIX_EN);
+
+		if (!HW_FEATURE(pAC, HWF_WA_DEV_563)) {
+			/* Enable TX Home Address & Routing Header checksum fix */
+			SK_OUT32(IoC, TBMU_TEST, TBMU_TEST_HOME_ADD_FIX_EN);
+		}
+	}
+
+	/* mark port as initialized */
+	pPrt->PState = SK_PRT_INIT;
+
+	return(0);
+}	/* SkGeInitPort */
+
+#if defined(SK_POWER_MGMT) || defined(SK_DIAG)
+
+/******************************************************************************
+ *
+ *	ComputeEvenParityForDword() - Compute even parity for a dword
+ *
+ * Description:
+ *	Generate even parity per byte of a dword
+ *	(number of 1s in a byte plus parity bit must be even.
+ *
+ * Returns:
+ *	4-bit parity (one bit per byte)
+ */
+static SK_U8 ComputeEvenParityForDword(
+SK_U32 Dword)
+{
+	/* Each byte contains b7 b6 b5 b4 b3 b2 b1 b0. */
+	Dword ^= Dword >> 4;
+	/* Each byte contains * * * * b7^b3 b6^b2 b5^b1 b4^b0. */
+	Dword ^= Dword >> 2;
+	/* Each byte contains * * * * * * b7^b5^b3^b1 b6^b4^b2^b0. */
+	Dword ^= Dword >> 1;
+	/* Each byte contains * * * * * * * b7^b6^b5^b4^b3^b2^b1^b0. */
+	Dword &= BIT_24 | BIT_16 | BIT_8 | BIT_0;
+	/* Each byte contains 0 0 0 0 0 0 0 b7^b6^b5^b4^b3^b2^b1^b0. */
+	Dword |= (Dword >> (24 - 3)) | (Dword >> (16 - 2)) | (Dword >> (8 - 1));
+
+	/* Return the lower nibble, which contains the parity bits. */
+	return ((SK_U8) Dword & 0x0f);
+}
+
+/******************************************************************************
+ *
+ *	SkGeRamRead() - Reads One quadword to RAM
+ *
+ * Returns:
+ *	0
+ */
+void SkGeRamRead(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	Addr,		/* Address to be read at (in quadwords) */
+SK_U32	*pLoDword,	/* Lower Dword to be read */
+SK_U32	*pHiDword,	/* Upper Dword to be read */
+int		RamSelect)	/* Select RAM buffer (for Yukon-2: Port) */
+{
+#ifdef SK_DIAG
+	int		fl;
+	SK_U8	Parity;
+	SK_U8	ParityExpected;
+#endif /* SK_DIAG */
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||	/* Rev. A1 or later */
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+
+		RamSelect <<= RAM_ADDR_SEL_BASE;
+
+		/* if Addr == BIT_29 use current position of the HW pointer */
+		if (Addr == RAM_ADDR_ADDR_MUX) {
+			Addr = RamSelect;
+		}
+		else {
+			if (pAC->GIni.GIChipId != CHIP_ID_YUKON_SUPR) {
+				/* Use given address (11 bits) */
+				Addr &= 0x7ffL;
+			}
+			else {
+				/* Yukon-Supreme has 256K SRAM so use different address mask */
+				Addr &= RAM_ADDR_MSK;
+			}
+
+			Addr |= RAM_ADDR_ADDR_MUX | RamSelect;
+		}
+
+		RamSelect = 0;	/* For using SELECT_RAM_BUFFER() */
+	}
+	else {	/* not Yukon-Ultra and not Yukon-Extreme and not Yukon-FE+ */
+		Addr += pAC->GIni.GIRamOffs / 8;
+	}
+
+#ifdef SK_DIAG
+	fl = spl5();	/* disable interrupt to avoid changing RAM address */
+#endif /* SK_DIAG */
+
+	SK_OUT32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_ADDR), Addr);
+
+	/* Read Access is initiated by reading the lower dword */
+	SK_IN32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_DATA_LO), pLoDword);
+	SK_IN32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_DATA_HI), pHiDword);
+
+#ifdef SK_DIAG
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
+		/* Yukon-Ultra, Rev. A1 or later. */
+
+		/* Read the Parity value. */
+		SK_IN8(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_PARITY), &Parity);
+
+		/* Check the Parity value. */
+		ParityExpected = ComputeEvenParityForDword(*pLoDword) |
+			(ComputeEvenParityForDword(*pHiDword) << 4);
+
+		if (Parity != ParityExpected) {
+			w_print("Wrong parity value %02x, should be %02x\n",
+				Parity, ParityExpected);
+		}
+	}
+
+	splx(fl);
+#endif /* SK_DIAG */
+
+	return;
+}
+
+#endif /* SK_POWER_MGMT || SK_DIAG */
+
+#if defined(SK_POWER_MGMT) || defined(SK_DIAG) || (defined(YUK2) && !defined(SK_SLIM))
+
+/******************************************************************************
+ *
+ *	SkGeRamWrite() - Writes One quadword to RAM
+ *
+ * Returns:
+ *	0
+ */
+void SkGeRamWrite(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	Addr,		/* Address to be written to (in quadwords) */
+SK_U32	LoDword,	/* Lower Dword to be written */
+SK_U32	HiDword,	/* Upper Dword to be written */
+int		RamSelect)	/* Select RAM buffer (for Yukon-2: Port) */
+{
+#ifdef SK_DIAG
+	int		fl;
+	SK_U8	Parity;
+#endif /* SK_DIAG */
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||	/* Rev. A1 or later */
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+
+		RamSelect <<= RAM_ADDR_SEL_BASE;
+
+		/* if Addr == BIT_29 use current position of the HW pointer */
+		if (Addr == RAM_ADDR_ADDR_MUX) {
+			Addr = RamSelect;
+		}
+		else {
+			if (pAC->GIni.GIChipId != CHIP_ID_YUKON_SUPR) {
+				/* Use given address (11 bits) */
+				Addr &= 0x7ffL;
+			}
+			else {
+				/* Yukon-Supreme has 256K SRAM so use different address mask */
+				Addr &= RAM_ADDR_MSK;
+			}
+
+			Addr |= RAM_ADDR_ADDR_MUX | RamSelect;
+		}
+
+		RamSelect = 0;	/* For using SELECT_RAM_BUFFER() on Yukon-Ultra. */
+	}
+	else {	/* not Yukon-Ultra and not Yukon-Extreme and not Yukon-FE+ */
+		Addr += pAC->GIni.GIRamOffs / 8;
+	}
+
+#ifdef SK_DIAG
+	fl = spl5();	/* disable interrupt to avoid changing RAM address */
+#endif /* SK_DIAG */
+
+	SK_OUT32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_ADDR), Addr);
+
+	/* For all adapters but the Yukon-Ultra,
+	 * Write Access is initiated by writing the upper dword.
+	 */
+	SK_OUT32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_DATA_LO), LoDword);
+	SK_OUT32(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_DATA_HI), HiDword);
+
+#ifdef SK_DIAG
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
+		/* Yukon-Ultra, Rev. A1 or later. */
+
+		/* Compute even parity for two dwords. */
+		Parity = ComputeEvenParityForDword(LoDword) |
+			(ComputeEvenParityForDword(HiDword) << 4);
+
+		/* Check if an inverted parity value should be written. */
+		if (para_get_val("WriteInvParity") == 1) {
+			Parity ^= 0xff;
+		}
+
+		/* Write the parity value. This initiates
+		 * the write access for the Yukon-Ultra.
+		 */
+		SK_OUT8(IoC, SELECT_RAM_BUFFER(RamSelect, B3_RAM_PARITY), Parity);
+	}
+
+	splx(fl);
+#endif /* SK_DIAG */
+
+	return;
+}
+
+#endif /* SK_POWER_MGMT || SK_DIAG || (YUK2 && !SK_SLIM) */
+
+#if defined(YUK2) && !defined(SK_SLIM)
+
+/******************************************************************************
+ *
+ * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2
+ *
+ * return:
+ *	0	o.k.
+ *	1	timeout
+ */
+int SkYuk2RestartRxBmu(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_U8		Byte;
+	SK_U16		Word;
+	SK_U16		MacCtrl;
+	SK_U16		MacCtrlSave;
+	SK_U16		RxCtrl;
+	SK_U16		FlushMask;
+	SK_U16		FlushTrsh;
+	SK_U32		RamAdr;
+	SK_U32		StartTime;
+	SK_U32		TimeOut;
+	SK_BOOL		TimeStampDisabled;
+	SK_GEPORT	*pPrt;			/* GIni Port struct pointer */
+	SK_U16		WordBuffer[4];	/* Buffer to handle MAC address */
+	int			i;
+	int			Rtv;
+
+	Rtv = 0;
+
+	/* read the MAC Interrupt source register */
+	SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Byte);
+
+	/* check if a packet was received by the MAC */
+	if ((Byte & GM_IS_RX_COMPL) == 0) {
+		/* workaround not necessary */
+		return(0);
+	}
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/*
+	 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
+	 2. save MAC Rx Control Register
+	 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO,
+		Rx BMU and Rx Prefetch Unit of the link.
+	 4. set Rx MAC FIFO Flush Mask to 0xffff
+		set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20
+	 5. set MAC to loopback mode and switch MAC back to Rx/Tx enable
+	 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register
+	 7. send one packet with a size of 64bytes (size below flush threshold)
+		from TXA RAM Buffer Queue to set the rx_sop flop:
+		- set TxAQ Write Pointer to (packet size in qwords + 2)
+		- set TxAQ Level to (packet size in qwords + 2)
+		- write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1
+		  according to figure 61 on page 330 of Yukon-2 Spec.
+		- write MAC header with Destination Address = own MAC address to
+		  TxAQ RAM Buffer Queue QWords 2 and 3
+		- set TxAQ Packet Counter to 1 -> packet is transmitted immediately
+	 8. poll MAC IRQ Source Register for IRQ Rx/Tx Frame Complete
+	 9. restore MAC Rx Control Register
+	10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
+	11. set MAC back to GMII mode
+	*/
+
+	/* save MAC General Purpose Control */
+	GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrlSave);
+
+	/* save Rx MAC FIFO Flush Mask */
+	SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask);
+
+	/* save Rx MAC FIFO Flush Threshold */
+	SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh);
+
+	/* save MAC Rx Control Register */
+	GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkYuk2RestartRxBmu: Port %d, RxCtrl=0x%04X\n",
+		 Port, RxCtrl));
+
+	/* configure the MAC FIFOs */
+	SkGeInitMacFifo(pAC, IoC, Port);
+
+	SkGeInitRamBufs(pAC, IoC, Port);
+
+	SkGeInitBmu(pAC, IoC, Port);
+
+	SK_IN8(IoC, GMAC_TI_ST_CTRL, &Byte);
+
+	TimeStampDisabled = (Byte & GMT_ST_START) == 0;
+
+	if (TimeStampDisabled) {
+		/* start Time Stamp Timer */
+		SkMacTimeStamp(pAC, IoC, Port, SK_TRUE);
+	}
+
+	/* configure Rx MAC FIFO */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF);
+
+	/* set Rx MAC FIFO Flush Mask */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff);
+
+	/* set Rx MAC FIFO Flush Threshold */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 32);
+
+	/* set to promiscuous mode */
+	Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
+
+	/* set MAC Rx Control Register */
+	GM_OUT16(IoC, Port, GM_RX_CTRL, Word);
+
+	MacCtrl = MacCtrlSave | GM_GPCR_LOOP_ENA | GM_GPCR_FL_PASS |
+		GM_GPCR_DUP_FULL | GM_GPCR_AU_ALL_DIS;
+
+	/* enable MAC Loopback Mode */
+	GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl);
+
+	/* enable MAC Rx/Tx */
+	GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+
+	/* clear MAC IRQ Rx Frame Complete */
+	SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
+
+	/* clear MAC IRQ Tx Frame Complete */
+	SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
+
+	/* check for half-duplex */
+	if ((MacCtrlSave & GM_GPCR_DUP_FULL) == 0) {
+		/* get current value of timestamp timer */
+		StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+		/* set delay to 20 ms */
+		TimeOut = HW_MS_TO_TICKS(pAC, 20);
+
+		do {
+			/* dummy read */
+			GM_IN16(IoC, Port, GM_GP_STAT, &Word);
+
+		} while (SkHwGetTimeDelta(pAC, IoC, StartTime) < TimeOut);
+	}
+
+	/* send one packet with a size of 64bytes from RAM buffer*/
+
+	RamAdr = pPrt->PXaQRamStart / 8;
+
+	SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10);
+
+	SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10);
+
+	/* write 1st status quad word (packet end address in RAM, packet length */
+	SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port);
+
+	/* write 2nd status quad word */
+	SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port);
+
+	for (i = 0; i < 3; i++) {
+		/* set MAC Destination Address */
+		WordBuffer[i] = pPrt->PMacAddr[i];
+	}
+
+	WordBuffer[3] = WordBuffer[0];
+
+	/* write DA to MAC header */
+	SkGeRamWrite(pAC, IoC, RamAdr + 2, (SK_U32)(*(SK_U32 *)&WordBuffer[0]),
+		(SK_U32)(*(SK_U32 *)&WordBuffer[2]), Port);
+
+	WordBuffer[0] = WordBuffer[1];
+	WordBuffer[1] = WordBuffer[2];
+	WordBuffer[2] = 0x3200;		/* len / type field (big endian) */
+	WordBuffer[3] = 0;
+
+	/* write SA and type field to MAC header */
+	SkGeRamWrite(pAC, IoC, RamAdr + 3, (SK_U32)(*(SK_U32 *)&WordBuffer[0]),
+		(SK_U32)(*(SK_U32 *)&WordBuffer[2]), Port);
+
+	SkGeRamWrite(pAC, IoC, RamAdr + 4, 0x4c56524d,	/* "MRVL" */
+		0x00464d2d, Port);							/* "-MF"  */
+
+	for (i = 0; i < 5; i++) {
+		/* fill packet with zeroes */
+		SkGeRamWrite(pAC, IoC, RamAdr + 5 + i, 0, 0, Port);
+	}
+
+	SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1);
+
+	/* get current value of timestamp timer */
+	StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+	/* set timeout to 10 ms */
+	TimeOut = HW_MS_TO_TICKS(pAC, 10);
+
+	do {
+		if (SkHwGetTimeDelta(pAC, IoC, StartTime) > TimeOut) {
+			Rtv = 1;
+			break;
+		}
+
+		/* read the MAC Interrupt source register */
+		SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Byte);
+
+	} while ((Byte & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) !=
+			 (GM_IS_TX_COMPL | GM_IS_RX_COMPL));
+
+	/* clear MAC IRQ Rx Frame Complete */
+	SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
+
+	if (TimeStampDisabled) {
+		/* stop Time Stamp Timer */
+		SkMacTimeStamp(pAC, IoC, Port, SK_FALSE);
+	}
+
+	/* restore MAC General Purpose Control */
+	GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrlSave);
+
+	/* restore MAC Rx Control Register */
+	GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl);
+
+	/* restore Rx MAC FIFO Flush Mask */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask);
+
+	/* restore Rx MAC FIFO Flush Threshold */
+	SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh);
+
+	return(Rtv);
+}	/* SkYuk2RestartRxBmu */
+
+/******************************************************************************
+ *
+ *	SkYuk2StopTx() - Stop Tx Path on Yukon-2 device family
+ *
+ * Description:
+ *	This function stops the transmit path of Yukon-2 devices.
+ *	Currently this function is only tested for Yukon-Extreme.
+ *	Please use SkYuk2StartTx() to restart a stopped port.
+ *
+ * return:
+ *	nothing
+ */
+void SkYuk2StopTx(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index 0 or 1 */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		Word;
+	SK_U32		XaCsr;
+	SK_U32		StartTime;
+	SK_U32		TimeOut;
+	int			ToutCnt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* Disable MAC Tx */
+	GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
+	Word &= ~GM_GPCR_TX_ENA;
+	GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
+
+	/* stop transmit queue */
+	SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_STOP);
+
+	/* If the BMU is in the reset state CSR_STOP will terminate immediately */
+
+	/* get current value of timestamp timer */
+	StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+	ToutCnt = 0;
+
+	TimeOut = HW_MS_TO_TICKS(pAC, SK_TICKS_PER_SEC / 18);
+
+
+	do {
+		XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
+
+		if (SkHwGetTimeDelta(pAC, IoC, StartTime) > TimeOut) {
+			/*
+			 * Timeout of 1/18 second reached.
+			 * This needs to be checked at 1/18 sec only.
+			 */
+			ToutCnt++;
+
+			if (ToutCnt > 1) {
+				/*
+				 * If BMU stop doesn't terminate, we assume that
+				 * we have a stable state and can reset the BMU,
+				 * the Prefetch Unit, and RAM buffer now.
+				 */
+				break;			/* ===> leave do/while loop here */
+			}
+			/*
+			 * Cache incoherency workaround: assume a start command
+			 * has been lost while sending the frame.
+			 */
+
+			/* get current value of timestamp timer */
+			StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+			if ((XaCsr & BMU_STOP) != 0) {
+				SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_START);
+			}
+
+			/*
+			 * After the previous operations the X(s|a)Csr does no
+			 * longer contain the proper values
+			 */
+			XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
+		}
+	} while ((XaCsr & BMU_IDLE) != BMU_IDLE);
+
+	/* Perform a local reset of the port's Tx path */
+	/* Reset the PCI FIFO of the async Tx queue */
+	SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_RST | BMU_RST_SET);
+
+	/* Reset the Tx prefetch units */
+	SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
+		PREF_UNIT_RST_SET);
+
+#ifdef SK_AVB
+	/* Reset the AVB prefetch units */
+	if (HW_SUP_AVB(pAC)) {
+		/* Resets the prefetch units before it sets the AVB mode */
+		SkYuk2AVBControl(pAC, IoC, Port,
+			SkYuk2AVBModeEnabled(pAC, IoC, Port));
+	}
+#endif /* SK_AVB */
+
+	if (HW_IS_RAM_IF_AVAIL(pAC)) {
+		/* Reset the RAM Buffer async Tx queue */
+		SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
+	}
+
+	if (pAC->GIni.GIAsfEnabled) {
+		/*
+		 * ASF FW checks start and end pointer of its ASF queue periodically.
+		 * The idea is to set the transmit queue in non operational mode when
+		 * stopping the port and to reset the ASF transmit queue when
+		 * re-starting the transmit path.
+		 * ASF will reinitialize the transmit queue by its own when trying
+		 * to send the next packet.
+		 */
+		SK_OUT8(IoC, RB_ADDR((Port ? Q_ASF_T2 : Q_ASF_T1), RB_CTRL), RB_DIS_OP_MD);
+	}
+
+	SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
+}
+
+/******************************************************************************
+ *
+ *	SkYuk2StartTx() - Start Tx Path on Yukon-2 device family
+ *
+ * Description:
+ *	This function re-starts the transmit path of a Yukon-2 device which was
+ *	previously stopped with SkYuk2StopTx().
+ *	Currently this function was only tested for Yukon-Extreme.
+ *
+ * return:
+ *	nothing
+ */
+void SkYuk2StartTx(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index 0 or 1 */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		Word;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pAC->GIni.GIAsfEnabled) {
+		/*
+		 * ASF TX queue is in non-operational state. Reset it now.
+		 * ASF firmware is checking start and end pointer its ASF queue
+		 * periodically.
+		 * The idea is to set the transmit queue in non operational mode when
+		 * stopping the port and to reset the ASF transmit queue when
+		 * re-starting the transmit path. ASF will reinitialize the
+		 * transmit queue by its own when trying to send the next packet.
+		 */
+		SK_OUT8(IoC, RB_ADDR((Port ? Q_ASF_T2 : Q_ASF_T1), RB_CTRL), RB_RST_SET);
+	}
+
+	/* configure Tx GMAC FIFO */
+	SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
+
+	SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+		/* set Rx Pause Threshold */
+		SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
+		SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP);
+
+		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EX &&
+			 pAC->GIni.GIChipRev != CHIP_REV_YU_EX_A0) ||
+			pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+			/* Yukon-Extreme B0 and further devices */
+			/* enable Store & Forward mode for TX */
+			SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
+		}
+		else {
+			if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
+				/* set Tx GMAC FIFO Almost Empty Threshold */
+				SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
+					(SK_ECU_JUMBO_WM << 16) | (SK_U16)SK_ECU_AE_THR);
+				/* disable Store & Forward mode for TX */
+				SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
+			}
+		}
+	}
+
+	if (HW_IS_RAM_IF_AVAIL(pAC)) {
+		DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
+			pPrt->PXaQRamEnd, SK_TX_RAM_Q);
+	}
+
+	/*
+	 * Tx Queue: Release all local resets if the queue is used !
+	 *		set watermark
+	 */
+
+	if (pPrt->PXAQSize != 0) {
+
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
+		SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
+
+		if (HW_FEATURE(pAC, HWF_TX_IP_ID_INCR_ON)) {
+			/* Enable Tx IP ID Increment */
+			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_TX_IPIDINCR_ON);
+		}
+
+		SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), SK_BMU_TX_WM);
+	}
+
+	/* WA for dev. #4.209 */
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+		pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
+		/* enable/disable Store & Forward mode for TX */
+		SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
+			pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ?
+			TX_STFW_ENA : TX_STFW_DIS);
+	}
+
+	/* Enable MAC Tx */
+	GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
+	Word |= GM_GPCR_TX_ENA;
+	GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
+}
+
+#endif /* YUK2 && !SK_SLIM */
+
+/* End of File */
+
diff -ruN linux/drivers/net/sk98lin/skgemib.c linux-new/drivers/net/sk98lin/skgemib.c
--- linux/drivers/net/sk98lin/skgemib.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgemib.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1492 @@
+/*****************************************************************************
+ *
+ * Name:	skgemib.c
+ * Project:	Gigabit Ethernet Adapters, PNMI-Module
+ * Version:	$Revision: #9 $
+ * Date:	$Date: 2011/02/03 $
+ * Purpose:	Private Network Management Interface Management Database
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*****************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgemib.c,v $
+ *	Revision 2.19  2010/04/29 14:27:32  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_OS_VERSION_INFO_SET.
+ *	
+ *	Revision 2.18  2009/10/27 15:00:47  tschilli
+ *	Added changes to support compilation without RMLT (SK_NO_RLMT)
+ *	
+ *	Revision 2.17  2009/02/25 13:26:40  sschmeck
+ *	Added OIDs for Win7 Power Management.
+ *	
+ *	Revision 2.16  2008/09/12 13:44:08  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_IP_INFO_EXT and OID_SKGE_ASF_DASH_SPECIAL_ACTION.
+ *	
+ *	Revision 2.15  2008/08/07 12:50:15  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_IP_INFO.
+ *	
+ *	Revision 2.14  2008/03/06 14:15:53  tschilli
+ *	Added OID OID_SKGE_ASF_DASH_MAX_USER.
+ *	
+ *	Revision 2.13  2008/02/27 16:07:52  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_USER_DAT and OID_SKGE_ASF_DASH_BUSY.
+ *	
+ *	Revision 2.12  2008/01/15 13:51:05  tschilli
+ *	Added OIDs OID_SKGE_ASF_DASH_CAP and OID_SKGE_ASF_DASH_ENA.
+ *	
+ *	Revision 2.11  2007/03/28 13:43:43  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_FW_REMOVE
+ *	- OID_SKGE_ASF_CHECK_SPI
+ *	
+ *	Revision 2.10  2007/01/17 15:19:18  rschmidt
+ *	Editorial changes.
+ *	
+ *	Revision 2.9  2005/12/21 09:49:48  tschilli
+ *	Added declaration of Asf() to get rid of FreeBSD compiler warnings.
+ *
+ *	Revision 2.8  2005/12/14 16:11:18  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.7  2004/10/26 12:42:18  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_FWVER_OID
+ *	- OID_SKGE_ASF_ACPI_OID
+ *	- OID_SKGE_ASF_SMBUS_OID
+ *
+ *	Revision 2.6  2004/06/14 06:51:42  tschilli
+ *	VCT OID added:
+ *	- OID_SKGE_VCT_CAPABILITIES
+ *
+ *	Revision 2.5  2004/05/13 13:48:34  tschilli
+ *	ASF OIDs added:
+ *	- OID_SKGE_ASF_KEY_OP
+ *	- OID_SKGE_ASF_KEY_ADM
+ *	- OID_SKGE_ASF_KEY_GEN
+ *	- OID_SKGE_ASF_CAP
+ *	ASF OIDs removed:
+ *	- OID_SKGE_ASF_PAR_2
+ *	- OID_SKGE_ASF_PAR_3
+ *	- OID_SKGE_ASF_PAR_4
+ *	- OID_SKGE_ASF_PAR_5
+ *	ASF OID changed:
+ *	- OID_SKGE_ASF_PAR_1
+ *
+ *	Revision 2.4  2004/03/08 14:27:06  mkunz
+ *	Changes of ASF OID
+ *
+ *	Revision 2.3  2004/02/26 16:01:20  mkunz
+ *	Changes for ASF
+ *
+ *	Revision 2.2  2004/02/02 15:58:14  mkunz
+ *	Added ASF support
+ *
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.11  2003/09/15 13:38:12  tschilli
+ *	OID_SKGE_PHY_LP_MODE included only after using #define SK_PHY_LP_MODE.
+ *
+ *	Revision 1.10  2003/08/15 12:28:59  tschilli
+ *	Added new OIDs:
+ *	OID_SKGE_DRIVER_RELDATE
+ *	OID_SKGE_DRIVER_FILENAME
+ *	OID_SKGE_CHIPID
+ *	OID_SKGE_RAMSIZE
+ *	OID_SKGE_VAUXAVAIL
+ *	OID_SKGE_PHY_TYPE
+ *	OID_SKGE_PHY_LP_MODE
+ *
+ *	Revision 1.9  2003/05/23 12:55:20  tschilli
+ *	OID_SKGE_BOARDLEVEL added.
+ *
+ *	Revision 1.8  2003/03/27 11:19:15  tschilli
+ *	Copyright messages changed.
+ *
+ *	Revision 1.7  2002/12/16 09:04:34  tschilli
+ *	Code for VCT handling added.
+ *
+ *	Revision 1.6  2002/08/09 15:40:21  rwahl
+ *	Editorial change (renamed ConfSpeedCap).
+ *
+ *	Revision 1.5  2002/08/09 11:05:34  rwahl
+ *	Added oid handling for link speed cap.
+ *
+ *	Revision 1.4  2002/08/09 09:40:27  rwahl
+ *	Added support for NDIS OID_PNP_xxx.
+ *
+ *	Revision 1.3  2002/07/17 19:39:54  rwahl
+ *	Added handler for OID_SKGE_SPEED_MODE & OID_SKGE_SPEED_STATUS.
+ *
+ *	Revision 1.2  2002/05/22 08:59:00  rwahl
+ *	- static functions only for release build.
+ *	- Source file must be included.
+ *
+ *	Revision 1.1  2002/05/22 08:12:42  rwahl
+ *	Initial version.
+ *
+ ****************************************************************************/
+
+/*
+ * PRIVATE OID handler function prototypes
+ */
+PNMI_STATIC int Addr(SK_AC *pAC, SK_IOC IoC, int action,
+	SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int* pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+#ifndef SK_NO_RLMT
+PNMI_STATIC int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int Monitor(SK_AC *pAC, SK_IOC IoC, int action,
+	SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+#endif
+PNMI_STATIC int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+
+#ifdef SK_POWER_MGMT
+PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+#endif /* SK_POWER_MGMT */
+
+#ifdef SK_DIAG_SUPPORT
+PNMI_STATIC int DiagActions(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+#endif /* SK_DIAG_SUPPORT */
+
+#ifdef SK_ASF
+PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance,
+	unsigned int TableIndex, SK_U32 NetIndex);
+#endif /* SK_ASF */
+
+
+/* defines *******************************************************************/
+#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
+
+
+/* global variables **********************************************************/
+
+/*
+ * Table to correlate OID with handler function and index to
+ * hardware register stored in StatAddress if applicable.
+ */
+PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = {
+	{OID_GEN_XMIT_OK,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX},
+	{OID_GEN_RCV_OK,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX},
+	{OID_GEN_XMIT_ERROR,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+	{OID_GEN_RCV_ERROR,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+	{OID_GEN_RCV_NO_BUFFER,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+	{OID_GEN_DIRECTED_FRAMES_XMIT,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST},
+	{OID_GEN_MULTICAST_FRAMES_XMIT,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST},
+	{OID_GEN_BROADCAST_FRAMES_XMIT,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST},
+	{OID_GEN_DIRECTED_FRAMES_RCV,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST},
+	{OID_GEN_MULTICAST_FRAMES_RCV,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST},
+	{OID_GEN_BROADCAST_FRAMES_RCV,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST},
+	{OID_GEN_RCV_CRC_ERROR,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS},
+	{OID_GEN_TRANSMIT_QUEUE_LENGTH,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+	{OID_802_3_PERMANENT_ADDRESS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, 0},
+	{OID_802_3_CURRENT_ADDRESS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, 0},
+	{OID_802_3_RCV_ERROR_ALIGNMENT,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING},
+	{OID_802_3_XMIT_ONE_COLLISION,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL},
+	{OID_802_3_XMIT_MORE_COLLISIONS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL},
+	{OID_802_3_XMIT_DEFERRED,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL},
+	{OID_802_3_XMIT_MAX_COLLISIONS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL},
+	{OID_802_3_RCV_OVERRUN,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW},
+	{OID_802_3_XMIT_UNDERRUN,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN},
+	{OID_802_3_XMIT_TIMES_CRS_LOST,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER},
+	{OID_802_3_XMIT_LATE_COLLISIONS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL},
+#ifdef SK_POWER_MGMT
+	{OID_PNP_CAPABILITIES,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, PowerManagement, 0},
+	{OID_PNP_SET_POWER,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PNP_QUERY_POWER,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, PowerManagement, 0},
+	{OID_PNP_ADD_WAKE_UP_PATTERN,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PNP_REMOVE_WAKE_UP_PATTERN,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PNP_ENABLE_WAKE_UP,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, PowerManagement, 0},
+#ifdef SK_POWER_MGMT_EX
+	{OID_PM_PARAMETERS,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, PowerManagement, 0},
+	{OID_PM_ADD_WOL_PATTERN,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PM_REMOVE_WOL_PATTERN,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PM_ADD_PROTOCOL_OFFLOAD,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+	{OID_PM_REMOVE_PROTOCOL_OFFLOAD,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, PowerManagement, 0},
+#endif /* SK_POWER_MGMT_EX */
+#endif /* SK_POWER_MGMT */
+#ifdef SK_DIAG_SUPPORT
+	{OID_SKGE_DIAG_MODE,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, DiagActions, 0},
+#endif /* SK_DIAG_SUPPORT */
+#ifdef SK_ASF
+	{OID_SKGE_ASF,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_STORE_CONFIG,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_ENA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_DASH_ENA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS_INT,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_HB_ENA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_HB_INT,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_WD_ENA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_WD_TIME,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_IP_SOURCE,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_MAC_SOURCE,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_IP_DEST,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_MAC_DEST,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_COMMUNITY_NAME,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RSP_ENA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS_COUNT_MIN,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS_COUNT_MAX,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS_INT_MIN,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_RETRANS_INT_MAX,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_HB_INT_MIN,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_HB_INT_MAX,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_WD_TIME_MIN,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_WD_TIME_MAX,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_HB_CAP,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_WD_TIMER_RES,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_GUID,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_KEY_OP,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_KEY_ADM,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_KEY_GEN,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_CAP,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_DASH_CAP,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_PAR_1,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_OVERALL_OID,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_FWVER_OID,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_ACPI_OID,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_SMBUS_OID,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_FW_REMOVE,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_CHECK_SPI,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_USER_DAT,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_DASH_MAX_USER,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_IP_INFO,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_BUSY,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_IP_INFO_EXT,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_DASH_OS_VERSION_INFO_SET,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, Asf, 0},
+	{OID_SKGE_ASF_DASH_SPECIAL_ACTION,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_FW_GET_FLASH_RESULT,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+	{OID_SKGE_ASF_DASH_FW_GET_VERSIONS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Asf, 0},
+#endif /* SK_ASF */
+	{OID_SKGE_MDB_VERSION,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(MgmtDBVersion),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_SUPPORTED_LIST,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_ALL_DATA,
+		0,
+		0,
+		0,
+		SK_PNMI_RW, OidStruct, 0},
+	{OID_SKGE_VPD_FREE_BYTES,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(VpdFreeBytes),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_ENTRIES_LIST,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(VpdEntriesList),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_ENTRIES_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(VpdEntriesNumber),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_KEY,
+		SK_PNMI_VPD_ENTRIES,
+		sizeof(SK_PNMI_VPD),
+		SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_VALUE,
+		SK_PNMI_VPD_ENTRIES,
+		sizeof(SK_PNMI_VPD),
+		SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_ACCESS,
+		SK_PNMI_VPD_ENTRIES,
+		sizeof(SK_PNMI_VPD),
+		SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess),
+		SK_PNMI_RO, Vpd, 0},
+	{OID_SKGE_VPD_ACTION,
+		SK_PNMI_VPD_ENTRIES,
+		sizeof(SK_PNMI_VPD),
+		SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction),
+		SK_PNMI_RW, Vpd, 0},
+	{OID_SKGE_PORT_NUMBER,		
+		1,
+		0,
+		SK_PNMI_MAI_OFF(PortNumber),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_DEVICE_TYPE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(DeviceType),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_DRIVER_DESCR,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(DriverDescr),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_DRIVER_VERSION,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(DriverVersion),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_DRIVER_RELDATE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(DriverReleaseDate),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_DRIVER_FILENAME,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(DriverFileName),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_HW_DESCR,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(HwDescr),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_HW_VERSION,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(HwVersion),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_CHIPSET,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(Chipset),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_CHIPID,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(ChipId),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RAMSIZE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RamSize),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_VAUXAVAIL,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(VauxAvail),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_ACTION,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(Action),
+		SK_PNMI_RW, Perform, 0},
+	{OID_SKGE_RESULT,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TestResult),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_BUS_TYPE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(BusType),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_BUS_SPEED,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(BusSpeed),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_BUS_WIDTH,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(BusWidth),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_SW_QUEUE_LEN,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxSwQueueLen),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_SW_QUEUE_MAX,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxSwQueueMax),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_RETRY,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxRetryCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RX_INTR_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RxIntrCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_INTR_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxIntrCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RX_NO_BUF_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RxNoBufCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_NO_BUF_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxNoBufCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_USED_DESCR_NO,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxUsedDescrNo),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RX_DELIVERED_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RxDeliveredCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RX_OCTETS_DELIV_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RxOctetsDeliveredCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RX_HW_ERROR_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RxHwErrorsCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TX_HW_ERROR_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TxHwErrorsCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_IN_ERRORS_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(InErrorsCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_OUT_ERROR_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(OutErrorsCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_ERR_RECOVERY_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(ErrRecoveryCts),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_SYSUPTIME,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(SysUpTime),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_SENSOR_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(SensorNumber),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_SENSOR_INDEX,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_DESCR,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_TYPE,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_VALUE,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_WAR_THRES_LOW,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_WAR_THRES_UPP,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_ERR_THRES_LOW,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_ERR_THRES_UPP,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_STATUS,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_WAR_CTS,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_ERR_CTS,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_WAR_TIME,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_SENSOR_ERR_TIME,
+		SK_PNMI_SENSOR_ENTRIES,
+		sizeof(SK_PNMI_SENSOR),
+		SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp),
+		SK_PNMI_RO, SensorStat, 0},
+	{OID_SKGE_CHKSM_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(ChecksumNumber),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_CHKSM_RX_OK_CTS,
+		SKCS_NUM_PROTOCOLS,
+		sizeof(SK_PNMI_CHECKSUM),
+		SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts),
+		SK_PNMI_RO, CsumStat, 0},
+	{OID_SKGE_CHKSM_RX_UNABLE_CTS,
+		SKCS_NUM_PROTOCOLS,
+		sizeof(SK_PNMI_CHECKSUM),
+		SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts),
+		SK_PNMI_RO, CsumStat, 0},
+	{OID_SKGE_CHKSM_RX_ERR_CTS,
+		SKCS_NUM_PROTOCOLS,
+		sizeof(SK_PNMI_CHECKSUM),
+		SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts),
+		SK_PNMI_RO, CsumStat, 0},
+	{OID_SKGE_CHKSM_TX_OK_CTS,
+		SKCS_NUM_PROTOCOLS,
+		sizeof(SK_PNMI_CHECKSUM),
+		SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts),
+		SK_PNMI_RO, CsumStat, 0},
+	{OID_SKGE_CHKSM_TX_UNABLE_CTS,
+		SKCS_NUM_PROTOCOLS,
+		sizeof(SK_PNMI_CHECKSUM),
+		SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts),
+		SK_PNMI_RO, CsumStat, 0},
+	{OID_SKGE_STAT_TX,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX},
+	{OID_SKGE_STAT_TX_OCTETS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET},
+	{OID_SKGE_STAT_TX_BROADCAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST},
+	{OID_SKGE_STAT_TX_MULTICAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST},
+	{OID_SKGE_STAT_TX_UNICAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST},
+	{OID_SKGE_STAT_TX_LONGFRAMES,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES},
+	{OID_SKGE_STAT_TX_BURST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST},
+	{OID_SKGE_STAT_TX_PFLOWC,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC},
+	{OID_SKGE_STAT_TX_FLOWC,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC},
+	{OID_SKGE_STAT_TX_SINGLE_COL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL},
+	{OID_SKGE_STAT_TX_MULTI_COL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL},
+	{OID_SKGE_STAT_TX_EXCESS_COL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL},
+	{OID_SKGE_STAT_TX_LATE_COL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL},
+	{OID_SKGE_STAT_TX_DEFFERAL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL},
+	{OID_SKGE_STAT_TX_EXCESS_DEF,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF},
+	{OID_SKGE_STAT_TX_UNDERRUN,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN},
+	{OID_SKGE_STAT_TX_CARRIER,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER},
+/*	{OID_SKGE_STAT_TX_UTIL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization),
+		SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
+	{OID_SKGE_STAT_TX_64,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64},
+	{OID_SKGE_STAT_TX_127,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127},
+	{OID_SKGE_STAT_TX_255,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255},
+	{OID_SKGE_STAT_TX_511,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511},
+	{OID_SKGE_STAT_TX_1023,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023},
+	{OID_SKGE_STAT_TX_MAX,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX},
+	{OID_SKGE_STAT_TX_SYNC,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC},
+	{OID_SKGE_STAT_TX_SYNC_OCTETS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET},
+	{OID_SKGE_STAT_RX,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX},
+	{OID_SKGE_STAT_RX_OCTETS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET},
+	{OID_SKGE_STAT_RX_BROADCAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST},
+	{OID_SKGE_STAT_RX_MULTICAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST},
+	{OID_SKGE_STAT_RX_UNICAST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST},
+	{OID_SKGE_STAT_RX_LONGFRAMES,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxLongFramesCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_LONGFRAMES},
+	{OID_SKGE_STAT_RX_PFLOWC,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC},
+	{OID_SKGE_STAT_RX_FLOWC,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC},
+	{OID_SKGE_STAT_RX_PFLOWC_ERR,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR},
+	{OID_SKGE_STAT_RX_FLOWC_UNKWN,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN},
+	{OID_SKGE_STAT_RX_BURST,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST},
+	{OID_SKGE_STAT_RX_MISSED,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED},
+	{OID_SKGE_STAT_RX_FRAMING,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING},
+	{OID_SKGE_STAT_RX_OVERFLOW,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW},
+	{OID_SKGE_STAT_RX_JABBER,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER},
+	{OID_SKGE_STAT_RX_CARRIER,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER},
+	{OID_SKGE_STAT_RX_IR_LENGTH,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH},
+	{OID_SKGE_STAT_RX_SYMBOL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL},
+	{OID_SKGE_STAT_RX_SHORTS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS},
+	{OID_SKGE_STAT_RX_RUNT,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT},
+	{OID_SKGE_STAT_RX_CEXT,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT},
+	{OID_SKGE_STAT_RX_TOO_LONG,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG},
+	{OID_SKGE_STAT_RX_FCS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS},
+/*	{OID_SKGE_STAT_RX_UTIL,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization),
+		SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
+	{OID_SKGE_STAT_RX_64,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64},
+	{OID_SKGE_STAT_RX_127,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127},
+	{OID_SKGE_STAT_RX_255,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255},
+	{OID_SKGE_STAT_RX_511,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511},
+	{OID_SKGE_STAT_RX_1023,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023},
+	{OID_SKGE_STAT_RX_MAX,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_STAT),
+		SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts),
+		SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX},
+	{OID_SKGE_PHYS_CUR_ADDR,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr),
+		SK_PNMI_RW, Addr, 0},
+	{OID_SKGE_PHYS_FAC_ADDR,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr),
+		SK_PNMI_RO, Addr, 0},
+	{OID_SKGE_PMD,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_CONNECTOR,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_PHY_TYPE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),
+		SK_PNMI_RO, MacPrivateConf, 0},
+#ifdef SK_PHY_LP_MODE
+		{OID_SKGE_PHY_LP_MODE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),
+		SK_PNMI_RW, MacPrivateConf, 0},
+#endif
+	{OID_SKGE_LINK_CAP,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_LINK_MODE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode),
+		SK_PNMI_RW, MacPrivateConf, 0},
+	{OID_SKGE_LINK_MODE_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_LINK_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_FLOWCTRL_CAP,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_FLOWCTRL_MODE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode),
+		SK_PNMI_RW, MacPrivateConf, 0},
+	{OID_SKGE_FLOWCTRL_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_PHY_OPERATION_CAP,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_PHY_OPERATION_MODE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode),
+		SK_PNMI_RW, MacPrivateConf, 0},
+	{OID_SKGE_PHY_OPERATION_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_SPEED_CAP,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedCapability),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_SPEED_MODE,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedMode),
+		SK_PNMI_RW, MacPrivateConf, 0},
+	{OID_SKGE_SPEED_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_CONF),
+		SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedStatus),
+		SK_PNMI_RO, MacPrivateConf, 0},
+	{OID_SKGE_TRAP,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(Trap),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_TRAP_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(TrapNumber),
+		SK_PNMI_RO, General, 0},
+#ifndef SK_NO_RLMT
+	{OID_SKGE_RLMT_MODE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtMode),
+		SK_PNMI_RW, Rlmt, 0},
+	{OID_SKGE_RLMT_PORT_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtPortNumber),
+		SK_PNMI_RO, Rlmt, 0},
+	{OID_SKGE_RLMT_PORT_ACTIVE,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtPortActive),
+		SK_PNMI_RO, Rlmt, 0},
+	{OID_SKGE_RLMT_PORT_PREFERRED,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtPortPreferred),
+		SK_PNMI_RW, Rlmt, 0},
+	{OID_SKGE_RLMT_CHANGE_CTS,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtChangeCts),
+		SK_PNMI_RO, Rlmt, 0},
+	{OID_SKGE_RLMT_CHANGE_TIME,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtChangeTime),
+		SK_PNMI_RO, Rlmt, 0},
+	{OID_SKGE_RLMT_CHANGE_ESTIM,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtChangeEstimate),
+		SK_PNMI_RO, Rlmt, 0},
+	{OID_SKGE_RLMT_CHANGE_THRES,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtChangeThreshold),
+		SK_PNMI_RW, Rlmt, 0},
+	{OID_SKGE_RLMT_PORT_INDEX,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_STATUS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_TX_HELLO_CTS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_RX_HELLO_CTS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_TX_SP_REQ_CTS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_RX_SP_CTS,
+		SK_PNMI_MAC_ENTRIES,
+		sizeof(SK_PNMI_RLMT),
+		SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts),
+		SK_PNMI_RO, RlmtStat, 0},
+	{OID_SKGE_RLMT_MONITOR_NUMBER,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(RlmtMonitorNumber),
+		SK_PNMI_RO, General, 0},
+	{OID_SKGE_RLMT_MONITOR_INDEX,
+		SK_PNMI_MONITOR_ENTRIES,
+		sizeof(SK_PNMI_RLMT_MONITOR),
+		SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex),
+		SK_PNMI_RO, Monitor, 0},
+	{OID_SKGE_RLMT_MONITOR_ADDR,
+		SK_PNMI_MONITOR_ENTRIES,
+		sizeof(SK_PNMI_RLMT_MONITOR),
+		SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr),
+		SK_PNMI_RO, Monitor, 0},
+	{OID_SKGE_RLMT_MONITOR_ERRS,
+		SK_PNMI_MONITOR_ENTRIES,
+		sizeof(SK_PNMI_RLMT_MONITOR),
+		SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts),
+		SK_PNMI_RO, Monitor, 0},
+	{OID_SKGE_RLMT_MONITOR_TIMESTAMP,
+		SK_PNMI_MONITOR_ENTRIES,
+		sizeof(SK_PNMI_RLMT_MONITOR),
+		SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp),
+		SK_PNMI_RO, Monitor, 0},
+	{OID_SKGE_RLMT_MONITOR_ADMIN,
+		SK_PNMI_MONITOR_ENTRIES,
+		sizeof(SK_PNMI_RLMT_MONITOR),
+		SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin),
+		SK_PNMI_RW, Monitor, 0},
+#endif
+	{OID_SKGE_MTU,
+		1,
+		0,
+		SK_PNMI_MAI_OFF(MtuSize),
+		SK_PNMI_RW, MacPrivateConf, 0},
+	{OID_SKGE_VCT_GET,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Vct, 0},
+	{OID_SKGE_VCT_SET,
+		0,
+		0,
+		0,
+		SK_PNMI_WO, Vct, 0},
+	{OID_SKGE_VCT_STATUS,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Vct, 0},
+	{OID_SKGE_VCT_CAPABILITIES,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, Vct, 0},
+	{OID_SKGE_BOARDLEVEL,
+		0,
+		0,
+		0,
+		SK_PNMI_RO, General, 0},
+};
+
diff -ruN linux/drivers/net/sk98lin/skgepnmi.c linux-new/drivers/net/sk98lin/skgepnmi.c
--- linux/drivers/net/sk98lin/skgepnmi.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgepnmi.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,9268 @@
+/*****************************************************************************
+ *
+ * Name:	skgepnmi.c
+ * Project:	Gigabit Ethernet Adapters, PNMI-Module
+ * Version:	$Revision: #7 $
+ * Date:	$Date: 2010/11/10 $
+ * Purpose:	Private Network Management Interface
+ *
+ ****************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skgepnmi.c,v $
+ *	Revision 2.44  2010/05/04 14:14:07  tschilli
+ *	Readded define SK_USE_FWCOMMON to allow compilation with ASF function calls
+ *	(accidentally removed at last check in).
+ *
+ *	Revision 2.43  2010/05/04 09:22:51  rschmidt
+ *	Adapted VCT results for Yukon-Optima.
+ *	Editorial changes.
+ *
+ *	Revision 2.42  2010/04/29 14:30:14  tschilli
+ *	Changed definition static void VctGetResults() to PNMI_STATIC void VctGetResults() to allow compilation with DEBUG flag set.
+ *
+ *	Revision 2.41  2010/03/23 16:28:28  tschilli
+ *	Removed unnecessary start of RLMT change count timer in case SK_NO_RLMT is set.
+ *	Added missing PNMI chipsets used for pAC->Pnmi.Chipset in SkPnmiInit().
+ *
+ *	Revision 2.40  2009/10/27 15:38:54  tschilli
+ *	Added define SK_USE_FWCOMMON to allow compilation with ASF function calls.
+ *
+ *	Revision 2.39  2009/10/27 08:26:35  tschilli
+ *	Added changes to support compilation without RLMT (SK_NO_RLMT)
+ *	Added changes to support new firmware common module (fwcommon)
+ *
+ *	Revision 2.38  2009/03/04 09:46:49  rschmidt
+ *	Used macro HW_HAS_NEWER_PHY for VCT DSP.
+ *	Fixed PREfast compiler warnings.
+ *	Editorial changes.
+ *
+ *	Revision 2.37  2009/02/25 13:41:00  sschmeck
+ *	Added OIDs for Win7 Power Management.
+ *
+ *	Revision 2.36  2009/02/17 13:44:04  rschmidt
+ *	Used RLMT change counter timer only for dual port adapters.
+ *	Adapted VCT for Yukon chips after Supreme.
+ *	Editorial changes.
+ *
+ *	Revision 2.35  2008/04/09 16:16:07  mschmid
+ *	Added Yukon-Ultra 2 support for VCT.
+ *
+ *	Revision 2.34  2008/04/01 08:50:20  tschilli
+ *	Fix: Removed unused variable Word in GetPhysStatVal().
+ *
+ *	Revision 2.33  2008/03/20 08:50:32  tschilli
+ *	Removed support of GENESIS adapters.
+ *
+ *	Revision 2.32  2007/11/06 16:42:32  mschmid
+ *	Modified bias to calculate cable length for Yukon-Extreme and Yukon-Supreme.
+ *
+ *	Revision 2.31  2007/11/05 08:00:28  tschilli
+ *	Added VCT support for Yukon-Supreme.
+ *
+ *	Revision 2.30  2007/09/25 15:22:46  tschilli
+ *	Removed unused variable from VctGetDspLength() to avoid a compiler warning.
+ *
+ *	Revision 2.29  2007/09/03 14:16:57  mkunz
+ *	Changed handling of VCT. The results are interpreted now in PNMI directly.
+ *	The mode they are written into the buffer is capabilities version = 1.
+ *	Known limitation: Dual Net support missing.
+ *
+ *	Revision 2.28  2007/07/25 14:01:19  mkarl
+ *	Fixed the problem that the first call to SkPnmiGetStruct failed when the
+ *	adapter has no VPD. This prevented the Novell driver from working with
+ *	Client32 on non-VPD adapters.
+ *
+ *	Revision 2.27  2007/01/12 10:37:12  rschmidt
+ *	Removed handling of VCT status and length from VctGetResults().
+ *	Editorial changes.
+ *
+ *	Revision 2.26  2005/12/21 09:53:21  tschilli
+ *	Removed public function declarations, declaration of Asf() and
+ *	declaration of Vct() to get rid of FreeBSD compiler warnings.
+ *
+ *	Revision 2.25  2005/12/14 16:11:18  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.24  2005/10/21 09:54:35  mkunz
+ *	Changes for DualNet WoL and Power Management.
+ *
+ *	Revision 2.23  2005/08/09 09:05:12  tschilli
+ *	Changed GetVpdKeyArr(), SkPnmiGetStruct(), Vpd() and General()
+ *	to fix VPD handling in case of wrong or missing VPD.
+ *
+ *	Revision 2.22  2005/05/17 12:13:57  tschilli
+ *	Moved initialisation of DSP variables for Vct() from
+ *	SK_INIT_IO to SK_INIT_DATA.
+ *
+ *	Revision 2.21  2005/05/11 11:50:12  tschilli
+ *	Vct(): Fixed instance number check in the case of using other
+ *	instance numbers than -1.
+ *
+ *	Revision 2.20  2005/05/03 06:46:13  tschilli
+ *	OID_SKGE_CHIPSET: Fixed return values for missing chipsets.
+ *	Fixed VCT code to retrieve correct values of the second port.
+ *
+ *	Revision 2.19  2004/10/29 09:09:43  tschilli
+ *	Fixed Lint error in GetVpdKeyArr().
+ *
+ *	Revision 2.18  2004/10/20 13:36:31  mkunz
+ *	Correct Rx error counters.
+ *
+ *	Revision 2.17  2004/09/17 11:50:03  tschilli
+ *	Changed VCT code for Yukon-FE.
+ *
+ *	Revision 2.16  2004/09/13 08:02:42  mkunz
+ *	Replaced SK_PNMI_HRX_MISSED through
+ *	SK_PNMI_HRX_OVERFLOW in
+ *	OID_GEN_RCV_NO_BUFFER.
+ *
+ *	Revision 2.15  2004/09/08 15:41:07  mkunz
+ *	Added counter of RX_MISSED to OID_GEN_RCV_NO_BUFFER.
+ *	This is the HW counter for the events when packets were lost due to
+ *	lack of NIC resources.
+ *
+ *	Revision 2.14  2004/08/25 12:35:00  mlindner
+ *	Fix: Removed unused semicolon
+ *
+ *	Revision 2.13  2004/06/14 06:50:30  tschilli
+ *	Vct(): Handling for OID_SKGE_VCT_CAPABILITIES added.
+ *	VctGetResults(): New cable status SK_PNMI_VCT_NOT_PRESENT added.
+ *	Variable CurrentPhyPowerState included into #ifdef SK_PHY_LP_MODE
+ *	to be not visible when compiling without SK_PHY_LP_MODE set.
+ *
+ *	Revision 2.12  2004/05/04 13:05:03  tschilli
+ *	SkPnmiEvent(): Unused variable pPrt removed.
+ *	OID_SKGE_PHY_TYPE in VirtualConf(): Missing break added.
+ *
+ *	Revision 2.11  2004/04/29 10:07:57  mkunz
+ *	Remember current PHY low power mode,
+ *	it is changed in a function call to
+ *	SkGmLeaveLowPowerMode but the
+ *	original one is still needed later.
+ *
+ *	Revision 2.10  2004/04/29 08:16:05  mkunz
+ *	Changed OID for low power mode
+ *
+ *	Revision 2.9  2004/04/29 07:46:32  mkunz
+ *	Roll back to previous version
+ *
+ *	Revision 2.8  2004/04/08 16:09:08  mkunz
+ *	Changes required for PHY low power mode handling
+ *
+ *	Revision 2.7  2004/03/20 14:36:11  mkunz
+ *	Fixed compile error, editorial change
+ *
+ *	Revision 2.6  2004/03/19 16:44:49  tschilli
+ *	Merged the changes of revision 1.113.
+ *	Merged the changes of revision 1.112.
+ *
+ *	Revision 2.5  2004/02/26 16:01:20  mkunz
+ *	Changes for ASF
+ *
+ *	Revision 2.4  2004/02/26 09:21:29  mkunz
+ *	Added #include "h/sky2le.h"
+ *
+ *	Revision 2.3  2004/02/02 15:58:14  mkunz
+ *	Added ASF support
+ *
+ *	Revision 2.2  2003/12/02 12:56:49  mkarl
+ *	Added ifdef GENESIS.
+ *
+ *	Revision 2.1  2003/10/27 14:16:08  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.113  2004/03/19 14:03:57  tschilli
+ *	OID_SKGE_MTU: Buffer handling fixes.
+ *	Two calls of SkEventDispatcher() in VCT code removed.
+ *	Vct(): Check of SK_PHY_MARV_COPPER moved back to the old location.
+ *	DualNet mode handling (SET operation) fixed for the OIDs:
+ *	- OID_SKGE_RLMT_PORT_PREFERRED
+ *	- OID_SKGE_LINK_MODE
+ *	- OID_SKGE_FLOWCTRL_MODE
+ *	- OID_SKGE_PHY_OPERATION_MODE
+ *	- OID_SKGE_SPEED_MODE
+ *	- OID_SKGE_PHY_LP_MODE
+ *	SK_PNMI_HRX_FCS: Added ifdef GENESIS.
+ *	Editorial changes.
+ *
+ *	Revision 1.112  2004/01/02 12:43:10  rschmidt
+ *	Removed HW-access to internal registers in SkPnmiInit(),
+ *	use of entries GIPciSlot64, GIPciClock66, GIPmdTyp and GIConTyp
+ *	from s_GeInit structure instead.
+ *	Replaced digital values of parameters with defines
+ *	SK_PNMI_EVT_TIMER_CHECK and SK_PNMI_VCT_TIMER_CHECK.
+ *	Added routine VctGetResults() for VCT calculation.
+ *	Fixed some error messages for driver release date and
+ *	driver file name.
+ *	Fixed handling of OID_SKGE_PHY_LP_MODE for dual port.
+ *	Changed handling of OID_SKGE_VCT_GET using VctGetResults().
+ *	Editorial changes.
+ *
+ *	Revision 1.111  2003/09/15 13:35:35  tschilli
+ *	Code for OID_SKGE_PHY_LP_MODE completed (using #define SK_PHY_LP_MODE).
+ *	SK_DIAG_ATTACHED handling for OID_SKGE_DIAG_MODE in DiagActions() changed.
+ *
+ *	Revision 1.110  2003/08/15 12:28:04  tschilli
+ *	Added new OIDs:
+ *	OID_SKGE_DRIVER_RELDATE
+ *	OID_SKGE_DRIVER_FILENAME
+ *	OID_SKGE_CHIPID
+ *	OID_SKGE_RAMSIZE
+ *	OID_SKGE_VAUXAVAIL
+ *	OID_SKGE_PHY_TYPE
+ *	OID_SKGE_PHY_LP_MODE
+ *
+ *	Added SK_DIAG_ATTACHED handling for OID_SKGE_DIAG_MODE in DiagActions().
+ *
+ *	Revision 1.109  2003/07/17 14:15:24  tschilli
+ *	Bug in SkPnmiGenIoctl() fixed.
+ *
+ *	Revision 1.108  2003/05/27 07:10:11  tschilli
+ *	Bug in SkPnmiGenIoctl() fixed.
+ *
+ *	Revision 1.107  2003/05/23 13:01:10  tschilli
+ *	Code for DIAG support added (#define SK_DIAG_SUPPORT).
+ *	Code for generic PNMI IOCTL support added. The new function
+ *	SkPnmiGenIoctl() is used for this purpose.
+ *	Handling of OID_SKGE_BOARDLEVEL added.
+ *	Incorrect buffer size handling of OID_SKGE_MTU during GET action fixed.
+ *	Return code handling in PowerManagement() fixed.
+ *	Editorial changes.
+ *
+ *	Revision 1.106  2003/04/10 14:47:31  rschmidt
+ *	Fixed handling for OID_GEN_RCV_OK and OID_GEN_XMIT_OK for YUKON's GMAC
+ *	in GetPhysStatVal().
+ *	Replaced macro PHY_READ() with function call SkXmPhyRead().
+ *	Made optimisations for readability and code size.
+ *	Editorial changes.
+ *
+ *	Revision 1.105  2003/04/09 12:51:32  rschmidt
+ *	Fixed XMAC only handling for some events in SkPnmiEvent().
+ *	Fixed return value for OID_GEN_RCV_OK (SK_PNMI_HRX) in GetPhysStatVal().
+ *	Editorial changes.
+ *
+ *	Revision 1.104  2003/03/27 11:18:21  tschilli
+ *	BRK statements from DEBUG code removed.
+ *	OID_GEN_XMIT_OK and OID_GEN_RCV_OK work with Yukon now.
+ *	Copyright messages changed.
+ *
+ *	Revision 1.103  2002/12/20 09:57:13  tschilli
+ *	SK_PNMI_EVT_VCT_RESET event code changed.
+ *	Unused variable from Vct() removed.
+ *
+ *	Revision 1.102  2002/12/16 14:03:24  tschilli
+ *	VCT code in Vct() changed.
+ *
+ *	Revision 1.101  2002/12/16 09:04:10  tschilli
+ *	Code for VCT handling added.
+ *
+ *	Revision 1.100  2002/09/26 14:28:13  tschilli
+ *	For XMAC the values in the SK_PNMI_PORT Port struct are copied to
+ *	the new SK_PNMI_PORT BufPort struct during a MacUpdate() call.
+ *	These values are used when GetPhysStatVal() is called. With this
+ *	mechanism you get the best results when software corrections for
+ *	counters are needed. Example: RX_LONGFRAMES.
+ *
+ *	Revision 1.99  2002/09/17 12:31:19  tschilli
+ *	OID_SKGE_TX_HW_ERROR_CTS, OID_SKGE_OUT_ERROR_CTS, OID_GEN_XMIT_ERROR:
+ *	Double count of SK_PNMI_HTX_EXCESS_COL in function General() removed.
+ *	OID_PNP_CAPABILITIES: sizeof(SK_PM_WAKE_UP_CAPABILITIES) changed to
+ *	sizeof(SK_PNP_CAPABILITIES) in function PowerManagement().
+ *
+ *	Revision 1.98  2002/09/10 09:00:03  rwahl
+ *	Adapted boolean definitions according sktypes.
+ *
+ *	Revision 1.97  2002/09/05 15:07:03  rwahl
+ *	Editorial changes.
+ *
+ *	Revision 1.96  2002/09/05 11:04:14  rwahl
+ *	- Rx/Tx packets statistics of virtual port were zero on link down (#10750)
+ *	- For GMAC the overflow IRQ for Rx longframe counter was not counted.
+ *	- Incorrect calculation for oids OID_SKGE_RX_HW_ERROR_CTS,
+ *	  OID_SKGE_IN_ERRORS_CTS,  OID_GEN_RCV_ERROR.
+ *	- Moved correction for OID_SKGE_STAT_RX_TOO_LONG to GetPhysStatVal().
+ *	- Editorial changes.
+ *
+ *	Revision 1.95  2002/09/04 08:53:37  rwahl
+ *	- Incorrect statistics for Rx_too_long counter with jumbo frame (#10751)
+ *	- StatRxFrameTooLong & StatRxPMaccErr counters were not reset.
+ *	- Fixed compiler warning for debug msg arg types.
+ *
+ *	Revision 1.94  2002/08/09 15:42:14  rwahl
+ *	- Fixed StatAddr table for GMAC.
+ *	- VirtualConf(): returned indeterminated status for speed oids if no
+ *	  active port.
+ *
+ *	Revision 1.93  2002/08/09 11:04:59  rwahl
+ *	Added handler for link speed caps.
+ *
+ *	Revision 1.92  2002/08/09 09:43:03  rwahl
+ *	- Added handler for NDIS OID_PNP_xxx ids.
+ *
+ *	Revision 1.91  2002/07/17 19:53:03  rwahl
+ *	- Added StatOvrflwBit table for XMAC & GMAC.
+ *	- Extended StatAddr table for GMAC. Added check of number of counters
+ *	  in enumeration and size of StatAddr table on init level.
+ *	- Added use of GIFunc table.
+ *	- ChipSet is not static anymore,
+ *	- Extended SIRQ event handler for both MAC types.
+ *	- Fixed rx short counter bug (#10620)
+ *	- Added handler for oids SKGE_SPEED_MODE & SKGE_SPEED_STATUS.
+ *	- Extended GetPhysStatVal() for GMAC.
+ *	- Editorial changes.
+ *
+ *	Revision 1.90  2002/05/22 08:56:25  rwahl
+ *	- Moved OID table to separate source file.
+ *	- Fix: TX_DEFFERAL counter incremented in full-duplex mode.
+ *	- Use string definitions for error msgs.
+ *
+ *	Revision 1.89  2001/09/18 10:01:30  mkunz
+ *	some OID's fixed for dualnetmode
+ *
+ *	Revision 1.88  2001/08/02 07:58:08  rwahl
+ *	- Fixed NetIndex to csum module at ResetCounter().
+ *
+ *	Revision 1.87  2001/04/06 13:35:09  mkunz
+ *	-Bugs fixed in handling of OID_SKGE_MTU and the VPD OID's
+ *
+ *	Revision 1.86  2001/03/09 09:18:03  mkunz
+ *	Changes in SK_DBG_MSG
+ *
+ *	Revision 1.85  2001/03/08 09:37:31  mkunz
+ *	Bugfix in ResetCounter for Pnmi.Port structure
+ *
+ *	Revision 1.84  2001/03/06 09:04:55  mkunz
+ *	Made some changes in instance calculation
+ *
+ *	Revision 1.83  2001/02/15 09:15:32  mkunz
+ *	Necessary changes for dual net mode added
+ *
+ *	Revision 1.82  2001/02/07 08:24:19  mkunz
+ *	-Made changes in handling of OID_SKGE_MTU
+ *
+ *	Revision 1.81  2001/02/06 09:58:00  mkunz
+ *	-Vpd bug fixed
+ *	-OID_SKGE_MTU added
+ *	-PNMI support for dual net mode. Interface function and macros extended
+ *
+ *	Revision 1.80  2001/01/22 13:41:35  rassmann
+ *	Supporting two nets on dual-port adapters.
+ *
+ *	Revision 1.79  2000/12/05 14:57:40  cgoos
+ *	SetStruct failed before first Link Up (link mode of virtual
+ *	port "INDETERMINATED").
+ *
+ *	Revision 1.78  2000/09/12 10:44:58  cgoos
+ *	Fixed SK_PNMI_STORE_U32 calls with typecasted argument.
+ *
+ *	Revision 1.77  2000/09/07 08:10:19  rwahl
+ *	- Modified algorithm for 64bit NDIS statistic counters;
+ *	  returns 64bit or 32bit value depending on passed buffer
+ *	  size. Indicate capability for 64bit NDIS counter, if passed
+ *	  buffer size is zero. OID_GEN_XMIT_ERROR, OID_GEN_RCV_ERROR,
+ *	  and OID_GEN_RCV_NO_BUFFER handled as 64bit counter, too.
+ *	- corrected OID_SKGE_RLMT_PORT_PREFERRED.
+ *
+ *	Revision 1.76  2000/08/03 15:23:39  rwahl
+ *	- Correction for FrameTooLong counter has to be moved to OID handling
+ *	  routines (instead of statistic counter routine).
+ *	- Fix in XMAC Reset Event handling: Only offset counter for hardware
+ *	  statistic registers are updated.
+ *
+ *	Revision 1.75  2000/08/01 16:46:05  rwahl
+ *	- Added StatRxLongFrames counter and correction of FrameTooLong counter.
+ *	- Added directive to control width (default = 32bit) of NDIS statistic
+ *	  counters (SK_NDIS_64BIT_CTR).
+ *
+ *	Revision 1.74  2000/07/04 11:41:53  rwahl
+ *	- Added volition connector type.
+ *
+ *	Revision 1.73  2000/03/15 16:33:10  rwahl
+ *	Fixed bug 10510; wrong reset of virtual port statistic counters.
+ *
+ *	Revision 1.72  1999/12/06 16:15:53  rwahl
+ *	Fixed problem of instance range for current and factory MAC address.
+ *
+ *	Revision 1.71  1999/12/06 10:14:20  rwahl
+ *	Fixed bug 10476; set operation for PHY_OPERATION_MODE.
+ *
+ *	Revision 1.70  1999/11/22 13:33:34  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.69  1999/10/18 11:42:15  rwahl
+ *	Added typecasts for checking event dependent param (debug only).
+ *
+ *	Revision 1.68  1999/10/06 09:35:59  cgoos
+ *	Added state check to PHY_READ call (hanged if called during startup).
+ *
+ *	Revision 1.67  1999/09/22 09:53:20  rwahl
+ *	- Read Broadcom register for updating FCS error counter (1000Base-T).
+ *
+ *	Revision 1.66  1999/08/26 13:47:56  rwahl
+ *	Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap.
+ *
+ *	Revision 1.65  1999/07/26 07:49:35  cgoos
+ *	Added two typecasts to avoid compiler warnings.
+ *
+ *	Revision 1.64  1999/05/20 09:24:12  cgoos
+ *	Changes for 1000Base-T (sensors, Master/Slave).
+ *
+ *	Revision 1.63  1999/04/13 15:11:58  mhaveman
+ *	Moved include of rlmt.h to header skgepnmi.h because some macros
+ *	are needed there.
+ *
+ *	Revision 1.62  1999/04/13 15:08:07  mhaveman
+ *	Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK
+ *	to grant unified interface by only using the PNMI header file.
+ *	SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK.
+ *
+ *	Revision 1.61  1999/04/13 15:02:48  mhaveman
+ *	Changes caused by review:
+ *	-Changed some comments
+ *	-Removed redundant check for OID_SKGE_PHYS_FAC_ADDR
+ *	-Optimized PRESET check.
+ *	-Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same
+ *	 address will now not cause this error. Removed corresponding check.
+ *
+ *	Revision 1.60  1999/03/23 10:41:23  mhaveman
+ *	Added comments.
+ *
+ *	Revision 1.59  1999/02/19 08:01:28  mhaveman
+ *	Fixed bug 10372 that after counter reset all ports were displayed
+ *	as inactive.
+ *
+ *	Revision 1.58  1999/02/16 18:04:47  mhaveman
+ *	Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME.
+ *
+ *	Revision 1.56  1999/01/27 12:29:11  mhaveman
+ *	SkTimerStart was called with time value in milli seconds but needs
+ *	micro seconds.
+ *
+ *	Revision 1.55  1999/01/25 15:00:38  mhaveman
+ *	Added support to allow multiple ports to be active. If this feature in
+ *	future will be used, the Management Data Base variables PORT_ACTIVE
+ *	and PORT_PREFERED should be moved to the port specific part of RLMT.
+ *	Currently they return the values of the first active physical port
+ *	found. A set to the virtual port will actually change all active
+ *	physical ports. A get returns the melted values of all active physical
+ *	ports. If the port values differ a return value INDETERMINATED will
+ *	be returned. This effects especially the CONF group.
+ *
+ *	Revision 1.54  1999/01/19 10:10:22  mhaveman
+ *	-Fixed bug 10354: Counter values of virtual port were wrong after port
+ *	 switches
+ *	-Added check if a switch to the same port is notified.
+ *
+ *	Revision 1.53  1999/01/07 09:25:21  mhaveman
+ *	Forgot to initialize a variable.
+ *
+ *	Revision 1.52  1999/01/05 10:34:33  mhaveman
+ *	Fixed little error in RlmtChangeEstimate calculation.
+ *
+ *	Revision 1.51  1999/01/05 09:59:07  mhaveman
+ *	-Moved timer start to init level 2
+ *	-Redesigned port switch average calculation to avoid 64bit
+ *	 arithmetic.
+ *
+ *	Revision 1.50  1998/12/10 15:13:59  mhaveman
+ *	-Fixed: PHYS_CUR_ADDR returned wrong addresses
+ *	-Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned
+ *	        always BAD_VALUE.
+ *	-Fixed: TRAP buffer seemed to sometimes suddenly empty
+ *
+ *	Revision 1.49  1998/12/09 16:17:07  mhaveman
+ *	Fixed: Couldnot delete VPD keys on UNIX.
+ *
+ *	Revision 1.48  1998/12/09 14:11:10  mhaveman
+ *	-Add: Debugmessage for XMAC_RESET supressed to minimize output.
+ *	-Fixed: RlmtChangeThreshold will now be initialized.
+ *	-Fixed: VPD_ENTRIES_LIST extended value with unnecessary space char.
+ *	-Fixed: On VPD key creation an invalid key name could be created
+ *	        (e.g. A5)
+ *	-Some minor changes in comments and code.
+ *
+ *	Revision 1.47  1998/12/08 16:00:31  mhaveman
+ *	-Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port
+ *		is active.
+ *	-Fixed: For the RLMT statistics group only the last value was
+ *		returned and the rest of the buffer was filled with 0xff
+ *	-Fixed: Mysteriously the preset on RLMT_MODE still returned
+ *		BAD_VALUE.
+ *	Revision 1.46  1998/12/08 10:04:56  mhaveman
+ *	-Fixed: Preset on RLMT_MODE returned always BAD_VALUE error.
+ *	-Fixed: Alignment error in GetStruct
+ *	-Fixed: If for Get/Preset/SetStruct the buffer size is equal or
+ *	        larger than SK_PNMI_MIN_STRUCT_SIZE the return value is stored
+ *		to the buffer. In this case the caller should always return
+ *	        ok to its upper routines. Only if the buffer size is less
+ *	        than SK_PNMI_MIN_STRUCT_SIZE and the return value is unequal
+ *	        to 0, an error should be returned by the caller.
+ *	-Fixed: Wrong number of instances with RLMT statistic.
+ *	-Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0.
+ *
+ *	Revision 1.45  1998/12/03 17:17:24  mhaveman
+ *	-Removed for VPD create action the buffer size limitation to 4 bytes.
+ *	-Pass now physical/active physical port to ADDR for CUR_ADDR set
+ *
+ *	Revision 1.44  1998/12/03 15:14:35  mhaveman
+ *	Another change to Vpd instance evaluation.
+ *
+ *	Revision 1.43  1998/12/03 14:18:10  mhaveman
+ *	-Fixed problem in PnmiSetStruct. It was impossible to set any value.
+ *	-Removed VPD key evaluation for VPD_FREE_BYTES and VPD_ACTION.
+ *
+ *	Revision 1.42  1998/12/03 11:31:47  mhaveman
+ *	Inserted cast to satisfy lint.
+ *
+ *	Revision 1.41  1998/12/03 11:28:16  mhaveman
+ *	Removed SK_PNMI_CHECKPTR
+ *
+ *	Revision 1.40  1998/12/03 11:19:07  mhaveman
+ *	Fixed problems
+ *	-A set to virtual port will now be ignored. A set with broadcast
+ *	 address to any port will be ignored.
+ *	-GetStruct function made VPD instance calculation wrong.
+ *	-Prefered port returned -1 instead of 0.
+ *
+ *	Revision 1.39  1998/11/26 15:30:29  mhaveman
+ *	Added sense mode to link mode.
+ *
+ *	Revision 1.38  1998/11/23 15:34:00  mhaveman
+ *	-Fixed bug for RX counters. On an RX overflow interrupt the high
+ *	 words of all RX counters were incremented.
+ *	-SET operations on FLOWCTRL_MODE and LINK_MODE accept now the
+ *	 value 0, which has no effect. It is usefull for multiple instance
+ *	 SETs.
+ *
+ *	Revision 1.37  1998/11/20 08:02:04  mhaveman
+ *	-Fixed: Ports were compared with MAX_SENSORS
+ *	-Fixed: Crash in GetTrapEntry with MEMSET macro
+ *	-Fixed: Conversions between physical, logical port index and instance
+ *
+ *	Revision 1.36  1998/11/16 07:48:53  mhaveman
+ *	Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings
+ *	on Solaris.
+ *
+ *	Revision 1.35  1998/11/16 07:45:34  mhaveman
+ *	SkAddrOverride now returns value and will be checked.
+ *
+ *	Revision 1.34  1998/11/10 13:40:37  mhaveman
+ *	Needed to change interface, because NT driver needs a return value
+ *	of needed buffer space on TOO_SHORT errors. Therefore all
+ *	SkPnmiGet/Preset/Set functions now have a pointer to the length
+ *	parameter, where the needed space on error is returned.
+ *
+ *	Revision 1.33  1998/11/03 13:52:46  mhaveman
+ *	Made file lint conform.
+ *
+ *	Revision 1.32  1998/11/03 13:19:07  mhaveman
+ *	The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in
+ *	Para32[0] the physical MAC index and in Para32[1] the new mode.
+ *
+ *	Revision 1.31  1998/11/03 12:30:40  gklug
+ *	fix: compiler warning memset
+ *
+ *	Revision 1.30  1998/11/03 12:04:46  mhaveman
+ *	Fixed problem in SENSOR_VALUE, which wrote beyond the buffer end
+ *	Fixed alignment problem with CHIPSET.
+ *
+ *	Revision 1.29  1998/11/02 11:23:54  mhaveman
+ *	Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry.
+ *
+ *	Revision 1.28  1998/11/02 10:47:16  mhaveman
+ *	Added syslog messages for internal errors.
+ *
+ *	Revision 1.27  1998/10/30 15:48:06  mhaveman
+ *	Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and
+ *	RlmtChangeThreshold calculation.
+ *
+ *	Revision 1.26  1998/10/29 15:36:55  mhaveman
+ *	-Fixed bug in trap buffer handling.
+ *	-OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR,
+ *	 OID_SKGE_HW_VERSION, OID_SKGE_VPD_ENTRIES_LIST, OID_SKGE_VPD_KEY,
+ *	 OID_SKGE_VPD_VALUE, and OID_SKGE_SENSOR_DESCR return values with
+ *	 a leading octet before each string storing the string length.
+ *	-Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize
+ *	 RlmtUpdate calls in GetStatVal.
+ *	-Inserted SK_PNMI_CHECKFLAGS macro increase readability.
+ *
+ *	Revision 1.25  1998/10/29 08:50:36  mhaveman
+ *	Fixed problems after second event simulation.
+ *
+ *	Revision 1.24  1998/10/28 08:44:37  mhaveman
+ *	-Fixed alignment problem
+ *	-Fixed problems during event simulation
+ *	-Fixed sequence of error return code (INSTANCE -> ACCESS -> SHORT)
+ *	-Changed type of parameter Instance back to SK_U32 because of VPD
+ *	-Updated new VPD function calls
+ *
+ *	Revision 1.23  1998/10/23 10:16:37  mhaveman
+ *	Fixed bugs after buffer test simulation.
+ *
+ *	Revision 1.22  1998/10/21 13:23:52  mhaveman
+ *	-Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc).
+ *	-Changed calculation of hundreds of seconds.
+ *
+ *	Revision 1.20  1998/10/20 07:30:45  mhaveman
+ *	Made type changes to unsigned integer where possible.
+ *
+ *	Revision 1.19  1998/10/19 10:51:30  mhaveman
+ *	-Made Bug fixes after simulation run
+ *	-Renamed RlmtMAC... to RlmtPort...
+ *	-Marked workarounds with Errata comments
+ *
+ *	Revision 1.18  1998/10/14 07:50:08  mhaveman
+ *	-For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT
+ *	 to HWACCESS.
+ *	-Provided all MEMCPY/MEMSET macros with (char *)pointers, because
+ *	 Solaris throwed warnings when mapping to bcopy/bset.
+ *
+ *	Revision 1.17  1998/10/13 07:42:01  mhaveman
+ *	-Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA
+ *	-Removed old cvs history entries
+ *	-Renamed MacNumber to PortNumber
+ *
+ *	Revision 1.16  1998/10/07 10:52:49  mhaveman
+ *	-Inserted handling of some OID_GEN_ Ids for Windows
+ *	-Fixed problem with 803.2 statistic.
+ *
+ *	Revision 1.15  1998/10/01 09:16:29  mhaveman
+ *	Added Debug messages for function call and UpdateFlag tracing.
+ *
+ *	Revision 1.14  1998/09/30 13:39:09  mhaveman
+ *	-Reduced namings of 'MAC' by replacing them with 'PORT'.
+ *	-Completed counting of OID_SKGE_RX_HW_ERROR_CTS, OID_SKGE_TX_HW_ERROR_CTS,
+ *	 OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS.
+ *	-SET check for RlmtMode
+ *
+ *	Revision 1.13  1998/09/28 13:13:08  mhaveman
+ *	Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN,
+ *	and SK_STRNCPY. (Same reasons as for mem.. and MEM..)
+ *
+ *	Revision 1.12  1998/09/16 08:18:36  cgoos
+ *	Fix: XM_INxx and XM_OUTxx called with different parameter order
+ *	Fix: inserted "Pnmi." into some pAC->pDriverDescription / Version.
+ *	Change: memset, memcpy to makros SK_MEMSET, SK_MEMCPY
+ *
+ *	Revision 1.11  1998/09/04 17:01:45  mhaveman
+ *	Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to
+ *	OID_SKGE_RX_NO_BUF_CTS.
+ *
+ *	Revision 1.10  1998/09/04 14:35:35  mhaveman
+ *	Added macro counters, that are counted by driver.
+ *
+ ****************************************************************************/
+
+#if defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/pnmi/V7/skgepnmi.c#7 $ (C) Marvell.";
+#endif
+
+#include "h/skdrv1st.h"
+#include "h/sktypes.h"
+#include "h/xmac_ii.h"
+#include "h/skdebug.h"
+#include "h/skqueue.h"
+#include "h/skgepnmi.h"
+#include "h/skgesirq.h"
+#include "h/skcsum.h"
+#include "h/skvpd.h"
+#include "h/skgehw.h"
+#include "h/sky2le.h"
+#include "h/skgeinit.h"
+#include "h/skdrv2nd.h"
+#include "h/skgepnm2.h"
+#ifdef SK_POWER_MGMT
+#include "h/skgepmgt.h"
+#endif /* SK_POWER_MGMT */
+
+/* defines *******************************************************************/
+
+#ifndef DEBUG
+#define PNMI_STATIC	static
+#else	/* DEBUG */
+#define PNMI_STATIC
+#endif /* DEBUG */
+
+/*
+ * Private Function prototypes
+ */
+
+PNMI_STATIC SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
+	PhysPortIndex);
+PNMI_STATIC SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
+	PhysPortIndex);
+PNMI_STATIC void CopyMac(char *pDst, SK_MAC_ADDR *pMac);
+PNMI_STATIC void CopyTrapQueue(SK_AC *pAC, char *pDstBuf);
+PNMI_STATIC SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC,
+	unsigned int PhysPortIndex, unsigned int StatIndex);
+PNMI_STATIC SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex,
+	unsigned int StatIndex, SK_U32 NetIndex);
+PNMI_STATIC char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size);
+PNMI_STATIC void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen,
+	unsigned int *pEntries);
+PNMI_STATIC int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr,
+	unsigned int KeyArrLen, unsigned int *pKeyNo);
+PNMI_STATIC int LookupId(SK_U32 Id);
+PNMI_STATIC int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac,
+	unsigned int LastMac);
+PNMI_STATIC int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf,
+	unsigned int *pLen, SK_U32 NetIndex);
+PNMI_STATIC int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id,
+	char *pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
+PNMI_STATIC void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac);
+PNMI_STATIC void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId,
+	unsigned int PortIndex);
+PNMI_STATIC void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId,
+	unsigned int SensorIndex);
+PNMI_STATIC void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId);
+PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
+#ifndef SK_NO_RLMT
+PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
+#endif
+PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
+PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
+PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
+PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32);
+
+/*
+ * Table to correlate OID with handler function and index to
+ * hardware register stored in StatAddress if applicable.
+ */
+#include "skgemib.c"
+
+/* global variables **********************************************************/
+
+/*
+ * Overflow status register bit table and corresponding counter
+ * dependent on MAC type - the number relates to the size of overflow
+ * mask returned by the pFnMacOverflow function
+ */
+PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = {
+/* Bit0  */	{ SK_PNMI_HTX, 				SK_PNMI_HTX_UNICAST},
+/* Bit1  */	{ SK_PNMI_HTX_OCTETHIGH, 	SK_PNMI_HTX_BROADCAST},
+/* Bit2  */	{ SK_PNMI_HTX_OCTETLOW, 	SK_PNMI_HTX_PMACC},
+/* Bit3  */	{ SK_PNMI_HTX_BROADCAST, 	SK_PNMI_HTX_MULTICAST},
+/* Bit4  */	{ SK_PNMI_HTX_MULTICAST, 	SK_PNMI_HTX_OCTETLOW},
+/* Bit5  */	{ SK_PNMI_HTX_UNICAST, 		SK_PNMI_HTX_OCTETHIGH},
+/* Bit6  */	{ SK_PNMI_HTX_LONGFRAMES, 	SK_PNMI_HTX_64},
+/* Bit7  */	{ SK_PNMI_HTX_BURST, 		SK_PNMI_HTX_127},
+/* Bit8  */	{ SK_PNMI_HTX_PMACC, 		SK_PNMI_HTX_255},
+/* Bit9  */	{ SK_PNMI_HTX_MACC, 		SK_PNMI_HTX_511},
+/* Bit10 */	{ SK_PNMI_HTX_SINGLE_COL, 	SK_PNMI_HTX_1023},
+/* Bit11 */	{ SK_PNMI_HTX_MULTI_COL, 	SK_PNMI_HTX_MAX},
+/* Bit12 */	{ SK_PNMI_HTX_EXCESS_COL, 	SK_PNMI_HTX_LONGFRAMES},
+/* Bit13 */	{ SK_PNMI_HTX_LATE_COL, 	SK_PNMI_HTX_RESERVED},
+/* Bit14 */	{ SK_PNMI_HTX_DEFFERAL, 	SK_PNMI_HTX_COL},
+/* Bit15 */	{ SK_PNMI_HTX_EXCESS_DEF, 	SK_PNMI_HTX_LATE_COL},
+/* Bit16 */	{ SK_PNMI_HTX_UNDERRUN, 	SK_PNMI_HTX_EXCESS_COL},
+/* Bit17 */	{ SK_PNMI_HTX_CARRIER, 		SK_PNMI_HTX_MULTI_COL},
+/* Bit18 */	{ SK_PNMI_HTX_UTILUNDER, 	SK_PNMI_HTX_SINGLE_COL},
+/* Bit19 */	{ SK_PNMI_HTX_UTILOVER, 	SK_PNMI_HTX_UNDERRUN},
+/* Bit20 */	{ SK_PNMI_HTX_64, 			SK_PNMI_HTX_RESERVED},
+/* Bit21 */	{ SK_PNMI_HTX_127, 			SK_PNMI_HTX_RESERVED},
+/* Bit22 */	{ SK_PNMI_HTX_255, 			SK_PNMI_HTX_RESERVED},
+/* Bit23 */	{ SK_PNMI_HTX_511, 			SK_PNMI_HTX_RESERVED},
+/* Bit24 */	{ SK_PNMI_HTX_1023, 		SK_PNMI_HTX_RESERVED},
+/* Bit25 */	{ SK_PNMI_HTX_MAX, 			SK_PNMI_HTX_RESERVED},
+/* Bit26 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit27 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit28 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit29 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit30 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit31 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
+/* Bit32 */	{ SK_PNMI_HRX, 				SK_PNMI_HRX_UNICAST},
+/* Bit33 */	{ SK_PNMI_HRX_OCTETHIGH, 	SK_PNMI_HRX_BROADCAST},
+/* Bit34 */	{ SK_PNMI_HRX_OCTETLOW, 	SK_PNMI_HRX_PMACC},
+/* Bit35 */	{ SK_PNMI_HRX_BROADCAST, 	SK_PNMI_HRX_MULTICAST},
+/* Bit36 */	{ SK_PNMI_HRX_MULTICAST, 	SK_PNMI_HRX_FCS},
+/* Bit37 */	{ SK_PNMI_HRX_UNICAST, 		SK_PNMI_HRX_RESERVED},
+/* Bit38 */	{ SK_PNMI_HRX_PMACC, 		SK_PNMI_HRX_OCTETLOW},
+/* Bit39 */	{ SK_PNMI_HRX_MACC, 		SK_PNMI_HRX_OCTETHIGH},
+/* Bit40 */	{ SK_PNMI_HRX_PMACC_ERR, 	SK_PNMI_HRX_BADOCTETLOW},
+/* Bit41 */	{ SK_PNMI_HRX_MACC_UNKWN,	SK_PNMI_HRX_BADOCTETHIGH},
+/* Bit42 */	{ SK_PNMI_HRX_BURST, 		SK_PNMI_HRX_UNDERSIZE},
+/* Bit43 */	{ SK_PNMI_HRX_MISSED, 		SK_PNMI_HRX_RUNT},
+/* Bit44 */	{ SK_PNMI_HRX_FRAMING, 		SK_PNMI_HRX_64},
+/* Bit45 */	{ SK_PNMI_HRX_OVERFLOW, 	SK_PNMI_HRX_127},
+/* Bit46 */	{ SK_PNMI_HRX_JABBER, 		SK_PNMI_HRX_255},
+/* Bit47 */	{ SK_PNMI_HRX_CARRIER, 		SK_PNMI_HRX_511},
+/* Bit48 */	{ SK_PNMI_HRX_IRLENGTH, 	SK_PNMI_HRX_1023},
+/* Bit49 */	{ SK_PNMI_HRX_SYMBOL, 		SK_PNMI_HRX_MAX},
+/* Bit50 */	{ SK_PNMI_HRX_SHORTS, 		SK_PNMI_HRX_LONGFRAMES},
+/* Bit51 */	{ SK_PNMI_HRX_RUNT, 		SK_PNMI_HRX_TOO_LONG},
+/* Bit52 */	{ SK_PNMI_HRX_TOO_LONG, 	SK_PNMI_HRX_JABBER},
+/* Bit53 */	{ SK_PNMI_HRX_FCS, 			SK_PNMI_HRX_RESERVED},
+/* Bit54 */	{ SK_PNMI_HRX_RESERVED, 	SK_PNMI_HRX_OVERFLOW},
+/* Bit55 */	{ SK_PNMI_HRX_CEXT, 		SK_PNMI_HRX_RESERVED},
+/* Bit56 */	{ SK_PNMI_HRX_UTILUNDER, 	SK_PNMI_HRX_RESERVED},
+/* Bit57 */	{ SK_PNMI_HRX_UTILOVER, 	SK_PNMI_HRX_RESERVED},
+/* Bit58 */	{ SK_PNMI_HRX_64, 			SK_PNMI_HRX_RESERVED},
+/* Bit59 */	{ SK_PNMI_HRX_127, 			SK_PNMI_HRX_RESERVED},
+/* Bit60 */	{ SK_PNMI_HRX_255, 			SK_PNMI_HRX_RESERVED},
+/* Bit61 */	{ SK_PNMI_HRX_511, 			SK_PNMI_HRX_RESERVED},
+/* Bit62 */	{ SK_PNMI_HRX_1023, 		SK_PNMI_HRX_RESERVED},
+/* Bit63 */	{ SK_PNMI_HRX_MAX, 			SK_PNMI_HRX_RESERVED}
+};
+
+/*
+ * Table for hardware register saving on resets and port switches
+ */
+PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] = {
+	/* SK_PNMI_HTX */
+	{{XM_TXF_OK, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_OCTETHIGH */
+	{{XM_TXO_OK_HI, SK_TRUE}, {GM_TXO_OK_HI, SK_TRUE}},
+	/* SK_PNMI_HTX_OCTETLOW */
+	{{XM_TXO_OK_LO, SK_FALSE}, {GM_TXO_OK_LO, SK_FALSE}},
+	/* SK_PNMI_HTX_BROADCAST */
+	{{XM_TXF_BC_OK, SK_TRUE}, {GM_TXF_BC_OK, SK_TRUE}},
+	/* SK_PNMI_HTX_MULTICAST */
+	{{XM_TXF_MC_OK, SK_TRUE}, {GM_TXF_MC_OK, SK_TRUE}},
+	/* SK_PNMI_HTX_UNICAST */
+	{{XM_TXF_UC_OK, SK_TRUE}, {GM_TXF_UC_OK, SK_TRUE}},
+	/* SK_PNMI_HTX_BURST */
+	{{XM_TXE_BURST, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_PMACC */
+	{{XM_TXF_MPAUSE, SK_TRUE}, {GM_TXF_MPAUSE, SK_TRUE}},
+	/* SK_PNMI_HTX_MACC */
+	{{XM_TXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_COL */
+	{{0, SK_FALSE}, {GM_TXF_COL, SK_TRUE}},
+	/* SK_PNMI_HTX_SINGLE_COL */
+	{{XM_TXF_SNG_COL, SK_TRUE}, {GM_TXF_SNG_COL, SK_TRUE}},
+	/* SK_PNMI_HTX_MULTI_COL */
+	{{XM_TXF_MUL_COL, SK_TRUE}, {GM_TXF_MUL_COL, SK_TRUE}},
+	/* SK_PNMI_HTX_EXCESS_COL */
+	{{XM_TXF_ABO_COL, SK_TRUE}, {GM_TXF_ABO_COL, SK_TRUE}},
+	/* SK_PNMI_HTX_LATE_COL */
+	{{XM_TXF_LAT_COL, SK_TRUE}, {GM_TXF_LAT_COL, SK_TRUE}},
+	/* SK_PNMI_HTX_DEFFERAL */
+	{{XM_TXF_DEF, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_EXCESS_DEF */
+	{{XM_TXF_EX_DEF, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_UNDERRUN */
+	{{XM_TXE_FIFO_UR, SK_TRUE}, {GM_TXE_FIFO_UR, SK_TRUE}},
+	/* SK_PNMI_HTX_CARRIER */
+	{{XM_TXE_CS_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_UTILUNDER */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_UTILOVER */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_64 */
+	{{XM_TXF_64B, SK_TRUE}, {GM_TXF_64B, SK_TRUE}},
+	/* SK_PNMI_HTX_127 */
+	{{XM_TXF_127B, SK_TRUE}, {GM_TXF_127B, SK_TRUE}},
+	/* SK_PNMI_HTX_255 */
+	{{XM_TXF_255B, SK_TRUE}, {GM_TXF_255B, SK_TRUE}},
+	/* SK_PNMI_HTX_511 */
+	{{XM_TXF_511B, SK_TRUE}, {GM_TXF_511B, SK_TRUE}},
+	/* SK_PNMI_HTX_1023 */
+	{{XM_TXF_1023B, SK_TRUE}, {GM_TXF_1023B, SK_TRUE}},
+	/* SK_PNMI_HTX_MAX */
+	{{XM_TXF_MAX_SZ, SK_TRUE}, {GM_TXF_1518B, SK_TRUE}},
+	/* SK_PNMI_HTX_LONGFRAMES  */
+	{{XM_TXF_LONG, SK_TRUE}, {GM_TXF_MAX_SZ, SK_TRUE}},
+	/* SK_PNMI_HTX_SYNC */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_SYNC_OCTET */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HTX_RESERVED */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX */
+	{{XM_RXF_OK, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_OCTETHIGH */
+	{{XM_RXO_OK_HI, SK_TRUE}, {GM_RXO_OK_HI, SK_TRUE}},
+	/* SK_PNMI_HRX_OCTETLOW */
+	{{XM_RXO_OK_LO, SK_FALSE}, {GM_RXO_OK_LO, SK_FALSE}},
+	/* SK_PNMI_HRX_BADOCTETHIGH */
+	{{0, SK_FALSE}, {GM_RXO_ERR_HI, SK_TRUE}},
+	/* SK_PNMI_HRX_BADOCTETLOW */
+	{{0, SK_FALSE}, {GM_RXO_ERR_LO, SK_TRUE}},
+	/* SK_PNMI_HRX_BROADCAST */
+	{{XM_RXF_BC_OK, SK_TRUE}, {GM_RXF_BC_OK, SK_TRUE}},
+	/* SK_PNMI_HRX_MULTICAST */
+	{{XM_RXF_MC_OK, SK_TRUE}, {GM_RXF_MC_OK, SK_TRUE}},
+	/* SK_PNMI_HRX_UNICAST */
+	{{XM_RXF_UC_OK, SK_TRUE}, {GM_RXF_UC_OK, SK_TRUE}},
+	/* SK_PNMI_HRX_PMACC */
+	{{XM_RXF_MPAUSE, SK_TRUE}, {GM_RXF_MPAUSE, SK_TRUE}},
+	/* SK_PNMI_HRX_MACC */
+	{{XM_RXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_PMACC_ERR */
+	{{XM_RXF_INV_MP, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_MACC_UNKWN */
+	{{XM_RXF_INV_MOC, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_BURST */
+	{{XM_RXE_BURST, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_MISSED */
+	{{XM_RXE_FMISS, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_FRAMING */
+	{{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_UNDERSIZE */
+	{{0, SK_FALSE}, {GM_RXF_SHT, SK_TRUE}},
+	/* SK_PNMI_HRX_OVERFLOW */
+	{{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}},
+	/* SK_PNMI_HRX_JABBER */
+	{{XM_RXF_JAB_PKT, SK_TRUE}, {GM_RXF_JAB_PKT, SK_TRUE}},
+	/* SK_PNMI_HRX_CARRIER */
+	{{XM_RXE_CAR_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_IRLENGTH */
+	{{XM_RXF_LEN_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_SYMBOL */
+	{{XM_RXE_SYM_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_SHORTS */
+	{{XM_RXE_SHT_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_RUNT */
+	{{XM_RXE_RUNT, SK_TRUE}, {GM_RXE_FRAG, SK_TRUE}},
+	/* SK_PNMI_HRX_TOO_LONG */
+	{{XM_RXF_LNG_ERR, SK_TRUE}, {GM_RXF_LNG_ERR, SK_TRUE}},
+	/* SK_PNMI_HRX_FCS */
+	{{XM_RXF_FCS_ERR, SK_TRUE}, {GM_RXF_FCS_ERR, SK_TRUE}},
+	/* SK_PNMI_HRX_CEXT */
+	{{XM_RXF_CEX_ERR, SK_TRUE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_UTILUNDER */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_UTILOVER */
+	{{0, SK_FALSE}, {0, SK_FALSE}},
+	/* SK_PNMI_HRX_64 */
+	{{XM_RXF_64B, SK_TRUE}, {GM_RXF_64B, SK_TRUE}},
+	/* SK_PNMI_HRX_127 */
+	{{XM_RXF_127B, SK_TRUE}, {GM_RXF_127B, SK_TRUE}},
+	/* SK_PNMI_HRX_255 */
+	{{XM_RXF_255B, SK_TRUE}, {GM_RXF_255B, SK_TRUE}},
+	/* SK_PNMI_HRX_511 */
+	{{XM_RXF_511B, SK_TRUE}, {GM_RXF_511B, SK_TRUE}},
+	/* SK_PNMI_HRX_1023 */
+	{{XM_RXF_1023B, SK_TRUE}, {GM_RXF_1023B, SK_TRUE}},
+	/* SK_PNMI_HRX_MAX */
+	{{XM_RXF_MAX_SZ, SK_TRUE}, {GM_RXF_1518B, SK_TRUE}},
+	/* SK_PNMI_HRX_LONGFRAMES */
+	{{0, SK_FALSE}, {GM_RXF_MAX_SZ, SK_TRUE}},
+	/* SK_PNMI_HRX_RESERVED */
+	{{0, SK_FALSE}, {0, SK_FALSE}}
+};
+
+
+/*****************************************************************************
+ *
+ * Public functions
+ *
+ */
+
+/*****************************************************************************
+ *
+ * SkPnmiInit - Init function of PNMI
+ *
+ * Description:
+ *	SK_INIT_DATA: Initializes the data structures
+ *	SK_INIT_IO:   Resets the XMAC statistics, determines the device and
+ *	              connector type.
+ *	SK_INIT_RUN:  Starts a timer event for port switch per hour
+ *	              calculation.
+ *
+ * Returns:
+ *	Always 0
+ */
+int SkPnmiInit(
+SK_AC	*pAC,		/* Pointer to adapter context */
+SK_IOC	IoC,		/* IO context handle */
+int		Level)		/* Initialization level */
+{
+	unsigned int	PortMax;	/* Number of ports */
+	unsigned int	PortIndex;	/* Current port index in loop */
+#ifndef SK_NO_RLMT
+	SK_EVPARA		EventParam;	/* Event struct for timer event */
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiInit: Called, level=%d\n", Level));
+
+	PortMax = pAC->GIni.GIMacsFound;
+
+	switch (Level) {
+
+	case SK_INIT_DATA:
+		SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
+
+		pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
+		pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+		pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
+
+		for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
+
+			pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
+			pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
+
+			/* Initialize DSP variables for Vct() to 0xff => Never written! */
+			pAC->GIni.GP[PortIndex].PCableLen = 0xff;
+			pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff;
+		}
+
+#ifdef SK_PNMI_CHECK
+		if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
+					   ("CounterOffset struct size (%d) differs from"
+						"SK_PNMI_MAX_IDX (%d)\n",
+						SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX));
+		}
+
+		if (SK_PNMI_MAX_IDX !=
+			(sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
+					   ("StatAddr table size (%d) differs from "
+						"SK_PNMI_MAX_IDX (%d)\n",
+						(sizeof(StatAddr) /
+						 (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)),
+						 SK_PNMI_MAX_IDX));
+		}
+#endif /* SK_PNMI_CHECK */
+		break;
+
+	case SK_INIT_IO:
+
+		/* Reset MAC counters. */
+		for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
+
+			pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
+		}
+
+		/* Get PCI bus speed. */
+		if (pAC->GIni.GIPciClock66) {
+
+			pAC->Pnmi.PciBusSpeed = 66;
+		}
+		else {
+			pAC->Pnmi.PciBusSpeed = 33;
+		}
+
+		/* Get PCI bus width. */
+		if (pAC->GIni.GIPciSlot64) {
+
+			pAC->Pnmi.PciBusWidth = 64;
+		}
+		else {
+			pAC->Pnmi.PciBusWidth = 32;
+		}
+
+		/* Get chipset. */
+		switch (pAC->GIni.GIChipId) {
+
+		case CHIP_ID_YUKON:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;
+			break;
+
+		case CHIP_ID_YUKON_LITE:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE;
+			break;
+
+		case CHIP_ID_YUKON_LP:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP;
+			break;
+
+		case CHIP_ID_YUKON_XL:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL;
+			break;
+
+		case CHIP_ID_YUKON_EC:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC;
+			break;
+
+		case CHIP_ID_YUKON_FE:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE;
+			break;
+
+		case CHIP_ID_YUKON_FE_P:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE_P;
+			break;
+
+		case CHIP_ID_YUKON_EC_U:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC_U;
+			break;
+
+		case CHIP_ID_YUKON_EX:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EX;
+			break;
+
+		case CHIP_ID_YUKON_SUPR:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_SUPR;
+			break;
+
+		case CHIP_ID_YUKON_UL_2:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_UL_2;
+			break;
+
+		case CHIP_ID_YUKON_OPT:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_OPT;
+			break;
+
+		case CHIP_ID_YUKON_PRM:
+			pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_PRM;
+			break;
+
+		default:
+			break;
+		}
+
+		/* Get PMD and Device Type. */
+		switch (pAC->GIni.GIPmdTyp) {
+
+		case 'S':
+			pAC->Pnmi.PMD = 3;
+			pAC->Pnmi.DeviceType = 0x00020001;
+			break;
+
+		case 'L':
+			pAC->Pnmi.PMD = 2;
+			pAC->Pnmi.DeviceType = 0x00020003;
+			break;
+
+		case 'C':
+			pAC->Pnmi.PMD = 4;
+			pAC->Pnmi.DeviceType = 0x00020005;
+			break;
+
+		case 'T':
+			pAC->Pnmi.PMD = 5;
+			pAC->Pnmi.DeviceType = 0x00020007;
+			break;
+
+		default :
+			pAC->Pnmi.PMD = 1;
+			pAC->Pnmi.DeviceType = 0;
+			break;
+		}
+
+		if (PortMax > 1) {
+
+			pAC->Pnmi.DeviceType++;
+		}
+
+		/* Get connector type. */
+		switch (pAC->GIni.GIConTyp) {
+
+		case 'C':
+			pAC->Pnmi.Connector = 2;
+			break;
+
+		case 'D':
+			pAC->Pnmi.Connector = 3;
+			break;
+
+		case 'F':
+			pAC->Pnmi.Connector = 4;
+			break;
+
+		case 'J':
+			pAC->Pnmi.Connector = 5;
+			break;
+
+		case 'V':
+			pAC->Pnmi.Connector = 6;
+			break;
+
+		default:
+			pAC->Pnmi.Connector = 1;
+			break;
+		}
+		break;
+
+	case SK_INIT_RUN:
+#ifndef SK_NO_RLMT
+		if (PortMax > 1) {
+			/* Start timer for RLMT change counter */
+			SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+			SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
+				SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
+				EventParam);
+		}
+#endif
+		break;
+
+	default:
+		break; /* Nothing to do. */
+	}
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiGetVar - Retrieves the value of a single OID
+ *
+ * Description:
+ *	Calls a general sub-function for all this stuff. If the instance
+ *	-1 is passed, the values of all instances are returned in an
+ *	array of values.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to take
+ *	                         the data.
+ *	SK_PNMI_ERR_UNKNOWN_OID  The requested OID is unknown
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+int SkPnmiGetVar(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 Id,		/* Object ID that is to be processed */
+void *pBuf,		/* Buffer to which the management data will be copied */
+unsigned int *pLen,	/* On call: buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiGetVar, Id=0x%x, Len=%d, Buf=%d, Inst=%d, NetIdx=%d\n",
+		 Id, *pLen, *(char *)pBuf, Instance, NetIndex));
+
+	return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen,
+		Instance, NetIndex));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiPreSetVar - Presets the value of a single OID
+ *
+ * Description:
+ *	Calls a general sub-function for all this stuff. The preset does
+ *	the same as a set, but returns just before finally setting the
+ *	new value. This is usefull to check if a set might be successfull.
+ *	If the instance -1 is passed, an array of values is supposed and
+ *	all instances of the OID will be set.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_OID  The requested OID is unknown.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+int SkPnmiPreSetVar(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 Id,		/* Object ID that is to be processed */
+void *pBuf,		/* Buffer to which the management data will be copied */
+unsigned int *pLen,	/* Total length of management data */
+SK_U32 Instance,	/* Instance (1..n) that is to be set or -1 */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
+			Id, *pLen, Instance, NetIndex));
+
+	return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
+		Instance, NetIndex));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiSetVar - Sets the value of a single OID
+ *
+ * Description:
+ *	Calls a general sub-function for all this stuff. The preset does
+ *	the same as a set, but returns just before finally setting the
+ *	new value. This is usefull to check if a set might be successfull.
+ *	If the instance -1 is passed, an array of values is supposed and
+ *	all instances of the OID will be set.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_OID  The requested OID is unknown.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+int SkPnmiSetVar(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 Id,		/* Object ID that is to be processed */
+void *pBuf,		/* Buffer to which the management data will be copied */
+unsigned int *pLen,	/* Total length of management data */
+SK_U32 Instance,	/* Instance (1..n) that is to be set or -1 */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiSetVar, Id=0x%x, Len=%d, Buf=%d, Inst=%d, NetIdx=%d\n",
+		 Id, *pLen, *(char *)pBuf, Instance, NetIndex));
+
+	return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen,
+		Instance, NetIndex));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ *	Runs through the IdTable, queries the single OIDs and stores the
+ *	returned data into the management database structure
+ *	SK_PNMI_STRUCT_DATA. The offset of the OID in the structure
+ *	is stored in the IdTable. The return value of the function will also
+ *	be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
+ *	minimum size of SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to take
+ *	                         the data.
+ *	SK_PNMI_ERR_UNKNOWN_NET  The requested NetIndex doesn't exist
+ */
+int SkPnmiGetStruct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+void *pBuf,		/* Buffer to which the management data will be copied. */
+unsigned int *pLen,	/* Length of buffer */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int		Ret;
+	unsigned int	TableIndex;
+	unsigned int	DstOffset;
+	unsigned int	InstanceNo;
+	unsigned int	InstanceCnt;
+	SK_U32		Instance;
+	unsigned int	TmpLen;
+	char		KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",
+			*pLen, NetIndex));
+
+	if (*pLen < SK_PNMI_STRUCT_SIZE) {
+
+		if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
+
+			SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
+		}
+
+		*pLen = SK_PNMI_STRUCT_SIZE;
+		return (SK_PNMI_ERR_TOO_SHORT);
+	}
+#ifndef SK_NO_RLMT
+	/* Check NetIndex. */
+	if (NetIndex >= pAC->Rlmt.NumNets) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#else
+	if (NetIndex >= pAC->GIni.GIMacsFound) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#endif
+
+	/* Update statistics. */
+	SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
+
+	if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
+		SK_PNMI_ERR_OK) {
+
+		SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+		*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+		return (Ret);
+	}
+#ifndef SK_NO_RLMT
+	if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
+
+		SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+		*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+		return (Ret);
+	}
+#endif
+	if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+		SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+		*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+		return (Ret);
+	}
+
+	/* Increment semaphores to indicate that an update was already done. */
+	pAC->Pnmi.MacUpdatedFlag ++;
+	pAC->Pnmi.RlmtUpdatedFlag ++;
+	pAC->Pnmi.SirqUpdatedFlag ++;
+
+	/*
+	 * Get VPD keys for instance calculation.
+	 * Please read comment in Vpd().
+	 */
+	if (!pAC->Pnmi.VpdKeyReadError) {
+		Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
+
+		if (Ret != SK_PNMI_ERR_OK && !pAC->Pnmi.VpdKeyReadError) {
+
+			pAC->Pnmi.MacUpdatedFlag --;
+			pAC->Pnmi.RlmtUpdatedFlag --;
+			pAC->Pnmi.SirqUpdatedFlag --;
+
+			SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+			SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+			*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+
+	/* Retrieve values. */
+	SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
+
+	for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
+
+		InstanceNo = IdTable[TableIndex].InstanceNo;
+		for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) {
+
+			DstOffset = IdTable[TableIndex].Offset +
+				(InstanceCnt - 1) *
+				IdTable[TableIndex].StructSize;
+
+			/*
+			 * For VPD the instance is not an index number but the key itself.
+			 * Determine with the instance counter the VPD key to be used.
+			 */
+			if ((IdTable[TableIndex].Id == OID_SKGE_VPD_KEY ||
+				 IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE ||
+				 IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS ||
+				 IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) &&
+				!pAC->Pnmi.VpdKeyReadError) {
+
+				SK_STRNCPY((char *)&Instance, KeyArr[InstanceCnt - 1], 4);
+			}
+			else {
+				Instance = (SK_U32)InstanceCnt;
+			}
+
+			TmpLen = *pLen - DstOffset;
+			Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET,
+				IdTable[TableIndex].Id, (char *)pBuf +
+				DstOffset, &TmpLen, Instance, TableIndex, NetIndex);
+
+			/*
+			 * An unknown instance error means that we reached
+			 * the last instance of that variable. Proceed with
+			 * the next OID in the table and ignore the return
+			 * code.
+			 */
+			if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
+
+				break;
+			}
+
+			if (Ret != SK_PNMI_ERR_OK) {
+
+				pAC->Pnmi.MacUpdatedFlag --;
+				pAC->Pnmi.RlmtUpdatedFlag --;
+				pAC->Pnmi.SirqUpdatedFlag --;
+
+				SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+				SK_PNMI_SET_STAT(pBuf, Ret, DstOffset);
+				*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+				return (Ret);
+			}
+		}
+	}
+
+	pAC->Pnmi.MacUpdatedFlag --;
+	pAC->Pnmi.RlmtUpdatedFlag --;
+	pAC->Pnmi.SirqUpdatedFlag --;
+
+	*pLen = SK_PNMI_STRUCT_SIZE;
+	SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
+	SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ *	Calls a general sub-function for all this set stuff. The preset does
+ *	the same as a set, but returns just before finally setting the
+ *	new value. This is usefull to check if a set might be successfull.
+ *	The sub-function runs through the IdTable, checks which OIDs are able
+ *	to set, and calls the handler function of the OID to perform the
+ *	preset. The return value of the function will also be stored in
+ *	SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ *	SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ */
+int SkPnmiPreSetStruct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+void *pBuf,		/* Buffer which contains the data to be set */
+unsigned int *pLen,	/* Length of buffer */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n",
+			*pLen, NetIndex));
+
+	return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf,
+    					pLen, NetIndex));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ *	Calls a general sub-function for all this set stuff. The return value
+ *	of the function will also be stored in SK_PNMI_STRUCT_DATA if the
+ *	passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE.
+ *	The sub-function runs through the IdTable, checks which OIDs are able
+ *	to set, and calls the handler function of the OID to perform the
+ *	set. The return value of the function will also be stored in
+ *	SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ *	SK_PNMI_MIN_STRUCT_SIZE.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ */
+int SkPnmiSetStruct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+void *pBuf,		/* Buffer which contains the data to be set */
+unsigned int *pLen,	/* Length of buffer */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+		("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n",
+			*pLen, NetIndex));
+
+	return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf,
+    					pLen, NetIndex));
+}
+
+/*****************************************************************************
+ *
+ * SkPnmiEvent - Event handler
+ *
+ * Description:
+ *	Handles the following events:
+ *	SK_PNMI_EVT_SIRQ_OVERFLOW     When a hardware counter overflows an
+ *	                              interrupt will be generated which is
+ *	                              first handled by SIRQ which generates a
+ *	                              this event. The event increments the
+ *	                              upper 32 bit of the 64 bit counter.
+ *	SK_PNMI_EVT_SEN_XXX           The event is generated by the I2C module
+ *	                              when a sensor reports a warning or
+ *	                              error. The event will store a trap
+ *	                              message in the trap buffer.
+ *	SK_PNMI_EVT_CHG_EST_TIMER     The timer event was initiated by this
+ *	                              module and is used to calculate the
+ *	                              port switches per hour.
+ *	SK_PNMI_EVT_CLEAR_COUNTER     The event clears all counters and
+ *	                              timestamps.
+ *	SK_PNMI_EVT_XMAC_RESET        The event is generated by the driver
+ *	                              before a hard reset of the XMAC is
+ *	                              performed. All counters will be saved
+ *	                              and added to the hardware counter
+ *	                              values after reset to grant continuous
+ *	                              counter values.
+ *	SK_PNMI_EVT_RLMT_PORT_UP      Generated by RLMT to notify that a port
+ *	                              went logically up. A trap message will
+ *	                              be stored to the trap buffer.
+ *	SK_PNMI_EVT_RLMT_PORT_DOWN    Generated by RLMT to notify that a port
+ *	                              went logically down. A trap message will
+ *	                              be stored to the trap buffer.
+ *	SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two
+ *	                              spanning tree root bridges were
+ *	                              detected. A trap message will be stored
+ *	                              to the trap buffer.
+ *	SK_PNMI_EVT_RLMT_ACTIVE_DOWN  Notifies PNMI that an active port went
+ *	                              down. PNMI will not further add the
+ *	                              statistic values to the virtual port.
+ *	SK_PNMI_EVT_RLMT_ACTIVE_UP    Notifies PNMI that a port went up and
+ *	                              is now an active port. PNMI will now
+ *	                              add the statistic data of this port to
+ *	                              the virtual port.
+ *	SK_PNMI_EVT_RLMT_SET_NETS     Notifies PNMI about the net mode. The first parameter
+ *	                              contains the number of nets. 1 means single net, 2 means
+ *	                              dual net. The second parameter is -1
+ *
+ * Returns:
+ *	Always 0
+ */
+int SkPnmiEvent(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 Event,		/* Event-Id */
+SK_EVPARA Param)	/* Event dependent parameter */
+{
+	unsigned int	PhysPortIndex;
+	unsigned int	MaxNetNumber;
+	int			CounterIndex;
+	SK_U16		MacStatus;
+	SK_U64		OverflowStatus;
+	SK_U64		Mask;
+	int			MacType;
+	SK_U64		Value;
+	SK_U32		Val32;
+	SK_U16		Register;
+	SK_EVPARA	EventParam;
+#ifndef SK_NO_RLMT
+	SK_U64		NewestValue;
+	SK_U64		OldestValue;
+	SK_U64		Delta;
+	SK_PNMI_ESTIMATE *pEst;
+#endif
+	SK_U32		NetIndex;
+	SK_U32		RetCode;
+
+#ifdef DEBUG
+	if (Event != SK_PNMI_EVT_XMAC_RESET) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+			("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n",
+			(unsigned int)Event, (unsigned int)Param.Para64));
+	}
+#endif /* DEBUG */
+	SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call");
+
+	MacType = pAC->GIni.GIMacType;
+
+	switch (Event) {
+
+	case SK_PNMI_EVT_SIRQ_OVERFLOW:
+		PhysPortIndex = (int)Param.Para32[0];
+		MacStatus = (SK_U16)Param.Para32[1];
+#ifdef DEBUG
+		if (PhysPortIndex >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter"
+				 " wrong, PhysPortIndex=0x%x\n",
+				PhysPortIndex));
+			return (0);
+		}
+#endif /* DEBUG */
+		OverflowStatus = 0;
+
+		/* Check which source caused an overflow interrupt. */
+		if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,
+				MacStatus, &OverflowStatus) != 0) ||
+			(OverflowStatus == 0)) {
+
+			SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+			return (0);
+		}
+
+		/*
+		 * Check the overflow status register and increment
+		 * the upper dword of corresponding counter.
+		 */
+		for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8;
+			CounterIndex ++) {
+
+			Mask = (SK_U64)1 << CounterIndex;
+			if ((OverflowStatus & Mask) == 0) {
+				continue;
+			}
+
+			switch (StatOvrflwBit[CounterIndex][MacType]) {
+
+			case SK_PNMI_HTX_UTILUNDER:
+			case SK_PNMI_HTX_UTILOVER:
+				if (MacType == SK_MAC_XMAC) {
+					XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, &Register);
+					Register |= XM_TX_SAM_LINE;
+					XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, Register);
+				}
+				break;
+
+			case SK_PNMI_HRX_UTILUNDER:
+			case SK_PNMI_HRX_UTILOVER:
+				if (MacType == SK_MAC_XMAC) {
+					XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, &Register);
+					Register |= XM_RX_SAM_LINE;
+					XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, Register);
+				}
+				break;
+
+			case SK_PNMI_HTX_OCTETHIGH:
+			case SK_PNMI_HTX_OCTETLOW:
+			case SK_PNMI_HTX_RESERVED:
+			case SK_PNMI_HRX_OCTETHIGH:
+			case SK_PNMI_HRX_OCTETLOW:
+			case SK_PNMI_HRX_IRLENGTH:
+			case SK_PNMI_HRX_RESERVED:
+
+			/* The following counters aren't be handled (id > 63). */
+			case SK_PNMI_HTX_SYNC:
+			case SK_PNMI_HTX_SYNC_OCTET:
+				break;
+
+			case SK_PNMI_HRX_LONGFRAMES:
+				if (MacType == SK_MAC_GMAC) {
+					pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] ++;
+				}
+				break;
+
+			default:
+				pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] ++;
+			}
+		}
+		break;
+
+	case SK_PNMI_EVT_SEN_WAR_LOW:
+#ifdef DEBUG
+		if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n",
+				(unsigned int)Param.Para64));
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate
+		 * an event for user space applications with the
+		 * SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW,
+			(unsigned int)Param.Para64);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		break;
+
+	case SK_PNMI_EVT_SEN_WAR_UPP:
+#ifdef DEBUG
+		if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n",
+				(unsigned int)Param.Para64));
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate
+		 * an event for user space applications with the
+		 * SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP,
+			(unsigned int)Param.Para64);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		break;
+
+	case SK_PNMI_EVT_SEN_ERR_LOW:
+#ifdef DEBUG
+		if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n",
+				(unsigned int)Param.Para64));
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate
+		 * an event for user space applications with the
+		 * SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW,
+			(unsigned int)Param.Para64);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		break;
+
+	case SK_PNMI_EVT_SEN_ERR_UPP:
+#ifdef DEBUG
+		if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
+				(unsigned int)Param.Para64));
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate
+		 * an event for user space applications with the
+		 * SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP,
+			(unsigned int)Param.Para64);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		break;
+
+	case SK_PNMI_EVT_CHG_EST_TIMER:
+#ifndef SK_NO_RLMT
+		/*
+		 * Calculate port switch average on a per hour basis
+		 *   Time interval for check       : 28125 ms (SK_PNMI_EVT_TIMER_CHECK)
+		 *   Number of values for average  : 8
+		 *
+		 * Be careful in changing these values, on change check
+		 *   - typedef of SK_PNMI_ESTIMATE (Size of EstValue
+		 *     array one less than value number)
+		 *   - Timer initialization SkTimerStart() in SkPnmiInit
+		 *   - Delta value below must be multiplicated with power of 2
+		 */
+		pEst = &pAC->Pnmi.RlmtChangeEstimate;
+		CounterIndex = pEst->EstValueIndex + 1;
+		if (CounterIndex == 7) {
+
+			CounterIndex = 0;
+		}
+		pEst->EstValueIndex = CounterIndex;
+
+		NewestValue = pAC->Pnmi.RlmtChangeCts;
+		OldestValue = pEst->EstValue[CounterIndex];
+		pEst->EstValue[CounterIndex] = NewestValue;
+
+		/*
+		 * Calculate average. Delta stores the number of
+		 * port switches per 28125 * 8 = 225000 ms
+		 */
+		if (NewestValue >= OldestValue) {
+
+			Delta = NewestValue - OldestValue;
+		}
+		else {
+			/* Overflow situation. */
+			Delta = (SK_U64)(0 - OldestValue) + NewestValue;
+		}
+
+		/*
+		 * Extrapolate delta to port switches per hour.
+		 *     Estimate = Delta * (3600000 / 225000)
+		 *              = Delta * 16
+		 *              = Delta << 4
+		 */
+		pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4;
+
+		/*
+		 * Check if threshold is exceeded. If the threshold is
+		 * permanently exceeded every 28125 ms an event will be
+		 * generated to remind the user of this condition.
+		 */
+		if ((pAC->Pnmi.RlmtChangeThreshold != 0) &&
+			(pAC->Pnmi.RlmtChangeEstimate.Estimate >=
+			pAC->Pnmi.RlmtChangeThreshold)) {
+
+			QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES);
+			(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		}
+
+		SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+		SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
+			SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
+			EventParam);
+#endif
+		break;
+
+	case SK_PNMI_EVT_CLEAR_COUNTER:
+		/*
+		 *  Param.Para32[0] contains the NetIndex (0 ..1).
+		 *  Param.Para32[1] is reserved, contains -1.
+		 */
+		NetIndex = (SK_U32)Param.Para32[0];
+
+#ifdef DEBUG
+#ifndef SK_NO_RLMT
+		if (NetIndex >= pAC->Rlmt.NumNets) {
+#else
+		if (NetIndex >= pAC->GIni.GIMacsFound) {
+#endif
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_CLEAR_COUNTER parameter wrong, NetIndex=%d\n",
+				NetIndex));
+
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Set all counters and timestamps to zero.
+		 * The according NetIndex is required as a
+		 * parameter of the event.
+		 */
+		ResetCounter(pAC, IoC, NetIndex);
+		break;
+
+	case SK_PNMI_EVT_XMAC_RESET:
+		/*
+		 * To grant continuous counter values store the current
+		 * XMAC statistic values to the entries 1..n of the
+		 * CounterOffset array. XMAC Errata #2
+		 */
+#ifdef DEBUG
+		if ((unsigned int)Param.Para64 >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n",
+				(unsigned int)Param.Para64));
+			return (0);
+		}
+#endif /* DEBUG */
+
+		PhysPortIndex = (unsigned int)Param.Para64;
+
+		/* Update XMAC statistic to get fresh values. */
+		if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+			SK_PNMI_ERR_OK) {
+
+			SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+			return (0);
+		}
+
+		/* Increment semaphore to indicate that an update was already done. */
+		pAC->Pnmi.MacUpdatedFlag ++;
+
+		for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+			CounterIndex ++) {
+
+			if (!StatAddr[CounterIndex][MacType].GetOffset) {
+				continue;
+			}
+
+			pAC->Pnmi.Port[PhysPortIndex].CounterOffset[CounterIndex] =
+				GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
+
+			pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] = 0;
+		}
+
+		pAC->Pnmi.MacUpdatedFlag --;
+		break;
+
+	case SK_PNMI_EVT_RLMT_PORT_UP:
+		PhysPortIndex = (unsigned int)Param.Para32[0];
+#ifdef DEBUG
+		if (PhysPortIndex >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter"
+				 " wrong, PhysPortIndex=%d\n", PhysPortIndex));
+
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate an event for
+		 * user space applications with the SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+
+		/* Bugfix for XMAC errata (#10620). */
+		if (MacType == SK_MAC_XMAC) {
+			/* Add incremental difference to offset (#10620). */
+			(void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
+				XM_RXE_SHT_ERR, &Val32);
+
+			Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
+				 CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
+
+			pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
+				Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
+		}
+
+		/* Tell VctStatus() that a link was up meanwhile. */
+		pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK;
+		break;
+
+	case SK_PNMI_EVT_RLMT_PORT_DOWN:
+		PhysPortIndex = (unsigned int)Param.Para32[0];
+
+#ifdef DEBUG
+		if (PhysPortIndex >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter"
+				 " wrong, PhysPortIndex=%d\n", PhysPortIndex));
+
+			return (0);
+		}
+#endif /* DEBUG */
+
+		/*
+		 * Store a trap message in the trap buffer and generate an event for
+		 * user space applications with the SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+
+		/* Bugfix #10620 - get zero level for incremental difference. */
+		if (MacType == SK_MAC_XMAC) {
+
+			(void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
+				XM_RXE_SHT_ERR, &Val32);
+
+			pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark =
+				(((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
+				 CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
+		}
+		break;
+
+	case SK_PNMI_EVT_RLMT_ACTIVE_DOWN:
+		PhysPortIndex = (unsigned int)Param.Para32[0];
+		NetIndex = (SK_U32)Param.Para32[1];
+
+#ifdef DEBUG
+		if (PhysPortIndex >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n",
+				PhysPortIndex));
+		}
+#ifndef SK_NO_RLMT
+		if (NetIndex >= pAC->Rlmt.NumNets) {
+#else
+		if (NetIndex >= pAC->GIni.GIMacsFound) {
+#endif
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n",
+				NetIndex));
+		}
+#endif /* DEBUG */
+
+		/* For now, ignore event if NetIndex != 0. */
+		if (Param.Para32[1] != 0) {
+
+			return (0);
+		}
+
+		/* Nothing to do if port is already inactive. */
+		if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+			return (0);
+		}
+
+		/*
+		 * Update statistic counters to calculate new offset for the virtual
+		 * port and increment semaphore to indicate that an update was already
+		 * done.
+		 */
+		if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+			SK_PNMI_ERR_OK) {
+
+			SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+			return (0);
+		}
+		pAC->Pnmi.MacUpdatedFlag ++;
+
+		/*
+		 * Calculate new counter offset for virtual port to grant continous
+		 * counting on port switches. The virtual port consists of all currently
+		 * active ports. The port down event indicates that a port is removed
+		 * from the virtual port. Therefore add the counter value of the removed
+		 * port to the CounterOffset for the virtual port to grant the same
+		 * counter value.
+		 */
+		for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+			CounterIndex ++) {
+
+			if (!StatAddr[CounterIndex][MacType].GetOffset) {
+				continue;
+			}
+
+			Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
+
+			pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
+		}
+
+		/* Set port to inactive. */
+		pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
+
+		pAC->Pnmi.MacUpdatedFlag --;
+		break;
+
+	case SK_PNMI_EVT_RLMT_ACTIVE_UP:
+		PhysPortIndex = (unsigned int)Param.Para32[0];
+		NetIndex = (SK_U32)Param.Para32[1];
+
+#ifdef DEBUG
+		if (PhysPortIndex >= SK_MAX_MACS) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n",
+				PhysPortIndex));
+		}
+#ifndef SK_NO_RLMT
+		if (NetIndex >= pAC->Rlmt.NumNets) {
+#else
+		if (NetIndex >= pAC->GIni.GIMacsFound) {
+#endif
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n",
+				NetIndex));
+		}
+#endif /* DEBUG */
+
+		/* For now, ignore event if NetIndex != 0. */
+		if (Param.Para32[1] != 0) {
+
+			return (0);
+		}
+
+		/* Nothing to do if port is already inactive. */
+		if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+			return (0);
+		}
+
+		/* Statistic maintenance. */
+		pAC->Pnmi.RlmtChangeCts ++;
+		pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+
+		/*
+		 * Store a trap message in the trap buffer and generate an event for
+		 * user space applications with the SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueRlmtNewMacTrap(pAC, PhysPortIndex);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+
+		/*
+		 * Update statistic counters to calculate new offset for the virtual
+		 * port and increment semaphore to indicate that an update was
+		 * already done.
+		 */
+		if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
+			SK_PNMI_ERR_OK) {
+
+			SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+			return (0);
+		}
+		pAC->Pnmi.MacUpdatedFlag ++;
+
+		/*
+		 * Calculate new counter offset for virtual port to grant continous
+		 * counting on port switches. A new port is added to the virtual port.
+		 * Therefore substract the counter value of the new port from the
+		 * CounterOffset for the virtual port to grant the same value.
+		 */
+		for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
+			CounterIndex ++) {
+
+			if (!StatAddr[CounterIndex][MacType].GetOffset) {
+				continue;
+			}
+
+			Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
+
+			pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
+		}
+
+		/* Set port to active. */
+		pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
+
+		pAC->Pnmi.MacUpdatedFlag --;
+		break;
+
+	case SK_PNMI_EVT_RLMT_SEGMENTATION:
+		/* Para.Para32[0] contains the NetIndex. */
+
+		/*
+		 * Store a trap message in the trap buffer and generate an event for
+		 * user space applications with the SK_DRIVER_SENDEVENT macro.
+		 */
+		QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION);
+		(void)SK_DRIVER_SENDEVENT(pAC, IoC);
+		break;
+
+	case SK_PNMI_EVT_RLMT_SET_NETS:
+		/*
+		 *  Param.Para32[0] contains the number of Nets.
+		 *  Param.Para32[1] is reserved, contains -1.
+		 */
+		/* Check number of nets. */
+		MaxNetNumber = pAC->GIni.GIMacsFound;
+
+		if (((unsigned int)Param.Para32[0] < 1) ||
+			((unsigned int)Param.Para32[0] > MaxNetNumber)) {
+
+			return (SK_PNMI_ERR_UNKNOWN_NET);
+		}
+
+		if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode */
+			pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
+		}
+		else { /* DualNet mode */
+			pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
+		}
+		break;
+
+	case SK_PNMI_EVT_VCT_RESET:
+		PhysPortIndex = Param.Para32[0];
+
+		if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
+
+			RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
+
+			if (RetCode == 2) {
+				/*
+				 * VCT test is still running.
+				 * Start VCT timer counter again.
+				 */
+				SK_MEMSET((char *)&Param, 0, sizeof(Param));
+
+				Param.Para32[0] = PhysPortIndex;
+				Param.Para32[1] = -1;
+
+				SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
+					SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
+
+				break;
+			}
+
+			VctGetResults(pAC, IoC, PhysPortIndex);
+
+			EventParam.Para32[0] = PhysPortIndex;
+			EventParam.Para32[1] = -1;
+			SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam);
+
+			/* SkEventDispatcher(pAC, IoC); */
+		}
+
+		break;
+
+	default:
+		break;
+	}
+
+	SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
+	return (0);
+}
+
+
+/******************************************************************************
+ *
+ * Private functions
+ *
+ */
+
+/*****************************************************************************
+ *
+ * PnmiVar - Gets, presets, and sets single OIDs
+ *
+ * Description:
+ *	Looks up the requested OID, calls the corresponding handler
+ *	function, and passes the parameters with the get, preset, or
+ *	set command. The function is called by SkGePnmiGetVar,
+ *	SkGePnmiPreSetVar, or SkGePnmiSetVar.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_XXX. For details have a look at the description of the
+ *	calling functions.
+ *	SK_PNMI_ERR_UNKNOWN_NET  The requested NetIndex doesn't exist
+ */
+PNMI_STATIC int PnmiVar(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* Total length of pBuf management data  */
+SK_U32 Instance,	/* Instance (1..n) that is to be set or -1 */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	TableIndex;
+	int		Ret;
+
+	if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_OID);
+	}
+#ifndef SK_NO_RLMT
+	/* Check NetIndex. */
+	if (NetIndex >= pAC->Rlmt.NumNets) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#else
+	if (NetIndex >= pAC->GIni.GIMacsFound) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#endif
+	SK_PNMI_CHECKFLAGS("PnmiVar: On call");
+
+	Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen,
+		Instance, TableIndex, NetIndex);
+
+	SK_PNMI_CHECKFLAGS("PnmiVar: On return");
+
+	return (Ret);
+}
+
+/*****************************************************************************
+ *
+ * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA
+ *
+ * Description:
+ *	The return value of the function will also be stored in
+ *	SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
+ *	SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable,
+ *	checks which OIDs are able to set, and calls the handler function of
+ *	the OID to perform the set. The return value of the function will
+ *	also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
+ *	minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called
+ *	by SkGePnmiPreSetStruct and SkGePnmiSetStruct.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_XXX. The codes are described in the calling functions.
+ *	SK_PNMI_ERR_UNKNOWN_NET  The requested NetIndex doesn't exist
+ */
+PNMI_STATIC int PnmiStruct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int  Action,	/* PRESET/SET action to be performed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* Length of pBuf management data buffer */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int		Ret;
+	unsigned int	TableIndex;
+	unsigned int	DstOffset;
+	unsigned int	Len;
+	unsigned int	InstanceNo;
+	unsigned int	InstanceCnt;
+	SK_U32		Instance;
+	SK_U32		Id;
+
+	/* Check if the passed buffer has the right size. */
+	if (*pLen < SK_PNMI_STRUCT_SIZE) {
+
+		/* Check if we can return the error within the buffer. */
+		if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
+
+			SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
+		}
+
+		*pLen = SK_PNMI_STRUCT_SIZE;
+		return (SK_PNMI_ERR_TOO_SHORT);
+	}
+#ifndef SK_NO_RLMT
+	/* Check NetIndex. */
+	if (NetIndex >= pAC->Rlmt.NumNets) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#else
+	if (NetIndex >= pAC->GIni.GIMacsFound) {
+		return (SK_PNMI_ERR_UNKNOWN_NET);
+	}
+#endif
+	SK_PNMI_CHECKFLAGS("PnmiStruct: On call");
+
+	/*
+	 * Update the values of RLMT and SIRQ and increment semaphores to
+	 * indicate that an update was already done.
+	 */
+#ifndef SK_NO_RLMT
+	if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
+
+		SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+		*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+		return (Ret);
+	}
+#endif
+	if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+		SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
+		*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+		return (Ret);
+	}
+
+	pAC->Pnmi.RlmtUpdatedFlag ++;
+	pAC->Pnmi.SirqUpdatedFlag ++;
+
+	/* PRESET/SET values. */
+	for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
+
+		if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&
+			(IdTable[TableIndex].Access != SK_PNMI_WO)) {
+			continue;
+		}
+
+		InstanceNo = IdTable[TableIndex].InstanceNo;
+		Id = IdTable[TableIndex].Id;
+
+		for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
+			InstanceCnt ++) {
+
+			DstOffset = IdTable[TableIndex].Offset +
+				(InstanceCnt - 1) * IdTable[TableIndex].StructSize;
+
+			/*
+			 * Because VPD multiple instance variables are
+			 * not setable we do not need to evaluate VPD
+			 * instances. Have a look to VPD instance
+			 * calculation in SkPnmiGetStruct().
+			 */
+			Instance = (SK_U32)InstanceCnt;
+
+			/* Evaluate needed buffer length. */
+			Len = 0;
+			Ret = IdTable[TableIndex].Func(pAC, IoC,
+				SK_PNMI_GET, IdTable[TableIndex].Id,
+				NULL, &Len, Instance, TableIndex, NetIndex);
+
+			if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
+
+				break;
+			}
+
+			if (Ret != SK_PNMI_ERR_TOO_SHORT) {
+
+				pAC->Pnmi.RlmtUpdatedFlag --;
+				pAC->Pnmi.SirqUpdatedFlag --;
+
+				SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+				SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset);
+				*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			if (Id == OID_SKGE_VPD_ACTION) {
+
+				switch (*(pBuf + DstOffset)) {
+
+				case SK_PNMI_VPD_CREATE:
+					Len = 3 + *(pBuf + DstOffset + 3);
+					break;
+
+				case SK_PNMI_VPD_DELETE:
+					Len = 3;
+					break;
+
+				default:
+					Len = 1;
+					break;
+				}
+			}
+
+			/* Call the OID handler function. */
+			Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
+				IdTable[TableIndex].Id, pBuf + DstOffset,
+				&Len, Instance, TableIndex, NetIndex);
+
+			if (Ret != SK_PNMI_ERR_OK) {
+
+				pAC->Pnmi.RlmtUpdatedFlag --;
+				pAC->Pnmi.SirqUpdatedFlag --;
+
+				SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+				SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset);
+				*pLen = SK_PNMI_MIN_STRUCT_SIZE;
+
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+		}
+	}
+
+	pAC->Pnmi.RlmtUpdatedFlag --;
+	pAC->Pnmi.SirqUpdatedFlag --;
+
+	SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
+	SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * LookupId - Lookup an OID in the IdTable
+ *
+ * Description:
+ *	Scans the IdTable to find the table entry of an OID.
+ *
+ * Returns:
+ *	The table index or -1 if not found.
+ */
+PNMI_STATIC int LookupId(
+SK_U32 Id)		/* Object identifier to be searched */
+{
+	int i;
+
+	for (i = 0; i < ID_TABLE_SIZE; i++) {
+
+		if (IdTable[i].Id == Id) {
+
+			return (i);
+		}
+	}
+
+	return (-1);
+}
+
+/*****************************************************************************
+ *
+ * OidStruct - Handler of OID_SKGE_ALL_DATA
+ *
+ * Description:
+ *	This OID performs a Get/Preset/SetStruct call and returns all data
+ *	in a SK_PNMI_STRUCT_DATA structure.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int OidStruct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	if (Id != OID_SKGE_ALL_DATA) {
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG);
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	/* Check instance. We only handle single instance variables. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	switch (Action) {
+
+	case SK_PNMI_GET:
+		return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex));
+
+	case SK_PNMI_PRESET:
+		return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex));
+
+	case SK_PNMI_SET:
+		return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex));
+	}
+
+	SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG);
+
+	*pLen = 0;
+	return (SK_PNMI_ERR_GENERAL);
+}
+
+/*****************************************************************************
+ *
+ * Perform - OID handler of OID_SKGE_ACTION
+ *
+ * Description:
+ *	None.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Perform(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int	Ret;
+	SK_U32	ActionOp;
+
+	/* Check instance. We only handle single instance variables. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	if (*pLen < sizeof(SK_U32)) {
+
+		*pLen = sizeof(SK_U32);
+		return (SK_PNMI_ERR_TOO_SHORT);
+	}
+
+	/* Check if a GET should be performed. */
+	if (Action == SK_PNMI_GET) {
+
+		/* A GET is easy. We always return the same value. */
+		ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
+		SK_PNMI_STORE_U32(pBuf, ActionOp);
+		*pLen = sizeof(SK_U32);
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* Continue with PRESET/SET action. */
+	if (*pLen > sizeof(SK_U32)) {
+
+		return (SK_PNMI_ERR_BAD_VALUE);
+	}
+
+	/* Check if the command is a known one. */
+	SK_PNMI_READ_U32(pBuf, ActionOp);
+	if (*pLen > sizeof(SK_U32) ||
+		(ActionOp != SK_PNMI_ACT_IDLE &&
+		ActionOp != SK_PNMI_ACT_RESET &&
+		ActionOp != SK_PNMI_ACT_SELFTEST &&
+		ActionOp != SK_PNMI_ACT_RESETCNT)) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_BAD_VALUE);
+	}
+
+	/* A PRESET ends here. */
+	if (Action == SK_PNMI_PRESET) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	switch (ActionOp) {
+
+	case SK_PNMI_ACT_IDLE:
+		/* Nothing to do. */
+		break;
+
+	case SK_PNMI_ACT_RESET:
+		/* Perform a driver reset or something that comes near to this. */
+		Ret = SK_DRIVER_RESET(pAC, IoC);
+		if (Ret != 0) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG);
+
+			return (SK_PNMI_ERR_GENERAL);
+		}
+		break;
+
+	case SK_PNMI_ACT_SELFTEST:
+		/*
+		 * Perform a driver selftest or something similar to this.
+		 * Currently this feature is not used and will probably
+		 * implemented in another way.
+		 */
+		Ret = SK_DRIVER_SELFTEST(pAC, IoC);
+		pAC->Pnmi.TestResult = Ret;
+		break;
+
+	case SK_PNMI_ACT_RESETCNT:
+		/* Set all counters and timestamps to zero. */
+		ResetCounter(pAC, IoC, NetIndex);
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG);
+
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX
+ *
+ * Description:
+ *	Retrieves the statistic values of the virtual port (logical
+ *	index 0). Only special OIDs of NDIS are handled which consist
+ *	of a 32 bit instead of a 64 bit value. The OIDs are public
+ *	because perhaps some other platform can use them too.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Mac8023Stat(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex,	/* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int     Ret;
+	SK_U64  StatVal;
+	SK_U32  StatVal32;
+	SK_BOOL Is64BitReq = SK_FALSE;
+
+	/* Only the active MAC is returned. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Check action type. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Check length. */
+	switch (Id) {
+
+	case OID_802_3_PERMANENT_ADDRESS:
+	case OID_802_3_CURRENT_ADDRESS:
+		if (*pLen < sizeof(SK_MAC_ADDR)) {
+
+			*pLen = sizeof(SK_MAC_ADDR);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+#ifndef SK_NDIS_64BIT_CTR
+		if (*pLen < sizeof(SK_U32)) {
+			*pLen = sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+#else /* SK_NDIS_64BIT_CTR */
+
+		/* For compatibility, at least 32 bits are required for OID. */
+		if (*pLen < sizeof(SK_U32)) {
+			/*
+			 * Indicate handling for 64 bit values,
+			 * if insufficient space is provided.
+			 */
+			*pLen = sizeof(SK_U64);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+		Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;
+#endif /* SK_NDIS_64BIT_CTR */
+		break;
+	}
+
+	/*
+	 * Update all statistics, because we retrieve virtual MAC, which
+	 * consists of multiple physical statistics and increment semaphore
+	 * to indicate that an update was already done.
+	 */
+	Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+	if (Ret != SK_PNMI_ERR_OK) {
+
+		*pLen = 0;
+		return (Ret);
+	}
+	pAC->Pnmi.MacUpdatedFlag ++;
+
+	/* Get value (MAC index 0 identifies the virtual MAC). */
+	switch (Id) {
+
+	case OID_802_3_PERMANENT_ADDRESS:
+		CopyMac(pBuf, &pAC->Addr.Net[NetIndex].PermanentMacAddress);
+		*pLen = sizeof(SK_MAC_ADDR);
+		break;
+
+	case OID_802_3_CURRENT_ADDRESS:
+		CopyMac(pBuf, &pAC->Addr.Net[NetIndex].CurrentMacAddress);
+		*pLen = sizeof(SK_MAC_ADDR);
+		break;
+
+	default:
+		StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);
+
+		/* By default 32 bit values are evaluated. */
+		if (!Is64BitReq) {
+			StatVal32 = (SK_U32)StatVal;
+			SK_PNMI_STORE_U32(pBuf, StatVal32);
+			*pLen = sizeof(SK_U32);
+		}
+		else {
+			SK_PNMI_STORE_U64(pBuf, StatVal);
+			*pLen = sizeof(SK_U64);
+		}
+		break;
+	}
+
+	pAC->Pnmi.MacUpdatedFlag --;
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX
+ *
+ * Description:
+ *	Retrieves the MAC statistic data.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int MacPrivateStat(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	LogPortMax;
+	unsigned int	LogPortIndex;
+	unsigned int	PhysPortMax;
+	unsigned int	Limit;
+	unsigned int	Offset;
+	int				MacType;
+	int				Ret;
+	SK_U64			StatVal;
+
+	/* Calculate instance if wished. MAC index 0 is the virtual MAC. */
+	PhysPortMax = pAC->GIni.GIMacsFound;
+	LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+	MacType = pAC->GIni.GIMacType;
+
+	if (pAC->Pnmi.DualNetActiveFlag) { /* DualNet mode */
+		LogPortMax--;
+	}
+
+	if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
+		/* Check instance range. */
+		if ((Instance < 1) || (Instance > LogPortMax)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+		LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+		Limit = LogPortIndex + 1;
+	}
+
+	else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
+
+		LogPortIndex = 0;
+		Limit = LogPortMax;
+	}
+
+	/* Check action. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Check length. */
+	if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
+
+		*pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
+		return (SK_PNMI_ERR_TOO_SHORT);
+	}
+
+	/*
+	 * Update MAC statistic and increment semaphore to indicate that
+	 * an update was already done.
+	 */
+	Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+	if (Ret != SK_PNMI_ERR_OK) {
+
+		*pLen = 0;
+		return (Ret);
+	}
+	pAC->Pnmi.MacUpdatedFlag ++;
+
+	/* Get value. */
+	Offset = 0;
+	for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+		switch (Id) {
+
+/* XXX not yet implemented due to XMAC problems
+		case OID_SKGE_STAT_TX_UTIL:
+			return (SK_PNMI_ERR_GENERAL);
+*/
+/* XXX not yet implemented due to XMAC problems
+		case OID_SKGE_STAT_RX_UTIL:
+			return (SK_PNMI_ERR_GENERAL);
+*/
+		case OID_SKGE_STAT_RX:
+			if (MacType == SK_MAC_GMAC) {
+				StatVal =
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HRX_BROADCAST, NetIndex) +
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HRX_MULTICAST, NetIndex) +
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HRX_UNICAST, NetIndex) -
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HRX_UNDERSIZE, NetIndex);
+			}
+			else {
+				StatVal = GetStatVal(pAC, IoC, LogPortIndex,
+					IdTable[TableIndex].Param, NetIndex);
+			}
+			break;
+
+		case OID_SKGE_STAT_TX:
+			if (MacType == SK_MAC_GMAC) {
+				StatVal =
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HTX_BROADCAST, NetIndex) +
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HTX_MULTICAST, NetIndex) +
+					GetStatVal(pAC, IoC, LogPortIndex,
+							   SK_PNMI_HTX_UNICAST, NetIndex);
+			}
+			else {
+				StatVal = GetStatVal(pAC, IoC, LogPortIndex,
+					IdTable[TableIndex].Param, NetIndex);
+			}
+			break;
+
+		default:
+			StatVal = GetStatVal(pAC, IoC, LogPortIndex,
+				IdTable[TableIndex].Param, NetIndex);
+		}
+		SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
+
+		Offset += sizeof(SK_U64);
+	}
+	*pLen = Offset;
+
+	pAC->Pnmi.MacUpdatedFlag --;
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR
+ *
+ * Description:
+ *	Get/Presets/Sets the current and factory MAC address. The MAC
+ *	address of the virtual port, which is reported to the OS, may
+ *	not be changed, but the physical ones. A set to the virtual port
+ *	will be ignored. No error should be reported because otherwise
+ *	a multiple instance set (-1) would always fail.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Addr(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int		Ret;
+	unsigned int	LogPortMax;
+	unsigned int	PhysPortMax;
+	unsigned int	LogPortIndex;
+	unsigned int	PhysPortIndex;
+	unsigned int	Limit;
+	unsigned int	Offset = 0;
+
+	/* Calculate instance if wished. MAC index 0 is the virtual MAC. */
+	PhysPortMax = pAC->GIni.GIMacsFound;
+	LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+	if (pAC->Pnmi.DualNetActiveFlag) { /* DualNet mode */
+		LogPortMax--;
+	}
+
+	if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
+		/* Check instance range. */
+		if ((Instance < 1) || (Instance > LogPortMax)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+		LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+		Limit = LogPortIndex + 1;
+	}
+	else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
+
+		LogPortIndex = 0;
+		Limit = LogPortMax;
+	}
+
+	/* Perform action. */
+	if (Action == SK_PNMI_GET) {
+
+		/* Check length. */
+		if (*pLen < (Limit - LogPortIndex) * 6) {
+
+			*pLen = (Limit - LogPortIndex) * 6;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+		/* Get value. */
+		for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+			switch (Id) {
+
+			case OID_SKGE_PHYS_CUR_ADDR:
+				if (LogPortIndex == 0) {
+					CopyMac(pBuf + Offset, &pAC->Addr.Net[NetIndex].CurrentMacAddress);
+				}
+				else {
+					PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+
+					CopyMac(pBuf + Offset,
+						&pAC->Addr.Port[PhysPortIndex].CurrentMacAddress);
+				}
+				Offset += 6;
+				break;
+
+			case OID_SKGE_PHYS_FAC_ADDR:
+				if (LogPortIndex == 0) {
+					CopyMac(pBuf + Offset,
+						&pAC->Addr.Net[NetIndex].PermanentMacAddress);
+				}
+				else {
+					PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+
+					CopyMac(pBuf + Offset,
+						&pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);
+				}
+				Offset += 6;
+				break;
+
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG);
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+		}
+
+		*pLen = Offset;
+	}
+	else {
+		/*
+		 * The logical MAC address may not be changed,
+		 * only the physical ones.
+		 */
+		if (Id == OID_SKGE_PHYS_FAC_ADDR) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_READ_ONLY);
+		}
+
+		/* Only the current address may be changed. */
+		if (Id != OID_SKGE_PHYS_CUR_ADDR) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		/* Check length. */
+		if (*pLen < (Limit - LogPortIndex) * 6) {
+
+			*pLen = (Limit - LogPortIndex) * 6;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		if (*pLen > (Limit - LogPortIndex) * 6) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_BAD_VALUE);
+		}
+
+		/* Check action. */
+		if (Action == SK_PNMI_PRESET) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_OK);
+		}
+
+		/* Set OID_SKGE_MAC_CUR_ADDR.  */
+		for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
+
+			/*
+			 * A set to virtual port and set of broadcast
+			 * address will be ignored.
+			 */
+			if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
+				"\xff\xff\xff\xff\xff\xff", 6) == 0) {
+				continue;
+			}
+
+			PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+
+			Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
+				(SK_MAC_ADDR *)(pBuf + Offset),
+				(LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS :
+				SK_ADDR_PHYSICAL_ADDRESS));
+			if (Ret != SK_ADDR_OVERRIDE_SUCCESS) {
+
+				return (SK_PNMI_ERR_GENERAL);
+			}
+		}
+		*pLen = Offset;
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX
+ *
+ * Description:
+ *	Retrieves the statistic values of the CSUM module. The CSUM data
+ *	structure must be available in the SK_AC even if the CSUM module
+ *	is not included, because PNMI reads the statistic data from the
+ *	CSUM part of SK_AC directly.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int CsumStat(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	Index;
+	unsigned int	Limit;
+	unsigned int	Offset = 0;
+	SK_U64		StatVal;
+
+	/* Calculate instance if wished. */
+	if (Instance != (SK_U32)(-1)) {
+
+		if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+		Index = (unsigned int)Instance - 1;
+		Limit = Index + 1;
+	}
+	else {
+		Index = 0;
+		Limit = SKCS_NUM_PROTOCOLS;
+	}
+
+	/* Check action. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Check length. */
+	if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
+
+		*pLen = (Limit - Index) * sizeof(SK_U64);
+		return (SK_PNMI_ERR_TOO_SHORT);
+	}
+
+	/* Get value. */
+	for (; Index < Limit; Index ++) {
+
+		switch (Id) {
+
+		case OID_SKGE_CHKSM_RX_OK_CTS:
+			StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxOkCts;
+			break;
+
+		case OID_SKGE_CHKSM_RX_UNABLE_CTS:
+			StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxUnableCts;
+			break;
+
+		case OID_SKGE_CHKSM_RX_ERR_CTS:
+			StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxErrCts;
+			break;
+
+		case OID_SKGE_CHKSM_TX_OK_CTS:
+			StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxOkCts;
+			break;
+
+		case OID_SKGE_CHKSM_TX_UNABLE_CTS:
+			StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxUnableCts;
+			break;
+
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
+		Offset += sizeof(SK_U64);
+	}
+
+	/* Store used buffer space. */
+	*pLen = Offset;
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX
+ *
+ * Description:
+ *	Retrieves the statistic values of the I2C module, which handles
+ *	the temperature and voltage sensors.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int SensorStat(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	i;
+	unsigned int	Index;
+	unsigned int	Limit;
+	unsigned int	Offset;
+	unsigned int	Len;
+	SK_U32		Val32;
+	SK_U64		Val64;
+
+	/* Calculate instance if wished. */
+	if ((Instance != (SK_U32)(-1))) {
+
+		if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+
+		Index = (unsigned int)Instance -1;
+		Limit = (unsigned int)Instance;
+	}
+	else {
+		Index = 0;
+		Limit = (unsigned int) pAC->I2c.MaxSens;
+	}
+
+	/* Check action. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Check length. */
+	switch (Id) {
+
+	case OID_SKGE_SENSOR_VALUE:
+	case OID_SKGE_SENSOR_WAR_THRES_LOW:
+	case OID_SKGE_SENSOR_WAR_THRES_UPP:
+	case OID_SKGE_SENSOR_ERR_THRES_LOW:
+	case OID_SKGE_SENSOR_ERR_THRES_UPP:
+		if (*pLen < (Limit - Index) * sizeof(SK_U32)) {
+
+			*pLen = (Limit - Index) * sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_SENSOR_DESCR:
+		for (Offset = 0, i = Index; i < Limit; i ++) {
+
+			Len = (unsigned int)
+				SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1;
+			if (Len >= SK_PNMI_STRINGLEN2) {
+
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011, SK_PNMI_ERR011MSG);
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+			Offset += Len;
+		}
+		if (*pLen < Offset) {
+
+			*pLen = Offset;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_SENSOR_INDEX:
+	case OID_SKGE_SENSOR_TYPE:
+	case OID_SKGE_SENSOR_STATUS:
+		if (*pLen < Limit - Index) {
+
+			*pLen = Limit - Index;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_SENSOR_WAR_CTS:
+	case OID_SKGE_SENSOR_WAR_TIME:
+	case OID_SKGE_SENSOR_ERR_CTS:
+	case OID_SKGE_SENSOR_ERR_TIME:
+		if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
+
+			*pLen = (Limit - Index) * sizeof(SK_U64);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG);
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	/* Get value. */
+	for (Offset = 0; Index < Limit; Index ++) {
+
+		switch (Id) {
+
+		case OID_SKGE_SENSOR_INDEX:
+			*(pBuf + Offset) = (char)Index;
+			Offset++;
+			break;
+
+		case OID_SKGE_SENSOR_DESCR:
+			Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
+			SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len);
+			*(pBuf + Offset) = (char)Len;
+			Offset += Len + 1;
+			break;
+
+		case OID_SKGE_SENSOR_TYPE:
+			*(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType;
+			Offset++;
+			break;
+
+		case OID_SKGE_SENSOR_VALUE:
+			Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_SENSOR_WAR_THRES_LOW:
+			Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+				SenThreWarnLow;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_SENSOR_WAR_THRES_UPP:
+			Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+				SenThreWarnHigh;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_SENSOR_ERR_THRES_LOW:
+			Val32 = (SK_U32)pAC->I2c.SenTable[Index].
+				SenThreErrLow;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_SENSOR_ERR_THRES_UPP:
+			Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_SENSOR_STATUS:
+			*(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag;
+			Offset++;
+			break;
+
+		case OID_SKGE_SENSOR_WAR_CTS:
+			Val64 = pAC->I2c.SenTable[Index].SenWarnCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_SENSOR_ERR_CTS:
+			Val64 = pAC->I2c.SenTable[Index].SenErrCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_SENSOR_WAR_TIME:
+			Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
+				SenBegWarnTS);
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_SENSOR_ERR_TIME:
+			Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
+				SenBegErrTS);
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+				("SensorStat: Unknown OID should be handled before"));
+
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+
+	/* Store used buffer space. */
+	*pLen = Offset;
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Vpd - OID handler function of OID_SKGE_VPD_XXX
+ *
+ * Description:
+ *	Get/preset/set of VPD.
+ *	As instance the name of a VPD key can be passed.
+ *	The Instance parameter is a SK_U32 and can be used as a string buffer
+ *	for the VPD key, because their maximum length is 4 byte.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Vpd(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_VPD_STATUS	*pVpdStatus;
+	unsigned int	BufLen;
+	char		Buf[256];
+	char		KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
+	char		KeyStr[SK_PNMI_VPD_KEY_SIZE];
+	unsigned int	KeyNo;
+	unsigned int	Offset;
+	unsigned int	Index;
+	unsigned int	FirstIndex;
+	unsigned int	LastIndex;
+	unsigned int	Len;
+	int		Ret;
+	SK_U32		Val32;
+
+	/*
+	 * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs.
+	 * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve
+	 * all statistical data, an error in GetVpdKeyArr() will generate a PNMI
+	 * error and terminate SkPnmiGetStruct() without filling in statistical
+	 * data into the PNMI struct. In this case the driver will get no values
+	 * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is
+	 * the first function to be called in SkPnmiGetStruct(), so any error
+	 * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will
+	 * be set during the first call to GetVpdKeyArr() to make successful calls
+	 * to SkPnmiGetStruct() possible. But there is another point to consider:
+	 * When filling in the statistical data into the PNMI struct, the VPD
+	 * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would
+	 * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again.
+	 * For this reason VpdKeyReadError is checked here and, if set, Vpd()
+	 * will return without doing anything and the return value SK_PNMI_ERR_OK.
+	 * Therefore SkPnmiGetStruct() is able to continue and fill in all other
+	 * statistical data.
+	 */
+	if (pAC->Pnmi.VpdKeyReadError) {
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* Get array of all currently stored VPD keys. */
+	Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);
+
+	if (Ret != SK_PNMI_ERR_OK) {
+		*pLen = 0;
+		return (Ret);
+	}
+
+	/*
+	 * If instance is not -1, try to find the requested VPD key for
+	 * the multiple instance variables. The other OIDs as for example
+	 * OID VPD_ACTION are single instance variables and must be
+	 * handled separatly.
+	 */
+	FirstIndex = 0;
+	LastIndex = KeyNo;
+
+	if ((Instance != (SK_U32)(-1))) {
+
+		if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE ||
+			Id == OID_SKGE_VPD_ACCESS) {
+
+			SK_STRNCPY(KeyStr, (char *)&Instance, 4);
+			KeyStr[4] = 0;
+
+			for (Index = 0; Index < KeyNo; Index ++) {
+
+				if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
+					FirstIndex = Index;
+					LastIndex = Index+1;
+					break;
+				}
+			}
+
+			if (Index == KeyNo) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_UNKNOWN_INST);
+			}
+		}
+		else if (Instance != 1) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+	}
+
+	/* Get value, if a query should be performed. */
+	if (Action == SK_PNMI_GET) {
+
+		switch (Id) {
+
+		case OID_SKGE_VPD_FREE_BYTES:
+			/* Check length of buffer. */
+			if (*pLen < sizeof(SK_U32)) {
+
+				*pLen = sizeof(SK_U32);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			/* Get number of free bytes. */
+			pVpdStatus = VpdStat(pAC, IoC);
+
+			if (pVpdStatus == NULL) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR017MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR018MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			Val32 = (SK_U32)pVpdStatus->vpd_free_rw;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_VPD_ENTRIES_LIST:
+			/* Check length. */
+			for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
+
+				Len += SK_STRLEN(KeyArr[Index]) + 1;
+			}
+
+			if (*pLen < Len) {
+
+				*pLen = Len;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			/* Get value. */
+			*(pBuf) = (char)Len - 1;
+
+			for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
+
+				Len = SK_STRLEN(KeyArr[Index]);
+				SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len);
+
+				Offset += Len;
+
+				if (Index < KeyNo - 1) {
+
+					*(pBuf + Offset) = ' ';
+					Offset++;
+				}
+			}
+			*pLen = Offset;
+			break;
+
+		case OID_SKGE_VPD_ENTRIES_NUMBER:
+			/* Check length. */
+			if (*pLen < sizeof(SK_U32)) {
+
+				*pLen = sizeof(SK_U32);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			Val32 = (SK_U32)KeyNo;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_VPD_KEY:
+			/* Check buffer length, if it is large enough. */
+			for (Len = 0, Index = FirstIndex;
+				Index < LastIndex; Index ++) {
+
+				Len += SK_STRLEN(KeyArr[Index]) + 1;
+			}
+			if (*pLen < Len) {
+
+				*pLen = Len;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			/*
+			 * Get the key to an intermediate buffer, because
+			 * we have to pretend a length byte.
+			 */
+			for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
+
+				Len = SK_STRLEN(KeyArr[Index]);
+
+				*(pBuf + Offset) = (char)Len;
+				SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len);
+				Offset += Len + 1;
+			}
+			*pLen = Offset;
+			break;
+
+		case OID_SKGE_VPD_VALUE:
+			/* Check the buffer length if it is large enough. */
+			for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
+
+				BufLen = 256;
+				if (VpdRead(pAC, IoC, KeyArr[Index], Buf, (int *)&BufLen) > 0 ||
+					BufLen >= SK_PNMI_VPD_DATALEN) {
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+						(SK_PNMI_ERR021MSG));
+
+					return (SK_PNMI_ERR_GENERAL);
+				}
+
+				Offset += BufLen + 1;
+			}
+
+			if (*pLen < Offset) {
+
+				*pLen = Offset;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			/*
+			 * Get the value to an intermediate buffer, because
+			 * we have to pretend a length byte.
+			 */
+			for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
+
+				BufLen = 256;
+				if (VpdRead(pAC, IoC, KeyArr[Index], Buf, (int *)&BufLen) > 0 ||
+					BufLen >= SK_PNMI_VPD_DATALEN) {
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+						(SK_PNMI_ERR022MSG));
+
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+
+				*(pBuf + Offset) = (char)BufLen;
+				SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen);
+				Offset += BufLen + 1;
+			}
+			*pLen = Offset;
+			break;
+
+		case OID_SKGE_VPD_ACCESS:
+			if (*pLen < LastIndex - FirstIndex) {
+
+				*pLen = LastIndex - FirstIndex;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
+
+				if (VpdMayWrite(KeyArr[Index])) {
+
+					*(pBuf + Offset) = SK_PNMI_VPD_RW;
+				}
+				else {
+					*(pBuf + Offset) = SK_PNMI_VPD_RO;
+				}
+				Offset++;
+			}
+			*pLen = Offset;
+			break;
+
+		case OID_SKGE_VPD_ACTION:
+			Offset = LastIndex - FirstIndex;
+			if (*pLen < Offset) {
+
+				*pLen = Offset;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			SK_MEMSET(pBuf, 0, Offset);
+			*pLen = Offset;
+			break;
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				(SK_PNMI_ERR023MSG));
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+	else {
+		/* The only OID which can be set is VPD_ACTION. */
+		if (Id != OID_SKGE_VPD_ACTION) {
+
+			if (Id == OID_SKGE_VPD_FREE_BYTES ||
+				Id == OID_SKGE_VPD_ENTRIES_LIST ||
+				Id == OID_SKGE_VPD_ENTRIES_NUMBER ||
+				Id == OID_SKGE_VPD_KEY ||
+				Id == OID_SKGE_VPD_VALUE ||
+				Id == OID_SKGE_VPD_ACCESS) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_READ_ONLY);
+			}
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+				(SK_PNMI_ERR024MSG));
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		/*
+		 * From this point we handle VPD_ACTION. Check the buffer
+		 * length. It should at least have the size of one byte.
+		 */
+		if (*pLen < 1) {
+
+			*pLen = 1;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+		/* The first byte contains the VPD action type we should perform. */
+		switch (*pBuf) {
+
+		case SK_PNMI_VPD_IGNORE:
+			/* Nothing to do. */
+			break;
+
+		case SK_PNMI_VPD_CREATE:
+			/*
+			 * We have to create a new VPD entry or we modify
+			 * an existing one. Check first the buffer length.
+			 */
+			if (*pLen < 4) {
+
+				*pLen = 4;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			KeyStr[0] = pBuf[1];
+			KeyStr[1] = pBuf[2];
+			KeyStr[2] = 0;
+
+			/* Is the entry writable or does it belong to the RO area ? */
+			if (!VpdMayWrite(KeyStr)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			Offset = (int)pBuf[3] & 0xFF;
+
+			SK_MEMCPY(Buf, pBuf + 4, Offset);
+			Buf[Offset] = 0;
+
+			/* A PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			/* Write the new entry or modify an existing one .*/
+			Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
+
+			if (Ret == SK_PNMI_VPD_NOWRITE) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			if (Ret != SK_PNMI_VPD_OK) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR025MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			/*
+			 * Perform an update of the VPD.
+			 * This is not mandantory, but just to be sure.
+			 */
+			Ret = VpdUpdate(pAC, IoC);
+
+			if (Ret != SK_PNMI_VPD_OK) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR026MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+			break;
+
+		case SK_PNMI_VPD_DELETE:
+			/* Check if the buffer size is plausible. */
+			if (*pLen < 3) {
+
+				*pLen = 3;
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			if (*pLen > 3) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			KeyStr[0] = pBuf[1];
+			KeyStr[1] = pBuf[2];
+			KeyStr[2] = 0;
+
+			/* Find the passed key in the array. */
+			for (Index = 0; Index < KeyNo; Index ++) {
+
+				if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
+
+					break;
+				}
+			}
+
+			/*
+			 * If we cannot find the key it is wrong, so we
+			 * return an appropriate error value.
+			 */
+			if (Index == KeyNo) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			/* Ok, you wanted it and you will get it. */
+			Ret = VpdDelete(pAC, IoC, KeyStr);
+
+			if (Ret != SK_PNMI_VPD_OK) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR027MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			/*
+			 * Perform an update of the VPD.
+			 * This is not mandantory, but just to be sure.
+			 */
+			Ret = VpdUpdate(pAC, IoC);
+			if (Ret != SK_PNMI_VPD_OK) {
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					(SK_PNMI_ERR028MSG));
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+			break;
+
+		default:
+			*pLen = 0;
+			return (SK_PNMI_ERR_BAD_VALUE);
+		}
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * General - OID handler function of various single instance OIDs
+ *
+ * Description:
+ *	The code is simple. No description necessary.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int General(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int		Ret;
+	unsigned int	Index;
+	unsigned int	Len;
+	unsigned int	Offset;
+	unsigned int	Val;
+	SK_U8		Val8;
+	SK_U16		Val16;
+	SK_U32		Val32;
+	SK_U64		Val64;
+	SK_U64		Val64RxHwErrs = 0;
+	SK_U64		Val64RxRunt = 0;
+	SK_U64		Val64RxFcs = 0;
+	SK_U64		Val64TxHwErrs = 0;
+	SK_BOOL		Is64BitReq = SK_FALSE;
+	char		Buf[256];
+	int			MacType;
+
+	/* Check instance. We only handle single instance variables. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Check action. We only allow get requests. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	MacType = pAC->GIni.GIMacType;
+
+	/* Check length for the various supported OIDs. */
+	switch (Id) {
+
+	case OID_GEN_XMIT_ERROR:
+	case OID_GEN_RCV_ERROR:
+	case OID_GEN_RCV_NO_BUFFER:
+#ifndef SK_NDIS_64BIT_CTR
+		if (*pLen < sizeof(SK_U32)) {
+			*pLen = sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+#else /* SK_NDIS_64BIT_CTR */
+
+		/* For compatibility, at least 32bit are required for OID. */
+		if (*pLen < sizeof(SK_U32)) {
+			/*
+			 * Indicate handling for 64bit values,
+			 * if insufficient space is provided.
+			 */
+			*pLen = sizeof(SK_U64);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+
+		Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;
+#endif /* SK_NDIS_64BIT_CTR */
+		break;
+
+	case OID_SKGE_PORT_NUMBER:
+	case OID_SKGE_DEVICE_TYPE:
+	case OID_SKGE_RESULT:
+	case OID_SKGE_RLMT_MONITOR_NUMBER:
+	case OID_GEN_TRANSMIT_QUEUE_LENGTH:
+	case OID_SKGE_TRAP_NUMBER:
+	case OID_SKGE_MDB_VERSION:
+	case OID_SKGE_BOARDLEVEL:
+	case OID_SKGE_CHIPID:
+	case OID_SKGE_RAMSIZE:
+		if (*pLen < sizeof(SK_U32)) {
+
+			*pLen = sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_CHIPSET:
+		if (*pLen < sizeof(SK_U16)) {
+
+			*pLen = sizeof(SK_U16);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_BUS_TYPE:
+	case OID_SKGE_BUS_SPEED:
+	case OID_SKGE_BUS_WIDTH:
+	case OID_SKGE_SENSOR_NUMBER:
+	case OID_SKGE_CHKSM_NUMBER:
+	case OID_SKGE_VAUXAVAIL:
+		if (*pLen < sizeof(SK_U8)) {
+
+			*pLen = sizeof(SK_U8);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_TX_SW_QUEUE_LEN:
+	case OID_SKGE_TX_SW_QUEUE_MAX:
+	case OID_SKGE_TX_RETRY:
+	case OID_SKGE_RX_INTR_CTS:
+	case OID_SKGE_TX_INTR_CTS:
+	case OID_SKGE_RX_NO_BUF_CTS:
+	case OID_SKGE_TX_NO_BUF_CTS:
+	case OID_SKGE_TX_USED_DESCR_NO:
+	case OID_SKGE_RX_DELIVERED_CTS:
+	case OID_SKGE_RX_OCTETS_DELIV_CTS:
+	case OID_SKGE_RX_HW_ERROR_CTS:
+	case OID_SKGE_TX_HW_ERROR_CTS:
+	case OID_SKGE_IN_ERRORS_CTS:
+	case OID_SKGE_OUT_ERROR_CTS:
+	case OID_SKGE_ERR_RECOVERY_CTS:
+	case OID_SKGE_SYSUPTIME:
+		if (*pLen < sizeof(SK_U64)) {
+
+			*pLen = sizeof(SK_U64);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		/* Checked later. */
+		break;
+	}
+
+	/* Update statistics. */
+	if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
+		Id == OID_SKGE_TX_HW_ERROR_CTS ||
+		Id == OID_SKGE_IN_ERRORS_CTS ||
+		Id == OID_SKGE_OUT_ERROR_CTS ||
+		Id == OID_GEN_XMIT_ERROR ||
+		Id == OID_GEN_RCV_ERROR) {
+
+		/*
+		 * Force the XMAC to update its statistic counters and
+		 * Increment semaphore to indicate that an update was
+		 * already done.
+		 */
+		Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
+		if (Ret != SK_PNMI_ERR_OK) {
+
+			*pLen = 0;
+			return (Ret);
+		}
+		pAC->Pnmi.MacUpdatedFlag ++;
+
+		/*
+		 * Some OIDs consist of multiple hardware counters. Those
+		 * values which are contained in all of them will be added
+		 * now.
+		 */
+		switch (Id) {
+
+		case OID_SKGE_RX_HW_ERROR_CTS:
+		case OID_SKGE_IN_ERRORS_CTS:
+		case OID_GEN_RCV_ERROR:
+			Val64RxHwErrs =
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
+
+
+			/*
+			 * In some cases the runt and fcs counters are incremented when collisions
+			 * occur. We have to correct those counters here.
+			 */
+			Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex);
+			Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex);
+
+			if (Val64RxRunt > Val64RxFcs) {
+				Val64RxRunt -= Val64RxFcs;
+				Val64RxHwErrs += Val64RxRunt;
+			}
+			else {
+				Val64RxFcs -= Val64RxRunt;
+				Val64RxHwErrs += Val64RxFcs;
+			}
+			break;
+
+		case OID_SKGE_TX_HW_ERROR_CTS:
+		case OID_SKGE_OUT_ERROR_CTS:
+		case OID_GEN_XMIT_ERROR:
+			Val64TxHwErrs =
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex) +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex);
+			break;
+		}
+	}
+
+	/* Retrieve value. */
+	switch (Id) {
+
+	case OID_SKGE_SUPPORTED_LIST:
+		Len = ID_TABLE_SIZE * sizeof(SK_U32);
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		for (Offset = 0, Index = 0; Offset < Len; Index ++) {
+
+			Val32 = (SK_U32)IdTable[Index].Id;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+		}
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_BOARDLEVEL:
+		Val32 = (SK_U32)pAC->GIni.GILevel;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_PORT_NUMBER:
+		Val32 = (SK_U32)pAC->GIni.GIMacsFound;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_DEVICE_TYPE:
+		Val32 = (SK_U32)pAC->Pnmi.DeviceType;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_DRIVER_DESCR:
+		if (pAC->Pnmi.pDriverDescription == NULL) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
+		if (Len > SK_PNMI_STRINGLEN1) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		*pBuf = (char)(Len - 1);
+		SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_DRIVER_VERSION:
+		if (pAC->Pnmi.pDriverVersion == NULL) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
+		if (Len > SK_PNMI_STRINGLEN1) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		*pBuf = (char)(Len - 1);
+		SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_DRIVER_RELDATE:
+		if (pAC->Pnmi.pDriverReleaseDate == NULL) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;
+		if (Len > SK_PNMI_STRINGLEN1) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		*pBuf = (char)(Len - 1);
+		SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverReleaseDate, Len - 1);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_DRIVER_FILENAME:
+		if (pAC->Pnmi.pDriverFileName == NULL) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;
+		if (Len > SK_PNMI_STRINGLEN1) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		*pBuf = (char)(Len - 1);
+		SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverFileName, Len - 1);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_HW_DESCR:
+		/*
+		 * The hardware description is located in the VPD.
+		 * This query may move to the initialization routine.
+		 * But the VPD is cached and therefore a call here
+		 * will not make much difference.
+		 * Please read comment in Vpd().
+		 */
+		if (pAC->Pnmi.VpdKeyReadError) {
+			return (SK_PNMI_ERR_OK);
+		}
+
+		Len = 256;
+		if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+		Len ++;
+		if (Len > SK_PNMI_STRINGLEN1) {
+
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		*pBuf = (char)(Len - 1);
+		SK_MEMCPY(pBuf + 1, Buf, Len - 1);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_HW_VERSION:
+		if (*pLen < 5) {
+
+			*pLen = 5;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
+		pBuf[0] = 4;
+		pBuf[1] = 'v';
+		pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f));
+		pBuf[3] = '.';
+		pBuf[4] = (char)('0' | (Val8 & 0x0f));
+		*pLen = 5;
+		break;
+
+	case OID_SKGE_CHIPSET:
+		Val16 = pAC->Pnmi.Chipset;
+		SK_PNMI_STORE_U16(pBuf, Val16);
+		*pLen = sizeof(SK_U16);
+		break;
+
+	case OID_SKGE_CHIPID:
+		Val32 = pAC->GIni.GIChipId;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_RAMSIZE:
+		Val32 = pAC->GIni.GIRamSize;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_VAUXAVAIL:
+		*pBuf = (char)pAC->GIni.GIVauxAvail;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_BUS_TYPE:
+		*pBuf = (char)SK_PNMI_BUS_PCI;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_BUS_SPEED:
+		*pBuf = pAC->Pnmi.PciBusSpeed;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_BUS_WIDTH:
+		*pBuf = pAC->Pnmi.PciBusWidth;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_RESULT:
+		Val32 = pAC->Pnmi.TestResult;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_SENSOR_NUMBER:
+		*pBuf = (char)pAC->I2c.MaxSens;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_CHKSM_NUMBER:
+		*pBuf = SKCS_NUM_PROTOCOLS;
+		*pLen = sizeof(char);
+		break;
+
+	case OID_SKGE_TRAP_NUMBER:
+		GetTrapQueueLen(pAC, &Len, &Val);
+		Val32 = (SK_U32)Val;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_TRAP:
+		GetTrapQueueLen(pAC, &Len, &Val);
+		if (*pLen < Len) {
+
+			*pLen = Len;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		CopyTrapQueue(pAC, pBuf);
+		*pLen = Len;
+		break;
+
+	case OID_SKGE_RLMT_MONITOR_NUMBER:
+		/* Not yet implemented by RLMT, therefore we return zero elements. */
+		Val32 = 0;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_SKGE_TX_SW_QUEUE_LEN:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
+					pAC->Pnmi.BufPort[1].TxSwQueueLen;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
+					pAC->Pnmi.Port[1].TxSwQueueLen;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_SW_QUEUE_MAX:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +
+					pAC->Pnmi.BufPort[1].TxSwQueueMax;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +
+					pAC->Pnmi.Port[1].TxSwQueueMax;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_RETRY:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +
+					pAC->Pnmi.BufPort[1].TxRetryCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxRetryCts +
+					pAC->Pnmi.Port[1].TxRetryCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_RX_INTR_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +
+					pAC->Pnmi.BufPort[1].RxIntrCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].RxIntrCts +
+					pAC->Pnmi.Port[1].RxIntrCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_INTR_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +
+					pAC->Pnmi.BufPort[1].TxIntrCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxIntrCts +
+					pAC->Pnmi.Port[1].TxIntrCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_RX_NO_BUF_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +
+					pAC->Pnmi.BufPort[1].RxNoBufCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].RxNoBufCts +
+					pAC->Pnmi.Port[1].RxNoBufCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_NO_BUF_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +
+					pAC->Pnmi.BufPort[1].TxNoBufCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxNoBufCts +
+					pAC->Pnmi.Port[1].TxNoBufCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_USED_DESCR_NO:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +
+					pAC->Pnmi.BufPort[1].TxUsedDescrNo;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +
+					pAC->Pnmi.Port[1].TxUsedDescrNo;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_RX_DELIVERED_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +
+					pAC->Pnmi.BufPort[1].RxDeliveredCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +
+					pAC->Pnmi.Port[1].RxDeliveredCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_RX_OCTETS_DELIV_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +
+					pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +
+					pAC->Pnmi.Port[1].RxOctetsDeliveredCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_RX_HW_ERROR_CTS:
+		SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_TX_HW_ERROR_CTS:
+		SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_IN_ERRORS_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = Val64RxHwErrs +
+					pAC->Pnmi.BufPort[0].RxNoBufCts +
+					pAC->Pnmi.BufPort[1].RxNoBufCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = Val64RxHwErrs +
+					pAC->Pnmi.Port[0].RxNoBufCts +
+					pAC->Pnmi.Port[1].RxNoBufCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_OUT_ERROR_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = Val64TxHwErrs +
+					pAC->Pnmi.BufPort[0].TxNoBufCts +
+					pAC->Pnmi.BufPort[1].TxNoBufCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = Val64TxHwErrs +
+					pAC->Pnmi.Port[0].TxNoBufCts +
+					pAC->Pnmi.Port[1].TxNoBufCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_ERR_RECOVERY_CTS:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +
+					pAC->Pnmi.BufPort[1].ErrRecoveryCts;
+			}
+		}
+		else {
+			/* DualNet mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;
+			}
+			/* SingleNet mode */
+			else {
+				Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +
+					pAC->Pnmi.Port[1].ErrRecoveryCts;
+			}
+		}
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_SYSUPTIME:
+		Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+		Val64 -= pAC->Pnmi.StartUpTime;
+		SK_PNMI_STORE_U64(pBuf, Val64);
+		*pLen = sizeof(SK_U64);
+		break;
+
+	case OID_SKGE_MDB_VERSION:
+		Val32 = SK_PNMI_MDB_VERSION;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	case OID_GEN_RCV_ERROR:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
+		}
+		else {
+			Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
+		}
+
+		/*
+		 * By default 32bit values are evaluated.
+		 */
+		if (!Is64BitReq) {
+			Val32 = (SK_U32)Val64;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+		}
+		else {
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+		}
+		break;
+
+	case OID_GEN_XMIT_ERROR:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
+		}
+		else {
+			Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
+		}
+
+		/*
+		 * By default 32bit values are evaluated.
+		 */
+		if (!Is64BitReq) {
+			Val32 = (SK_U32)Val64;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+		}
+		else {
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+		}
+		break;
+
+	case OID_GEN_RCV_NO_BUFFER:
+		/* For XMAC, use the frozen SW counters (BufPort). */
+		if (MacType == SK_MAC_XMAC) {
+			Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
+
+		}
+		else {
+			Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts +
+				GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
+		}
+
+		/*
+		 * By default 32bit values are evaluated.
+		 */
+		if (!Is64BitReq) {
+			Val32 = (SK_U32)Val64;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+		}
+		else {
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+		}
+		break;
+
+	case OID_GEN_TRANSMIT_QUEUE_LENGTH:
+		Val32 = (SK_U32)pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
+		SK_PNMI_STORE_U32(pBuf, Val32);
+		*pLen = sizeof(SK_U32);
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG);
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
+		Id == OID_SKGE_TX_HW_ERROR_CTS ||
+		Id == OID_SKGE_IN_ERRORS_CTS ||
+		Id == OID_SKGE_OUT_ERROR_CTS ||
+		Id == OID_GEN_XMIT_ERROR ||
+		Id == OID_GEN_RCV_ERROR) {
+
+		pAC->Pnmi.MacUpdatedFlag --;
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+#ifndef SK_NO_RLMT
+/*****************************************************************************
+ *
+ * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance.
+ *
+ * Description:
+ *	Get/Presets/Sets the RLMT OIDs.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Rlmt(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int		Ret;
+	unsigned int	PhysPortIndex;
+	unsigned int	PhysPortMax;
+	SK_EVPARA	EventParam;
+	SK_U32		Val32;
+	SK_U64		Val64;
+
+	/* Check instance. Only single instance OIDs are allowed here. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Perform the requested action. */
+	if (Action == SK_PNMI_GET) {
+
+		/* Check if the buffer length is large enough. */
+		switch (Id) {
+
+		case OID_SKGE_RLMT_MODE:
+		case OID_SKGE_RLMT_PORT_ACTIVE:
+		case OID_SKGE_RLMT_PORT_PREFERRED:
+			if (*pLen < sizeof(SK_U8)) {
+
+				*pLen = sizeof(SK_U8);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		case OID_SKGE_RLMT_PORT_NUMBER:
+			if (*pLen < sizeof(SK_U32)) {
+
+				*pLen = sizeof(SK_U32);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_CTS:
+		case OID_SKGE_RLMT_CHANGE_TIME:
+		case OID_SKGE_RLMT_CHANGE_ESTIM:
+		case OID_SKGE_RLMT_CHANGE_THRES:
+			if (*pLen < sizeof(SK_U64)) {
+
+				*pLen = sizeof(SK_U64);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG);
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		/*
+		 * Update RLMT statistic and increment semaphores to indicate
+		 * that an update was already done. Maybe RLMT will hold its
+		 * statistic always up to date some time. Then we can
+		 * remove this type of call.
+		 */
+		if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
+
+			*pLen = 0;
+			return (Ret);
+		}
+		pAC->Pnmi.RlmtUpdatedFlag ++;
+
+		/* Retrieve value. */
+		switch (Id) {
+
+		case OID_SKGE_RLMT_MODE:
+			*pBuf = (char)pAC->Rlmt.Net[0].RlmtMode;
+			*pLen = sizeof(char);
+			break;
+
+		case OID_SKGE_RLMT_PORT_NUMBER:
+			Val32 = (SK_U32)pAC->GIni.GIMacsFound;
+			SK_PNMI_STORE_U32(pBuf, Val32);
+			*pLen = sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_RLMT_PORT_ACTIVE:
+			*pBuf = 0;
+			/*
+			 * If multiple ports may become active this OID
+			 * doesn't make sense any more. A new variable in
+			 * the port structure should be created. However,
+			 * for this variable the first active port is
+			 * returned.
+			 */
+			PhysPortMax = pAC->GIni.GIMacsFound;
+
+			for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+				PhysPortIndex ++) {
+
+				if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+					*pBuf = (char)SK_PNMI_PORT_PHYS2LOG(PhysPortIndex);
+					break;
+				}
+			}
+			*pLen = sizeof(char);
+			break;
+
+		case OID_SKGE_RLMT_PORT_PREFERRED:
+			*pBuf = (char)SK_PNMI_PORT_PHYS2LOG(pAC->Rlmt.Net[NetIndex].Preference);
+			*pLen = sizeof(char);
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_CTS:
+			Val64 = pAC->Pnmi.RlmtChangeCts;
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_TIME:
+			Val64 = pAC->Pnmi.RlmtChangeTime;
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_ESTIM:
+			Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate;
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_THRES:
+			Val64 = pAC->Pnmi.RlmtChangeThreshold;
+			SK_PNMI_STORE_U64(pBuf, Val64);
+			*pLen = sizeof(SK_U64);
+			break;
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+				("Rlmt: Unknown OID should be handled before"));
+
+			pAC->Pnmi.RlmtUpdatedFlag --;
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		pAC->Pnmi.RlmtUpdatedFlag --;
+	}
+	else {
+		/* Perform a PRESET or SET. */
+		switch (Id) {
+
+		case OID_SKGE_RLMT_MODE:
+			/* Check if the buffer length is plausible. */
+			if (*pLen < sizeof(char)) {
+
+				*pLen = sizeof(char);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			/* Check if the value range is correct. */
+			if (*pLen != sizeof(char) ||
+				(*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
+				*(SK_U8 *)pBuf > 15) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_OK);
+			}
+			/* Send an event to RLMT to change the mode. */
+			SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+			EventParam.Para32[0] |= (SK_U32)(*pBuf);
+			EventParam.Para32[1] = 0;
+			if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
+				EventParam) > 0) {
+
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG);
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+			break;
+
+		case OID_SKGE_RLMT_PORT_PREFERRED:
+			/* PRESET/SET action makes no sense in Dual Net mode */
+			if (pAC->Pnmi.DualNetActiveFlag) {
+				break;
+			}
+
+			/* Check if the buffer length is plausible. */
+			if (*pLen < sizeof(char)) {
+
+				*pLen = sizeof(char);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			/* Check if the value range is correct. */
+			if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
+				(SK_U8)pAC->GIni.GIMacsFound) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_OK);
+			}
+
+			/*
+			 * Send an event to RLMT change the preferred port.
+			 * A param of -1 means automatic mode. RLMT will
+			 * make the decision which is the preferred port.
+			 */
+			SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+			EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
+			EventParam.Para32[1] = NetIndex;
+			if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
+				EventParam) > 0) {
+
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG);
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+			break;
+
+		case OID_SKGE_RLMT_CHANGE_THRES:
+			/* Check if the buffer length is plausible. */
+			if (*pLen < sizeof(SK_U64)) {
+
+				*pLen = sizeof(SK_U64);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+
+			/* There are not many restrictions to the value range. */
+			if (*pLen != sizeof(SK_U64)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_OK);
+			}
+			/*
+			 * Store the new threshold, which will be taken
+			 * on the next timer event.
+			 */
+			SK_PNMI_READ_U64(pBuf, Val64);
+			pAC->Pnmi.RlmtChangeThreshold = Val64;
+			break;
+
+		default:
+			/* The other OIDs are not be able for set. */
+			*pLen = 0;
+			return (SK_PNMI_ERR_READ_ONLY);
+		}
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance.
+ *
+ * Description:
+ *	Performs get requests on multiple instance variables.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int RlmtStat(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	PhysPortMax;
+	unsigned int	PhysPortIndex;
+	unsigned int	Limit;
+	unsigned int	Offset;
+	int		Ret;
+	SK_U32		Val32;
+	SK_U64		Val64;
+
+	/* Calculate the port indexes from the instance. */
+	PhysPortMax = pAC->GIni.GIMacsFound;
+
+	if ((Instance != (SK_U32)(-1))) {
+		/* Check instance range. */
+		if ((Instance < 1) || (Instance > PhysPortMax)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+
+		/* SingleNet mode */
+		PhysPortIndex = Instance - 1;
+
+		/* DualNet mode */
+		if (pAC->Pnmi.DualNetActiveFlag) {
+			PhysPortIndex = NetIndex;
+		}
+
+		/* Both net modes. */
+		Limit = PhysPortIndex + 1;
+	}
+	else {
+		/* SingleNet mode */
+		PhysPortIndex = 0;
+		Limit = PhysPortMax;
+
+		/* DualNet mode */
+		if (pAC->Pnmi.DualNetActiveFlag) {
+			PhysPortIndex = NetIndex;
+			Limit = PhysPortIndex + 1;
+		}
+	}
+
+	/* Currently only GET requests are allowed. */
+	if (Action != SK_PNMI_GET) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Check if the buffer length is large enough. */
+	switch (Id) {
+
+	case OID_SKGE_RLMT_PORT_INDEX:
+	case OID_SKGE_RLMT_STATUS:
+		if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
+
+			*pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_SKGE_RLMT_TX_HELLO_CTS:
+	case OID_SKGE_RLMT_RX_HELLO_CTS:
+	case OID_SKGE_RLMT_TX_SP_REQ_CTS:
+	case OID_SKGE_RLMT_RX_SP_CTS:
+		if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) {
+
+			*pLen = (Limit - PhysPortIndex) * sizeof(SK_U64);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG);
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+
+	}
+
+	/*
+	 * Update statistic and increment semaphores to indicate that
+	 * an update was already done.
+	 */
+	if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
+
+		*pLen = 0;
+		return (Ret);
+	}
+	pAC->Pnmi.RlmtUpdatedFlag ++;
+
+	/* Get value. */
+	Offset = 0;
+	for (; PhysPortIndex < Limit; PhysPortIndex ++) {
+
+		switch (Id) {
+
+		case OID_SKGE_RLMT_PORT_INDEX:
+			Val32 = PhysPortIndex;
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_RLMT_STATUS:
+			if (pAC->Rlmt.Port[PhysPortIndex].PortState ==
+				SK_RLMT_PS_INIT ||
+				pAC->Rlmt.Port[PhysPortIndex].PortState ==
+				SK_RLMT_PS_DOWN) {
+
+				Val32 = SK_PNMI_RLMT_STATUS_ERROR;
+			}
+			else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+				Val32 = SK_PNMI_RLMT_STATUS_ACTIVE;
+			}
+			else {
+				Val32 = SK_PNMI_RLMT_STATUS_STANDBY;
+			}
+			SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+			Offset += sizeof(SK_U32);
+			break;
+
+		case OID_SKGE_RLMT_TX_HELLO_CTS:
+			Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_RX_HELLO_CTS:
+			Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_TX_SP_REQ_CTS:
+			Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		case OID_SKGE_RLMT_RX_SP_CTS:
+			Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts;
+			SK_PNMI_STORE_U64(pBuf + Offset, Val64);
+			Offset += sizeof(SK_U64);
+			break;
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+				("RlmtStat: Unknown OID should be errored before"));
+
+			pAC->Pnmi.RlmtUpdatedFlag --;
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+	*pLen = Offset;
+
+	pAC->Pnmi.RlmtUpdatedFlag --;
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * Monitor - OID handler function for RLMT_MONITOR_XXX
+ *
+ * Description:
+ *	Because RLMT currently does not support the monitoring of
+ *	remote adapter cards, we return always an empty table.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occured.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int Monitor(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	Index;
+	unsigned int	Limit;
+	unsigned int	Offset;
+	unsigned int	Entries;
+
+	/* Not implemented yet. Return always an empty table. */
+	Entries = 0;
+
+	/* Calculate instance if wished. */
+	if ((Instance != (SK_U32)(-1))) {
+
+		if ((Instance < 1) || (Instance > Entries)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+
+		Index = (unsigned int)Instance - 1;
+		Limit = (unsigned int)Instance;
+	}
+	else {
+		Index = 0;
+		Limit = Entries;
+	}
+
+	/* GET/SET value. */
+	if (Action == SK_PNMI_GET) {
+
+		for (Offset = 0; Index < Limit; Index ++) {
+
+			switch (Id) {
+
+			case OID_SKGE_RLMT_MONITOR_INDEX:
+			case OID_SKGE_RLMT_MONITOR_ADDR:
+			case OID_SKGE_RLMT_MONITOR_ERRS:
+			case OID_SKGE_RLMT_MONITOR_TIMESTAMP:
+			case OID_SKGE_RLMT_MONITOR_ADMIN:
+				break;
+
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046, SK_PNMI_ERR046MSG);
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+		}
+		*pLen = Offset;
+	}
+	else {
+		/* Only MONITOR_ADMIN can be set. */
+		if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_READ_ONLY);
+		}
+
+		/* Check if the length is plausible. */
+		if (*pLen < (Limit - Index)) {
+
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		/* Okay, we have a wide value range. */
+		if (*pLen != (Limit - Index)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_BAD_VALUE);
+		}
+
+		/*
+		 * Not yet implemented. Return always BAD_VALUE,
+		 * because the table is empty.
+		 */
+		*pLen = 0;
+		return (SK_PNMI_ERR_BAD_VALUE);
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+#endif
+/*****************************************************************************
+ *
+ * MacPrivateConf - OID handler function of OIDs concerning the configuration
+ *
+ * Description:
+ *	Get/Presets/Sets the OIDs concerning the configuration.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_BAD_VALUE    The passed value is not in the valid
+ *	                         value range.
+ *	SK_PNMI_ERR_READ_ONLY    The OID is read-only and cannot be set.
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+PNMI_STATIC int MacPrivateConf(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	PhysPortMax;
+	unsigned int	PhysPortIndex;
+	unsigned int	LogPortMax;
+	unsigned int	LogPortIndex;
+	unsigned int	Limit;
+	unsigned int	Offset;
+	char		Val8;
+	char 		*pBufPtr;
+	int			Ret;
+	SK_EVPARA	EventParam;
+	SK_U32		Val32;
+#ifdef SK_PHY_LP_MODE
+	SK_U8	CurrentPhyPowerState;
+#endif /* SK_PHY_LP_MODE */
+
+	/* Calculate instance if wished. MAC index 0 is the virtual MAC. */
+	PhysPortMax = pAC->GIni.GIMacsFound;
+	LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+	if (pAC->Pnmi.DualNetActiveFlag) { /* DualNet mode */
+		LogPortMax--;
+	}
+
+	if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
+		/* Check instance range. */
+		if ((Instance < 1) || (Instance > LogPortMax)) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_UNKNOWN_INST);
+		}
+		LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
+		Limit = LogPortIndex + 1;
+	}
+
+	else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
+
+		LogPortIndex = 0;
+		Limit = LogPortMax;
+	}
+
+	/* Perform action. */
+	if (Action == SK_PNMI_GET) {
+
+		/* Check length. */
+		switch (Id) {
+
+		case OID_SKGE_PMD:
+		case OID_SKGE_CONNECTOR:
+		case OID_SKGE_LINK_CAP:
+		case OID_SKGE_LINK_MODE:
+		case OID_SKGE_LINK_MODE_STATUS:
+		case OID_SKGE_LINK_STATUS:
+		case OID_SKGE_FLOWCTRL_CAP:
+		case OID_SKGE_FLOWCTRL_MODE:
+		case OID_SKGE_FLOWCTRL_STATUS:
+		case OID_SKGE_PHY_OPERATION_CAP:
+		case OID_SKGE_PHY_OPERATION_MODE:
+		case OID_SKGE_PHY_OPERATION_STATUS:
+		case OID_SKGE_SPEED_CAP:
+		case OID_SKGE_SPEED_MODE:
+		case OID_SKGE_SPEED_STATUS:
+#ifdef SK_PHY_LP_MODE
+		case OID_SKGE_PHY_LP_MODE:
+#endif
+			if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
+
+				*pLen = (Limit - LogPortIndex) * sizeof(SK_U8);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		case OID_SKGE_MTU:
+		case OID_SKGE_PHY_TYPE:
+			if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
+
+				*pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG);
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		/*
+		 * Update statistic and increment semaphore to indicate
+		 * that an update was already done.
+		 */
+		if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
+
+			*pLen = 0;
+			return (Ret);
+		}
+		pAC->Pnmi.SirqUpdatedFlag ++;
+
+		/* Get value. */
+		Offset = 0;
+		for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+			pBufPtr = pBuf + Offset;
+
+			switch (Id) {
+
+			case OID_SKGE_PMD:
+				*pBufPtr = pAC->Pnmi.PMD;
+				Offset++;
+				break;
+
+			case OID_SKGE_CONNECTOR:
+				*pBufPtr = pAC->Pnmi.Connector;
+				Offset++;
+				break;
+
+			case OID_SKGE_PHY_TYPE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						continue;
+					}
+					/* Get value for physical port. */
+					PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+					Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
+				}
+				else { /* DualNet mode */
+
+					Val32 = pAC->GIni.GP[NetIndex].PhyType;
+				}
+				SK_PNMI_STORE_U32(pBufPtr, Val32);
+				Offset += sizeof(SK_U32);
+				break;
+
+#ifdef SK_PHY_LP_MODE
+			case OID_SKGE_PHY_LP_MODE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						continue;
+					}
+					/* Get value for physical port. */
+					PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+					*pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState;
+				}
+				Offset += sizeof(SK_U8);
+				break;
+#endif
+
+			case OID_SKGE_LINK_CAP:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_LINK_MODE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_LINK_MODE_STATUS:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr =
+							CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_LINK_STATUS:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_FLOWCTRL_CAP:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_FLOWCTRL_MODE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_FLOWCTRL_STATUS:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_PHY_OPERATION_CAP:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_PHY_OPERATION_MODE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_PHY_OPERATION_STATUS:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSStatus;
+					}
+				}
+				else {
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_SPEED_CAP:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_SPEED_MODE:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_SPEED_STATUS:
+				if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+					if (LogPortIndex == 0) {
+						/* Get value for virtual port. */
+						VirtualConf(pAC, IoC, Id, pBufPtr);
+					}
+					else {
+						/* Get value for physical port. */
+						PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
+							pAC, LogPortIndex);
+
+						*pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
+					}
+				}
+				else { /* DualNet mode */
+
+					*pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;
+				}
+				Offset++;
+				break;
+
+			case OID_SKGE_MTU:
+				Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex);
+				SK_PNMI_STORE_U32(pBufPtr, Val32);
+				Offset += sizeof(SK_U32);
+				break;
+
+			default:
+				SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+					("MacPrivateConf: Unknown OID should be handled before"));
+
+				pAC->Pnmi.SirqUpdatedFlag --;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+		}
+		*pLen = Offset;
+		pAC->Pnmi.SirqUpdatedFlag --;
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/*
+	 * From here SET or PRESET action. Check if the passed
+	 * buffer length is plausible.
+	 */
+	switch (Id) {
+
+	case OID_SKGE_LINK_MODE:
+	case OID_SKGE_FLOWCTRL_MODE:
+	case OID_SKGE_PHY_OPERATION_MODE:
+	case OID_SKGE_SPEED_MODE:
+		if (*pLen < Limit - LogPortIndex) {
+
+			*pLen = Limit - LogPortIndex;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		if (*pLen != Limit - LogPortIndex) {
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_BAD_VALUE);
+		}
+		break;
+
+#ifdef SK_PHY_LP_MODE
+	case OID_SKGE_PHY_LP_MODE:
+		if (*pLen < Limit - LogPortIndex) {
+
+			*pLen = Limit - LogPortIndex;
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+#endif /* SK_PHY_LP_MODE */
+
+	case OID_SKGE_MTU:
+		if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
+
+			*pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		*pLen = 0;
+		return (SK_PNMI_ERR_READ_ONLY);
+	}
+
+	/* Perform PRESET or SET. */
+	Offset = 0;
+	for (; LogPortIndex < Limit; LogPortIndex ++) {
+
+		Val8 = *(pBuf + Offset);
+
+		switch (Id) {
+
+		case OID_SKGE_LINK_MODE:
+			/* Check the value range. */
+			if (Val8 == 0) {
+				Offset++;
+				break;
+			}
+			if (Val8 < SK_LMODE_HALF ||
+				(LogPortIndex != 0 && Val8 > SK_LMODE_AUTOSENSE) ||
+				(LogPortIndex == 0 && Val8 > SK_LMODE_INDETERMINATED)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+				if (LogPortIndex == 0) {
+					/*
+					 * The virtual port consists of all currently active ports.
+					 * Find them and send an event with the new link mode to SIRQ.
+					 */
+					for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+						PhysPortIndex ++) {
+
+						if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+							continue;
+						}
+
+						EventParam.Para32[0] = PhysPortIndex;
+						EventParam.Para32[1] = (SK_U32)Val8;
+						if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
+							EventParam) > 0) {
+
+							SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR043,
+								SK_PNMI_ERR043MSG);
+
+							*pLen = 0;
+							return (SK_PNMI_ERR_GENERAL);
+						}
+					} /* for */
+				}
+				else {
+					/* Send an event with the new link mode to SIRQ */
+					EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+						pAC, LogPortIndex);
+					EventParam.Para32[1] = (SK_U32)Val8;
+					if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
+						EventParam) > 0) {
+
+						SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR043,
+							SK_PNMI_ERR043MSG);
+
+						*pLen = 0;
+						return (SK_PNMI_ERR_GENERAL);
+					}
+				}
+			}
+			else { /* DualNet mode */
+
+				/* Send an event with the new link mode to SIRQ */
+				EventParam.Para32[0] = NetIndex;
+				EventParam.Para32[1] = (SK_U32)Val8;
+				if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
+					EventParam) > 0) {
+
+					SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR043,
+						SK_PNMI_ERR043MSG);
+
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			}
+			Offset++;
+			break;
+
+		case OID_SKGE_FLOWCTRL_MODE:
+			/* Check the value range. */
+			if (Val8 == 0) {
+				Offset++;
+				break;
+			}
+			if (Val8 < SK_FLOW_MODE_NONE ||
+				(LogPortIndex != 0 && Val8 > SK_FLOW_MODE_SYM_OR_REM) ||
+				(LogPortIndex == 0 && Val8 > SK_FLOW_MODE_INDETERMINATED)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+				if (LogPortIndex == 0) {
+					/*
+					 * The virtual port consists of all currently active ports.
+					 * Find them and send an event with the new flow control mode to SIRQ.
+					 */
+					for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+						PhysPortIndex ++) {
+
+						if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+							continue;
+						}
+
+						EventParam.Para32[0] = PhysPortIndex;
+						EventParam.Para32[1] = (SK_U32)Val8;
+						if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
+							EventParam) > 0) {
+
+							SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR044,
+								SK_PNMI_ERR044MSG);
+
+							*pLen = 0;
+							return (SK_PNMI_ERR_GENERAL);
+						}
+					}
+				}
+				else {
+					/* Send an event with the new flow control mode to SIRQ */
+					EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+						pAC, LogPortIndex);
+					EventParam.Para32[1] = (SK_U32)Val8;
+					if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
+						EventParam) > 0) {
+
+						SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR044,
+							SK_PNMI_ERR044MSG);
+
+						*pLen = 0;
+						return (SK_PNMI_ERR_GENERAL);
+					}
+				}
+			}
+			else { /* DualNet mode */
+				/* Send an event with the new flow control mode to SIRQ */
+				EventParam.Para32[0] = NetIndex;
+				EventParam.Para32[1] = (SK_U32)Val8;
+				if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
+					EventParam) > 0) {
+
+					SK_ERR_LOG(pAC, SK_ERRCL_SW,
+						SK_PNMI_ERR044,
+						SK_PNMI_ERR044MSG);
+
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			}
+			Offset++;
+			break;
+
+		case OID_SKGE_PHY_OPERATION_MODE :
+			/* Check the value range. */
+			if (Val8 == 0) {
+				/* Mode of this port remains unchanged. */
+				Offset++;
+				break;
+			}
+			if (Val8 < SK_MS_MODE_AUTO ||
+				(LogPortIndex != 0 && Val8 > SK_MS_MODE_SLAVE) ||
+				(LogPortIndex == 0 && Val8 > SK_MS_MODE_INDETERMINATED)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+				if (LogPortIndex == 0) {
+					/*
+					 * The virtual port consists of all currently active ports.
+					 * Find them and send an event with new master/slave (role)
+					 * mode to the SIRQ module.
+					 */
+					for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+						PhysPortIndex ++) {
+
+						if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+							continue;
+						}
+
+						EventParam.Para32[0] = PhysPortIndex;
+						EventParam.Para32[1] = (SK_U32)Val8;
+						if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
+							EventParam) > 0) {
+
+							SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042,
+								SK_PNMI_ERR042MSG);
+
+							*pLen = 0;
+							return (SK_PNMI_ERR_GENERAL);
+						}
+					}
+				}
+				else {
+					/* Send an event with the new role mode to SIRQ */
+					EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+						pAC, LogPortIndex);
+					EventParam.Para32[1] = (SK_U32)Val8;
+					if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
+						EventParam) > 0) {
+
+						SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042,
+							SK_PNMI_ERR042MSG);
+
+						*pLen = 0;
+						return (SK_PNMI_ERR_GENERAL);
+					}
+				}
+			}
+			else { /* DualNet mode */
+				/* Send an event with the new master/slave (role) to SIRQ */
+				EventParam.Para32[0] = NetIndex;
+				EventParam.Para32[1] = (SK_U32)Val8;
+				if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
+					EventParam) > 0) {
+
+					SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042,
+						SK_PNMI_ERR042MSG);
+
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			}
+			Offset++;
+			break;
+
+		case OID_SKGE_SPEED_MODE:
+			/* Check the value range. */
+			if (Val8 == 0) {
+				Offset++;
+				break;
+			}
+			if (Val8 < (SK_LSPEED_AUTO) ||
+				(LogPortIndex != 0 && Val8 > SK_LSPEED_1000MBPS) ||
+				(LogPortIndex == 0 && Val8 > SK_LSPEED_INDETERMINATED)) {
+
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+				if (LogPortIndex == 0) {
+
+					/*
+					 * The virtual port consists of all currently active ports.
+					 * Find them and send an event with the new link speed to
+					 * the SIRQ module.
+					 */
+					for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+						PhysPortIndex ++) {
+
+						if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+							continue;
+						}
+
+						EventParam.Para32[0] = PhysPortIndex;
+						EventParam.Para32[1] = (SK_U32)Val8;
+						if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
+							EventParam) > 0) {
+
+							SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR045,
+								SK_PNMI_ERR045MSG);
+
+							*pLen = 0;
+							return (SK_PNMI_ERR_GENERAL);
+						}
+					}
+				}
+				else {
+					/* Send an event with the new link speed to SIRQ */
+					EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
+						pAC, LogPortIndex);
+					EventParam.Para32[1] = (SK_U32)Val8;
+					if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
+						EventParam) > 0) {
+
+						SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR045,
+							SK_PNMI_ERR045MSG);
+
+						*pLen = 0;
+						return (SK_PNMI_ERR_GENERAL);
+					}
+				}
+			}
+			else { /* DualNet mode */
+				/* Send an event with the new link speed to SIRQ */
+				EventParam.Para32[0] = NetIndex;
+				EventParam.Para32[1] = (SK_U32)Val8;
+				if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
+					EventParam) > 0) {
+
+					SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR045,
+						SK_PNMI_ERR045MSG);
+
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			}
+			Offset++;
+			break;
+
+		case OID_SKGE_MTU:
+			/* Check the value range. */
+			SK_PNMI_READ_U32((pBuf + Offset), Val32);
+
+			if (Val32 == 0) {
+				/* MTU of this port remains unchanged. */
+				Offset += sizeof(SK_U32);
+				break;
+			}
+
+			if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32)) {
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (SK_DRIVER_SET_MTU(pAC, IoC, NetIndex, Val32)) {
+				return (SK_PNMI_ERR_GENERAL);
+			}
+
+			Offset += sizeof(SK_U32);
+			break;
+
+#ifdef SK_PHY_LP_MODE
+		case OID_SKGE_PHY_LP_MODE:
+			/* The PRESET ends here. */
+			if (Action == SK_PNMI_PRESET) {
+
+				return (SK_PNMI_ERR_OK);
+			}
+
+			if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode */
+				if (LogPortIndex == 0) {
+					Offset = 0;
+					continue;
+				}
+			}
+			/* Set value for physical port. */
+			PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+			CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
+
+			switch (Val8) {
+
+			case PHY_PM_OPERATIONAL_MODE:
+				/* If LowPowerMode is active, we can leave it. */
+				if (CurrentPhyPowerState) {
+
+					Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
+
+					if (CurrentPhyPowerState == PHY_PM_DEEP_SLEEP ||
+						CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN) {
+
+						SkDrvInitAdapter(pAC);
+					}
+					break;
+				}
+				else {
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			case PHY_PM_DEEP_SLEEP:
+			case PHY_PM_IEEE_POWER_DOWN:
+				/* If no LowPowerMode is active, we can enter it. */
+				if (!CurrentPhyPowerState) {
+					SkDrvDeInitAdapter(pAC);
+				}
+
+			case PHY_PM_ENERGY_DETECT:
+			case PHY_PM_ENERGY_DETECT_PLUS:
+				/* If no LowPowerMode is active, we can enter it. */
+				if (!CurrentPhyPowerState) {
+
+					Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
+					break;
+				}
+				else {
+					*pLen = 0;
+					return (SK_PNMI_ERR_GENERAL);
+				}
+			default:
+				*pLen = 0;
+				return (SK_PNMI_ERR_BAD_VALUE);
+			}
+			Offset++;
+			break;
+#endif /* SK_PHY_LP_MODE */
+
+		default:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+				("MacPrivateConf: Unknown OID should be handled before set"));
+
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * VirtualConf - Calculates the values of configuration OIDs for virtual port
+ *
+ * Description:
+ *	We handle here the get of the configuration group OIDs, which are
+ *	a little bit complicated. The virtual port consists of all currently
+ *	active physical ports. If multiple ports are active and configured
+ *	differently we get in some trouble to return a single value. So we
+ *	get the value of the first active port and compare it with that of
+ *	the other active ports. If they are not the same, we return a value
+ *	that indicates that the state is indeterminated.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void VirtualConf(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf)		/* Buffer used for the management data transfer */
+{
+	unsigned int	PhysPortMax;
+	unsigned int	PhysPortIndex;
+	SK_U8		Val8;
+	SK_U32		Val32;
+	SK_BOOL		PortActiveFlag;
+	SK_GEPORT	*pPrt;
+
+	*pBuf = 0;
+	PortActiveFlag = SK_FALSE;
+	PhysPortMax = pAC->GIni.GIMacsFound;
+
+	for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) {
+
+		pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+		/* Check if the physical port is active. */
+		if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+			continue;
+		}
+
+		PortActiveFlag = SK_TRUE;
+
+		switch (Id) {
+
+		case OID_SKGE_PHY_TYPE:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+				Val32 = pPrt->PhyType;
+				SK_PNMI_STORE_U32(pBuf, Val32);
+				continue;
+			}
+			break;
+
+		case OID_SKGE_LINK_CAP:
+
+			/*
+			 * Different capabilities should not happen, but
+			 * in the case of the cases OR them all together.
+			 * From a curious point of view the virtual port
+			 * is capable of all found capabilities.
+			 */
+			*pBuf |= pPrt->PLinkCap;
+			break;
+
+		case OID_SKGE_LINK_MODE:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PLinkModeConf;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different link mode
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PLinkModeConf) {
+
+				*pBuf = SK_LMODE_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_LINK_MODE_STATUS:
+			/* Get the link mode of the physical port. */
+			Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
+
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = Val8;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different link mode status
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != Val8) {
+
+				*pBuf = SK_LMODE_STAT_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_LINK_STATUS:
+			/* Get the link status of the physical port. */
+			Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
+
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = Val8;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different link status
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != Val8) {
+
+				*pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_FLOWCTRL_CAP:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PFlowCtrlCap;
+				continue;
+			}
+
+			/*
+			 * From a curious point of view the virtual port
+			 * is capable of all found capabilities.
+			 */
+			*pBuf |= pPrt->PFlowCtrlCap;
+			break;
+
+		case OID_SKGE_FLOWCTRL_MODE:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PFlowCtrlMode;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different flow-control mode
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PFlowCtrlMode) {
+
+				*pBuf = SK_FLOW_MODE_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_FLOWCTRL_STATUS:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PFlowCtrlStatus;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different flow-control status
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PFlowCtrlStatus) {
+
+				*pBuf = SK_FLOW_STAT_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_PHY_OPERATION_CAP:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PMSCap;
+				continue;
+			}
+
+			/*
+			 * From a curious point of view the virtual port
+			 * is capable of all found capabilities.
+			 */
+			*pBuf |= pPrt->PMSCap;
+			break;
+
+		case OID_SKGE_PHY_OPERATION_MODE:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PMSMode;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different master/slave mode
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PMSMode) {
+
+				*pBuf = SK_MS_MODE_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_PHY_OPERATION_STATUS:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PMSStatus;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different master/slave status
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PMSStatus) {
+
+				*pBuf = SK_MS_STAT_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_SPEED_MODE:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PLinkSpeed;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different link speed
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PLinkSpeed) {
+
+				*pBuf = SK_LSPEED_INDETERMINATED;
+			}
+			break;
+
+		case OID_SKGE_SPEED_STATUS:
+			/* Check if it is the first active port. */
+			if (*pBuf == 0) {
+
+				*pBuf = pPrt->PLinkSpeedUsed;
+				continue;
+			}
+
+			/*
+			 * If we find an active port with a different link speed used
+			 * than the first one we return indeterminated.
+			 */
+			if (*pBuf != pPrt->PLinkSpeedUsed) {
+
+				*pBuf = SK_LSPEED_STAT_INDETERMINATED;
+			}
+			break;
+		}
+	}
+
+	/* If no port is active return an indeterminated answer. */
+	if (!PortActiveFlag) {
+
+		switch (Id) {
+
+		case OID_SKGE_LINK_CAP:
+			*pBuf = SK_LMODE_CAP_INDETERMINATED;
+			break;
+
+		case OID_SKGE_LINK_MODE:
+			*pBuf = SK_LMODE_INDETERMINATED;
+			break;
+
+		case OID_SKGE_LINK_MODE_STATUS:
+			*pBuf = SK_LMODE_STAT_INDETERMINATED;
+			break;
+
+		case OID_SKGE_LINK_STATUS:
+			*pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
+			break;
+
+		case OID_SKGE_FLOWCTRL_CAP:
+		case OID_SKGE_FLOWCTRL_MODE:
+			*pBuf = SK_FLOW_MODE_INDETERMINATED;
+			break;
+
+		case OID_SKGE_FLOWCTRL_STATUS:
+			*pBuf = SK_FLOW_STAT_INDETERMINATED;
+			break;
+
+		case OID_SKGE_PHY_OPERATION_CAP:
+			*pBuf = SK_MS_CAP_INDETERMINATED;
+			break;
+
+		case OID_SKGE_PHY_OPERATION_MODE:
+			*pBuf = SK_MS_MODE_INDETERMINATED;
+			break;
+
+		case OID_SKGE_PHY_OPERATION_STATUS:
+			*pBuf = SK_MS_STAT_INDETERMINATED;
+			break;
+		case OID_SKGE_SPEED_CAP:
+			*pBuf = SK_LSPEED_CAP_INDETERMINATED;
+			break;
+
+		case OID_SKGE_SPEED_MODE:
+			*pBuf = SK_LSPEED_INDETERMINATED;
+			break;
+
+		case OID_SKGE_SPEED_STATUS:
+			*pBuf = SK_LSPEED_STAT_INDETERMINATED;
+			break;
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * CalculateLinkStatus - Determins the link status of a physical port
+ *
+ * Description:
+ *	Determins the link status the following way:
+ *	  LSTAT_PHY_DOWN:  Link is down
+ *	  LSTAT_AUTONEG:   Auto-negotiation failed
+ *	  LSTAT_LOG_DOWN:  Link is up but RLMT did not yet put the port
+ *	                   logically up.
+ *	  LSTAT_LOG_UP:    RLMT marked the port as up
+ *
+ * Returns:
+ *	Link status of physical port
+ */
+PNMI_STATIC SK_U8 CalculateLinkStatus(
+SK_AC *pAC,			/* Pointer to adapter context */
+SK_IOC IoC,			/* IO context handle */
+unsigned int PhysPortIndex)	/* Physical port index */
+{
+	SK_U8	Result = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
+
+	if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) {
+
+		Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN;
+	}
+	else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) {
+
+		Result = SK_PNMI_RLMT_LSTAT_AUTONEG;
+	}
+#ifndef SK_NO_RLMT
+	else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) {
+
+		Result = SK_PNMI_RLMT_LSTAT_LOG_UP;
+	}
+	else {
+		Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN;
+	}
+#endif
+	return (Result);
+}
+
+/*****************************************************************************
+ *
+ * CalculateLinkModeStatus - Determins the link mode status of a phys. port
+ *
+ * Description:
+ *	The COMMON module only tells us if the mode is half or full duplex.
+ *	But in the decade of auto sensing it is usefull for the user to
+ *	know if the mode was negotiated or forced. Therefore we have a
+ *	look to the mode, which was last used by the negotiation process.
+ *
+ * Returns:
+ *	The link mode status
+ */
+PNMI_STATIC SK_U8 CalculateLinkModeStatus(
+SK_AC *pAC,			/* Pointer to adapter context */
+SK_IOC IoC,			/* IO context handle */
+unsigned int PhysPortIndex)	/* Physical port index */
+{
+	SK_U8	Result;
+
+	/* Get the current mode, which can be full or half duplex. */
+	Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
+
+	/* Check if no valid mode could be found (link is down). */
+	if (Result < SK_LMODE_STAT_HALF) {
+
+		Result = SK_LMODE_STAT_UNKNOWN;
+	}
+	else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
+		/*
+		 * Auto-negotiation was used to bring up the link. Change
+		 * the already found duplex status that it indicates
+		 * auto-negotiation was involved.
+		 */
+		if (Result == SK_LMODE_STAT_HALF) {
+
+			Result = SK_LMODE_STAT_AUTOHALF;
+		}
+		else if (Result == SK_LMODE_STAT_FULL) {
+
+			Result = SK_LMODE_STAT_AUTOFULL;
+		}
+	}
+
+	return (Result);
+}
+
+/*****************************************************************************
+ *
+ * GetVpdKeyArr - Obtain an array of VPD keys
+ *
+ * Description:
+ *	Read the VPD keys and build an array of VPD keys, which are
+ *	easy to access.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK	     Task successfully performed.
+ *	SK_PNMI_ERR_GENERAL  Something went wrong.
+ */
+PNMI_STATIC int GetVpdKeyArr(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+char *pKeyArr,		/* Ptr KeyArray */
+unsigned int KeyArrLen,	/* Length of array in bytes */
+unsigned int *pKeyNo)	/* Number of keys */
+{
+	unsigned int		BufKeysLen = SK_PNMI_VPD_BUFSIZE;
+	char			BufKeys[SK_PNMI_VPD_BUFSIZE];
+	unsigned int		StartOffset;
+	unsigned int		Offset;
+	int			Index;
+	int			Ret;
+
+	SK_MEMSET(pKeyArr, 0, KeyArrLen);
+
+	/* Get VPD key list. */
+	Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen, (int *)pKeyNo);
+
+	if (Ret > 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+			(SK_PNMI_ERR014MSG));
+
+		/* Please read comment in Vpd(). */
+		pAC->Pnmi.VpdKeyReadError = SK_TRUE;
+
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	/* If no keys are available return now. */
+	if (*pKeyNo == 0 || BufKeysLen == 0) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+	/*
+	 * If the key list is too long for us trunc it and give a
+	 * errorlog notification. This case should not happen because
+	 * the maximum number of keys is limited due to RAM limitations.
+	 */
+	if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+			(SK_PNMI_ERR015MSG));
+
+		*pKeyNo = SK_PNMI_VPD_ENTRIES;
+	}
+
+	/* Build an array of fixed string size and copy the keys together */
+	for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen;
+		Offset ++) {
+
+		if (BufKeys[Offset] != 0) {
+			continue;
+		}
+
+		if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
+					   (SK_PNMI_ERR016MSG));
+
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
+			&BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);
+
+		Index ++;
+		StartOffset = Offset + 1;
+	}
+
+	/* Last key not zero terminated? Get it anyway. */
+	if (StartOffset < Offset) {
+
+		SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
+			&BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * SirqUpdate - Let the SIRQ update its internal values
+ *
+ * Description:
+ *	Just to be sure that the SIRQ module holds its internal data
+ *	structures up to date, we send an update event before we make
+ *	any access.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK	     Task successfully performed.
+ *	SK_PNMI_ERR_GENERAL  Something went wrong.
+ */
+PNMI_STATIC int SirqUpdate(
+SK_AC *pAC,	/* Pointer to adapter context */
+SK_IOC IoC)	/* IO context handle */
+{
+	SK_EVPARA	EventParam;
+
+	/* Was the module already updated during the current PNMI call? */
+	if (pAC->Pnmi.SirqUpdatedFlag > 0) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* Send an synchronuous update event to the module. */
+	SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+	if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) {
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG);
+
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+#ifndef SK_NO_RLMT
+/*****************************************************************************
+ *
+ * RlmtUpdate - Let the RLMT update its internal values
+ *
+ * Description:
+ *	Just to be sure that the RLMT module holds its internal data
+ *	structures up to date, we send an update event before we make
+ *	any access.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK	     Task successfully performed.
+ *	SK_PNMI_ERR_GENERAL  Something went wrong.
+ */
+PNMI_STATIC int RlmtUpdate(
+SK_AC *pAC,	/* Pointer to adapter context */
+SK_IOC IoC,	/* IO context handle */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_EVPARA	EventParam;
+
+	/* Was the module already updated during the current PNMI call? */
+	if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* Send an synchronuous update event to the module. */
+	SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+	EventParam.Para32[0] = NetIndex;
+	EventParam.Para32[1] = (SK_U32)-1;
+	if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG);
+
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+#endif
+/*****************************************************************************
+ *
+ * MacUpdate - Force the XMAC to output the current statistic
+ *
+ * Description:
+ *	The XMAC holds its statistic internally. To obtain the current
+ *	values we must send a command so that the statistic data will
+ *	be written to a predefined memory area on the adapter.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK	     Task successfully performed.
+ *	SK_PNMI_ERR_GENERAL  Something went wrong.
+ */
+PNMI_STATIC int MacUpdate(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+unsigned int FirstMac,	/* Index of the first Mac to be updated */
+unsigned int LastMac)	/* Index of the last Mac to be updated */
+{
+	unsigned int	MacIndex;
+
+	/*
+	 * Were the statistics already updated during the
+	 * current PNMI call?
+	 */
+	if (pAC->Pnmi.MacUpdatedFlag > 0) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* Send an update command to all MACs specified. */
+	for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
+
+		/*
+		 * Freeze the current SW counters.
+		 * (This should be done as close as possible to the update of the
+		 * HW counters).
+		 */
+		if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
+			pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
+		}
+
+		/*  Update the HW counter  */
+		if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
+
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	}
+
+	return (SK_PNMI_ERR_OK);
+}
+
+/*****************************************************************************
+ *
+ * GetStatVal - Retrieve an XMAC statistic counter
+ *
+ * Description:
+ *	Retrieves the statistic counter of a virtual or physical port. The
+ *	virtual port is identified by the index 0. It consists of all
+ *	currently active ports. To obtain the counter value for this port
+ *	we must add the statistic counter of all active ports. To grant
+ *	continuous counter values for the virtual port even when port
+ *	switches occur we must additionally add a delta value, which was
+ *	calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event.
+ *
+ * Returns:
+ *	Requested statistic value
+ */
+PNMI_STATIC SK_U64 GetStatVal(
+SK_AC *pAC,					/* Pointer to adapter context */
+SK_IOC IoC,					/* IO context handle */
+unsigned int LogPortIndex,	/* Index of the logical Port to be processed */
+unsigned int StatIndex,		/* Index to statistic value */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	unsigned int	PhysPortIndex;
+	unsigned int	PhysPortMax;
+	SK_U64			Val = 0;
+
+	if (pAC->Pnmi.DualNetActiveFlag) {	/* DualNet mode */
+
+		PhysPortIndex = NetIndex;
+
+		Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
+	}
+	else {	/* SingleNet mode */
+
+		if (LogPortIndex == 0) {
+
+			PhysPortMax = pAC->GIni.GIMacsFound;
+
+			/* Add counter of all active ports. */
+			for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
+				PhysPortIndex ++) {
+
+				if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
+
+					Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
+				}
+			}
+
+			/* Correct value because of port switches. */
+			Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
+		}
+		else {
+			/* Get counter value of physical port. */
+			PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
+
+			Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
+		}
+	}
+	return (Val);
+}
+
+/*****************************************************************************
+ *
+ * GetPhysStatVal - Get counter value for physical port
+ *
+ * Description:
+ *	Builds a 64bit counter value. Except for the octet counters
+ *	the lower 32bit are counted in hardware and the upper 32bit
+ *	in software by monitoring counter overflow interrupts in the
+ *	event handler. To grant continous counter values during XMAC
+ *	resets (caused by a workaround) we must add a delta value.
+ *	The delta was calculated in the event handler when a
+ *	SK_PNMI_EVT_XMAC_RESET was received.
+ *
+ * Returns:
+ *	Counter value
+ */
+PNMI_STATIC SK_U64 GetPhysStatVal(
+SK_AC *pAC,					/* Pointer to adapter context */
+SK_IOC IoC,					/* IO context handle */
+unsigned int PhysPortIndex,	/* Index of the logical Port to be processed */
+unsigned int StatIndex)		/* Index to statistic value */
+{
+	SK_U64	Val = 0;
+	SK_U32	LowVal = 0;
+	SK_U32	HighVal = 0;
+	int		MacType;
+	unsigned int HelpIndex;
+	SK_GEPORT	*pPrt;
+
+	SK_PNMI_PORT	*pPnmiPrt;
+	SK_GEMACFUNC	*pFnMac;
+
+	pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+	MacType = pAC->GIni.GIMacType;
+
+	/* For XMAC, use the frozen SW counters (BufPort) */
+	if (MacType == SK_MAC_XMAC) {
+		pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
+	}
+	else {
+		pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex];
+	}
+
+	pFnMac   = &pAC->GIni.GIFunc;
+
+	switch (StatIndex) {
+
+	case SK_PNMI_HTX:
+		if (MacType == SK_MAC_GMAC) {
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HTX_BROADCAST][MacType].Reg,
+							&LowVal);
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HTX_MULTICAST][MacType].Reg,
+							&HighVal);
+			LowVal += HighVal;
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HTX_UNICAST][MacType].Reg,
+							&HighVal);
+			LowVal += HighVal;
+		}
+		else {
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+										  StatAddr[StatIndex][MacType].Reg,
+										  &LowVal);
+		}
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HRX:
+		if (MacType == SK_MAC_GMAC) {
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HRX_BROADCAST][MacType].Reg,
+							&LowVal);
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HRX_MULTICAST][MacType].Reg,
+							&HighVal);
+			LowVal += HighVal;
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+							StatAddr[SK_PNMI_HRX_UNICAST][MacType].Reg,
+							&HighVal);
+			LowVal += HighVal;
+		}
+		else {
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+										  StatAddr[StatIndex][MacType].Reg,
+										  &LowVal);
+		}
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HTX_OCTET:
+	case SK_PNMI_HRX_OCTET:
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &HighVal);
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex + 1][MacType].Reg,
+									  &LowVal);
+		break;
+
+	case SK_PNMI_HTX_BURST:
+	case SK_PNMI_HTX_EXCESS_DEF:
+	case SK_PNMI_HTX_CARRIER:
+		/* Not supported by GMAC. */
+		if (MacType == SK_MAC_GMAC) {
+			return (Val);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HTX_MACC:
+		/* GMAC only supports PAUSE MAC control frames. */
+		if (MacType == SK_MAC_GMAC) {
+			HelpIndex = SK_PNMI_HTX_PMACC;
+		}
+		else {
+			HelpIndex = StatIndex;
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+								StatAddr[HelpIndex][MacType].Reg,
+								&LowVal);
+
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HTX_COL:
+	case SK_PNMI_HRX_UNDERSIZE:
+		/* Not supported by XMAC. */
+		if (MacType == SK_MAC_XMAC) {
+			return (Val);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HTX_DEFFERAL:
+		/* Not supported by GMAC. */
+		if (MacType == SK_MAC_GMAC) {
+			return (Val);
+		}
+
+		/*
+		 * XMAC counts frames with deferred transmission
+		 * even in full-duplex mode.
+		 *
+		 * In full-duplex mode the counter remains constant!
+		 */
+		if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) ||
+			(pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL)) {
+
+			LowVal = 0;
+			HighVal = 0;
+		}
+		else {
+			/* Otherwise get contents of hardware register. */
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+										  StatAddr[StatIndex][MacType].Reg,
+										  &LowVal);
+			HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		}
+		break;
+
+	case SK_PNMI_HRX_BADOCTET:
+		/* Not supported by XMAC. */
+		if (MacType == SK_MAC_XMAC) {
+			return (Val);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &HighVal);
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex + 1][MacType].Reg,
+									  &LowVal);
+		break;
+
+	case SK_PNMI_HTX_OCTETLOW:
+	case SK_PNMI_HRX_OCTETLOW:
+	case SK_PNMI_HRX_BADOCTETLOW:
+		return (Val);
+
+	case SK_PNMI_HRX_LONGFRAMES:
+		/* For XMAC the SW counter is managed by PNMI. */
+		if (MacType == SK_MAC_XMAC) {
+			return (pPnmiPrt->StatRxLongFrameCts);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HRX_TOO_LONG:
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+								StatAddr[StatIndex][MacType].Reg,
+								&LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+
+		Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
+
+		if (MacType == SK_MAC_GMAC) {
+			/* For GMAC the SW counter is additionally managed by PNMI. */
+			Val += pPnmiPrt->StatRxFrameTooLongCts;
+		}
+		else {
+			/*
+			 * Frames longer than IEEE 802.3 frame max size are counted
+			 * by XMAC in frame_too_long counter even reception of long
+			 * frames was enabled and the frame was correct.
+			 * So correct the value by subtracting RxLongFrame counter.
+			 */
+			Val -= pPnmiPrt->StatRxLongFrameCts;
+		}
+
+		LowVal = (SK_U32)Val;
+		HighVal = (SK_U32)(Val >> 32);
+		break;
+
+	case SK_PNMI_HRX_SHORTS:
+		/* Not supported by GMAC. */
+		if (MacType == SK_MAC_GMAC) {
+
+			/* Instead, SK_PNMI_HRX_UNDERSIZE is used. */
+			Val = GetStatVal(pAC, IoC, PhysPortIndex,
+							   SK_PNMI_HRX_UNDERSIZE, 0);
+			return (Val);
+		}
+
+		/*
+		 * XMAC counts short frame errors even if link down (#10620).
+		 * If the link is down, the counter remains constant.
+		 */
+		if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {
+
+			/* Otherwise get incremental difference. */
+			(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+										  StatAddr[StatIndex][MacType].Reg,
+										  &LowVal);
+			HighVal = pPnmiPrt->CounterHigh[StatIndex];
+
+			Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
+			Val -= pPnmiPrt->RxShortZeroMark;
+
+			LowVal = (SK_U32)Val;
+			HighVal = (SK_U32)(Val >> 32);
+		}
+		break;
+
+	case SK_PNMI_HRX_MACC:
+	case SK_PNMI_HRX_MACC_UNKWN:
+	case SK_PNMI_HRX_BURST:
+	case SK_PNMI_HRX_MISSED:
+	case SK_PNMI_HRX_FRAMING:
+	case SK_PNMI_HRX_CARRIER:
+	case SK_PNMI_HRX_IRLENGTH:
+	case SK_PNMI_HRX_SYMBOL:
+	case SK_PNMI_HRX_CEXT:
+		/* Not supported by GMAC. */
+		if (MacType == SK_MAC_GMAC) {
+			return (Val);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	case SK_PNMI_HRX_PMACC_ERR:
+		/* For GMAC the SW counter is managed by PNMI. */
+		if (MacType == SK_MAC_GMAC) {
+			return (pPnmiPrt->StatRxPMaccErr);
+		}
+
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	/* SW counter managed by PNMI. */
+	case SK_PNMI_HTX_SYNC:
+		LowVal = (SK_U32)pPnmiPrt->StatSyncCts;
+		HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);
+		break;
+
+	/* SW counter managed by PNMI. */
+	case SK_PNMI_HTX_SYNC_OCTET:
+		LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;
+		HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);
+		break;
+
+	case SK_PNMI_HRX_FCS:
+		/*
+		 * Broadcom filters FCS errors and counts them in
+		 * Receive Error Counter register.
+		 */
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+
+	default:
+		(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
+									  StatAddr[StatIndex][MacType].Reg,
+									  &LowVal);
+		HighVal = pPnmiPrt->CounterHigh[StatIndex];
+		break;
+	}
+
+	Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
+
+	/* Correct value because of possible XMAC reset (XMAC Errata #2). */
+	Val += pPnmiPrt->CounterOffset[StatIndex];
+
+	return (Val);
+}
+
+/*****************************************************************************
+ *
+ * ResetCounter - Set all counters and timestamps to zero
+ *
+ * Description:
+ *	Notifies other common modules which store statistic data to
+ *	reset their counters and finally reset our own counters.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void ResetCounter(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+SK_U32 NetIndex)
+{
+	unsigned int	PhysPortIndex;
+	SK_EVPARA	EventParam;
+
+	SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
+
+	/* Notify sensor module. */
+	SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
+#ifndef SK_NO_RLMT
+	/* Notify RLMT module. */
+	EventParam.Para32[0] = NetIndex;
+	EventParam.Para32[1] = (SK_U32)-1;
+	SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
+	EventParam.Para32[1] = 0;
+#endif
+	/* Notify SIRQ module. */
+	SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
+
+	/* Notify CSUM module. */
+#ifdef SK_USE_CSUM
+	EventParam.Para32[0] = NetIndex;
+	EventParam.Para32[1] = (SK_U32)-1;
+	SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS,
+		EventParam);
+#endif /* SK_USE_CSUM */
+
+	/* Clear XMAC statistics. */
+	for (PhysPortIndex = 0; PhysPortIndex <
+		(unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
+
+		(void)pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PhysPortIndex);
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterOffset,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterOffset));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncOctetsCts,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncOctetsCts));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatRxLongFrameCts,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatRxLongFrameCts));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatRxFrameTooLongCts,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatRxFrameTooLongCts));
+
+		SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatRxPMaccErr,
+			0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatRxPMaccErr));
+	}
+
+	/* Clear local statistics. */
+	SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,
+		  sizeof(pAC->Pnmi.VirtualCounterOffset));
+
+	pAC->Pnmi.RlmtChangeCts = 0;
+	pAC->Pnmi.RlmtChangeTime = 0;
+
+	SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
+		sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
+	pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
+	pAC->Pnmi.RlmtChangeEstimate.Estimate = 0;
+	pAC->Pnmi.Port[NetIndex].TxSwQueueMax = 0;
+	pAC->Pnmi.Port[NetIndex].TxRetryCts = 0;
+	pAC->Pnmi.Port[NetIndex].RxIntrCts = 0;
+	pAC->Pnmi.Port[NetIndex].TxIntrCts = 0;
+	pAC->Pnmi.Port[NetIndex].RxNoBufCts = 0;
+	pAC->Pnmi.Port[NetIndex].TxNoBufCts = 0;
+	pAC->Pnmi.Port[NetIndex].TxUsedDescrNo = 0;
+	pAC->Pnmi.Port[NetIndex].RxDeliveredCts = 0;
+	pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts = 0;
+	pAC->Pnmi.Port[NetIndex].ErrRecoveryCts = 0;
+}
+
+/*****************************************************************************
+ *
+ * GetTrapEntry - Get an entry in the trap buffer
+ *
+ * Description:
+ *	The trap buffer stores various events. A user application somehow
+ *	gets notified that an event occurred and retrieves the trap buffer
+ *	contens (or simply polls the buffer). The buffer is organized as
+ *	a ring which stores the newest traps at the beginning. The oldest
+ *	traps are overwritten by the newest ones. Each trap entry has a
+ *	unique number, so that applications may detect new trap entries.
+ *
+ * Returns:
+ *	A pointer to the trap entry
+ */
+PNMI_STATIC char* GetTrapEntry(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_U32 TrapId,		/* SNMP ID of the trap */
+unsigned int Size)	/* Space needed for trap entry */
+{
+	unsigned int	BufPad = pAC->Pnmi.TrapBufPad;
+	unsigned int	BufFree = pAC->Pnmi.TrapBufFree;
+	unsigned int	Beg = pAC->Pnmi.TrapQueueBeg;
+	unsigned int	End = pAC->Pnmi.TrapQueueEnd;
+	char			*pBuf = &pAC->Pnmi.TrapBuf[0];
+	int			Wrap;
+	unsigned int	NeededSpace;
+	unsigned int	EntrySize;
+	SK_U32			Val32;
+	SK_U64			Val64;
+
+	/* Last byte of entry will get a copy of the entry length. */
+	Size ++;
+
+	/* Calculate needed buffer space. */
+	if (Beg >= Size) {
+
+		NeededSpace = Size;
+		Wrap = SK_FALSE;
+	}
+	else {
+		NeededSpace = Beg + Size;
+		Wrap = SK_TRUE;
+	}
+
+	/*
+	 * Check if enough buffer space is provided. Otherwise
+	 * free some entries. Leave one byte space between begin
+	 * and end of buffer to make it possible to detect whether
+	 * the buffer is full or empty.
+	 */
+	while (BufFree < NeededSpace + 1) {
+
+		if (End == 0) {
+
+			End = SK_PNMI_TRAP_QUEUE_LEN;
+		}
+
+		EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1);
+		BufFree += EntrySize;
+		End -= EntrySize;
+#ifdef DEBUG
+		SK_MEMSET(pBuf + End, (char)(-1), EntrySize);
+#endif /* DEBUG */
+		if (End == BufPad) {
+#ifdef DEBUG
+			SK_MEMSET(pBuf, (char)(-1), End);
+#endif /* DEBUG */
+			BufFree += End;
+			End = 0;
+			BufPad = 0;
+		}
+	}
+
+	/*
+	 * Insert new entry as first entry. Newest entries are
+	 * stored at the beginning of the queue.
+	 */
+	if (Wrap) {
+
+		BufPad = Beg;
+		Beg = SK_PNMI_TRAP_QUEUE_LEN - Size;
+	}
+	else {
+		Beg = Beg - Size;
+	}
+	BufFree -= NeededSpace;
+
+	/* Save the current offsets. */
+	pAC->Pnmi.TrapQueueBeg = Beg;
+	pAC->Pnmi.TrapQueueEnd = End;
+	pAC->Pnmi.TrapBufPad = BufPad;
+	pAC->Pnmi.TrapBufFree = BufFree;
+
+	/* Initialize the trap entry. */
+	*(pBuf + Beg + Size - 1) = (char)Size;
+	*(pBuf + Beg) = (char)Size;
+	Val32 = (pAC->Pnmi.TrapUnique) ++;
+	SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32);
+	SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId);
+	Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
+	SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64);
+
+	return (pBuf + Beg);
+}
+
+/*****************************************************************************
+ *
+ * CopyTrapQueue - Copies the trap buffer for the TRAP OID
+ *
+ * Description:
+ *	On a query of the TRAP OID the trap buffer contents will be
+ *	copied continuously to the request buffer, which must be large
+ *	enough. No length check is performed.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void CopyTrapQueue(
+SK_AC *pAC,		/* Pointer to adapter context */
+char *pDstBuf)		/* Buffer to which the queued traps will be copied */
+{
+	unsigned int	BufPad = pAC->Pnmi.TrapBufPad;
+	unsigned int	Trap = pAC->Pnmi.TrapQueueBeg;
+	unsigned int	End = pAC->Pnmi.TrapQueueEnd;
+	char		*pBuf = &pAC->Pnmi.TrapBuf[0];
+	unsigned int	Len;
+	unsigned int	DstOff = 0;
+
+	while (Trap != End) {
+
+		Len = (unsigned int)*(pBuf + Trap);
+
+		/*
+		 * Last byte containing a copy of the length will
+		 * not be copied.
+		 */
+		*(pDstBuf + DstOff) = (char)(Len - 1);
+		SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2);
+		DstOff += Len - 1;
+
+		Trap += Len;
+		if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
+
+			Trap = BufPad;
+		}
+	}
+}
+
+/*****************************************************************************
+ *
+ * GetTrapQueueLen - Get the length of the trap buffer
+ *
+ * Description:
+ *	Evaluates the number of currently stored traps and the needed
+ *	buffer size to retrieve them.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void GetTrapQueueLen(
+SK_AC *pAC,		/* Pointer to adapter context */
+unsigned int *pLen,	/* Length in Bytes of all queued traps */
+unsigned int *pEntries)	/* Returns number of trapes stored in queue */
+{
+	unsigned int	BufPad = pAC->Pnmi.TrapBufPad;
+	unsigned int	Trap = pAC->Pnmi.TrapQueueBeg;
+	unsigned int	End = pAC->Pnmi.TrapQueueEnd;
+	char		*pBuf = &pAC->Pnmi.TrapBuf[0];
+	unsigned int	Len;
+	unsigned int	Entries = 0;
+	unsigned int	TotalLen = 0;
+
+	while (Trap != End) {
+
+		Len = (unsigned int)*(pBuf + Trap);
+		TotalLen += Len - 1;
+		Entries ++;
+
+		Trap += Len;
+		if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
+
+			Trap = BufPad;
+		}
+	}
+
+	*pEntries = Entries;
+	*pLen = TotalLen;
+}
+
+/*****************************************************************************
+ *
+ * QueueSimpleTrap - Store a simple trap to the trap buffer
+ *
+ * Description:
+ *	A simple trap is a trap with now additional data. It consists
+ *	simply of a trap code.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void QueueSimpleTrap(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_U32 TrapId)		/* Type of sensor trap */
+{
+	GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN);
+}
+
+/*****************************************************************************
+ *
+ * QueueSensorTrap - Stores a sensor trap in the trap buffer
+ *
+ * Description:
+ *	Gets an entry in the trap buffer and fills it with sensor related
+ *	data.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void QueueSensorTrap(
+SK_AC *pAC,			/* Pointer to adapter context */
+SK_U32 TrapId,			/* Type of sensor trap */
+unsigned int SensorIndex)	/* Index of sensor which caused the trap */
+{
+	char		*pBuf;
+	unsigned int	Offset;
+	unsigned int	DescrLen;
+	SK_U32		Val32;
+
+	/* Get trap buffer entry. */
+	DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
+
+	pBuf = GetTrapEntry(pAC, TrapId,
+		SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
+	Offset = SK_PNMI_TRAP_SIMPLE_LEN;
+
+	/* Store additionally sensor trap related data. */
+	Val32 = OID_SKGE_SENSOR_INDEX;
+	SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+	*(pBuf + Offset + 4) = 4;
+	Val32 = (SK_U32)SensorIndex;
+	SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
+	Offset += 9;
+
+	Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR;
+	SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+	*(pBuf + Offset + 4) = (char)DescrLen;
+	SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc,
+		DescrLen);
+	Offset += DescrLen + 5;
+
+	Val32 = OID_SKGE_SENSOR_TYPE;
+	SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+	*(pBuf + Offset + 4) = 1;
+	*(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType;
+	Offset += 6;
+
+	Val32 = OID_SKGE_SENSOR_VALUE;
+	SK_PNMI_STORE_U32(pBuf + Offset, Val32);
+	*(pBuf + Offset + 4) = 4;
+	Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue;
+	SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
+}
+
+/*****************************************************************************
+ *
+ * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer
+ *
+ * Description:
+ *	Nothing further to explain.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void QueueRlmtNewMacTrap(
+SK_AC *pAC,		/* Pointer to adapter context */
+unsigned int ActiveMac)	/* Index (0..n) of the currently active port */
+{
+	char	*pBuf;
+	SK_U32	Val32;
+
+	pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
+		SK_PNMI_TRAP_RLMT_CHANGE_LEN);
+
+	Val32 = OID_SKGE_RLMT_PORT_ACTIVE;
+	SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
+	*(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
+	*(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac;
+}
+
+/*****************************************************************************
+ *
+ * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer
+ *
+ * Description:
+ *	Nothing further to explain.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void QueueRlmtPortTrap(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_U32 TrapId,		/* Type of RLMT port trap */
+unsigned int PortIndex)	/* Index of the port, which changed its state */
+{
+	char	*pBuf;
+	SK_U32	Val32;
+
+	pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
+
+	Val32 = OID_SKGE_RLMT_PORT_INDEX;
+	SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
+	*(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
+	*(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex;
+}
+
+/*****************************************************************************
+ *
+ * CopyMac - Copies a MAC address
+ *
+ * Description:
+ *	Nothing further to explain.
+ *
+ * Returns:
+ *	Nothing
+ */
+PNMI_STATIC void CopyMac(
+char		*pDst,	/* Pointer to destination buffer */
+SK_MAC_ADDR *pMac)	/* Pointer of Source */
+{
+	int	i;
+
+	for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
+
+		*(pDst + i) = pMac->a[i];
+	}
+}
+
+#ifdef SK_POWER_MGMT
+/*****************************************************************************
+ *
+ * PowerManagement - OID handler function of PowerManagement OIDs
+ *
+ * Description:
+ *	The code is simple. No description necessary.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                               exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+
+PNMI_STATIC int PowerManagement(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* Get/PreSet/Set action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer to which to mgmt data will be retrieved */
+unsigned int *pLen,	/* On call: buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	int i;
+	unsigned int HwPortIndex;
+	SK_U32	RetCode = SK_PNMI_ERR_GENERAL;
+
+	/* Check instance. We only handle single instance variables. */
+	if ((Instance != (SK_U32)(-1))) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Get hardware port index */
+	HwPortIndex = NetIndex;
+
+	/* Check length. */
+	switch (Id) {
+
+#ifdef SK_POWER_MGMT_EX
+	case OID_PM_PARAMETERS:
+		if (*pLen < sizeof(NDIS_PM_PARAMETERS)) {
+
+			*pLen = sizeof(NDIS_PM_PARAMETERS);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+#endif /* SK_POWER_MGMT_EX */
+
+	case OID_PNP_CAPABILITIES:
+		if (*pLen < sizeof(SK_PNP_CAPABILITIES)) {
+
+			*pLen = sizeof(SK_PNP_CAPABILITIES);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_PNP_SET_POWER:
+	case OID_PNP_QUERY_POWER:
+		if (*pLen < sizeof(SK_DEVICE_POWER_STATE)) {
+
+			*pLen = sizeof(SK_DEVICE_POWER_STATE);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+#ifdef SK_POWER_MGMT_EX
+	case OID_PM_ADD_WOL_PATTERN:
+
+		if (*pLen < sizeof(NDIS_PM_WOL_PATTERN)) {
+
+			*pLen = sizeof(NDIS_PM_WOL_PATTERN);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+	case OID_PM_REMOVE_WOL_PATTERN:
+		if (*pLen < sizeof(ULONG)) {
+
+			*pLen = sizeof(ULONG);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+	case OID_PM_ADD_PROTOCOL_OFFLOAD:
+		if (*pLen < sizeof(NDIS_PM_PROTOCOL_OFFLOAD)) {
+
+			*pLen = sizeof(NDIS_PM_PROTOCOL_OFFLOAD);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+	case OID_PM_REMOVE_PROTOCOL_OFFLOAD:
+		if (*pLen < sizeof(ULONG)) {
+
+			*pLen = sizeof(ULONG);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+#endif /* SK_POWER_MGMT_EX */
+
+	case OID_PNP_ADD_WAKE_UP_PATTERN:
+	case OID_PNP_REMOVE_WAKE_UP_PATTERN:
+		if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) {
+
+			*pLen = sizeof(SK_PM_PACKET_PATTERN);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	case OID_PNP_ENABLE_WAKE_UP:
+		if (*pLen < sizeof(SK_U32)) {
+
+			*pLen = sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+	}
+
+	/* Perform action. */
+	if (Action == SK_PNMI_GET) {
+
+		/* Get value. */
+		switch (Id) {
+
+#ifdef SK_POWER_MGMT_EX
+		case OID_PM_PARAMETERS:
+			SkPowerQueryPmParameters(pAC, IoC, HwPortIndex, pBuf, pLen);
+			break;
+#endif /* SK_POWER_MGMT_EX */
+
+		case OID_PNP_CAPABILITIES:
+			RetCode = SkPowerQueryPnPCapabilities(pAC, IoC, pBuf, pLen);
+			break;
+
+		case OID_PNP_QUERY_POWER:
+			/*
+			 * The Windows DDK describes: An OID_PNP_QUERY_POWER requests
+			 * the miniport to indicate whether it can transition its NIC
+			 * to the low-power state.
+			 * A miniport driver must always return NDIS_STATUS_SUCCESS
+			 * to a query of OID_PNP_QUERY_POWER.
+			 */
+			*pLen = sizeof(SK_DEVICE_POWER_STATE);
+			RetCode = SK_PNMI_ERR_OK;
+			break;
+
+			/*
+			 * NDIS handles these OIDs as write-only.
+			 * So in case of get action the buffer with written length = 0
+			 * is returned.
+			 */
+#ifdef SK_POWER_MGMT_EX
+		case OID_PM_ADD_WOL_PATTERN:
+		case OID_PM_REMOVE_WOL_PATTERN:
+		case OID_PM_ADD_PROTOCOL_OFFLOAD:
+		case OID_PM_REMOVE_PROTOCOL_OFFLOAD:
+#endif /* SK_POWER_MGMT_EX */
+		case OID_PNP_SET_POWER:
+		case OID_PNP_ADD_WAKE_UP_PATTERN:
+		case OID_PNP_REMOVE_WAKE_UP_PATTERN:
+			SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, ("Query of OID 0x%x not supported\n", Id));
+			*pLen = 0;
+			RetCode = SK_PNMI_ERR_NOT_SUPPORTED;
+			break;
+
+		case OID_PNP_ENABLE_WAKE_UP:
+			RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen);
+			break;
+
+		default:
+			RetCode = SK_PNMI_ERR_GENERAL;
+			break;
+		}
+
+		return (RetCode);
+	}
+
+	/* Perform PRESET or SET. */
+
+	/* The POWER module does not support PRESET action. */
+	if (Action == SK_PNMI_PRESET) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	i = HwPortIndex;
+
+	switch (Id) {
+
+#ifdef SK_POWER_MGMT_EX
+	case OID_PM_PARAMETERS:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerSetPMParameters(pAC, IoC, HwPortIndex, pBuf, pLen))) {
+				break;
+			}
+		}
+
+		break;
+#endif /* SK_POWER_MGMT_EX */
+
+	case OID_PNP_SET_POWER:
+		/* Dual net mode? */
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+#ifdef SK_POWER_MGMT_EX
+	case OID_PM_ADD_WOL_PATTERN:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerAddWoLPattern(pAC,IoC,i,pBuf,pLen))) {
+				break;
+			}
+		}
+		break;
+
+#endif /* SK_POWER_MGMT_EX */
+
+	case OID_PNP_ADD_WAKE_UP_PATTERN:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+#ifdef SK_POWER_MGMT_EX
+	case OID_PM_REMOVE_WOL_PATTERN:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerRemoveWolPattern(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+	case OID_PM_ADD_PROTOCOL_OFFLOAD:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerAddProtocolOffload(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+	case OID_PM_REMOVE_PROTOCOL_OFFLOAD:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerRemoveProtocolOffload(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+#endif /* SK_POWER_MGMT_EX */
+
+	case OID_PNP_REMOVE_WAKE_UP_PATTERN:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+	case OID_PNP_ENABLE_WAKE_UP:
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+			if ((RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen))) {
+				break;
+			}
+		}
+		break;
+
+	default:
+		RetCode = SK_PNMI_ERR_READ_ONLY;
+	}
+
+	return (RetCode);
+}
+#endif /* SK_POWER_MGMT */
+
+#ifdef SK_DIAG_SUPPORT
+/*****************************************************************************
+ *
+ * DiagActions - OID handler function of Diagnostic driver
+ *
+ * Description:
+ *	The code is simple. No description necessary.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't exist
+ *                           (e.g. port instance 3 on a two port adapter)
+ */
+
+PNMI_STATIC int DiagActions(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_U32	DiagStatus;
+	SK_U32	RetCode = SK_PNMI_ERR_GENERAL;
+
+	/* Check instance. We only handle single instance variables. */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Check length. */
+	switch (Id) {
+
+	case OID_SKGE_DIAG_MODE:
+		if (*pLen < sizeof(SK_U32)) {
+
+			*pLen = sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, SK_PNMI_ERR040MSG);
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	/* Perform action. */
+	if (Action == SK_PNMI_GET) {
+
+		/* Get value. */
+		switch (Id) {
+
+		case OID_SKGE_DIAG_MODE:
+			DiagStatus = pAC->Pnmi.DiagAttached;
+			SK_PNMI_STORE_U32(pBuf, DiagStatus);
+			*pLen = sizeof(SK_U32);
+			RetCode = SK_PNMI_ERR_OK;
+			break;
+
+		default:
+			*pLen = 0;
+			RetCode = SK_PNMI_ERR_GENERAL;
+			break;
+		}
+		return (RetCode);
+	}
+
+	/* From here SET or PRESET value. */
+
+	/* PRESET value is not supported. */
+	if (Action == SK_PNMI_PRESET) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	/* SET value. */
+	switch (Id) {
+
+		case OID_SKGE_DIAG_MODE:
+			/* Handle the SET. */
+			switch (*pBuf) {
+			/* Attach the DIAG to this adapter. */
+			case SK_DIAG_ATTACHED:
+				/* Check if we come from running. */
+				if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
+
+					RetCode = SkDrvLeaveDiagMode(pAC);
+				}
+				else if (pAC->Pnmi.DiagAttached == SK_DIAG_IDLE) {
+
+					RetCode = SK_PNMI_ERR_OK;
+				}
+				else {
+
+					RetCode = SK_PNMI_ERR_GENERAL;
+				}
+
+				if (RetCode == SK_PNMI_ERR_OK) {
+
+					pAC->Pnmi.DiagAttached = SK_DIAG_ATTACHED;
+				}
+				break;
+
+			/* Enter the DIAG mode in the driver. */
+			case SK_DIAG_RUNNING:
+				RetCode = SK_PNMI_ERR_OK;
+
+				/*
+				 * If DiagAttached is set, we can tell the driver
+				 * to enter the DIAG mode.
+				 */
+				if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {
+					/* If DiagMode is not active, we can enter it. */
+					if (!pAC->DiagModeActive) {
+
+						RetCode = SkDrvEnterDiagMode(pAC);
+					}
+					else {
+
+						RetCode = SK_PNMI_ERR_GENERAL;
+					}
+				}
+				else {
+
+					RetCode = SK_PNMI_ERR_GENERAL;
+				}
+
+				if (RetCode == SK_PNMI_ERR_OK) {
+
+					pAC->Pnmi.DiagAttached = SK_DIAG_RUNNING;
+				}
+				break;
+
+			case SK_DIAG_IDLE:
+				/* Check if we come from running. */
+				if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
+
+					RetCode = SkDrvLeaveDiagMode(pAC);
+				}
+				else if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {
+
+					RetCode = SK_PNMI_ERR_OK;
+				}
+				else {
+
+					RetCode = SK_PNMI_ERR_GENERAL;
+				}
+
+				if (RetCode == SK_PNMI_ERR_OK) {
+
+					pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
+				}
+				break;
+
+			default:
+				RetCode = SK_PNMI_ERR_BAD_VALUE;
+				break;
+			}
+			break;
+
+		default:
+			RetCode = SK_PNMI_ERR_GENERAL;
+	}
+
+	if (RetCode == SK_PNMI_ERR_OK) {
+		*pLen = sizeof(SK_U32);
+	}
+	else {
+
+		*pLen = 0;
+	}
+	return (RetCode);
+}
+#endif /* SK_DIAG_SUPPORT */
+
+/*****************************************************************************
+*
+* VctGetDspLength
+*
+* Description:
+*	Calculates the DSP length
+*
+* Returns:
+ *	Nothing
+*/
+static void VctGetDspLength(
+SK_AC		*pAC,
+SK_IOC		IoC,
+SK_U32		Port,
+SK_PNMI_VCT	*pvctInfo)
+{
+	SK_U8	port_cable_length;
+	SK_U8	len;
+
+	/* Calculate DSP length */
+	if (pAC->GIni.GP[Port].PLinkSpeedUsed != SK_LSPEED_1000MBPS) {
+
+		pvctInfo->CableLen = DSP_CABLE_RANGE_NOT_SUPPORTED;
+		return;
+	}
+
+	port_cable_length = pAC->GIni.GP[Port].PCableLen;
+
+	if (HW_HAS_NEWER_PHY(pAC)) {
+
+		if (port_cable_length < 13) {
+			len = 1;
+		}
+		else if (port_cable_length < 36) {
+			len = 3 * (port_cable_length) - 38;
+		}
+		else if (port_cable_length < 68) {
+			len = port_cable_length + (port_cable_length / 2);
+		}
+		else {
+			len = port_cable_length + 37;
+		}
+
+		if (len <= DSP_CABLE_RANGE_UNDER_50_END) {
+			pvctInfo->CableLen = DSP_CABLE_RANGE_UNDER_50;
+		}
+		else if (len <= DSP_CABLE_RANGE_50_TO_80_END) {
+			pvctInfo->CableLen = DSP_CABLE_RANGE_50_TO_80;
+		}
+		else if (len <= DSP_CABLE_RANGE_80_TO_140_END) {
+			pvctInfo->CableLen = DSP_CABLE_RANGE_80_TO_150;
+		}
+		else {
+			pvctInfo->CableLen = DSP_CABLE_RANGE_ABOVE_140;
+		}
+	}
+	else {
+		pvctInfo->CableLen = port_cable_length;
+	}
+}
+
+/*****************************************************************************
+ *
+ * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT)
+ *
+ * Description:
+ *	The code is simple. No description necessary.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was performed successfully.
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *	                         the correct data (e.g. a 32bit value is
+ *	                         needed, but a 16 bit value was passed).
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter).
+ *	SK_PNMI_ERR_READ_ONLY	 Only the Get action is allowed.
+ *
+ */
+
+PNMI_STATIC int Vct(
+SK_AC *pAC,		/* Pointer to adapter context */
+SK_IOC IoC,		/* IO context handle */
+int Action,		/* GET/PRESET/SET action */
+SK_U32 Id,		/* Object ID that is to be processed */
+char *pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,	/* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,	/* Instance (-1,2..n) that is to be queried */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+	SK_GEPORT	*pPrt;
+	SK_PNMI_VCT	*pVctBackupData;
+	SK_U32		LogPortMax;
+	SK_U32		PhysPortMax;
+	SK_U32		PhysPortIndex;
+	SK_U32		Limit;
+	SK_U32		Offset;
+	SK_U32		RetCode;
+	int			i;
+	SK_EVPARA	Para;
+
+	RetCode = SK_PNMI_ERR_GENERAL;
+
+	/* Calculate the port indexes from the instance. */
+	PhysPortMax = pAC->GIni.GIMacsFound;
+	LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
+
+	/* Dual net mode? */
+	if (pAC->Pnmi.DualNetActiveFlag) {
+		LogPortMax--;
+	}
+
+	if ((Instance != (SK_U32) (-1))) {
+		/*
+		 * Get one instance of that OID, so check the instance range:
+		 * There is no virtual port with an Instance == 1, so we get
+		 * the values from one physical port only.
+		 */
+		if (pAC->Pnmi.DualNetActiveFlag) {
+			PhysPortIndex = NetIndex;
+		}
+		else {
+			if ((Instance < 2) || (Instance > LogPortMax)) {
+				*pLen = 0;
+				return (SK_PNMI_ERR_UNKNOWN_INST);
+			}
+			PhysPortIndex = Instance - 2;
+		}
+		Limit = PhysPortIndex + 1;
+	}
+	else {
+		/*
+		 * Instance == (SK_U32) (-1), so get all instances of that OID.
+		 * There is no virtual port with an Instance == 1, so we get
+		 * the values from all physical ports.
+		 */
+
+		/* DualNet mode */
+		if (pAC->Pnmi.DualNetActiveFlag) {
+			PhysPortIndex = NetIndex;
+			Limit = PhysPortIndex + 1;
+		}
+		/* SingleNet mode */
+		else {
+			PhysPortIndex = 0;
+			Limit = PhysPortMax;
+		}
+	}
+
+	pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+	/* Check MAC type. */
+	if ((Id != OID_SKGE_VCT_CAPABILITIES) &&
+		(pPrt->PhyType != SK_PHY_MARV_COPPER)) {
+		*pLen = 0;
+		return (SK_PNMI_ERR_NOT_SUPPORTED);
+	}
+
+	/* Check action type. */
+	if (Action == SK_PNMI_GET) {
+		/* Check length. */
+		switch (Id) {
+
+		case OID_SKGE_VCT_GET:
+			if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
+				*pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		case OID_SKGE_VCT_STATUS:
+		case OID_SKGE_VCT_CAPABILITIES:
+			if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
+				*pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
+				return (SK_PNMI_ERR_TOO_SHORT);
+			}
+			break;
+
+		default:
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+
+		/* Get value. */
+		Offset = 0;
+		for (; PhysPortIndex < Limit; PhysPortIndex++) {
+
+			pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+			switch (Id) {
+
+			case OID_SKGE_VCT_GET:
+				if (!pPrt->PHWLinkUp &&
+					(pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
+
+					RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
+
+					if (RetCode == 0) {
+
+						/* VCT test is finished, so save the data. */
+						VctGetResults(pAC, IoC, PhysPortIndex);
+
+						Para.Para32[0] = PhysPortIndex;
+						Para.Para32[1] = -1;
+						SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
+
+						/* SkEventDispatcher(pAC, IoC); */
+					}
+				}
+
+				/* Initialize backup data pointer. */
+				pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
+
+				/* Get all results. */
+				CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
+
+				Offset++;
+
+				VctGetDspLength(pAC, IoC, PhysPortIndex, pVctBackupData);
+
+				*(pBuf + Offset) = pVctBackupData->CableLen;
+				Offset++;
+				for (i = 0; i < 4; i++) {
+
+					SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]);
+					Offset += sizeof(SK_U32);
+				}
+				for (i = 0; i < 4; i++) {
+
+					*(pBuf + Offset) = pVctBackupData->MdiPairSts[i];
+					Offset++;
+				}
+
+				RetCode = SK_PNMI_ERR_OK;
+				break;
+
+			case OID_SKGE_VCT_STATUS:
+				CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
+
+				Offset++;
+				RetCode = SK_PNMI_ERR_OK;
+				break;
+
+			case OID_SKGE_VCT_CAPABILITIES:
+				if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
+					*(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED;
+				}
+				else {
+					*(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED_VERSION;
+				}
+				Offset++;
+
+				RetCode = SK_PNMI_ERR_OK;
+				break;
+
+			default:
+				*pLen = 0;
+				return (SK_PNMI_ERR_GENERAL);
+			}
+		} /* for */
+		*pLen = Offset;
+
+		return (RetCode);
+	} /* if SK_PNMI_GET */
+
+	/*
+	 * From here SET or PRESET action. Check if the passed
+	 * buffer length is plausible.
+	 */
+
+	/* Check length. */
+	switch (Id) {
+	case OID_SKGE_VCT_SET:
+		if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
+			*pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);
+			return (SK_PNMI_ERR_TOO_SHORT);
+		}
+		break;
+
+	default:
+		*pLen = 0;
+		return (SK_PNMI_ERR_GENERAL);
+	}
+
+	/* Perform PRESET or SET. */
+
+	/* VCT does not support PRESET action. */
+	if (Action == SK_PNMI_PRESET) {
+
+		return (SK_PNMI_ERR_OK);
+	}
+
+	Offset = 0;
+	for (; PhysPortIndex < Limit; PhysPortIndex++) {
+
+		pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+		switch (Id) {
+		/* Start VCT test */
+		case OID_SKGE_VCT_SET:
+			if (!pPrt->PHWLinkUp) {
+				SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
+
+				RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
+
+				if (RetCode == 0) { /* RetCode: 0 => Start! */
+					pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
+					pAC->Pnmi.VctStatus[PhysPortIndex] &=
+						~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK);
+
+					/* Start VCT timer counter. */
+					SK_MEMSET((char *)&Para, 0, sizeof(Para));
+					Para.Para32[0] = PhysPortIndex;
+					Para.Para32[1] = -1;
+
+					SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
+						SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
+
+					SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
+					RetCode = SK_PNMI_ERR_OK;
+				}
+				else { /* RetCode: 2 => Running! */
+					SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
+					RetCode = SK_PNMI_ERR_OK;
+				}
+			}
+			else { /* RetCode: 4 => Link! */
+				RetCode = 4;
+				SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
+				RetCode = SK_PNMI_ERR_OK;
+			}
+			Offset += sizeof(SK_U32);
+			break;
+
+		default:
+			*pLen = 0;
+			return (SK_PNMI_ERR_GENERAL);
+		}
+	} /* for */
+	*pLen = Offset;
+	return (RetCode);
+
+} /* Vct */
+
+
+/*****************************************************************************
+*
+* VctGetResults
+*
+* Description:
+*	Read and calculate the results
+*
+* Returns:
+ *	Nothing
+*/
+PNMI_STATIC void VctGetResults(
+SK_AC		*pAC,
+SK_IOC		IoC,
+SK_U32		Port)
+{
+	int			i;
+	SK_U8		tmp_u8;
+	SK_U32		tmp_u32;
+	SK_U32		MinCableLen;
+	SK_GEPORT	*pPrt;
+	SK_PNMI_VCT *pVctInfo;
+	int			ChipId;
+
+	pPrt = &pAC->GIni.GP[Port];
+	pVctInfo = &pAC->Pnmi.VctBackup[Port];
+
+	ChipId = pAC->GIni.GIChipId;
+
+	/* Calculate VCT length and status */
+	if (ChipId == CHIP_ID_YUKON_EX || ChipId >= CHIP_ID_YUKON_SUPR) {
+		/*
+		 * For Yukon-Extreme PHY the previous VCT status determination is
+		 * different and therefore the status result from PNMI is not valid.
+		 * Calculate VCT status for each cable pair based on reflection
+		 * amplitude polarity and amplitude value.
+		 */
+		for (i = 0; i < 4; i++) {
+			/* Invalid VCT status for cable pair */
+			if ((pPrt->PMdiPairLen[i]) == 0xff &&
+				(pPrt->PMdiPairSts[i]) == 0xff) {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_TEST_FAIL;
+			}
+			/* No fault reported for cable pair */
+			else if ((pPrt->PMdiPairLen[i]) == 0 &&
+					 (pPrt->PMdiPairSts[i]) == 0) {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_NORMAL_CABLE;
+			}
+			/*
+			 * Positive reflection amplitude polarity and amplitude value
+			 * greater than 40 --> open/broken cable pair.
+			 */
+			else if ((pPrt->PMdiPairSts[i] & 0x80) &&
+					 ((pPrt->PMdiPairSts[i] & 0x7f) > 40)) {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_OPEN_CABLE;
+			}
+			/*
+			 * Negative reflection amplitude polarity and amplitude value
+			 * greater than 40 --> short at same cable pair.
+			 */
+			else if (((pPrt->PMdiPairSts[i] & 0x80) == 0) &&
+					 ((pPrt->PMdiPairSts[i] & 0x7f) > 40)) {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_SHORT_CABLE;
+			}
+			/*
+			 * Positive or negative reflection amplitude polarity and amplitude value
+			 * less than or equal to 40 --> impedance missmatch at same cable pair.
+			 */
+			else {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
+			}
+		}
+	}
+	else {
+		for (i = 0; i < 4; i++) {
+			if ((ChipId == CHIP_ID_YUKON_FE ||
+				 ChipId == CHIP_ID_YUKON_FE_P) && (i > 1)) {
+				pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_NOT_PRESENT;
+			}
+			else {
+				if ((pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) &&
+					(pPrt->PMdiPairLen[i] > 28) && (pPrt->PMdiPairLen[i] < 0xff)) {
+					pVctInfo->MdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
+				}
+				else {
+					pVctInfo->MdiPairSts[i] = pPrt->PMdiPairSts[i];
+				}
+			}
+		}
+	}
+
+	/*
+	 * Calculate length for each cable pair.
+	 * Ignore values <= MinLength, the linear factor is 4/5.
+	 */
+	switch (ChipId) {
+	case CHIP_ID_YUKON_FE:
+		MinCableLen = 25;
+		break;
+	case CHIP_ID_YUKON_FE_P:
+		MinCableLen = 17;
+		break;
+	case CHIP_ID_YUKON_EX:
+	case CHIP_ID_YUKON_SUPR:
+	case CHIP_ID_YUKON_UL_2:
+		MinCableLen = 13;
+		break;
+	case CHIP_ID_YUKON_OPT:
+	case CHIP_ID_YUKON_PRM:
+		MinCableLen = 7;
+		break;
+	default:
+		MinCableLen = 35;
+		break;
+	}
+
+	for (i=0; i<4; i++) {
+		if ((pPrt->PMdiPairLen[i] > (SK_U32)MinCableLen) &&
+			(pPrt->PMdiPairLen[i] < (SK_U32)0xff)) {
+
+			pVctInfo->MdiPairLen[i] = 1000UL *
+				((pPrt->PMdiPairLen[i] - MinCableLen) * 4 / 5);
+		}
+		else {
+			/* No cable or short cable. */
+			pVctInfo->MdiPairLen[i] = 0;
+		}
+	}
+
+	/* Swap pair length and status for Yukon-FE due to HW design issue */
+	if (ChipId  == CHIP_ID_YUKON_FE) {
+
+		tmp_u8 = pVctInfo->MdiPairSts[0];
+		pVctInfo->MdiPairSts[0] = pVctInfo->MdiPairSts[1];
+		pVctInfo->MdiPairSts[1] = tmp_u8;
+
+		tmp_u32 = pVctInfo->MdiPairLen[0];
+		pVctInfo->MdiPairLen[0] = pVctInfo->MdiPairLen[1];
+		pVctInfo->MdiPairLen[1] = tmp_u32;
+	}
+
+	pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING;
+	pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
+	pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_OLD_VCT_DATA;
+
+} /* GetVctResults */
+
+
+PNMI_STATIC void CheckVctStatus(
+SK_AC		*pAC,
+SK_IOC		IoC,
+char		*pBuf,
+SK_U32		Offset,
+SK_U32		PhysPortIndex)
+{
+	SK_GEPORT 	*pPrt;
+	SK_PNMI_VCT	*pVctData;
+	SK_U8		VctStatus;
+	SK_U32		RetCode;
+
+	pPrt = &pAC->GIni.GP[PhysPortIndex];
+
+	pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
+	pVctData->VctStatus = SK_PNMI_VCT_NONE;
+
+	VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex];
+
+	if (!pPrt->PHWLinkUp) {
+
+		/* Was a VCT test ever made before? */
+		if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
+			if (VctStatus & SK_PNMI_VCT_LINK) {
+				pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
+			}
+			else {
+				pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
+			}
+		}
+
+		/* Check VCT test status. */
+		RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
+
+		if (RetCode == 2) { /* VCT test is running. */
+			pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;
+		}
+		else { /* VCT data was copied to pAC here. Check PENDING state. */
+			if (VctStatus & SK_PNMI_VCT_PENDING) {
+				pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
+			}
+		}
+
+		if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
+			pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
+		}
+	}
+	else {
+		/* Was a VCT test ever made before? */
+		if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
+			pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
+			pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
+		}
+
+		/* DSP only valid in 100/1000 modes. */
+		if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
+			pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
+		}
+	}
+} /* CheckVctStatus */
+
+
+/*****************************************************************************
+ *
+ *      SkPnmiGenIoctl - Handles new generic PNMI IOCTL, calls the needed
+ *                       PNMI function depending on the subcommand and
+ *                       returns all data belonging to the complete database
+ *                       or OID request.
+ *
+ * Description:
+ *	Looks up the requested subcommand, calls the corresponding handler
+ *	function and passes all required parameters to it.
+ *	The function is called by the driver. It is needed to handle the new
+ *  generic PNMI IOCTL. This IOCTL is given to the driver and contains both
+ *  the OID and a subcommand to decide what kind of request has to be done.
+ *
+ * Returns:
+ *	SK_PNMI_ERR_OK           The request was successfully performed
+ *	SK_PNMI_ERR_GENERAL      A general severe internal error occurred
+ *	SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to take
+ *	                         the data.
+ *	SK_PNMI_ERR_UNKNOWN_OID  The requested OID is unknown
+ *	SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *	                         adapter.
+ */
+int SkPnmiGenIoctl(
+SK_AC		*pAC,		/* Pointer to adapter context struct */
+SK_IOC		IoC,		/* I/O context */
+void		*pBuf,		/* Buffer used for the management data transfer */
+unsigned int *pLen,		/* Length of buffer */
+SK_U32		NetIndex)	/* NetIndex (0..n), in single net mode always zero */
+{
+SK_I32	Mode;			/* Store value of subcommand. */
+SK_U32	Oid;			/* Store value of OID. */
+int		ReturnCode;		/* Store return value to show status of PNMI action. */
+int 	HeaderLength;	/* Length of desired action plus OID. */
+
+	ReturnCode = SK_PNMI_ERR_GENERAL;
+
+	SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));
+	SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32));
+	HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);
+	*pLen = *pLen - HeaderLength;
+	SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen);
+
+	switch (Mode) {
+	case SK_GET_SINGLE_VAR:
+		ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
+				(char *)pBuf + sizeof(SK_I32), pLen,
+				((SK_U32) (-1)), NetIndex);
+		SK_PNMI_STORE_U32(pBuf, ReturnCode);
+		*pLen = *pLen + sizeof(SK_I32);
+		break;
+	case SK_PRESET_SINGLE_VAR:
+		ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
+				(char *)pBuf + sizeof(SK_I32), pLen,
+				((SK_U32) (-1)), NetIndex);
+		SK_PNMI_STORE_U32(pBuf, ReturnCode);
+		*pLen = *pLen + sizeof(SK_I32);
+		break;
+	case SK_SET_SINGLE_VAR:
+		ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
+				(char *)pBuf + sizeof(SK_I32), pLen,
+				((SK_U32) (-1)), NetIndex);
+		SK_PNMI_STORE_U32(pBuf, ReturnCode);
+		*pLen = *pLen + sizeof(SK_I32);
+		break;
+	case SK_GET_FULL_MIB:
+		ReturnCode = SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex);
+		break;
+	case SK_PRESET_FULL_MIB:
+		ReturnCode = SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex);
+		break;
+	case SK_SET_FULL_MIB:
+		ReturnCode = SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex);
+		break;
+	default:
+		break;
+	}
+
+	return (ReturnCode);
+
+} /* SkGeIocGen */
+
+#ifdef SK_ASF
+/*****************************************************************************
+ *
+ * Asf
+ *
+ * Description:
+ *  The code is simple. No description necessary.
+ *
+ * Returns:
+ *  SK_PNMI_ERR_OK           The request was successfully performed.
+ *  SK_PNMI_ERR_GENERAL      A general severe internal error occurred.
+ *  SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
+ *                           the correct data (e.g. a 32bit value is
+ *                           needed, but a 16 bit value was passed).
+ *  SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
+ *                           exist (e.g. port instance 3 on a two port
+ *                           adapter.
+ */
+
+PNMI_STATIC int Asf(
+SK_AC *pAC,     /* Pointer to adapter context */
+SK_IOC IoC,     /* IO context handle */
+int Action,     /* GET/PRESET/SET action */
+SK_U32 Id,      /* Object ID that is to be processed */
+char *pBuf,     /* Buffer used for the management data transfer */
+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
+SK_U32 Instance,    /* Instance (1..n) that is to be queried or -1 */
+unsigned int TableIndex, /* Index to the Id table */
+SK_U32 NetIndex)    /* NetIndex (0..n), in single net mode always zero */
+{
+	SK_U32  RetCode = SK_PNMI_ERR_GENERAL;
+
+	/*
+	 * Check instance. We only handle single instance variables.
+	 */
+	if (Instance != (SK_U32)(-1) && Instance != 1) {
+
+		*pLen = 0;
+		return (SK_PNMI_ERR_UNKNOWN_INST);
+	}
+
+	/* Perform action. */
+	/* GET value. */
+	if (Action == SK_PNMI_GET) {
+		switch (Id) {
+		case OID_SKGE_ASF:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwGet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#else
+			RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#endif
+			break;
+		default:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwGetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#else
+			RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#endif
+			break;
+		}
+
+		return (RetCode);
+	}
+
+	/* PRESET value. */
+	if (Action == SK_PNMI_PRESET) {
+		switch (Id) {
+		case OID_SKGE_ASF:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#else
+			RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#endif
+			break;
+		default:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#else
+			RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#endif
+			break;
+		}
+	}
+
+	/* SET value. */
+	if (Action == SK_PNMI_SET) {
+		switch (Id) {
+		case OID_SKGE_ASF:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#else
+			RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
+#endif
+			break;
+		default:
+#ifdef SK_USE_FWCOMMON
+			RetCode = FwSetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#else
+			RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *)pBuf, pLen);
+#endif
+			break;
+		}
+	}
+	return (RetCode);
+}
+#endif /* SK_ASF */
diff -ruN linux/drivers/net/sk98lin/skgesirq.c linux-new/drivers/net/sk98lin/skgesirq.c
--- linux/drivers/net/sk98lin/skgesirq.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgesirq.c	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,1938 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/skgesirq.c#12 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #12 $, $Change: 5903 $
+ * Date:	$DateTime: 2011/03/29 15:10:31 $
+ * Purpose:	Special IRQ module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+ *	Special Interrupt handler
+ *
+ *	The following abstract should show how this module is included
+ *	in the driver path:
+ *
+ *	In the ISR of the driver the bits for frame transmission complete and
+ *	for receive complete are checked and handled by the driver itself.
+ *	The bits of the slow path mask are checked after that and then the
+ *	entry into the so-called "slow path" is prepared. It is an implementors
+ *	decision whether this is executed directly or just scheduled by
+ *	disabling the mask. In the interrupt service routine some events may be
+ *	generated, so it would be a good idea to call the EventDispatcher
+ *	right after this ISR.
+ *
+ *	The Interrupt source register of the adapter is NOT read by this module.
+ *	SO if the drivers implementor needs a while loop around the
+ *	slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
+ *	each loop entered.
+ *
+ *	However, the MAC Interrupt status registers are read in a while loop.
+ *
+ */
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#ifndef SK_SLIM
+#ifndef SK_NO_PNMI
+#include "h/skgepnmi.h"		/* PNMI Definitions */
+#endif /* !SK_NO_PNMI */
+#ifndef SK_NO_RLMT
+#include "h/skrlmt.h"		/* RLMT Definitions */
+#endif /* !SK_NO_RLMT */
+#endif
+#include "h/skdrv2nd.h"		/* Adapter Control and Driver specific Def. */
+
+/* local variables ************************************************************/
+
+/* local function prototypes */
+static int	SkGePortCheckUpGmac(SK_AC *, SK_IOC, int, SK_BOOL);
+static void	SkPhyIsrGmac(SK_AC *, SK_IOC, int, SK_U16);
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkHWInitDefSense() - Default Autosensing mode initialization
+ *
+ * Description: sets the PLinkMode for HWInit
+ *
+ * Returns: N/A
+ */
+static void SkHWInitDefSense(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
+		pPrt->PLinkMode = pPrt->PLinkModeConf;
+		return;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("AutoSensing: First mode %d on Port %d\n",
+		(int)SK_LMODE_AUTOFULL, Port));
+
+	pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL;
+
+	return;
+}	/* SkHWInitDefSense */
+#endif
+
+
+/******************************************************************************
+ *
+ *	SkHWLinkDown() - Link Down handling
+ *
+ * Description: handles the hardware link down signal
+ *
+ * Returns: N/A
+ */
+void SkHWLinkDown(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* Disable all MAC interrupts */
+	SkMacIrqDisable(pAC, IoC, Port);
+
+	/* Disable Receiver and Transmitter */
+	SkMacRxTxDisable(pAC, IoC, Port);
+
+#ifndef SK_SLIM
+	/* Init default sense mode */
+	SkHWInitDefSense(pAC, IoC, Port);
+#endif
+
+	if (!pPrt->PHWLinkUp) {
+		return;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Link down Port %d\n", Port));
+
+	/* Set Link to DOWN */
+	pPrt->PHWLinkUp = SK_FALSE;
+	pPrt->PPhyQLink = SK_FALSE;
+
+#ifndef SK_SLIM
+	/* Reset Port stati */
+	pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
+	pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
+	pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED;
+#endif /* !SK_SLIM */
+
+	if (!pAC->GIni.GIDontInitPhy) {
+		/* Re-init PHY */
+		SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
+	}
+
+	/* Do NOT signal to RLMT */
+
+	/* Do NOT start the timer here */
+}	/* SkHWLinkDown */
+
+
+/******************************************************************************
+ *
+ *	SkHWLinkUp() - Link Up handling
+ *
+ * Description: handles the hardware link up signal
+ *
+ * Returns: N/A
+ */
+void SkHWLinkUp(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pPrt->PHWLinkUp) {
+		/* We do NOT need to proceed on active link */
+		return;
+	}
+
+	pPrt->PHWLinkUp = SK_TRUE;
+
+#ifndef SK_SLIM
+	pPrt->PAutoNegFail = SK_FALSE;
+	pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
+
+	if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
+		pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
+		pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
+		/* Link is up and no Auto-negotiation should be done */
+
+		/* Link speed should be the configured one */
+		switch (pPrt->PLinkSpeed) {
+		case SK_LSPEED_AUTO:
+			/* default is 1000 Mbps */
+		case SK_LSPEED_1000MBPS:
+			pPrt->PLinkSpeedUsed = (SK_U8)
+				((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
+				 SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS;
+			break;
+		case SK_LSPEED_100MBPS:
+			pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
+			break;
+		case SK_LSPEED_10MBPS:
+			pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
+			break;
+		}
+
+		/* Set Link Mode Status */
+		pPrt->PLinkModeStatus = (SK_U8)((pPrt->PLinkMode == SK_LMODE_FULL) ?
+			 SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF);
+
+		/* Set Flow Control Status using Flow Control Mode */
+		switch (pPrt->PFlowCtrlMode) {
+
+		case SK_FLOW_MODE_NONE:
+			pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+			break;
+
+		case SK_FLOW_MODE_LOC_SEND:
+			pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
+			break;
+
+		case SK_FLOW_MODE_SYMMETRIC:
+			pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+			break;
+
+		case SK_FLOW_MODE_SYM_OR_REM:
+			pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
+			break;
+
+		default:
+			pPrt->PFlowCtrlStatus = SK_FLOW_STAT_INDETERMINATED;
+			break;
+		}
+#endif /* !SK_SLIM */
+
+		/* enable Rx/Tx */
+		(void)SkMacRxTxEnable(pAC, IoC, Port);
+#ifndef SK_SLIM
+	}
+#endif /* !SK_SLIM */
+}	/* SkHWLinkUp */
+
+
+#ifndef DISABLE_YUKON_I
+/******************************************************************************
+ *
+ *	SkMacParity() - MAC parity workaround
+ *
+ * Description: handles MAC parity errors correctly
+ *
+ * Returns: N/A
+ */
+static void SkMacParity(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_EVPARA	Para;
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	SK_U32		TxMax;		/* Tx Max Size Counter */
+
+	TxMax = 0;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* clear IRQ Tx Parity Error */
+	/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
+	SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)
+		((pAC->GIni.GIChipId == CHIP_ID_YUKON &&
+		 pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
+
+	if (pPrt->PCheckPar) {
+
+		if (Port == MAC_1) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
+		}
+		Para.Para64 = Port;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+
+		Para.Para32[0] = Port;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+		return;
+	}
+
+	/* Check whether frames with a size of 1k were sent */
+	(void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
+
+	if (TxMax > 0) {
+		/* From now on check the parity */
+		pPrt->PCheckPar = SK_TRUE;
+	}
+}	/* SkMacParity */
+
+/******************************************************************************
+ *
+ *	SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon)
+ *
+ * Description: handles all HW Error interrupts
+ *
+ * Returns: N/A
+ */
+static void SkGeYuHwErr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	HwStatus)	/* Interrupt status word */
+{
+	SK_EVPARA	Para;
+	SK_U16		Word;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("HW-Error Status: 0x%08lX\n", HwStatus));
+
+	if ((HwStatus & (IS_IRQ_MST_ERR | IS_IRQ_STAT)) != 0) {
+		/* PCI Errors occurred */
+		if ((HwStatus & IS_IRQ_STAT) != 0) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
+		}
+
+		/* Reset all bits in the PCI STATUS register */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), &Word);
+
+		SK_TST_MODE_ON(IoC);
+		SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
+		SK_TST_MODE_OFF(IoC);
+
+		Para.Para64 = 0;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+	}
+
+	/* This is necessary only for Rx timing measurements */
+	if ((HwStatus & IS_IRQ_TIST_OV) != 0) {
+		/* increment Time Stamp Timer counter (high) */
+#ifndef SK_SLIM
+		pAC->GIni.GITimeStampCnt++;
+#endif
+		/* clear Time Stamp Timer IRQ */
+		SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
+	}
+
+	if ((HwStatus & IS_IRQ_SENSOR) != 0) {
+		/* no sensors on 32-bit Yukon */
+		if (pAC->GIni.GIYukon32Bit) {
+			/* disable HW Error IRQ */
+			pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
+		}
+	}
+
+	if ((HwStatus & IS_RAM_RD_PAR) != 0) {
+
+		SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
+		Para.Para64 = 0;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+	}
+
+	if ((HwStatus & IS_RAM_WR_PAR) != 0) {
+
+		SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
+		Para.Para64 = 0;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+	}
+
+	if ((HwStatus & IS_M1_PAR_ERR) != 0) {
+		SkMacParity(pAC, IoC, MAC_1);
+	}
+
+	if ((HwStatus & IS_M2_PAR_ERR) != 0) {
+		SkMacParity(pAC, IoC, MAC_2);
+	}
+
+	if ((HwStatus & IS_R1_PAR_ERR) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_P);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
+		Para.Para64 = MAC_1;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+
+		Para.Para32[0] = MAC_1;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((HwStatus & IS_R2_PAR_ERR) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
+		Para.Para64 = MAC_2;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+
+		Para.Para32[0] = MAC_2;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+}	/* SkGeYuHwErr */
+#endif /* !DISABLE_YUKON_I */
+
+#ifdef YUK2
+/******************************************************************************
+ *
+ *	SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only)
+ *
+ * Description: handles the HW Error interrupts for a specific port.
+ *
+ * Returns: N/A
+ */
+static void SkYuk2HwPortErr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	HwStatus,	/* Interrupt status word */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_EVPARA	Para;
+	int			Queue;
+
+	if (Port == MAC_2) {
+		HwStatus >>= 8;
+	}
+
+	if ((HwStatus & Y2_HWE_L1_MASK) == 0) {
+		return;
+	}
+
+	if ((HwStatus & Y2_IS_PAR_RD1) != 0) {
+		/* Clear IRQ */
+		SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR);
+
+		if (Port == MAC_1) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG);
+		}
+	}
+
+	if ((HwStatus & Y2_IS_PAR_WR1) != 0) {
+		/* Clear IRQ */
+		SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR);
+
+		if (Port == MAC_1) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG);
+		}
+	}
+
+	if ((HwStatus & Y2_IS_PAR_MAC1) != 0) {
+		/* Clear IRQ */
+		SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
+
+		if (Port == MAC_1) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
+		}
+	}
+
+	if ((HwStatus & Y2_IS_PAR_RX1) != 0) {
+		if (Port == MAC_1) {
+			Queue = Q_R1;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
+		}
+		else {
+			Queue = Q_R2;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
+		}
+		/* Clear IRQ */
+		SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR);
+	}
+
+	if ((HwStatus & Y2_IS_TCP_TXS1) != 0) {
+		if (Port == MAC_1) {
+			Queue = Q_XS1;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG);
+		}
+		else {
+			Queue = Q_XS2;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG);
+		}
+		/* Clear IRQ */
+		SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
+	}
+
+	if ((HwStatus & Y2_IS_TCP_TXA1) != 0) {
+		if (Port == MAC_1) {
+			Queue = Q_XA1;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG);
+		}
+		else {
+			Queue = Q_XA2;
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG);
+		}
+		/* Clear IRQ */
+		SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
+	}
+
+	Para.Para64 = Port;
+	SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+
+	Para.Para32[0] = Port;
+	SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+
+}	/* SkYuk2HwPortErr */
+
+/******************************************************************************
+ *
+ *	SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only)
+ *
+ * Description: handles all HW Error interrupts
+ *
+ * Returns: N/A
+ */
+static void SkYuk2HwErr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	HwStatus)	/* Interrupt status word */
+{
+	SK_EVPARA	Para;
+	SK_U16		Word;
+	SK_U32		DWord;
+	SK_U32		TlpHead[4];
+	int			i;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("HW-Error Status: 0x%08lX\n", HwStatus));
+
+	/* This is necessary only for Rx timing measurements */
+	if ((HwStatus & Y2_IS_TIST_OV) != 0) {
+#ifndef SK_SLIM
+		/* increment Time Stamp Timer counter (high) */
+		pAC->GIni.GITimeStampCnt++;
+#endif
+		/* clear Time Stamp Timer IRQ */
+		SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
+	}
+
+	/* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */
+	if ((HwStatus & Y2_IS_PCI_NEXP) != 0) {
+		/*
+		 * This error is also mapped either to Master Abort (Y2_IS_MST_ERR)
+		 * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there.
+		 * Therefore handle this event just by printing an error log entry.
+		 */
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG);
+	}
+
+	if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
+		/* PCI Errors occurred */
+		if ((HwStatus & Y2_IS_IRQ_STAT) != 0) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
+		}
+		else {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
+		}
+
+		/* Reset all bits in the PCI STATUS register */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), &Word);
+
+		SK_TST_MODE_ON(IoC);
+		SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
+		SK_TST_MODE_OFF(IoC);
+
+		Para.Para64 = 0;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+	}
+
+	/* check for PCI-Express Uncorrectable Error*/
+	if ((HwStatus & Y2_IS_PCI_EXP) != 0) {
+		/*
+		 * On PCI-Express bus bridges are called root complexes (RC).
+		 * PCI-Express errors are recognized by the root complex too,
+		 * which requests the system to handle the problem. After error
+		 * occurence it may be that no access to the adapter may be performed
+		 * any longer.
+		 */
+
+		/* Get uncorrectable error status */
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PEX_UNC_ERR_STAT), &DWord);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+			("PEX Uncorr.Error Status: 0x%08lX\n", DWord));
+
+		/* check for Flow Control Protocol Error (FCPE) */
+		if (DWord == PEX_FLOW_CTRL_P &&
+			/* check if ASPM L1 enabled */
+			(pAC->GIni.GIPexLinkCtrl & PEX_LC_ASPM_LC_L1) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+				("Flow Control Protocol Error (FCPE)\n"));
+		}
+		else if (DWord != PEX_UNSUP_REQ) {
+			/* ignore Unsupported Request Errors */
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG);
+
+			if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
+				/*
+				 * Stop only, if the uncorrectable error is fatal or
+				 * Poisoned TLP occurred
+				 */
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:"));
+
+				for (i = 0; i < 4; i++) {
+					/* get TLP Header from Log Registers */
+					SK_IN32(IoC, PCI_C2(pAC, IoC, PEX_HEADER_LOG + i*4), &TlpHead[i]);
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+						(" 0x%08lX", TlpHead[i]));
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n"));
+
+				/* check for vendor defined broadcast message */
+				if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) {
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+						("Vendor defined broadcast message\n"));
+				}
+				else {
+					Para.Para64 = 0;
+					SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+
+					pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
+					/* Rewrite HW IRQ mask */
+					SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
+				}
+			}
+		}
+
+		/* clear any PEX errors */
+		SK_TST_MODE_ON(IoC);
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PEX_UNC_ERR_STAT), ALL_32_BITS);
+		SK_TST_MODE_OFF(IoC);
+
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PEX_UNC_ERR_STAT), &DWord);
+
+		if ((DWord & PEX_RX_OV) != 0) {
+			/* Dev #4.205 occurred */
+			pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
+
+			pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
+		}
+	}
+
+	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+		SkYuk2HwPortErr(pAC, IoC, HwStatus, i);
+	}
+
+}	/* SkYuk2HwErr */
+#endif /* YUK2 */
+
+/******************************************************************************
+ *
+ *	SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine
+ *
+ * Description: calls the preselected special ISR (slow path)
+ *
+ * Returns: N/A
+ */
+void SkGeSirqIsr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O context */
+SK_U32	Istatus)	/* Interrupt status word */
+{
+	pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus);
+}
+#ifndef DISABLE_YUKON_I
+/******************************************************************************
+ *
+ *	SkGeYuSirqIsr() - Special Interrupt Service Routine
+ *
+ * Description: handles all non data transfer specific interrupts (slow path)
+ *
+ * Returns: N/A
+ */
+void SkGeYuSirqIsr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	Istatus)	/* Interrupt status word */
+{
+	SK_EVPARA	Para;
+	SK_U32		RegVal32;	/* Read register value */
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	SK_U16		PhyInt;
+	int			i;
+	int			Rtv;
+
+	if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
+		/* read the HW Error Interrupt source */
+		SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
+
+		SkGeYuHwErr(pAC, IoC, RegVal32);
+	}
+
+	/*
+	 * Packet Timeout interrupts
+	 */
+	/* Check whether MACs are correctly initialized */
+	if (((Istatus & (IS_PA_TO_RX1 | IS_PA_TO_TX1)) != 0) &&
+		pAC->GIni.GP[MAC_1].PState == SK_PRT_RESET) {
+		/* MAC 1 was not initialized but Packet timeout occurred */
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E004,
+			SKERR_SIRQ_E004MSG);
+	}
+
+	if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
+		pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
+		/* MAC 2 was not initialized but Packet timeout occurred */
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
+			SKERR_SIRQ_E005MSG);
+	}
+
+	if ((Istatus & IS_PA_TO_RX1) != 0) {
+		/* Means network is filling us up */
+		SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E002,
+			SKERR_SIRQ_E002MSG);
+		SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX1);
+	}
+
+	if ((Istatus & IS_PA_TO_RX2) != 0) {
+		/* Means network is filling us up */
+		SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E003,
+			SKERR_SIRQ_E003MSG);
+		SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX2);
+	}
+
+	if ((Istatus & IS_PA_TO_TX1) != 0) {
+
+		pPrt = &pAC->GIni.GP[MAC_1];
+
+		/* May be a normal situation in a server with a slow network */
+		SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
+	}
+
+	if ((Istatus & IS_PA_TO_TX2) != 0) {
+
+		pPrt = &pAC->GIni.GP[MAC_2];
+
+		/* May be a normal situation in a server with a slow network */
+		SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
+	}
+
+	/* Check interrupts of the particular queues */
+	if ((Istatus & IS_R1_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
+			SKERR_SIRQ_E006MSG);
+		Para.Para64 = MAC_1;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_1;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((Istatus & IS_R2_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
+			SKERR_SIRQ_E007MSG);
+		Para.Para64 = MAC_2;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_2;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((Istatus & IS_XS1_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
+			SKERR_SIRQ_E008MSG);
+		Para.Para64 = MAC_1;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_1;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((Istatus & IS_XA1_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
+			SKERR_SIRQ_E009MSG);
+		Para.Para64 = MAC_1;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_1;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((Istatus & IS_XS2_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
+			SKERR_SIRQ_E010MSG);
+		Para.Para64 = MAC_2;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_2;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	if ((Istatus & IS_XA2_C) != 0) {
+		/* Clear IRQ */
+		SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
+			SKERR_SIRQ_E011MSG);
+		Para.Para64 = MAC_2;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+		Para.Para32[0] = MAC_2;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+
+	/* External reg interrupt */
+	if ((Istatus & IS_EXT_REG) != 0) {
+		/* Test IRQs from PHY */
+		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+
+			pPrt = &pAC->GIni.GP[i];
+
+			if (pPrt->PState == SK_PRT_RESET) {
+				continue;
+			}
+
+			/* Read PHY Interrupt Status */
+			Rtv = SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt);
+
+			if (Rtv == 0 && (PhyInt & PHY_M_DEF_MSK) != 0) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+					("Port %d PHY Int: 0x%04X\n", i, PhyInt));
+
+				SkPhyIsrGmac(pAC, IoC, i, PhyInt);
+			}
+		}
+	}
+
+	/* TWSI Ready interrupt */
+	if ((Istatus & IS_I2C_READY) != 0) {
+#ifdef SK_SLIM
+		/* clear TWSI IRQ */
+		SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
+#else /* SK_SLIM */
+		SkI2cIsr(pAC, IoC);
+#endif /* !SK_SLIM */
+	}
+
+	/* SW forced interrupt */
+	if ((Istatus & IS_IRQ_SW) != 0) {
+		/* clear the software IRQ */
+		SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
+	}
+
+	if ((Istatus & IS_LNK_SYNC_M1) != 0) {
+		/*
+		 * We do NOT need the Link Sync interrupt, because it shows
+		 * only a link going down.
+		 */
+		/* clear interrupt */
+		SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ);
+	}
+
+	/* Check MAC after link sync counter */
+	if ((Istatus & IS_MAC1) != 0) {
+		/* IRQ from MAC 1 */
+		SkMacIrq(pAC, IoC, MAC_1);
+	}
+
+	if ((Istatus & IS_LNK_SYNC_M2) != 0) {
+		/*
+		 * We do NOT need the Link Sync interrupt, because it shows
+		 * us only a link going down.
+		 */
+		/* clear interrupt */
+		SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ);
+	}
+
+	/* Check MAC after link sync counter */
+	if ((Istatus & IS_MAC2) != 0) {
+		/* IRQ from MAC 2 */
+		SkMacIrq(pAC, IoC, MAC_2);
+	}
+
+	/* Timer interrupt (served last) */
+	if ((Istatus & IS_TIMINT) != 0) {
+		/* check for HW Errors */
+		if (((Istatus & IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) {
+			/* read the HW Error Interrupt source */
+			SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
+
+			SkGeYuHwErr(pAC, IoC, RegVal32);
+		}
+
+		SkHwtIsr(pAC, IoC);
+	}
+
+}	/* SkGeYuSirqIsr */
+#endif /* !DISABLE_YUKON_I */
+#ifdef YUK2
+/******************************************************************************
+ *
+ *	SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only)
+ *
+ * Description: handles the HW Error interrupts for a specific port.
+ *
+ * Returns: N/A
+ */
+static void SkYuk2PortSirq(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	IStatus,	/* Interrupt status word */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_EVPARA	Para;
+	int			Queue;
+	int			Rtv;
+	SK_U16		PhyInt;
+#ifdef DEBUG
+	SK_U32		Time;
+#endif /* DEBUG */
+
+	if (Port == MAC_2) {
+		IStatus >>= 8;
+	}
+
+	/* Interrupt from PHY */
+	if ((IStatus & Y2_IS_IRQ_PHY1) != 0 &&
+		pAC->GIni.GP[Port].PState != SK_PRT_RESET) {
+		/* Read PHY Interrupt Status */
+		Rtv = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
+
+		if (Rtv == 0 && (PhyInt & PHY_M_DEF_MSK) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+				("Port %d PHY Int: 0x%04X\n", Port, PhyInt));
+
+			SkPhyIsrGmac(pAC, IoC, Port, PhyInt);
+		}
+	}
+
+	if ((IStatus & Y2_IS_PHY_QLNK & pAC->GIni.GIValIrqMask) != 0) {
+
+#if defined(DEBUG) && !defined(SK_SLIM)
+		Time = (SK_U32)SkOsGetTime(pAC) - pAC->GIni.GIPhyInitTime;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("PHY Quick Link IRQ (%lu tics, %u.%u sec)\n", Time,
+			 (unsigned)(Time / SK_TICKS_PER_SEC),
+			 (unsigned)((Time % SK_TICKS_PER_SEC) * 10) / SK_TICKS_PER_SEC));
+#endif /* DEBUG && !SK_SLIM */
+
+		pAC->GIni.GP[Port].PPhyQLink = SK_TRUE;
+
+		/* disable PHY Quick Link */
+		pAC->GIni.GIValIrqMask &= ~Y2_IS_PHY_QLNK;
+
+		SK_OUT32(IoC, B0_IMSK, pAC->GIni.GIValIrqMask);
+
+		/* reset PHY Link Detect */
+		SK_IN16(IoC, PCI_C(pAC, PSM_CONFIG_REG4), &PhyInt);
+
+		SK_TST_MODE_ON(IoC);
+		SK_OUT16(IoC, PCI_C(pAC, PSM_CONFIG_REG4), PhyInt | BIT_0S);
+		SK_TST_MODE_OFF(IoC);
+
+		Para.Para32[0] = Port;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_LINK_UP, Para);
+	}
+
+	/* Interrupt from MAC */
+	if ((IStatus & Y2_IS_IRQ_MAC1) != 0) {
+		SkMacIrq(pAC, IoC, Port);
+	}
+
+	if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) {
+		if ((IStatus & Y2_IS_CHK_RX1) != 0) {
+			if (Port == MAC_1) {
+				Queue = Q_R1;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006,
+					SKERR_SIRQ_E006MSG);
+			}
+			else {
+				Queue = Q_R2;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007,
+					SKERR_SIRQ_E007MSG);
+			}
+			/* Clear IRQ */
+			SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
+		}
+
+		if ((IStatus & Y2_IS_CHK_TXS1) != 0) {
+			if (Port == MAC_1) {
+				Queue = Q_XS1;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008,
+					SKERR_SIRQ_E008MSG);
+			}
+			else {
+				Queue = Q_XS2;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010,
+					SKERR_SIRQ_E010MSG);
+			}
+			/* Clear IRQ */
+			SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
+		}
+
+		if ((IStatus & Y2_IS_CHK_TXA1) != 0) {
+			if (Port == MAC_1) {
+				Queue = Q_XA1;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009,
+					SKERR_SIRQ_E009MSG);
+			}
+			else {
+				Queue = Q_XA2;
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011,
+					SKERR_SIRQ_E011MSG);
+			}
+			/* Clear IRQ */
+			SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
+		}
+
+		Para.Para64 = Port;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+
+		Para.Para32[0] = Port;
+		SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+	}
+}	/* SkYuk2PortSirq */
+#endif /* YUK2 */
+
+/******************************************************************************
+ *
+ *	SkYuk2SirqIsr() - Special Interrupt Service Routine (Yukon-2 only)
+ *
+ * Description: handles all non data transfer specific interrupts (slow path)
+ *
+ * Returns: N/A
+ */
+void SkYuk2SirqIsr(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	Istatus)	/* Interrupt status word */
+{
+#ifdef YUK2
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	SK_EVPARA	Para;
+	SK_U8		Byte;
+	SK_U16		Word;
+	SK_U32		DWord;
+	SK_U32		RegVal32;	/* Read register value */
+
+	pPrt = &pAC->GIni.GP[MAC_1];
+
+	/* HW Error indicated ? */
+	if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
+		/* read the HW Error Interrupt source */
+		SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
+
+		SkYuk2HwErr(pAC, IoC, RegVal32);
+	}
+
+	/* Interrupt from ASF Subsystem */
+	if ((Istatus & Y2_IS_ASF) != 0) {
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+			pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR) {
+			/* clear IRQ */
+			SK_IN32(IoC, HCU_CCSR, &DWord);
+
+			SK_OUT32(IoC, HCU_CCSR, DWord | HCU_CCSR_CLR_IRQ_HOST);
+
+#ifdef USE_HCI2HOST_INT
+			Para.Para64 = 0;
+			SkEventQueue(pAC, SKGE_ASF, 3, Para);
+#endif
+		}
+		else { /* Yukon-2, -EC */
+			/* clear IRQ */
+			/* later on clearing should be done in ASF ISR handler */
+			SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
+
+			SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Byte | (SK_U8)Y2_ASF_CLR_HSTI);
+			/* Call IRQ handler in ASF Module */
+			/* TBD */
+		}
+	}
+
+	/* check IRQ from polling unit */
+	if ((Istatus & Y2_IS_POLL_CHK) != 0) {
+		/* Clear IRQ Check */
+		SK_OUT8(IoC, POLL_CTRL, PC_CLR_IRQ_CHK);
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036,
+			SKERR_SIRQ_E036MSG);
+		Para.Para64 = 0;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+	}
+
+	/* TWSI Ready interrupt */
+	if ((Istatus & Y2_IS_TWSI_RDY) != 0) {
+
+		/* clear TWSI IRQ */
+		SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
+
+		/* TWSI IRQ is Pause Packet IRQ */
+		if (HW_FEATURE(pAC, HWF_NEW_FLOW_CONTROL) &&
+			pPrt->PLinkSpeedUsed == (SK_U8)SK_LSPEED_STAT_1000MBPS) {
+
+			/* get number of Xmitted Pause Packets */
+			(void)SkGmMacStatistic(pAC, IoC, MAC_1, GM_TXF_MPAUSE, &DWord);
+
+			Word = (SK_U16)(DWord - pPrt->PPauseTxCnt);
+
+			/* save the value */
+			pPrt->PPauseTxCnt = DWord;
+
+#ifdef DEBUG
+			if (Word != 1) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+					("Pause Packets ON & OFF, %u\n", Word));
+			}
+#endif /* DEBUG */
+
+			if ((Word % 2) == 1) {
+				/* toggle Pause Packet (On/Off) */
+				pPrt->PPauseFlag ^= SK_TRUE;
+			}
+
+			/* get Rx GMAC FIFO Write Level */
+			SK_IN16(IoC, RX_GMF_WLEV, &Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+				("Pause Packet IRQ, Level: 0x%03X, Cnt = %u, Pause %s\n",
+				 Word, DWord, pPrt->PPauseFlag ? "ON" : "off"));
+
+			if (pPrt->PPauseFlag) {
+				/* check if a stopped 30ms timer IRQ is pending */
+				if ((Istatus & Y2_IS_TIMINT) != 0) {
+					/* clear timer IRQ */
+					SK_OUT8(IoC, B2_TI_CTRL, TIM_CLR_IRQ);
+
+					/* to avoid handling this timer IRQ */
+					Istatus &= ~Y2_IS_TIMINT;
+				}
+
+				if (Word > (SK_U16)SK_ECU_LLPP) {
+					/* start a 30 ms timer */
+					Para.Para32[0] = 0;
+					SkTimerStart(pAC, IoC, &pPrt->PPauseTimer,
+						SK_PAUSE_PKT_TIME, SKGE_HWAC, SK_HWEV_PAUSE_PACKET,
+						Para);
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+						("start timer\n"));
+				}
+			}
+			else if (pPrt->PPauseTimer.TmActive) {
+				/* stop the 30 ms timer */
+				SkTimerStop(pAC, IoC, &pPrt->PPauseTimer);
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+					("stop timer\n"));
+			}
+		}
+#ifndef SK_SLIM
+		else {
+			SkI2cIsr(pAC, IoC);
+		}
+#endif
+	}
+
+	/* SW forced interrupt */
+	if ((Istatus & Y2_IS_IRQ_SW) != 0) {
+		/* clear the software IRQ */
+		SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
+	}
+
+	if ((Istatus & (Y2_IS_L1_MASK | Y2_IS_PHY_QLNK)) != 0) {
+		/* IRQ from 1st port */
+		SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1);
+	}
+
+	if ((Istatus & Y2_IS_L2_MASK & pAC->GIni.GIValIrqMask) != 0) {
+		/* IRQ from 2nd port */
+		if (pAC->GIni.GIMacsFound == 1) {
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E037, SKERR_SIRQ_E037MSG);
+			Para.Para64 = 0;
+			SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
+
+			return;
+		}
+
+		SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2);
+	}
+
+	/* Timer interrupt (served last) */
+	if ((Istatus & Y2_IS_TIMINT) != 0) {
+
+		if (((Istatus & Y2_IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) {
+			/* read the HW Error Interrupt source */
+			SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
+
+			/* otherwise we would generate error log entries periodically */
+			RegVal32 &= pAC->GIni.GIValHwIrqMask;
+
+			if (RegVal32 != 0) {
+				SkYuk2HwErr(pAC, IoC, RegVal32);
+			}
+		}
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+			("Timer Int: 0x%08lX\n", Istatus));
+
+		SkHwtIsr(pAC, IoC);
+	}
+#endif /* YUK2 */
+
+}	/* SkYuk2SirqIsr */
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUp() - Check if the link is up
+ *
+ * return:
+ *	0	o.k. nothing needed
+ *	1	Restart needed on this port
+ *	2	Link came up
+ */
+static int SkGePortCheckUp(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	SK_BOOL		AutoNeg;	/* Is Auto-negotiation used ? */
+	int			Rtv;		/* Return value */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
+			  pPrt->PLinkMode != SK_LMODE_FULL;
+
+	Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg);
+
+	return(Rtv);
+}	/* SkGePortCheckUp */
+
+
+/******************************************************************************
+ *
+ * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY
+ *
+ * return:
+ *	0	o.k. nothing needed
+ *	1	Restart needed on this port
+ *	2	Link came up
+ */
+static int SkGePortCheckUpGmac(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL	AutoNeg)	/* Is Auto-negotiation used ? */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	int			Done;
+	int			ChipId;
+	SK_U16		PhyStat;	/* PHY Status */
+	SK_U16		PhySpecStat;/* PHY Specific Status */
+	SK_U16		ResAb;		/* Master/Slave resolution */
+	SK_U16		Word;		/* I/O helper */
+	SK_U32		Val32;
+
+#ifndef SK_SLIM
+	SK_EVPARA	Para;
+	int			i;
+	SK_U16		DspOffs;	/* DSP Register Offset */
+	SK_U16		DspCtrl;	/* DSP Control Value */
+	SK_U16		DspIncr;	/* Increment to access MDI pair */
+#ifdef DEBUG
+	SK_U16		LinkPartAb;	/* Link Partner Ability */
+#endif /* DEBUG */
+#endif /* !SK_SLIM */
+
+#ifdef xDEBUG
+	SK_U64	StartTime;
+#endif /* DEBUG */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	ChipId = pAC->GIni.GIChipId;
+
+	if (pPrt->PHWLinkUp) {
+		/* check for PHY status only in newer chips */
+		if (ChipId >= CHIP_ID_YUKON_FE_P) {
+			/* check for link through GPHY Control */
+			SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &Val32);
+
+			if ((Val32 & GPC_PHY_LINK_UP) == 0) {
+				/* Link is down */
+				return(SK_HW_PS_RESTART);
+			}
+		}
+
+		/* don't poll PHY register */
+		return(SK_HW_PS_NONE);
+	}
+
+	/* Read PHY Status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
+
+	SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
+
+	if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Phy1000BT: 0x%04X, ", ResAb));
+
+		if ((ResAb & PHY_B_1000S_MSF) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
+
+			pPrt->PAutoNegFail = SK_TRUE;
+			pPrt->PMSStatus = SK_MS_STAT_FAULT;
+
+			return(SK_HW_PS_RESTART);
+		}
+	}
+
+	/* Read PHY Specific Status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PhySpecStat: 0x%04X\n", PhySpecStat));
+
+#if defined(DEBUG) && !defined(SK_SLIM)
+	/* Read PHY Auto-Negotiation Expansion */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb);
+
+	if ((LinkPartAb & PHY_ANE_RX_PG) != 0 ||
+		(PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
+		/* Read PHY Next Page Link Partner */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Page received, NextPage: 0x%04X\n", Word));
+	}
+#endif /* DEBUG && !SK_SLIM */
+
+	if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
+		/* Link down */
+		return(SK_HW_PS_NONE);
+	}
+
+	if (pAC->GIni.GICopperType) {
+
+#if defined(DEBUG) && !defined(SK_SLIM)
+		if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Link Partner is not AN able, AN Exp.: 0x%04X\n", Word));
+		}
+		else if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0 &&
+				 (ResAb & PHY_B_1000S_LP_FD) == 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Link Partner is not capable of 1000FD\n"));
+		}
+
+		if ((LinkPartAb & PHY_ANE_PAR_DF) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Parallel Detection Fault, AN Exp.: 0x%04X\n", Word));
+		}
+#endif /* DEBUG && !SK_SLIM */
+
+		/* check only Gigabit adapters */
+		if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+			/* check for 2 pair downshift */
+			if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) {
+#ifndef SK_SLIM
+				/* Downshift detected */
+				Para.Para64 = Port;
+				SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat));
+
+				SK_ERR_LOG(pAC, SK_ERRCL_INFO, SKERR_SIRQ_E025,
+					SKERR_SIRQ_E025MSG);
+#endif /* !SK_SLIM */
+
+				if (ChipId == CHIP_ID_YUKON_PRM) {
+					/* read General Purpose Status */
+					GM_IN16(IoC, Port, GM_GP_STAT, &Word);
+
+					if ((Word & GM_GPSR_GIG_SPEED) != 0) {
+						SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+							("MAC speed mismatch, GPSR=0x%04X\n", Word));
+
+						/* read General Purpose Control */
+						GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
+
+						Word &= ~GM_GPCR_GIGS_ENA;
+						Word |= GM_GPCR_SPEED_100 | GM_GPCR_AU_SPD_DIS;
+
+						/* change General Purpose Control */
+						GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
+					}
+				}
+			}
+
+			pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
+				SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
+		}
+
+#ifndef SK_SLIM
+		if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat));
+		}
+
+		if (HW_HAS_NEWER_PHY(pAC)) {
+			/* on PHY 88E1112 cable length is in Reg. 26, Page 5 */
+			if (ChipId == CHIP_ID_YUKON_XL) {
+#ifdef XXX
+				/* select page 5 to access VCT DSP distance register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
+
+				/* get VCT DSP distance */
+				SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat);
+
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+
+				pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK);
+#endif /* XXX */
+				DspOffs = 29;
+				DspCtrl = 0x8754;
+				DspIncr = 0x1000;
+			}
+			else {
+				if (ChipId <= CHIP_ID_YUKON_UL_2) {
+					/* PHY 88E1149R */
+					DspOffs = 19;
+					DspCtrl = 0x1018;
+				}
+				else {
+					/* PHY 88E1240/88E1340 */
+					DspOffs = 16;
+					DspCtrl = 0x1118;
+				}
+				DspIncr = 0x0001;
+
+				/* select page 0xff to access VCT DSP distance register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00ff);
+			}
+
+			for (Word = 0, i = 0; i < 4; i++) {
+				/* select register for MDI pair 0..3 */
+				SkGmPhyWrite(pAC, IoC, Port, DspOffs, DspCtrl + i * DspIncr);
+
+				/* get length for MDI pair 0..3 */
+				SkGmPhyRead(pAC, IoC, Port, DspOffs + 2, &PhySpecStat);
+
+				Word += PhySpecStat;
+			}
+
+			pPrt->PCableLen = Word / 4;	/* calculate the average */
+
+			/* set page register back to 0 */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+		}
+		else {	/* CHIP_ID_YUKON || CHIP_ID_YUKON_LITE || CHIP_ID_YUKON_EC */
+			/* on these PHYs the rough estimated cable length is in Reg. 17 */
+			pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
+		}
+#endif /* !SK_SLIM */
+	}
+
+#ifdef xDEBUG
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("LinkUp Port %d, PHY register dump: 0x%04X\n", Port));
+
+	for (i = 0; i < PHY_MARV_PAGE_ADDR; i++) {
+		/* dump all PHY register */
+		SkGmPhyRead(pAC, IoC, Port, i, &Word);
+	}
+
+	StartTime = SkOsGetTime(pAC);
+
+	while (SkOsGetTime(pAC) - StartTime < SK_TICKS_PER_SEC / 2) {
+		/* dummy PHY read */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_STATUS), &Word);
+	}
+#endif /* DEBUG */
+
+	if (AutoNeg) {
+		/* Auto-Negotiation Complete ? */
+		if ((PhyStat & PHY_ST_AN_OVER) != 0) {
+
+			SkHWLinkUp(pAC, IoC, Port);
+
+			Done = SkMacAutoNegDone(pAC, IoC, Port);
+
+			return((Done != SK_AND_OK) ? SK_HW_PS_RESTART : SK_HW_PS_LINK);
+		}
+
+		return(SK_HW_PS_NONE);
+	}
+
+	/* No Auto-Negotiation */
+#if defined(DEBUG) && !defined(SK_SLIM)
+	if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("ERROR: LiPa auto detected on port %d\n", Port));
+	}
+#endif /* DEBUG && !SK_SLIM */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("Link sync, Port %d\n", Port));
+
+	SkHWLinkUp(pAC, IoC, Port);
+
+	return(SK_HW_PS_LINK);
+}	/* SkGePortCheckUpGmac */
+
+
+/******************************************************************************
+ *
+ *	SkGeSirqEvent() - Event Service Routine
+ *
+ * Description:
+ *
+ * Notes:
+ */
+int SkGeSirqEvent(
+SK_AC		*pAC,		/* Adapter Context */
+SK_IOC		IoC,		/* I/O Context */
+SK_U32		Event,		/* Module specific Event */
+SK_EVPARA	Para)		/* Event specific Parameter */
+{
+	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
+	int			Port;
+	SK_U16		Word;
+	SK_U32		Val32;
+	int			PortStat;
+	SK_BOOL		LinkUpFlag;
+#ifndef SK_SLIM
+	SK_U8		Val8;
+#endif
+
+	Port = (int)Para.Para32[0];
+	pPrt = &pAC->GIni.GP[Port];
+
+	LinkUpFlag = SK_FALSE;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("SIRQ HW Event: %u\n", Event));
+
+	switch (Event) {
+	case SK_HWEV_WATIM:
+		if (pPrt->PState == SK_PRT_RESET) {
+
+			PortStat = SK_HW_PS_NONE;
+		}
+		else {
+			/* Check whether port came up */
+			PortStat = SkGePortCheckUp(pAC, IoC, Port);
+		}
+
+		switch (PortStat) {
+		case SK_HW_PS_RESTART:
+			if (pPrt->PHWLinkUp) {
+				/* Set Link to down */
+				SkHWLinkDown(pAC, IoC, Port);
+
+				/*
+				 * Signal directly to RLMT to ensure correct
+				 * sequence of SWITCH and RESET event.
+				 */
+				SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+			}
+
+			/* Restart needed */
+			SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
+			break;
+
+		case SK_HW_PS_LINK:
+			/* Signal to RLMT */
+			SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
+			break;
+		}
+
+		/* Start again the check timer */
+		if (pPrt->PHWLinkUp) {
+
+			Val32 = SK_WA_ACT_TIME;
+
+			if (pAC->GIni.GIChipId == CHIP_ID_YUKON_PRM) {
+				/* reduce check timer */
+				Val32 /= 2;
+			}
+		}
+		else {
+			Val32 = SK_WA_INA_TIME * 5;
+		}
+		/* Start workaround Errata #2 timer */
+		SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32,
+			SKGE_HWAC, SK_HWEV_WATIM, Para);
+
+		break;
+
+	case SK_HWEV_PORT_START:
+
+#ifndef SK_SLIM
+		if (pAC->GIni.GIDontInitPhy) {
+
+#ifdef XXX
+			PortStat = SkGePortCheckUp(pAC, IoC, Port);
+
+			if (PortStat == SK_HW_PS_LINK) {
+				/* Link is already up */
+				LinkUpFlag = SK_TRUE;
+			}
+#endif /* XXX */
+
+			/* check for link through GPHY Control */
+			SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &Val32);
+
+			if ((Val32 & GPC_PHY_LINK_UP) != 0) {
+				/* Link is already up */
+				LinkUpFlag = SK_TRUE;
+			}
+			else {
+				/* reset this flag to allow PHY init */
+				pAC->GIni.GIDontInitPhy = SK_FALSE;
+			}
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SK_HWEV_PORT_START: Link is %s\n",
+				 LinkUpFlag ? "Up" : "Down"));
+		}
+#endif /* !SK_SLIM */
+
+		if (!LinkUpFlag) {
+#ifndef SK_SLIM
+			if (pPrt->PHWLinkUp) {
+				/*
+				 * Signal directly to RLMT to ensure correct
+				 * sequence of SWITCH and RESET event.
+				 */
+				SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+			}
+#endif /* !SK_SLIM */
+
+			SkHWLinkDown(pAC, IoC, Port);
+		}
+
+		/* Schedule Port RESET */
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
+
+		/* Start workaround Errata #2 timer */
+		SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
+			SKGE_HWAC, SK_HWEV_WATIM, Para);
+
+		break;
+
+	case SK_HWEV_PORT_STOP:
+#ifndef SK_SLIM
+		if (pPrt->PHWLinkUp) {
+			/*
+			 * Signal directly to RLMT to ensure correct
+			 * sequence of SWITCH and RESET event.
+			 */
+			SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
+		}
+#endif /* !SK_SLIM */
+
+		/* Stop Workaround Timer */
+		SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
+
+		SkHWLinkDown(pAC, IoC, Port);
+		break;
+
+#ifndef SK_SLIM
+	case SK_HWEV_UPDATE_STAT:
+		/* We do NOT need to update any statistics */
+		break;
+
+	case SK_HWEV_CLEAR_STAT:
+		/* We do NOT need to clear any statistics */
+		break;
+
+	case SK_HWEV_SET_LMODE:
+		Val8 = (SK_U8)Para.Para32[1];
+
+		if (pPrt->PLinkModeConf != Val8) {
+			/* Set New link mode */
+			pPrt->PLinkModeConf = Val8;
+			/* Restart Port */
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+		}
+		break;
+
+	case SK_HWEV_SET_FLOWMODE:
+		Val8 = (SK_U8)Para.Para32[1];
+
+		if (pPrt->PFlowCtrlMode != Val8) {
+			/* Set New Flow Control mode */
+			pPrt->PFlowCtrlMode = Val8;
+			/* Restart Port */
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+		}
+		break;
+
+	case SK_HWEV_SET_ROLE:
+		/* not possible for fiber */
+		if (!pAC->GIni.GICopperType) {
+			break;
+		}
+
+		Val8 = (SK_U8)Para.Para32[1];
+
+		if (pPrt->PMSMode != Val8) {
+			/* Set New Role (Master/Slave) mode */
+			pPrt->PMSMode = Val8;
+			/* Restart Port */
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+		}
+		break;
+
+	case SK_HWEV_SET_SPEED:
+		if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
+			break;
+		}
+
+		Val8 = (SK_U8)Para.Para32[1];
+
+		if (pPrt->PLinkSpeed != Val8) {
+			/* Set New Speed parameter */
+			pPrt->PLinkSpeed = Val8;
+			/* Restart Port */
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para);
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
+		}
+		break;
+#endif /* !SK_SLIM */
+
+	case SK_HWEV_PAUSE_PACKET:
+		/* get Rx GMAC FIFO Write Level */
+		SK_IN16(IoC, RX_GMF_WLEV, &Word);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Rx GMAC FIFO Level: 0x%03X\n", Word));
+
+		if (Word > (SK_U16)SK_ECU_LLPP) {
+			/* to signal that a Pause ON Packet was sent */
+			pPrt->PPauseFlag = SK_FALSE;
+
+			/* send one Pause Packet */
+			GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
+
+			/* this will generate also a Pause Packet IRQ */
+			GM_OUT16(IoC, Port, GM_GP_CTRL, Word | BIT_15S);
+
+			/* clear bit 15 to be able to re-send one Pause Packet */
+			GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Send a Pause Packet\n"));
+		}
+
+		break;
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
+		break;
+	}
+
+	return(0);
+}	/* SkGeSirqEvent */
+
+
+/******************************************************************************
+ *
+ *	SkPhyIsrGmac() - PHY interrupt service routine
+ *
+ * Description: handles all interrupts from Marvell PHY
+ *
+ * Returns: N/A
+ */
+static void SkPhyIsrGmac(
+SK_AC		*pAC,		/* Adapter Context */
+SK_IOC		IoC,		/* I/O Context */
+int			Port,		/* Port Index (MAC_1 + n) */
+SK_U16		IStatus)	/* Interrupt Status */
+{
+	SK_GEPORT	*pPrt;	/* GIni Port struct pointer */
+	SK_EVPARA	Para;
+#ifdef xDEBUG
+	int		i;
+	SK_U16		Word;
+	SK_U32		DWord;
+#endif /* DEBUG */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus));
+
+	if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) {
+
+		Para.Para32[0] = (SK_U32)Port;
+
+		if (pPrt->PHWLinkUp) {
+
+#ifdef xDEBUG
+			/* read the GMAC Interrupt source register */
+			SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("GmacIrqSrc: 0x%02X\n", Word));
+
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Link Status changed, PhySpecStat: 0x%04X, ", Word));
+
+			if (Word != 0 && (IStatus & PHY_M_IS_SYMB_ERROR) != 0) {
+				/* read all MIB Counters */
+				for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
+					GM_IN32(IoC, Port, GM_MIB_CNT_BASE + 8*i, &DWord);
+
+					SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+						("MIB Addr 0x%04X: 0x%08lX\n",
+						BASE_GMAC_1 + GM_MIB_CNT_BASE + 8*i, DWord));
+				}
+			}
+#endif /* DEBUG */
+
+			SkHWLinkDown(pAC, IoC, Port);
+
+#ifdef XXX
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("AutoNeg.Adv: 0x%04X\n", Word));
+
+			/* Set Auto-negotiation advertisement */
+			if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE &&
+				pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
+				/* restore Asymmetric Pause bit */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
+					(SK_U16)(Word | PHY_M_AN_ASP));
+			}
+#endif /* XXX */
+
+			/* Signal to RLMT */
+			SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
+		}
+		else {
+			if ((IStatus & PHY_M_IS_AN_COMPL) != 0) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Auto-Negotiation completed\n"));
+			}
+
+			if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Link Speed changed\n"));
+			}
+
+			/* trigger SkGePortCheckUp */
+			SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para);
+		}
+	}
+
+	if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
+		/* the copper PHY makes 1 retry */
+		if (pAC->GIni.GICopperType) {
+			/* not logged as error, it might be the first attempt */
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Auto-Negotiation Error\n"));
+
+#ifndef SK_SLIM
+			/*
+			 * #979 Workaround for magnetics with incorrect inductivity.
+			 *
+			 * The issue happens with 100Mbps and auto-negotiation only.
+			 * The specificity of the issue is that a 100Mbit link cannot be
+			 * established although speed and duplex mode can be exchanged during
+			 * auto-negotiation process.
+			 * The workaround forces a good link. It is only executed if an
+			 * auto-negotiation error occurs and next pages have already been
+			 * exchanged. If a workaround is executed only a 100Mbps HD mode is
+			 * establised.
+			 */
+			if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+				(IStatus & PHY_M_IS_AN_PR) != 0) {
+				/* apply workaround for 100M Link */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x0180);
+			}
+#endif /* !SK_SLIM */
+		}
+		else {
+			/* Auto-Negotiation Error */
+			SK_ERR_LOG(pAC, SK_ERRCL_INFO, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
+		}
+	}
+
+	if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
+		/* FIFO Overflow/Underrun Error */
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
+	}
+
+}	/* SkPhyIsrGmac */
+
+/* End of File */
+
diff -ruN linux/drivers/net/sk98lin/skgespilole.c linux-new/drivers/net/sk98lin/skgespilole.c
--- linux/drivers/net/sk98lin/skgespilole.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skgespilole.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,62 @@
+/******************************************************************************
+ *
+ * Name:	skspilole.c
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools
+ * Purpose:	Contains Low Level Functions for the integration of the skspi.c module
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *	Server Adapters.
+ *
+ *	Address all question to: gr-msgg-linux@marvell.com
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ *****************************************************************************/
+
+static const char SysKonnectFileId[] =
+	"@(#) $Id: skgespilole.c,v 1.1.2.2 2007/11/20 10:22:20 mlindner Exp $ (C) Marvell.";
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+int spi_timer(SK_AC *pAC, unsigned int t)
+{
+	if (t) {
+		pAC->TimeBuf = SkOsGetTime(pAC)+(SK_U64)t*SK_TICKS_PER_SEC;
+	} else {
+		if (pAC->TimeBuf <= SkOsGetTime(pAC)) {
+			return(1);
+		}
+	}
+
+	return(0);
+}
+
+/*  dummies */
+void fl_print(char *msg, ...)
+{
+}
+
+unsigned char *spi_malloc( unsigned short size )
+{
+	return(kmalloc(size,GFP_KERNEL));
+}
+
+void spi_free( unsigned char *buf )
+{
+	kfree(buf);
+}
+
diff -ruN linux/drivers/net/sk98lin/sklm80.c linux-new/drivers/net/sk98lin/sklm80.c
--- linux/drivers/net/sk98lin/sklm80.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sklm80.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/twsi/V4/sklm80.c#4 $
+ * Project:	Gigabit Ethernet Adapters, TWSI-Module
+ * Version:	$Revision: #4 $, $Change: 4277 $
+ * Date:	$DateTime: 2010/11/05 10:41:17 $
+ * Purpose:	Functions to access Voltage and Temperature Sensor (LM80)
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+	LM80 functions
+*/
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#include "h/lm80.h"
+#include "h/skdrv2nd.h"		/* Adapter Control- and Driver specific Def. */
+
+#ifdef SK_DIAG
+#define BREAK_OR_WAIT(pAC, IoC, Event)	SkI2cWait(pAC, IoC, Event)
+#else  /* nSK_DIAG */
+#define BREAK_OR_WAIT(pAC, IoC, Event)	break
+#endif /* nSK_DIAG */
+
+#ifdef SK_DIAG
+/*
+ * read the register 'Reg' from the device 'Dev'
+ *
+ * return	read error	-1
+ *		success		the read value
+ */
+int	SkLm80RcvReg(
+SK_IOC	IoC,		/* Adapter Context */
+int		Dev,		/* I2C device address */
+int		Reg)		/* register to read */
+{
+	int	Val = 0;
+	int	TempExt;
+
+	/* Signal device number */
+	if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) {
+		return(-1);
+	}
+
+	if (SkI2cSndByte(IoC, Reg)) {
+		return(-1);
+	}
+
+	/* repeat start */
+	if (SkI2cSndDev(IoC, Dev, I2C_READ)) {
+		return(-1);
+	}
+
+	switch (Reg) {
+	case LM80_TEMP_IN:
+		Val = (int)SkI2cRcvByte(IoC, 1);
+
+		/* First: correct the value: it might be negative */
+		if ((Val & 0x80) != 0) {
+			/* Value is negative */
+			Val = Val - 256;
+		}
+		Val = Val * SK_LM80_TEMP_LSB;
+		SkI2cStop(IoC);
+
+		TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL);
+
+		if (Val > 0) {
+			Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
+		}
+		else {
+			Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
+		}
+		return(Val);
+		break;
+	case LM80_VT0_IN:
+	case LM80_VT1_IN:
+	case LM80_VT2_IN:
+	case LM80_VT3_IN:
+		Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
+		break;
+
+	default:
+		Val = (int)SkI2cRcvByte(IoC, 1);
+		break;
+	}
+
+	SkI2cStop(IoC);
+	return(Val);
+}
+#endif /* SK_DIAG */
+
+/*
+ * read a sensors value (LM80 specific)
+ *
+ * This function reads a sensors value from the TWSI sensor chip LM80.
+ * The sensor is defined by its index into the sensors database in the struct
+ * pAC points to.
+ *
+ * Returns	1 if the read is completed
+ *		0 if the read must be continued (TWSI Bus still allocated)
+ */
+int SkLm80ReadSensor(
+SK_AC		*pAC,	/* Adapter Context */
+SK_IOC		IoC,	/* I/O Context needed in level 1 and 2 */
+SK_SENSOR	*pSen)	/* Sensor to be read */
+{
+	SK_I32		Value;
+
+	switch (pSen->SenState) {
+	case SK_SEN_IDLE:
+		/* Send address to ADDR register */
+		SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, pSen->SenReg, 0);
+
+		pSen->SenState = SK_SEN_VALUE;
+		BREAK_OR_WAIT(pAC, IoC, I2C_READ);
+
+	case SK_SEN_VALUE:
+		/* Read value from data register */
+		SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
+
+		Value &= 0xff; /* only least significant byte is valid */
+
+		/* Do NOT check the Value against the thresholds */
+		/* Checking is done in the calling instance */
+
+		if (pSen->SenType == SK_SEN_VOLT) {
+			/* Voltage sensor */
+			pSen->SenValue = Value * SK_LM80_VT_LSB;
+			pSen->SenState = SK_SEN_IDLE;
+			return(1);
+		}
+
+		if (pSen->SenType == SK_SEN_FAN) {
+			if (Value != 0 && Value != 0xff) {
+				/* Fan speed counter */
+				pSen->SenValue = SK_LM80_FAN_FAKTOR / Value;
+			}
+			else {
+				/* Indicate Fan error */
+				pSen->SenValue = 0;
+			}
+			pSen->SenState = SK_SEN_IDLE;
+			return(1);
+		}
+
+		/* First: correct the value: it might be negative */
+		if ((Value & 0x80) != 0) {
+			/* Value is negative */
+			Value = Value - 256;
+		}
+
+		/* We have a temperature sensor and need to get the signed extension.
+		 * For now we get the extension from the last reading, so in the normal
+		 * case we won't see flickering temperatures.
+		 */
+		pSen->SenValue = (Value * SK_LM80_TEMP_LSB) +
+			(pSen->SenValue % SK_LM80_TEMP_LSB);
+
+		/* Send address to ADDR register */
+		SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
+
+		pSen->SenState = SK_SEN_VALEXT;
+		BREAK_OR_WAIT(pAC, IoC, I2C_READ);
+
+	case SK_SEN_VALEXT:
+		/* Read value from data register */
+		SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
+		Value &= LM80_TEMP_LSB_9; /* only bit 7 is valid */
+
+		/* cut the LSB bit */
+		pSen->SenValue = ((pSen->SenValue / SK_LM80_TEMP_LSB) *
+			SK_LM80_TEMP_LSB);
+
+		if (pSen->SenValue < 0) {
+			/* Value negative: The bit value must be subtracted */
+			pSen->SenValue -= ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
+		}
+		else {
+			/* Value positive: The bit value must be added */
+			pSen->SenValue += ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
+		}
+
+		pSen->SenState = SK_SEN_IDLE;
+		return(1);
+
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG);
+		return(1);
+	}
+
+	/* Not completed */
+	return(0);
+}
+
diff -ruN linux/drivers/net/sk98lin/skpflash.c linux-new/drivers/net/sk98lin/skpflash.c
--- linux/drivers/net/sk98lin/skpflash.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skpflash.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,805 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/skpflash.c#6 $
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools, Drivers
+ * Version:	$Revision: #6 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains parallel Flash EEPROM specific functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#ifndef SK_PFL_NO_UPDATE
+#ifdef MRVL_UEFI
+#include <stdlib.h>
+#endif /* !MRVL_UEFI */
+#endif	/* !SK_PFL_NO_UPDATE */
+#include "h/skdrv2nd.h"
+
+/* defines ******************************************************************/
+
+#ifdef Core
+#define fl_print pAC->Gui.WPrint
+#elif defined(VCPU)
+#define fl_print c_print
+#else
+extern void fl_print(char *str, ...);
+#endif /* Core */
+
+#define	SK_PFL_PART_INFO	0
+#define	SK_PFL_PART_MAIN	1
+
+#define SK_PFL_TIMER_SET	3	/* parallel flash timeout value (sec.) */
+#define SK_PFL_TIMEOUT		0	/* Timeout check flag */
+
+/* SPI EPROM BUSY CHECK */
+#define SK_PFL_IS_BUSY_WR(w)	(((w) & BIT_31) != 0)
+#define SK_PFL_IS_BUSY_RD(w)	(((w) & BIT_31) == 0)
+#define SK_PFL_IS_BUSY_CMD(w)	(((w) & (BIT_31 | BIT_30 | BIT_29 | BIT_28)) != 0)
+
+/* wait loop for parallel flash to finish a read (start spi_timer() before) */
+#define SK_PFL_WAIT_LP_FINISH_RD(pAC, IoC, stat) {							\
+	do {																	\
+		if (spi_timer(pAC, SK_PFL_TIMEOUT)) {								\
+			fl_print("\nRead timeout at parallel flash: %d sec.\n",			\
+				SK_PFL_TIMER_SET);											\
+			break;															\
+		}																	\
+		SK_IN32(IoC, FCU_MEM_CTRL, &stat);									\
+	} while (SK_PFL_IS_BUSY_RD(stat));										\
+}
+
+/* wait loop for parallel flash to finish a write (start spi_timer() before) */
+#define SK_PFL_WAIT_LP_FINISH_WR(pAC, IoC, stat) {							\
+	do {																	\
+		if (spi_timer(pAC, SK_PFL_TIMEOUT)) {								\
+			fl_print("\nWrite timeout at parallel flash: %d sec.\n",		\
+				SK_PFL_TIMER_SET);											\
+			break;															\
+		}																	\
+		SK_IN32(IoC, FCU_MEM_CTRL, &stat);									\
+	} while (SK_PFL_IS_BUSY_WR(stat));										\
+}
+
+/* wait for parallel flash to finish reading */
+#define SK_PFL_WAIT_FINISH_RD(pAC, IoC) {									\
+	volatile unsigned long stat;											\
+	/* wait for command to finish */										\
+	spi_timer(pAC, SK_PFL_TIMER_SET);										\
+	SK_PFL_WAIT_LP_FINISH_RD(pAC, IoC, stat);								\
+}
+
+/* wait for parallel flash to finish writing */
+#define SK_PFL_WAIT_FINISH_WR(pAC, IoC) {									\
+	volatile unsigned long stat;											\
+	/* wait for command to finish */										\
+	spi_timer(pAC, SK_PFL_TIMER_SET);										\
+	SK_PFL_WAIT_LP_FINISH_WR(pAC, IoC, stat);								\
+}
+
+/* wait for parallel flash to finish a command (write, erase, ...) */
+#define SK_PFL_WAIT_FINISH_CMD(pAC, IoC) {									\
+	volatile unsigned long stat2;											\
+	SK_PFL_WAIT_FINISH_WR(pAC, IoC);										\
+	/* wait for command to finish or timeout */								\
+	spi_timer(pAC, SK_PFL_TIMER_SET);										\
+	do {																	\
+		if (spi_timer(pAC, SK_PFL_TIMEOUT)) {								\
+			fl_print("\nCommand timeout at parallel flash: %d sec.\n",		\
+				SK_PFL_TIMER_SET);											\
+			break;															\
+		}																	\
+		/* bits 31..29 == 001: read access to parallel flash register. */	\
+		/* bits 26..24 == 010: 32-bit access. */							\
+		/* bits 7..0: register address */									\
+		SK_OUT32(IoC, FCU_MEM_CTRL, BIT_29 | (2 << 24) | 0);				\
+		SK_PFL_WAIT_LP_FINISH_RD(pAC, IoC, stat2);							\
+		SK_IN32(IoC, FCU_RD_DATA, &stat2);									\
+	} while (SK_PFL_IS_BUSY_CMD(stat2));									\
+}
+
+/* typedefs ******************************************************************/
+
+/* global variables **********************************************************/
+
+/* local variables **********************************************************/
+
+/*
+ * Yukon-II family parallel flash device table
+ */
+static SK_PFL_DEVICE SkPflDevTable[] = {
+	{
+		"SupremeInternal", 0x7F7F7FE9, "88E8075", 0x0291,
+		{0x800, 0x8000}, {1, 12},
+		{0x05, 0x15, 0x02, 0x07, 0x52, 0x82, 0x87, 0xD2}
+	},
+	{
+		"SupremeInternal", 0x7F7F7FE9, "88E8075", 0x0290,
+		{0x800, 0x8000}, {1, 12},
+		{0x05, 0x15, 0x02, 0x07, 0x52, 0x82, 0x87, 0xD2}
+	}
+};
+
+/* function prototypes *******************************************************/
+
+/* low level SPI programming external interface */
+extern int  spi_timer(SK_AC *pAC, unsigned int t);
+#ifndef SK_PFL_NO_UPDATE
+extern void *spi_malloc(unsigned long size);
+extern void spi_free(void *memblock);
+#endif	/* !SK_PFL_NO_UPDATE */
+
+/* local functions ***********************************************************/
+
+/*****************************************************************************
+ *
+ * SkPflCommand - Executes a command at the parallel flash
+ *
+ * Description:
+ *	This function will send a command to the parallel flash
+ *	and wait for it to complete.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void SkPflCommand(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		Part,
+SK_U8	Cmd,	/* comand code */
+SK_U16	Data)	/* data for command (if needed) */
+{
+	SK_OUT32(IoC, FCU_WR_DATA, BIT_31 | (Cmd << 16) | Data);
+
+	/* bits 31..29 == 101: write access to parallel flash register. */
+	/* bits 26..24 == 010: 32-bit access. */
+	/* bits 7..0: register address */
+	SK_OUT32(IoC, FCU_MEM_CTRL, BIT_31 | BIT_29 | (2 << 24) | 0);
+
+	/* wait for the parallel flash to finish the command */
+	SK_PFL_WAIT_FINISH_CMD(pAC, IoC);
+}	/* SkPflCommand */
+
+/*****************************************************************************
+ *
+ * SkPflEraseSector - Erase the specified sector of the parallel flash
+ *
+ * Description:
+ *	This function will erase the sector specified
+ *	thus allowing data to be written.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void SkPflEraseSector(
+SK_AC			*pAC,
+SK_IOC			IoC,
+int				Part,
+unsigned long	sector_num)		/* sector to be erased */
+{
+	if (Part == SK_PFL_PART_MAIN) {
+		SkPflCommand(pAC, IoC, Part, pAC->pfl.pPflDev->opcodes.OpPageErase,
+			(SK_U16) sector_num);
+	}
+	else {
+		SkPflCommand(pAC, IoC, Part, pAC->pfl.pPflDev->opcodes.OpInfoPageErase,
+			(SK_U16) sector_num);
+	}
+}
+
+/*****************************************************************************
+ *
+ * SkPflErase - Erases the specified sectors of the parallel flash
+ *
+ * Description:
+ *	Erase all sectors of the flash prom affected by the address
+ *	range denoted by parameters "off" (address offset) and "len"
+ *	(length of address range).
+ *
+ * Returns:
+ *	0	Success
+ *	(1	Timeout)
+ */
+static int SkPflErase(
+SK_AC			*pAC,
+SK_IOC			IoC,
+int				Part,
+unsigned long	off,	/* start offset in parallel flash for erase */
+unsigned long	len)	/* length in parallel flash for erase */
+{
+	unsigned long	i;
+	unsigned long	StartSect;
+	unsigned long	EndSect;
+
+	if (len == 0) {
+		return (0);
+	}
+
+	/* Erase all affected sectors. */
+	StartSect = off / pAC->pfl.pPflDev->SectorSize[Part];
+	EndSect   = (off + len - 1) / pAC->pfl.pPflDev->SectorSize[Part];
+#ifdef SK_LINUX
+	SK_DBG_PRINTF("%s: Erase flash ", DRV_NAME);
+#endif /* SK_LINUX */
+	for (i = StartSect; i <= EndSect; i++) {
+		SkPflEraseSector(pAC, IoC, Part, i);
+#ifdef SK_LINUX
+		SK_DBG_PRINTF(".");
+#else /* !SK_LINUX */
+		fl_print(".");
+#endif /* !SK_LINUX */
+	}
+
+#ifdef SK_LINUX
+	SK_DBG_PRINTF(" finished!\n");
+#endif /* SK_LINUX */
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * SkPflReadDword - Reads a dword from the parallel flash
+ *
+ * Description:
+ *	The function reads a dword from the specified address in the parallel flash.
+ *
+ * Returns:
+ *	The DWord read
+ */
+static SK_U32 SkPflReadDword(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		Part,
+SK_U32	Addr)		/* address in the parallel flash to read from */
+{
+	SK_U32	Val;
+
+	Addr &= (1 << 20) - 1;
+	Addr |= (2 << 24);
+	/* bits 31..29 == 000: read access to information memory. */
+	/* bits 26..24 == 010: 32-bit access. */
+	Addr |= (Part << 30);
+
+	SK_OUT32(IoC, FCU_MEM_CTRL, Addr);
+	SK_PFL_WAIT_FINISH_RD(pAC, IoC);
+	SK_IN32(IoC, FCU_RD_DATA, &Val);
+
+	return (Val);
+}
+
+/*****************************************************************************
+ *
+ * SkPflWriteDword - Writes a dword into the parallel flash
+ *
+ * Description:
+ *	This function writes the specified dword into the specified parallel flash
+ *	location. The parallel flash should have been put previously in write enable
+ *	mode and the target sector erased for the access to succeed.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void SkPflWriteDword(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		Part,		/* Info or main part */
+SK_U32	Addr,		/* Address to write to */
+SK_U32	Val)		/* New value to be written */
+{
+	Addr &= (1 << 20) - 1;
+	Addr |= BIT_31;
+	Addr |= (2 << 24);
+	/* bits 31..29 == 100: write access to information memory. */
+	/* bits 26..24 == 010: 32-bit access. */
+	Addr |= (Part << 30);
+
+	SK_OUT32(IoC, FCU_WR_DATA, Val);
+	SK_OUT32(IoC, FCU_MEM_CTRL, Addr);
+	SK_PFL_WAIT_FINISH_WR(pAC, IoC);
+}
+
+/*****************************************************************************
+ *
+ * SkPflReadChipId - Reads parallel flash IDs
+ *
+ * Description:
+ *	This function reads the IDs of the parallel flash.
+ *
+ * Returns:
+ *	Nothing (parallel flash manufacturer and device ID in parameters)
+ */
+static void SkPflReadChipId(
+SK_AC	*pAC,
+SK_IOC	IoC,
+SK_U32	*pManId,
+SK_U16	*pDevId)
+{
+	/* Put manufacturer and device ID into proper registers. */
+	SkPflCommand(pAC, IoC, -1, pAC->pfl.pPflDev->opcodes.OpReadManDev, 0);
+
+	/* bits 31..29 == 001: read access to parallel flash register. */
+	/* bits 26..24 == 010: 32-bit access. */
+	/* bits 7..0: register address */
+	SK_OUT32(IoC, FCU_MEM_CTRL, BIT_29 | (2 << 24) | 0x18);
+	SK_PFL_WAIT_FINISH_RD(pAC, IoC);
+	SK_IN32(IoC, FCU_RD_DATA, pManId);
+	*pManId = FL_SWAP32(*pManId);
+
+	SK_OUT32(IoC, FCU_MEM_CTRL, BIT_29 | (2 << 24) | 0x1C);
+	SK_PFL_WAIT_FINISH_RD(pAC, IoC);
+	SK_IN16(IoC, FCU_RD_DATA, pDevId);
+	*pDevId = FL_SWAP16(*pDevId);
+
+	return;
+}
+
+/*****************************************************************************
+ *
+ * SkPflSetDevPtr - Sets a pointer to the correct device table entry
+ *
+ * Description:
+ *	This function identifies the parallel flash device and sets
+ *	the pointer to its device table entry.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void SkPflSetDevPtr(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	SK_U32	i;
+	SK_U32	ManId;
+	SK_U16	DevId;
+
+	/* search for parallel flash in device table */
+	for (i = 0; i < (sizeof(SkPflDevTable) / sizeof(SkPflDevTable[0])); i++) {
+
+		/* Used by e.g. SkPflReadChipId(). */
+		pAC->pfl.pPflDev = &SkPflDevTable[i];
+
+		SkPflReadChipId(pAC, IoC, &ManId, &DevId);
+		if ((SkPflDevTable[i].ManId == ManId) &&
+			(SkPflDevTable[i].DevId == DevId)) {
+			fl_print("\nFlash Device: %s ", SkPflDevTable[i].pDevName);
+			fl_print("(VID 0x%08x, ", ManId);
+			fl_print("DID 0x%04x)\n", DevId);
+			return;
+		}
+	}
+
+	pAC->pfl.pPflDev = NULL;
+	return;
+}
+
+/*****************************************************************************
+ *
+ * SkPflCheck - Determines whether a parallel flash is present
+ *
+ * Description:
+ *	This function determines whether a parallel flash is present.
+ *
+ * Returns:
+ *	0	No parallel flash
+ *	1	Parallel flash detected
+ */
+int SkPflCheck(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+#ifdef XXX
+	unsigned long opcodes;
+#endif	/* XXX */
+
+	SK_IN8(IoC, B2_CHIP_ID, &pAC->pfl.YkChipId);
+	if (pAC->pfl.YkChipId == CHIP_ID_YUKON_SUPR) {
+
+		SkPflSetDevPtr(pAC, IoC);
+		if (pAC->pfl.pPflDev == NULL) {
+			/* unknown or no flash */
+			fl_print("\nFlash device\t: none\n");
+			return (0);
+		}
+
+#ifdef XXX
+		/*
+		 * set the opcodes for the SPI flash found
+		 */
+		SK_IN32(IoC, SPI_Y2_OPCODE_REG1, &opcodes);
+
+		opcodes &= 0x000000ffL;
+		opcodes |= ((((unsigned long)(pAC->pfl.pPflDev->opcodes.op_read)) << 8) |
+					(((unsigned long)(pAC->pfl.pPflDev->opcodes.op_read_id)) << 16) |
+					(((unsigned long)(pAC->pfl.pPflDev->opcodes.op_read_status)) << 24));
+
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG1, opcodes);
+
+		opcodes = (((unsigned long)(pAC->pfl.pPflDev->opcodes.op_write_enable)) |
+				   (((unsigned long)(pAC->pfl.pPflDev->opcodes.op_write)) << 8) |
+				   (((unsigned long)(pAC->pfl.pPflDev->opcodes.op_sector_erase)) << 16) |
+				   (((unsigned long)(pAC->pfl.pPflDev->opcodes.op_chip_erase)) << 24));
+
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, opcodes);
+#endif	/* XXX */
+
+		return (1);
+	}
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * SkPflDoManage - Reads, verifies, writes, or erases parallel flash
+ *
+ * Description:
+ *	This function reads from parallel flash, verifies data, writes to
+ *	parallel flash and verifies data, or erases parts of the parallel flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int SkPflDoManage(
+SK_AC	*pAC,
+SK_IOC	IoC,
+int		Part,	/* SK_PFL_PART_INFO or SK_PFL_PART_MAIN */
+SK_U8	*pData,	/* data buffer - might be NULL for action SK_PFL_ERASE only */
+SK_U32	Offs,	/* start offset in flash for action - must be a multiple of 4 */
+SK_U32	Len,	/* length in parallel flash - must be a multiple of 4 */
+int		Action)	/* SK_PFL_READ / SK_PFL_VERIFY / SK_PFL_WRITE / SK_PFL_ERASE */
+{
+	SK_U32	Addr;
+	SK_U32	Addr2;
+	SK_U32	FplData;
+	SK_U32	*pFplData;
+	SK_U32	Progress;
+	SK_U32	LastProgress;
+	int		RetVal;
+	SK_BOOL	Fill64ByteBlock;
+
+	RetVal = 0;
+	Fill64ByteBlock = SK_FALSE;
+
+	Progress = LastProgress = 0;
+
+#ifdef VCPU
+	fl_print("SkPflDoManage() action: %d, pData: %08lx, Part: %d, Offs: %08lx, "
+		"Len: %d.\n", Action, pData, Part, Offs, Len);
+#endif	/* VCPU */
+
+	if (Action == SK_PFL_ERASE) {
+		/* erase the affected sectors */
+		fl_print("Erasing: ");
+		RetVal = SkPflErase(pAC, IoC, Part, Offs, Len);
+	}
+	else {
+		if (Action == SK_PFL_WRITE) {
+#ifdef SK_LINUX
+			SK_FLASH_RESCHED();
+#else /* !SK_LINUX */
+			fl_print("Writing: ");
+#endif /* !SK_LINUX */
+
+			if ((Offs & 63) != 0) {
+				/*
+				 * Fill the start of the on-chip 64-byte buffer
+				 * with data from flash if writing starts later.
+				 */
+				for (Addr2 = Offs & ~63; Addr2 < Offs; Addr2 += 4) {
+					/* Read a dword from parallel flash. */
+					FplData = SkPflReadDword(pAC, IoC, Part, Addr2);
+				}
+			}
+
+			/*
+			 * If the data does not fill a single 64-byte block
+			 * to the end, remember to fill the end of the
+			 * on-chip 64-byte buffer with data from flash.
+			 */
+			Fill64ByteBlock = (Offs + Len - (Offs & ~63) < 64);
+		}
+		else if (Action == SK_PFL_READ) {
+			fl_print("Reading: ");
+		}
+		else if (Action == SK_PFL_VERIFY) {
+			fl_print("Verify : ");
+		}
+		for (Addr = Offs, pFplData = (SK_U32 *) pData;
+			Addr < Offs + Len; Addr += 4, pFplData++) {
+
+			Progress = ((Addr - Offs) * 100) / Len;
+
+			if ((Progress - LastProgress) >= 10) {
+				fl_print(".");
+				LastProgress += 10;
+			}
+
+			switch (Action) {
+			case SK_PFL_READ:
+				/* Read a dword from parallel flash. */
+				FplData = SkPflReadDword(pAC, IoC, Part, Addr);
+				*pFplData = FplData;
+				break;
+
+			case SK_PFL_VERIFY:
+				/* Read and verify dword from parallel flash. */
+				FplData = SkPflReadDword(pAC, IoC, Part, Addr);
+				if (FplData != *pFplData) {
+					fl_print("\n*** Verify error in parallel flash at address "
+						"0x%08lx, is %08lx, should be %08lx\n",
+						Addr, FplData, *pFplData);
+					RetVal = 1;
+				}
+				break;
+
+			case SK_PFL_WRITE:
+				if (Fill64ByteBlock) {
+					/*
+					 * Fill the end of the on-chip
+					 * 64-byte buffer with data from flash.
+					 */
+					for (Addr2 = Offs + Len; Addr2 < ((Offs + Len + 63) & ~63);
+						Addr2 += 4) {
+						/* Read a dword from parallel flash. */
+						FplData = SkPflReadDword(pAC, IoC, Part, Addr2);
+					}
+					Fill64ByteBlock = SK_FALSE;
+				}
+
+				/* Write a dword to the parallel flash. */
+				FplData = *pFplData;
+				SkPflWriteDword(pAC, IoC, Part, Addr, FplData);
+				if ((Addr + 4 >= Offs + Len) || (((Addr + 4) & 63) == 0)) {
+					/*
+					 * Last DWord of buffer or last DWord
+					 * of a 64-byte block was written.
+					 */
+					if (Part == SK_PFL_PART_MAIN) {
+						SkPflCommand(pAC, IoC, Part,
+							pAC->pfl.pPflDev->opcodes.OpProgram, 0);
+					}
+					else {
+						SkPflCommand(pAC, IoC, Part,
+							pAC->pfl.pPflDev->opcodes.OpInfoProgram, 0);
+					}
+
+					if ((Addr + 4 < Offs + Len) &&
+						(Offs + Len - (Addr + 4) < 64)) {
+						/*
+						 * The last 64-byte block is started now -
+						 * and it is incomplete. So remember to fill
+						 * the end of the on-chip 64-byte buffer with
+						 * data from flash.
+						 */
+						Fill64ByteBlock = SK_TRUE;
+					}
+				}
+				break;
+			}	/* switch */
+
+			if (RetVal != 0) {
+				break;
+			}
+		}	/* for */
+	}
+
+	fl_print("\tDone\n");
+
+	if (Action == SK_PFL_WRITE) {
+		RetVal = SkPflDoManage(pAC, IoC, Part, pData, Offs, Len, SK_PFL_VERIFY);
+	}
+
+	return (RetVal);
+}
+
+/*****************************************************************************
+ *
+ * SkPflManage - Reads, verifies, writes, or erases main part
+ *
+ * Description:
+ *	This function reads from the main part of the parallel flash, verifies data,
+ *	writes to the main part of the parallel flash and verifies data, or erases
+ *	parts of the main part of parallel flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int SkPflManage(
+SK_AC	*pAC,
+SK_IOC	IoC,
+SK_U8	*pData,	/* data buffer - might be NULL for action SK_PFL_ERASE only */
+SK_U32	Offs,	/* start offset in flash for action - must be a multiple of 4 */
+SK_U32	Len,	/* length in parallel flash - must be a multiple of 4 */
+int		Action)	/* SK_PFL_READ / SK_PFL_VERIFY / SK_PFL_WRITE / SK_PFL_ERASE */
+{
+	SK_U32	FSize;
+
+	if ((pAC->pfl.pPflDev == NULL) || ((Offs & 3) != 0) || ((Len & 3) != 0)) {
+		return (1);
+	}
+
+	if ((pData == NULL) && (Action != SK_PFL_ERASE)) {
+		return (1);
+	}
+
+	FSize = pAC->pfl.pPflDev->NumSectors[SK_PFL_PART_MAIN] *
+		pAC->pfl.pPflDev->SectorSize[SK_PFL_PART_MAIN];
+	if (Offs + Len > FSize) {
+		return (1);
+	}
+
+	return (SkPflDoManage(pAC, IoC, SK_PFL_PART_MAIN, pData, Offs, Len, Action));
+}	/* SkPflManage */
+
+/*****************************************************************************
+ *
+ * SkPflManage - Reads, verifies, writes, or erases info part
+ *
+ * Description:
+ *	This function reads from the info part of the parallel flash, verifies data,
+ *	writes to the info part of the parallel flash and verifies data, or erases
+ *	parts of the info part of parallel flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int SkPflManageInfo(
+SK_AC	*pAC,
+SK_IOC	IoC,
+SK_U8	*pData,	/* data buffer - might be NULL for action SK_PFL_ERASE only */
+SK_U32	Offs,	/* start offset in flash for action - must be a multiple of 4 */
+SK_U32	Len,	/* length in parallel flash - must be a multiple of 4 */
+int		Action)	/* SK_PFL_READ / SK_PFL_VERIFY / SK_PFL_WRITE / SK_PFL_ERASE */
+{
+	SK_U32	FSize;
+
+	if ((pAC->pfl.pPflDev == NULL) || ((Offs & 3) != 0) || ((Len & 3) != 0)) {
+		return (1);
+	}
+
+	if ((pData == NULL) && (Action != SK_PFL_ERASE)) {
+		return (1);
+	}
+
+	FSize = pAC->pfl.pPflDev->NumSectors[SK_PFL_PART_INFO] *
+		pAC->pfl.pPflDev->SectorSize[SK_PFL_PART_INFO];
+	if (Offs + Len > FSize) {
+		return (1);
+	}
+
+	return (SkPflDoManage(pAC, IoC, SK_PFL_PART_INFO, pData, Offs, Len, Action));
+}	/* SkPflManageInfo */
+
+#ifdef XXX
+
+#ifndef SK_PFL_NO_UPDATE
+
+/*****************************************************************************
+ *
+ * SkPflUpdateConfig - Updates part of the config area in the parallel flash
+ *
+ * Description:
+ *	This function updates part of configuration area in the parallel flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int SkPflUpdateConfig(
+SK_AC	*pAC,
+SK_IOC	IoC,
+SK_U8	*pData,	/* data buffer */
+SK_U32	Offs,	/* start offset in parallel flash (config area) for operation */
+SK_U32	Len)	/* length of changing data */
+{
+	SK_U8	*pSpiBuf;
+	SK_U32	SectorSize;
+	SK_U32	StartSector;
+	SK_U32	EndSector;
+	int		i;
+
+	/* RARAsafe */
+	return (1);
+
+	/* RARA or SK_PFL_PART_MAIN? */
+	SectorSize = pAC->pfl.pPflDev->SectorSize[SK_PFL_PART_INFO];
+
+	/* Determine the affected sectors. */
+	StartSector = Offs / SectorSize;
+	EndSector   = (Offs + Len - 1) / SectorSize;
+
+	/* Allocate the necessary memory to temporary save the affected sectors. */
+	pSpiBuf = spi_malloc(((EndSector - StartSector) + 1) * SectorSize);
+
+	if (pSpiBuf == NULL) {
+		return (51);
+	}
+
+	/* Read out the affected sectors. */
+	if (SkPflManage(pAC, IoC, pSpiBuf, StartSector * SectorSize,
+		((EndSector - StartSector) + 1) * SectorSize, SPI_READ)) {
+
+		spi_free(pSpiBuf);
+		return (1);
+	}
+
+	/* Update the just read out data. */
+	for (i = 0; i < Len; i++) {
+		pSpiBuf[Offs + i - SPI_LSECT_OFF] = pData[i];
+	}
+
+	/* Erase the affected sectors. */
+	if (SkPflErase(pAC, IoC, StartSector * SectorSize,
+		((EndSector - StartSector) + 1) * SectorSize)) {
+
+		spi_free(pSpiBuf);
+		return (7);
+	}
+
+	/* Write the updated data back to the flash. */
+	if (SkPflManage(pAC, IoC, pSpiBuf, StartSector * SectorSize,
+		((EndSector - StartSector) + 1) * SectorSize, SPI_WRITE)) {
+
+		spi_free(pSpiBuf);
+		return (8);
+	}
+
+	spi_free(pSpiBuf);
+	return (0);
+}
+
+#endif	/* !SK_PFL_NO_UPDATE */
+
+/*****************************************************************************
+ *
+ * SkPflVpdTransfer - Reads or updates data in the VPD area in the parallel flash
+ *
+ * Description:
+ *	This function reads or updates data in the VPD area in the parallel flash.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int SkPflVpdTransfer(
+SK_AC	*pAC,
+SK_IOC	IoC,
+SK_U8	*pData,	/* data buffer */
+SK_U32	Addr,	/* VPD start address */
+SK_U32	Len,	/* number of bytes to read or write */
+int		Dir)	/* transfer direction may be VPD_READ or VPD_WRITE */
+{
+	if (Dir == VPD_READ) {
+		return (SkPflManage/SkPflManageInfo(pAC, IoC, pBuf,
+			SPI_VPD_OFF + Addr, Len, SPI_READ));
+	}
+	else {
+#ifndef SK_PFL_NO_UPDATE
+		return (SkPflUpdateConfig(pAC, IoC, pBuf, SPI_VPD_OFF + Addr, Len));
+#else	/* SK_PFL_NO_UPDATE */
+		return (1);
+#endif	/* SK_PFL_NO_UPDATE */
+	}
+}
+
+#endif	/* XXX */
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/skproc.c linux-new/drivers/net/sk98lin/skproc.c
--- linux/drivers/net/sk98lin/skproc.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skproc.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,472 @@
+/******************************************************************************
+ *
+ * Name:	skproc.c
+ * Project:	Yukon/Yukon2, PCI Gigabit Ethernet Adapter
+ * Purpose:	Functions to display statictic data
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	(C)Copyright 1998-2002 SysKonnect GmbH.
+ *	(C)Copyright 2002-2011 Marvell.
+ *
+ *	Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include "h/skversion.h"
+
+extern struct SK_NET_DEVICE *SkGeRootDev;
+
+/******************************************************************************
+ *
+ * Local Function Prototypes and Local Variables
+ *
+ *****************************************************************************/
+
+static int sk_proc_print(void *writePtr, char *format, ...);
+static void sk_gen_browse(void *buffer);
+static int len;
+
+static int sk_seq_show(struct seq_file *seq, void *v);
+static int sk_proc_open(struct inode *inode, struct file *file);
+struct file_operations sk_proc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= sk_proc_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+struct net_device *currDev = NULL;
+
+/*****************************************************************************
+ *
+ * 	sk_gen_browse -generic  print "summaries" entry
+ *
+ * Description:
+ *	This function fills the proc entry with statistic data about
+ *	the ethernet device.
+ *
+ * Returns:	N/A
+ *
+ */
+static void sk_gen_browse(
+void *buffer)  /* buffer where the statistics will be stored in */
+{
+	struct SK_NET_DEVICE	*SkgeProcDev = SkGeRootDev;
+	struct SK_NET_DEVICE	*next;
+	SK_BOOL			DisableStatistic = 0;
+	SK_PNMI_STRUCT_DATA 	*pPnmiStruct;
+	SK_PNMI_STAT		*pPnmiStat;
+	unsigned long		Flags;
+	unsigned int		Size;
+	DEV_NET			*pNet;
+	SK_AC			*pAC;
+	char			sens_msg[50];
+	int 			card_type;
+	int			MaxSecurityCount = 0;
+	int 			t;
+	int 			i;
+
+	while (SkgeProcDev) {
+		MaxSecurityCount++;
+		if (MaxSecurityCount > 100) {
+			printk("Max limit for sk_proc_read security counter!\n");
+			return;
+		}
+
+		#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+			pNet = (DEV_NET*) SkgeProcDev->priv;
+        	#else
+                	pNet = netdev_priv(SkgeProcDev);
+#endif
+		pAC = pNet->pAC;
+		next = pAC->Next;
+		pPnmiStruct = &pAC->PnmiStruct;
+		/* NetIndex in GetStruct is now required, zero is only dummy */
+
+		for (t=pAC->GIni.GIMacsFound; t > 0; t--) {
+			if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1)
+				t--;
+
+			spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+			Size = SK_PNMI_STRUCT_SIZE;
+			DisableStatistic = 0;
+			if (pAC->BoardLevel == SK_INIT_DATA) {
+				SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA));
+				if (pAC->DiagModeActive == DIAG_NOTACTIVE) {
+					pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
+				}
+			} else {
+				SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1);
+			}
+			spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+			if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) {
+				if (!pAC->GIni.GIYukon32Bit)
+					card_type = 64;
+				else
+					card_type = 32;
+
+				pPnmiStat = &pPnmiStruct->Stat[0];
+				len = sk_proc_print(buffer,
+					"\nDetailed statistic for device %s\n",
+					pAC->dev[t-1]->name);
+				len += sk_proc_print(buffer,
+					"=======================================\n");
+
+				/* Board statistics */
+				len += sk_proc_print(buffer,
+					"\nBoard statistics\n\n");
+				len += sk_proc_print(buffer,
+					"Card name                      %s\n",
+					pAC->DeviceStr);
+				len += sk_proc_print(buffer,
+					"Vendor/Device ID               %x/%x\n",
+					pAC->PciDev->vendor,
+					pAC->PciDev->device);
+				len += sk_proc_print(buffer,
+					"Card type (Bit)                %d\n",
+					card_type);
+
+				if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
+					len += sk_proc_print(buffer,
+					"Interrupt Moderation           static (%d ints/sec)\n",
+					pAC->DynIrqModInfo.MaxModIntsPerSec);
+				} else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
+					len += sk_proc_print(buffer,
+					"Interrupt Moderation           dynamic (%d ints/sec)\n",
+					pAC->DynIrqModInfo.MaxModIntsPerSec);
+				} else {
+					len += sk_proc_print(buffer,
+					"Interrupt Moderation           disabled\n");
+				}
+
+				if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
+					len += sk_proc_print(buffer,
+						"Bus type                       PCI-Express\n");
+					len += sk_proc_print(buffer,
+						"Bus width (Lanes)              %d\n",
+						pAC->GIni.GIPexWidth);
+				} else {
+					if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
+						len += sk_proc_print(buffer,
+							"Bus type                       PCI-X\n");
+						if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) {
+							len += sk_proc_print(buffer,
+								"Bus speed (MHz)                133\n");
+						} else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) {
+							len += sk_proc_print(buffer,
+								"Bus speed (MHz)                100\n");
+						} else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) {
+							len += sk_proc_print(buffer,
+								"Bus speed (MHz)                66\n");
+						} else {
+							len += sk_proc_print(buffer,
+								"Bus speed (MHz)                33\n");
+						}
+					} else {
+						len += sk_proc_print(buffer,
+							"Bus type                       PCI\n");
+						len += sk_proc_print(buffer,
+							"Bus speed (MHz)                %d\n",
+							pPnmiStruct->BusSpeed);
+					}
+					len += sk_proc_print(buffer,
+						"Bus width (Bit)                %d\n",
+						pPnmiStruct->BusWidth);
+				}
+
+				len += sk_proc_print(buffer,
+					"Driver version                 %s (%s)\n",
+					VER_STRING, PATCHLEVEL);
+				len += sk_proc_print(buffer,
+					"Driver release date            %s\n",
+					pAC->Pnmi.pDriverReleaseDate);
+				len += sk_proc_print(buffer,
+					"Hardware revision              v%d.%d\n",
+					(pAC->GIni.GIPciHwRev >> 4) & 0x0F,
+					pAC->GIni.GIPciHwRev & 0x0F);
+
+				if (!netif_running(pAC->dev[t-1])) {
+					len += sk_proc_print(buffer,
+						"\n      Device %s is down.\n"
+						"      Therefore no statistics are available.\n"
+						"      After bringing the device up (ifconfig)"
+						" statistics will\n"
+						"      be displayed.\n",
+						pAC->dev[t-1]->name);
+					DisableStatistic = 1;
+				}
+
+				/* Display only if statistic info available */
+				/* Print sensor informations */
+				if (!DisableStatistic) {
+					for (i=0; i < pAC->I2c.MaxSens; i ++) {
+						/* Check type */
+						switch (pAC->I2c.SenTable[i].SenType) {
+						case 1:
+							strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
+							strcat(sens_msg, " (C)");
+							len += sk_proc_print(buffer,
+								"%-25s      %d.%02d\n",
+								sens_msg,
+								pAC->I2c.SenTable[i].SenValue / 10,
+								pAC->I2c.SenTable[i].SenValue %
+								10);
+
+							strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
+							strcat(sens_msg, " (F)");
+							len += sk_proc_print(buffer,
+								"%-25s      %d.%02d\n",
+								sens_msg,
+								((((pAC->I2c.SenTable[i].SenValue)
+								*10)*9)/5 + 3200)/100,
+								((((pAC->I2c.SenTable[i].SenValue)
+								*10)*9)/5 + 3200) % 10);
+							break;
+						case 2:
+							strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
+							strcat(sens_msg, " (V)");
+							len += sk_proc_print(buffer,
+								"%-25s      %d.%03d\n",
+								sens_msg,
+								pAC->I2c.SenTable[i].SenValue / 1000,
+								pAC->I2c.SenTable[i].SenValue % 1000);
+							break;
+						case 3:
+							strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
+							strcat(sens_msg, " (rpm)");
+							len += sk_proc_print(buffer,
+								"%-25s      %d\n",
+								sens_msg,
+								pAC->I2c.SenTable[i].SenValue);
+							break;
+						default:
+							break;
+						}
+					}
+
+					/*Receive statistics */
+					len += sk_proc_print(buffer,
+					"\nReceive statistics\n\n");
+
+					len += sk_proc_print(buffer,
+						"Received bytes                 %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxOctetsOkCts);
+					len += sk_proc_print(buffer,
+						"Received packets               %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxOkCts);
+#if 0
+					if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
+						pAC->HWRevision < 12) {
+						pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
+							pPnmiStat->StatRxShortsCts;
+						pPnmiStat->StatRxShortsCts = 0;
+					}
+#endif
+					if (pAC->dev[t-1]->mtu > 1500)
+						pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
+							pPnmiStat->StatRxTooLongCts;
+
+					len += sk_proc_print(buffer,
+						"Receive errors                 %Lu\n",
+						(unsigned long long) pPnmiStruct->InErrorsCts);
+					len += sk_proc_print(buffer,
+						"Receive dropped                %Lu\n",
+						(unsigned long long) pPnmiStruct->RxNoBufCts);
+					len += sk_proc_print(buffer,
+						"Received multicast             %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxMulticastOkCts);
+#ifdef ADVANCED_STATISTIC_OUTPUT
+					len += sk_proc_print(buffer,
+						"Receive error types\n");
+					len += sk_proc_print(buffer,
+						"   length                      %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxRuntCts);
+					len += sk_proc_print(buffer,
+						"   buffer overflow             %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxFifoOverflowCts);
+					len += sk_proc_print(buffer,
+						"   bad crc                     %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxFcsCts);
+					len += sk_proc_print(buffer,
+						"   framing                     %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxFramingCts);
+					len += sk_proc_print(buffer,
+						"   missed frames               %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxMissedCts);
+
+					if (pAC->dev[t-1]->mtu > 1500)
+						pPnmiStat->StatRxTooLongCts = 0;
+
+					len += sk_proc_print(buffer,
+						"   too long                    %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxTooLongCts);
+					len += sk_proc_print(buffer,
+						"   carrier extension           %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxCextCts);
+					len += sk_proc_print(buffer,
+						"   too short                   %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxShortsCts);
+					len += sk_proc_print(buffer,
+						"   symbol                      %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxSymbolCts);
+					len += sk_proc_print(buffer,
+						"   LLC MAC size                %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxIRLengthCts);
+					len += sk_proc_print(buffer,
+						"   carrier event               %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxCarrierCts);
+					len += sk_proc_print(buffer,
+						"   jabber                      %Lu\n",
+						(unsigned long long) pPnmiStat->StatRxJabberCts);
+#endif
+
+					/*Transmit statistics */
+					len += sk_proc_print(buffer,
+					"\nTransmit statistics\n\n");
+
+					len += sk_proc_print(buffer,
+						"Transmitted bytes              %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxOctetsOkCts);
+					len += sk_proc_print(buffer,
+						"Transmitted packets            %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxOkCts);
+					len += sk_proc_print(buffer,
+						"Transmit errors                %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
+					len += sk_proc_print(buffer,
+						"Transmit dropped               %Lu\n",
+						(unsigned long long) pPnmiStruct->TxNoBufCts);
+					len += sk_proc_print(buffer,
+						"Transmit collisions            %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
+#ifdef ADVANCED_STATISTIC_OUTPUT
+					len += sk_proc_print(buffer,
+						"Transmit error types\n");
+					len += sk_proc_print(buffer,
+						"   excessive collision         %ld\n",
+						pAC->stats.tx_aborted_errors);
+					len += sk_proc_print(buffer,
+						"   carrier                     %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxCarrierCts);
+					len += sk_proc_print(buffer,
+						"   fifo underrun               %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxFifoUnderrunCts);
+					len += sk_proc_print(buffer,
+						"   heartbeat                   %Lu\n",
+						(unsigned long long) pPnmiStat->StatTxCarrierCts);
+					len += sk_proc_print(buffer,
+						"   window                      %ld\n",
+						pAC->stats.tx_window_errors);
+#endif
+				} /* if (!DisableStatistic) */
+
+			} /* if (strcmp(pACname, currDeviceName) == 0) */
+		}
+		SkgeProcDev = next;
+	}
+}
+
+/*****************************************************************************
+ *
+ *      sk_proc_print - generic line print
+ *
+ * Description:
+ *	This function fills the proc entry with statistic data about the
+ *	ethernet device.
+ *
+ * Returns:
+ *	the number of bytes written
+ *
+ */
+static int sk_proc_print(
+void *writePtr, /* the buffer pointer         */
+char *format,   /* the format of the string   */
+...)            /* variable list of arguments */
+{
+#define MAX_LEN_SINGLE_LINE 256
+	char     str[MAX_LEN_SINGLE_LINE];
+	va_list  a_start;
+	int      lenght = 0;
+
+	struct seq_file *seq = (struct seq_file *) writePtr;
+
+	SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE);
+
+	va_start(a_start, format);
+	vsprintf(str, format, a_start);
+	va_end(a_start);
+
+	lenght = strlen(str);
+
+	seq_printf(seq, str);
+	return lenght;
+}
+
+/*****************************************************************************
+ *
+ *      sk_seq_show - show proc information of a particular adapter
+ *
+ * Description:
+ *	This function fills the proc entry with statistic data about the
+ *	ethernet device. It invokes the generic sk_gen_browse() to print
+ *	out all items one per one.
+ *
+ * Returns:
+ *	the number of bytes written
+ *
+ */
+static int sk_seq_show(
+struct seq_file *seq,  /* the sequence pointer */
+void            *v)    /* additional pointer   */
+{
+	void *castedBuffer = (void *) seq;
+	currDev = seq->private;
+	sk_gen_browse(castedBuffer);
+	return 0;
+}
+
+/*****************************************************************************
+ *
+ *      sk_proc_open - register the show function when proc is open'ed
+ *
+ * Description:
+ *	This function is called whenever a sk98lin proc file is queried.
+ *
+ * Returns:
+ *	the return value of single_open()
+ *
+ */
+static int sk_proc_open(
+struct inode *inode,  /* the inode of the file   */
+struct file  *file)   /* the file pointer itself */
+{
+	return single_open(file, sk_seq_show, PDE(inode)->data);
+}
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/skqueue.c linux-new/drivers/net/sk98lin/skqueue.c
--- linux/drivers/net/sk98lin/skqueue.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skqueue.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,351 @@
+/******************************************************************************
+ *
+ * Name:	skqueue.c
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	Management of an event queue.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: skqueue.c,v $
+ *	Revision 2.10  2010/07/07 15:49:22  malthoff
+ *	Added macros to activate log capability.
+ *	
+ *	Revision 2.9  2010/03/09 11:24:02  rschmidt
+ *	Added use of define SK_NO_PNMI for VxWorks.
+ *	Editorial changes.
+ *	
+ *	Revision 2.8  2009/10/27 14:47:52  tschilli
+ *	Added define SK_NO_RLMT to allow compilation without RLMT.
+ *
+ *	Revision 2.7  2009/02/17 11:12:37  rschmidt
+ *	Fixed PREfast compiler warnings.
+ *	Editorial changes.
+ *
+ *	Revision 2.6  2007/07/17 15:31:56  rschmidt
+ *	Replaced debug output PRINTF with SK_DBG_MSG.
+ *	Changed return handling in SkEventQueue().
+ *	Editorial changes.
+ *
+ *	Revision 2.5  2005/12/14 16:11:02  ibrueder
+ *	Added copyright header flags.
+ *
+ *	Revision 2.4  2005/01/24 16:02:57  omater
+ *	First working Miniport with LBFO (LACP) support.
+ *
+ *	Revision 2.3  2004/05/14 13:28:18  malthoff
+ *	Reworked the function headers.
+ *	Added comments and descriptions.
+ *	Added Init Level Check for each function.
+ *	Addd Debug Prints.
+ *
+ *	Revision 2.2  2004/02/26 16:02:58  mkunz
+ *	Changes for ASF.
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.20  2003/09/16 13:44:00  rschmidt
+ *	Added (C) Marvell to SysKonnectFileId.
+ *	Editorial changes.
+ *
+ *	Revision 1.19  2003/05/13 18:00:07  mkarl
+ *	Removed calls to RLMT, TWSI, and PNMI for SLIM driver (SK_SLIM).
+ *	Editorial changes.
+ *
+ *	Revision 1.18  2002/05/07 14:11:11  rwahl
+ *	Fixed Watcom Precompiler error.
+ *
+ *	Revision 1.17  2002/03/25 10:06:41  mkunz
+ *	SkIgnoreEvent deleted
+ *
+ *	Revision 1.16  2002/03/15 10:51:59  mkunz
+ *	Added event classes for link aggregation
+ *
+ *	Revision 1.15  1999/11/22 13:36:29  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.14  1998/10/15 15:11:35  gklug
+ *	fix: ID_sccs to SysKonnectFileId
+ *
+ *	Revision 1.13  1998/09/08 08:47:52  gklug
+ *	add: Init Level handling
+ *
+ *	Revision 1.12  1998/09/08 07:43:20  gklug
+ *	fix: SIRQ Event function name
+ *
+ *	Revision 1.11  1998/09/08 05:54:34  gklug
+ *	chg: define SK_CSUM is replaced by SK_USE_CSUM
+ *
+ *	Revision 1.10  1998/09/03 14:14:49  gklug
+ *	add: CSUM and HWAC Eventclass and function.
+ *
+ *	Revision 1.9  1998/08/19 09:50:50  gklug
+ *	fix: remove struct keyword from C-code (see CCC) add typedefs
+ *
+ *	Revision 1.8  1998/08/17 13:43:11  gklug
+ *	chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ *	Revision 1.7  1998/08/14 07:09:11  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.6  1998/08/11 12:13:14  gklug
+ *	add: return code feature of Event service routines
+ *	add: correct Error log calls
+ *
+ *	Revision 1.5  1998/08/07 12:53:45  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.4  1998/08/07 09:20:48  gklug
+ *	adapt functions to C coding conventions.
+ *
+ *	Revision 1.3  1998/08/05 11:29:32  gklug
+ *	rmv: Timer event entry. Timer will queue event directly
+ *
+ *	Revision 1.2  1998/07/31 11:22:40  gklug
+ *	Initial version
+ *
+ *	Revision 1.1  1998/07/30 15:14:01  gklug
+ *	Initial version. Adapted from SMT
+ *
+ ******************************************************************************/
+
+/*
+ *	Event queue and dispatcher
+ */
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/schedule/V3/skqueue.c#5 $ (C) Marvell.";
+#endif
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#include "h/skqueue.h"		/* Queue Definitions */
+#include "h/skdrv2nd.h"		/* Adapter Control- and Driver specific Def. */
+
+/******************************************************************************
+ *
+ *	SkEventInit() - init event queue management
+ *
+ * Description:
+ *	This function initializes event queue management.
+ *	It must be called during Init Level 0.
+ *
+ * Returns:
+ *	nothing
+ */
+void	SkEventInit(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	Ioc,	/* I/O Context */
+int		Level)	/* Init Level */
+{
+	switch (Level) {
+	case SK_INIT_DATA:
+		pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue;
+		break;
+	default:
+		break;
+	}
+}
+
+/******************************************************************************
+ *
+ *	SkEventQueue() - add event to queue
+ *
+ * Description:
+ *	This function adds an event to the event queue.
+ *	At least Init Level 1 is required to queue events,
+ *	but will be scheduled at Init Level 2.
+ *
+ * returns:
+ *	nothing
+ */
+void	SkEventQueue(
+SK_AC		*pAC,	/* Adapter Context */
+SK_U32		Class,	/* Event Class */
+SK_U32		Event,	/* Event to be queued */
+SK_EVPARA	Para)	/* Event Parameter */
+{
+
+	if (pAC->GIni.GILevel == SK_INIT_DATA) {
+		SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG);
+		return;
+	}
+
+	SK_EVENT_LOCK_ACQUIRE(pAC);
+
+	if (pAC->Event.EvPut < &pAC->Event.EvQueue[SK_MAX_EVENT]) {
+		pAC->Event.EvPut->Class = Class;
+		pAC->Event.EvPut->Event = Event;
+		pAC->Event.EvPut->Para = Para;
+
+		if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT]) {
+			pAC->Event.EvPut = pAC->Event.EvQueue;
+		}
+	}
+
+	SK_EVENT_LOCK_RELEASE(pAC);
+
+	if (pAC->Event.EvPut == pAC->Event.EvGet) {
+		SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
+	}
+}
+
+/******************************************************************************
+ *
+ *	SkEventDispatcher() - Event Dispatcher
+ *
+ * Description:
+ *	The event dispatcher performs the following operations:
+ *		while event queue is not empty
+ *			- get event from queue
+ *			- send event to state machine
+ *
+ * CAUTION:
+ *	The event functions MUST report an error if performing a reinitialization
+ *	of the event queue, e.g. performing Init Level 0..2 while in dispatcher call!
+ *	ANY OTHER return value delays scheduling the other events in the queue.
+ *	In this case the event blocks the queue until the error condition is cleared!
+ *
+ * Returns:
+ *	The return value error reported by individual event function
+ */
+int	SkEventDispatcher(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SK_EVENTELEM	*pEv;	/* pointer into queue */
+	SK_U32			Class;
+	int			Rtv;
+
+	if (pAC->GIni.GILevel != SK_INIT_RUN) {
+		SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG);
+	}
+
+	pEv = pAC->Event.EvGet;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_QUEUE,
+		("Dispatch get 0x%x, put 0x%x\n", (SK_U32)pEv, (SK_U32)pAC->Event.EvPut));
+
+	if (!SK_EVENT_MUTEX_ACQUIRE(pAC)) {
+		/* another thread is already dispatching events */
+		return 0;
+	}
+
+	Rtv = 0;
+	while (pEv != pAC->Event.EvPut) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_QUEUE,
+			("Dispatch Class %d, Event %d\n", pEv->Class, pEv->Event));
+
+		switch (Class = pEv->Class) {
+#ifndef SK_USE_LAC_EV
+#ifndef SK_SLIM
+#ifndef SK_NO_RLMT
+		case SKGE_RLMT:		/* RLMT Event */
+			Rtv = SkRlmtEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#endif /* !SK_NO_RLMT */
+		case SKGE_I2C:		/* I2C Event */
+			Rtv = SkI2cEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#ifndef SK_NO_PNMI
+		case SKGE_PNMI:		/* PNMI Event */
+			Rtv = SkPnmiEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#endif /* !SK_NO_PNMI */
+#endif	/* not SK_SLIM */
+#endif	/* not SK_USE_LAC_EV */
+		case SKGE_DRV:		/* Driver Event */
+			Rtv = SkDrvEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#ifndef SK_USE_SW_TIMER
+		case SKGE_HWAC:
+			Rtv = SkGeSirqEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#else /* !SK_USE_SW_TIMER */
+		case SKGE_SWT :
+			Rtv = SkSwtEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#endif /* !SK_USE_SW_TIMER */
+#if defined(SK_USE_LAC_EV) || defined(SK_LBFO)
+		case SKGE_LACP :
+			Rtv = SkLacpEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+		case SKGE_RSF :
+			Rtv = SkRsfEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+		case SKGE_MARKER :
+			Rtv = SkMarkerEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+		case SKGE_FD :
+			Rtv = SkFdEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#endif /* SK_USE_LAC_EV */
+#ifdef SK_ASF
+		case SKGE_ASF :
+			Rtv = SkAsfEvent(pAC,IoC,pEv->Event,pEv->Para);
+			break ;
+#endif
+#ifdef	SK_USE_CSUM
+		case SKGE_CSUM :
+			Rtv = SkCsEvent(pAC, IoC, pEv->Event, pEv->Para);
+			break;
+#endif	/* SK_USE_CSUM */
+		default :
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, SKERR_Q_E002MSG);
+			Rtv = 0;
+		}
+
+		if (Rtv != 0) {
+			/*
+			 * Special Case: See CAUTION statement above.
+			 * We assume the event queue is reset.
+			 */
+			if (pAC->Event.EvGet != pAC->Event.EvQueue &&
+				pAC->Event.EvGet != pEv) {
+				/*
+				 * Create an error log entry if the event queue isn't reset.
+				 * In this case it may be blocked.
+				 */
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG);
+			}
+
+			break;
+		}
+
+		if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT]) {
+
+			pEv = pAC->Event.EvQueue;
+		}
+
+		/* Renew get: it is used in queue_events to detect overruns */
+		pAC->Event.EvGet = pEv;
+	}
+
+	SK_EVENT_MUTEX_RELEASE(pAC);
+	return(Rtv);
+}
+
+/* End of file */
diff -ruN linux/drivers/net/sk98lin/skspi.c linux-new/drivers/net/sk98lin/skspi.c
--- linux/drivers/net/sk98lin/skspi.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skspi.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1806 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/flashfun/V2/skspi.c#10 $
+ * Project:	Flash Programmer, Manufacturing and Diagnostic Tools
+ * Version:	$Revision: #10 $, $Change: 4280 $
+ * Date:	$DateTime: 2010/11/05 11:55:33 $
+ * Purpose:	Contains SPI-Flash EEPROM specific functions
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#ifndef SK_SPI_NO_UPDATE
+#ifdef MRVL_UEFI
+#include <stdlib.h>
+#endif /* !MRVL_UEFI */
+#endif /* !SK_SPI_NO_UPDATE */
+#include "h/skdrv2nd.h"
+
+
+/* defines *******************************************************************/
+
+/* SPI flash types of max. 1 MB (8Mbit) are currently supported */
+#define MAX_SPI_FLASH_SIZE			0x100000L			
+
+/* man_name, man_id */
+#define SPI_MAN_ATMEL		"Atmel",	SPI_MAN_ID_ATMEL
+#define SPI_MAN_INTEL		"Intel",	SPI_MAN_ID_INTEL
+#define SPI_MAN_WBOND		"WinBnd",	SPI_MAN_ID_WINBOND
+#define SPI_MAN_SST			"SST",		SPI_MAN_ID_SST
+#define SPI_MAN_NUMONYX		"Numonyx",	SPI_MAN_ID_NUMONYX
+#define SPI_MAN_NUM			"Numonyx",	SPI_MAN_ID_NUM
+#define SPI_MAN_ST			"ST"
+#define SPI_MAN_CHTEK		"ChTek",	SPI_MAN_ID_CHTEK
+#define SPI_MAN_MXIC		"MXIC",		SPI_MAN_ID_MXIC
+
+/* RARAtbd determine id_byte_count and dev_id2 where the latter is "-0" */
+
+/* dev_name, dev_id, sector_size, sector_num, set_protocol, clk_rate_div, id_byte_count, dev_id2 */
+#define SPI_AT25F2048		"AT25F2048",	 0x63, 0x10000,   4, 0, 0, 1, 0
+#define SPI_AT25F1024		"AT25F1024",	 0x60, 0x8000,    4, 0, 0, 1, 0
+#define SPI_AT25DF021		"AT25DF021",	 0x43, 0x1000,   64, 0, 0, 3, 0
+#define SPI_AT25DF041A		"AT25DF041A",	 0x44, 0x1000,  128, 0, 0, 3, 1
+#define SPI_AT26DF081A		"AT26DF081A",	 0x45, 0x1000,  256, 0, 0, 3, 1
+#define SPI_AT26DF161A		"AT26DF161A",	 0x46, 0x1000,  512, 0, 0, 3, 1
+#define SPI_AT26DF321		"AT26DF321",	 0x47, 0x1000, 1024, 0, 0, 3, 0
+#define SPI_AT25FS010		"AT25FS010",	 0x66, 0x1000,   32, 0, 0, 2, 1
+#define SPI_AT25FS040		"AT25FS040",	 0x66, 0x1000,   32, 0, 0, 2, 4
+#define SPI_QB25F016S33B8	"QB25F016S33B8", 0x89, 0x10000,  32, 0, 0, 1, -0
+#define SPI_W25X10			"W25X10",		 0x10, 0x1000,   32, 1, 1, 1, -0
+#define SPI_SST25VF512		"SST25VF512",	 0x48, 0x1000,   16, 1, 0, 1, -0
+#define SPI_SST25VF010		"SST25VF010/SST25VF010A",	 0x49, 0x1000,   32, 1, 0, 1, -0
+#define SPI_SST25VF020		"SST25VF020",	 0x43, 0x1000,   64, 1, 0, 1, -0
+#define SPI_SST25VF040		"SST25VF040",	 0x44, 0x1000,  128, 1, 0, 1, -0
+#define SPI_SST25VF040B		"SST25VF040B",	 0x8d, 0x1000,  128, 1, 0, 1, -0
+#define SPI_X_M25P80		"M25P80",		 0x20, 0x10000,  16, 0, 0, 2, 0x13
+#define SPI_X_M25P20		"M25P20",		 0x20, 0x10000,	  4, 0, 0, 2, 0x11
+#define SPI_X_M25P10A		"M25P10A",		 0x20, 0x8000,	  4, 0, 0, 2, 0x10
+#define SPI_M25P80			"M25P80",		 0x20, 0x10000,  16, 1, 0, 1, -0
+#define SPI_ST_M25P80		"ST M25P80",	 0x13, 0x10000,  16, 1, 0, 1, -0
+#define SPI_M25P20			"M25P20",		 0x11, 0x10000,   4, 1, 0, 1, -0
+#define SPI_M25P10			"M25P10",		 0x10, 0x8000,    4, 1, 0, 1, -0
+#define SPI_Pm25LV512A		"Pm25LV512A",	 0x7b, 0x1000,   16, 1, 0, 1, -0
+#define SPI_Pm25LV010A		"Pm25LV010A",	 0x7c, 0x1000,   32, 1, 0, 1, -0
+#define SPI_Pm25LV020		"Pm25LV020",	 0x7d, 0x1000,   64, 1, 0, 1, -0
+#define SPI_Pm25LV040		"Pm25LV040",	 0x7e, 0x1000,  128, 1, 0, 1, -0
+#define SPI_Pm25LD010C		"Pm25LD010C",	 0x10, 0x1000,   32, 1, 0, 1, -0
+#define SPI_Pm25LD020C		"Pm25LD020C",	 0x11, 0x1000,   64, 1, 0, 1, -0
+#define SPI_MX25L200x		"MX25L2005/MX25L2006E",	 0x11,  0x1000, 64, 1, 0, 1, -0
+#define SPI_MX25L400x		"MX25L4005A/MX25L4005C/MX25L4006E",	 0x12,  0x1000, 128, 1, 0, 1, -0
+
+/* op_read, op_write, op_write_enable, op_write_disable, op_read_status */
+#define SPI_CMDS_GENERIC	0x03, 0x02, 0x06, 0x04, 0x05
+
+/* op_read, op_write_aai, op_write_enable, op_write_disable, op_read_status */
+#define SPI_CMDS_SST_GENERIC	0x03, 0xad, 0x06, 0x04, 0x05
+
+
+/* GENERICS, op_read_id, op_sector_erase, op_chip_erase, op_write_status, op_read_sect_protect */
+#define SPI_CMDS_ATMEL_F	{SPI_CMDS_GENERIC, 0x15, 0x52, 0x62, 0, 0}
+#define SPI_CMDS_ATMEL_DF	{SPI_CMDS_GENERIC, 0x9f, 0x20, 0x60, 1, 0x3c}
+#define SPI_CMDS_ATMEL_FS	{SPI_CMDS_GENERIC, 0xab, 0x20, 0xc7, 0, 0}
+#define SPI_CMDS_INTEL		{SPI_CMDS_GENERIC, 0x9f, 0xd8, 0xc7, 0, 0}
+#define SPI_CMDS_WINBOND	{SPI_CMDS_GENERIC, 0x90, 0x20, 0xc7, 0, 0}
+#define SPI_CMDS_SST		{SPI_CMDS_GENERIC, 0x90, 0x20, 0x60, 0, 0}
+#define SPI_CMDS_SST_040B	{SPI_CMDS_SST_GENERIC, 0x90, 0x20, 0x60, 0, 0}
+#define SPI_CMDS_ST			{SPI_CMDS_GENERIC, 0xab, 0xd8, 0xc7, 0, 0}
+#define SPI_CMDS_CHTEK		{SPI_CMDS_GENERIC, 0xab, 0xd7, 0xc7, 0, 0}
+#define SPI_CMDS_CHTEK_LD	{SPI_CMDS_GENERIC, 0x90, 0xd7, 0xc7, 0, 0}
+#define SPI_CMDS_MXIC		{SPI_CMDS_GENERIC, 0x90, 0x20, 0xc7, 0, 0}
+
+
+/* typedefs ******************************************************************/
+
+/* function prototypes *******************************************************/
+
+#ifdef Core
+#define fl_print	pAC->Gui.WPrint
+#elif defined(VCPU)
+#define fl_print	c_print
+#else
+extern void fl_print(char *str, ...);
+#endif /* Core */
+
+/* low level SPI programming external interface */
+extern int  spi_timer(SK_AC *pAC, unsigned int);
+#ifndef SK_SPI_NO_UPDATE
+extern void *spi_malloc(unsigned long);
+extern void spi_free(void *);
+#endif	/* !SK_SPI_NO_UPDATE */
+
+/* global variables **********************************************************/
+
+/* local variables ***********************************************************/
+
+/*
+ * Yukon-II family SPI flash device table
+ *
+ *											timeout for chip erase
+ *											  |
+ *											 \/	
+ */
+SK_SPI_DEVICE spi_yuk2_dev_table[] = {
+	{SPI_MAN_ATMEL,		SPI_AT25F2048,		10, SPI_CMDS_ATMEL_F},
+	{SPI_MAN_ATMEL,		SPI_AT25F1024,		 6, SPI_CMDS_ATMEL_F},
+	{SPI_MAN_ATMEL,		SPI_AT25DF021,		 6, SPI_CMDS_ATMEL_DF},
+	{SPI_MAN_ATMEL,		SPI_AT25DF041A,		10, SPI_CMDS_ATMEL_DF},
+	{SPI_MAN_ATMEL,		SPI_AT26DF081A,		20, SPI_CMDS_ATMEL_DF},
+	{SPI_MAN_ATMEL,		SPI_AT26DF161A,		40, SPI_CMDS_ATMEL_DF},
+	{SPI_MAN_ATMEL,		SPI_AT26DF321,		65, SPI_CMDS_ATMEL_DF},
+	{SPI_MAN_ATMEL,		SPI_AT25FS010,		30, SPI_CMDS_ATMEL_FS},
+	{SPI_MAN_ATMEL,		SPI_AT25FS040,		10, SPI_CMDS_ATMEL_FS},
+	{SPI_MAN_INTEL,		SPI_QB25F016S33B8, 140, SPI_CMDS_INTEL},
+	{SPI_MAN_WBOND,		SPI_W25X10,			10, SPI_CMDS_WINBOND},
+	{SPI_MAN_SST,		SPI_SST25VF512,		 2, SPI_CMDS_SST},
+	{SPI_MAN_SST,		SPI_SST25VF010,		 2, SPI_CMDS_SST},
+	{SPI_MAN_SST,		SPI_SST25VF020,		 2, SPI_CMDS_SST},
+	{SPI_MAN_SST,		SPI_SST25VF040,		 2, SPI_CMDS_SST},
+	{SPI_MAN_SST,		SPI_SST25VF040B,	 2, SPI_CMDS_SST_040B},
+	{SPI_MAN_NUMONYX,	SPI_X_M25P80,		30, SPI_CMDS_INTEL},
+	{SPI_MAN_NUMONYX,	SPI_X_M25P20,		10, SPI_CMDS_INTEL},
+	{SPI_MAN_NUMONYX,	SPI_X_M25P10A,		15, SPI_CMDS_INTEL},
+	{SPI_MAN_NUM,		SPI_M25P80,			99, SPI_CMDS_ST},
+	{SPI_MAN_CHTEK,		SPI_Pm25LD010C,		 2, SPI_CMDS_CHTEK_LD},
+	{SPI_MAN_CHTEK,		SPI_Pm25LD020C,		 2, SPI_CMDS_CHTEK_LD},
+	{SPI_MAN_MXIC,		SPI_MX25L200x,		10, SPI_CMDS_MXIC},
+	{SPI_MAN_MXIC,		SPI_MX25L400x,		10, SPI_CMDS_MXIC},
+	{SPI_MAN_ST,  0x13,	SPI_ST_M25P80,		99, SPI_CMDS_ST},
+	{SPI_MAN_ST,  0x11,	SPI_M25P20,			99, SPI_CMDS_ST},
+	{SPI_MAN_ST,  0x10,	SPI_M25P10,			99, SPI_CMDS_ST},
+	{SPI_MAN_CHTEK,		SPI_Pm25LV512A,		 2, SPI_CMDS_CHTEK},
+	{SPI_MAN_CHTEK,		SPI_Pm25LV010A,		 2, SPI_CMDS_CHTEK},
+	{SPI_MAN_CHTEK,		SPI_Pm25LV020,		 2, SPI_CMDS_CHTEK},
+	{SPI_MAN_CHTEK,		SPI_Pm25LV040,		 2, SPI_CMDS_CHTEK},
+};
+
+/* local functions ***********************************************************/
+
+/*****************************************************************************
+ *
+ * spi_yuk_flash_erase - Erases sectors of the SPI Eprom
+ *
+ * Description:
+ *	This function erases sectors of the SPI Eprom.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk_flash_erase(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	off,	/* start offset in flash eprom for erase */
+unsigned long	len)	/* length in flash eprom for erase */
+{
+	char			cr;
+	unsigned long	creg, i;
+
+	if ((off + len - 1) > 0x1ffffL) {
+		return (1);	/* more than 4 segments for erase */
+	}
+
+	/* Save SPI control register */
+	SK_IN32(IoC, SPI_CTRL_REG, &creg);
+
+#ifdef XXX
+	/* there is some problem with chip erase. dr */
+
+	/*
+	 * RA:	Additionally, the newer SPI EPROM AT25FS010 used with
+	 *		some 88E8001 chips uses a different code for chip erase.
+	 */
+
+	/* use faster chip erase command if all sectors should be erased */
+	if (len > SPI_SECT_SIZE * 3L) {
+
+		SK_OUT32(IoC, SPI_CTRL_REG, SPI_CHIP_ERASE);
+
+		spi_timer(pAC, SPI_TIMER_SET);
+
+		do {
+			if (spi_timer(pAC, SPI_TIMEOUT)) {
+				fl_print("\nSPI chip erase timeout: %d sec\n", SPI_TIMER_SET);
+				return (1);
+			}
+
+			/* Read device status */
+			SK_IN8(IoC, SPI_CTRL_REG, &cr);
+		} while (cr & 1);		/* is chip busy? */
+
+		/* Restore SPI control register */
+		SK_OUT32(IoC, SPI_CTRL_REG, creg);
+
+		return (0);
+	}
+#endif
+
+	for (i = (off >> 15); i <= ((off + len - 1) >> 15); i++) {
+		/* Clear chip command */
+		SK_OUT32(IoC, SPI_CTRL_REG, (i << 22) | SPI_SECT_ERASE);
+
+		spi_timer(pAC, SPI_TIMER_SET);
+
+		do {
+			if (spi_timer(pAC, SPI_TIMEOUT)) {
+				fl_print("\nSPI chip erase timeout: %d sec\n", SPI_TIMER_SET);
+				return (1);
+			}
+
+			/* Read device status */
+			SK_IN8(IoC, SPI_CTRL_REG, &cr);
+		} while (cr & 1);		/* is chip busy ? */
+	}
+
+	/* Restore SPI control register */
+	SK_OUT32(IoC, SPI_CTRL_REG, creg);
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * rol2 - Rotates a 16-bit value left by 2
+ *
+ * Description:
+ *	This function rotates a 16-bit value left by 2.
+ *
+ * Returns:
+ *	Address
+ */
+static unsigned short rol2(
+SK_AC			*pAC,
+unsigned short	addr)
+{
+	/* YUKON-Lite Rev. A1 */
+	if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_LITE) {
+
+		/* switch address bits [1:0] with [14:13] */
+		addr = ((addr >> 13) & 0x0003) | ((addr << 2) & 0x7ffc);
+	}
+
+	return (addr);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk_flash_manage - Reads, verifies or writes SPI Eprom
+ *
+ * Description:
+ *	This function reads, verifies or writes the SPI Eprom.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk_flash_manage(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom for operation */
+unsigned long	len,	/* length in flash eprom */
+int				flag)	/* action SPI_READ / SPI_VERIFY / SPI_WRITE */
+{
+	unsigned long	a1, a2, cr, i;
+	unsigned short	addr, as, ret=0;
+	unsigned char	ch, tr;
+	unsigned long	progress;
+	unsigned long	last_progress;
+
+	/* Save VPD lower address */
+	SK_IN32(IoC, SPI_ADR_REG1, &a1);
+
+	/* Save VPD higher address */
+	SK_IN32(IoC, SPI_ADR_REG2, &a2);
+
+	/* Set VPD lower address to 0 (15 higher bit) */
+	SK_OUT32(IoC, SPI_ADR_REG1, SPI_VPD_MIN);
+
+	/* Set VPD higher address to 0x7fff (15 higher bit) */
+	SK_OUT32(IoC, SPI_ADR_REG2, SPI_VPD_MAX);
+
+	/* Save SPI control register */
+	SK_IN32(IoC, SPI_CTRL_REG, &cr);
+
+	/* Enable VPD to SPI mapping (set bit 19) */
+	SK_OUT32(IoC, SPI_CTRL_REG, SPI_VPD_MAP);
+
+	/* Save Test Control Register 1 */
+	SK_IN8(IoC, B2_TST_REG1, &tr);
+
+	/* Enable write to mapped PCI config register file */
+	SK_OUT8(IoC, B2_TST_REG1, 2);
+
+	progress = last_progress = 0;
+
+	for (i = off, addr = (unsigned short)(off >> 2); i < off + len; i++) {
+		progress = (i * 100) / len;
+
+#ifdef MRVL_UEFI
+		if ((progress - last_progress) >= 20) {
+			w_print(".");
+			last_progress += 20;
+		}
+#else	/*  MRVL_UEFI */
+		if ((progress - last_progress) >= 10) {
+			fl_print(".");
+			last_progress += 10;
+		}
+#endif	/*  MRVL_UEFI */
+
+		/* Set new address to VPD Address reg, initiate reading */
+		if ((i % 4) == 0) {
+
+			SK_OUT16(IoC, VPD_ADR_REG, rol2(pAC, addr));
+			addr++;
+
+			/* Wait for termination */
+			spi_timer(pAC, SPI_TIMER_SET);
+
+			do {
+				/* Read VPD_ADDR reg for flag check */
+				SK_IN16(IoC, VPD_ADR_REG, &as);
+
+				if (spi_timer(pAC, SPI_TIMEOUT)) {
+					fl_print("\nSPI read timeout: %d sec. Offset:0x%05lx\n",
+						SPI_TIMER_SET, i);
+					ret = 1;
+					break;
+				}
+			} while (!(as & VPD_FLAG_MASK)); /* check  flag */
+
+			if (ret != 0) {
+				break;
+			}
+		}
+
+		switch (flag) {
+		case SPI_READ:
+			/* Read byte from VPD port */
+			SK_IN8(IoC, (unsigned short)(VPD_DATA_PORT + i % 4), &ch);
+			*(data++) = ch;
+			break;
+		case SPI_VERIFY:
+			/* Read and verify byte from VPD port */
+			SK_IN8(IoC, (unsigned short)(VPD_DATA_PORT + i % 4), &ch);
+			if (ch != *(data++)) {
+				fl_print("\n*** SPI data verify error at address 0x%05lx, "
+					"is %x, should be %x\n", i, ch, *(data - 1));
+				ret = 1;
+			}
+			break;
+		case SPI_WRITE:
+			/* Write byte to VPD port */
+			SK_OUT8(IoC, (unsigned short)(VPD_DATA_PORT +
+				(unsigned short)(i % 4)), *data);
+			data++;
+
+			if ((i % 4) == 3) {
+				/* Set old Address to VPD_ADDR reg, initiate writing */
+				SK_OUT16(IoC, (unsigned short)VPD_ADR_REG, (unsigned short)
+					(rol2(pAC, (unsigned short)(addr - 1)) | VPD_FLAG_MASK));
+
+				/* Wait for termination */
+				spi_timer(pAC, SPI_TIMER_SET);
+
+				do {
+					/* Read VPD_ADDR reg for flag check*/
+					SK_IN16(IoC, VPD_ADR_REG, &as);
+
+					if (spi_timer(pAC, SPI_TIMEOUT)) {
+						fl_print("\nSPI write timeout: %d sec. Offset: 0x%05lx\n",
+							SPI_TIMER_SET, i);
+						ret = 1;
+						break;
+					}
+				} while (as & VPD_FLAG_MASK); /* check  flag */
+			}
+			break;
+		}
+
+		if (ret != 0) {
+			break;
+		}
+	}
+	/* Restore Test Control Register 1 */
+	SK_OUT8(IoC, B2_TST_REG1, tr);
+
+	/* Restore VPD lower address*/
+	SK_OUT32(IoC, SPI_ADR_REG1, a1);
+
+	/* Restore VPD higher address*/
+	SK_OUT32(IoC, SPI_ADR_REG2, a2);
+
+	/* Restore SPI control register */
+	SK_OUT32(IoC, SPI_CTRL_REG, cr);
+
+	fl_print(".");
+	return (ret);
+}
+
+#ifndef SK_SPI_NO_UPDATE
+
+/*****************************************************************************
+ *
+ * spi_yuk_update_config - Updates part of config area
+ *
+ * Description:
+ *	This function updates part of the config area.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk_update_config(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom (config area) for operation */
+unsigned long	len)	/* length of changing data */
+{
+	unsigned char *spibuf;
+	unsigned long i;
+
+	spibuf = spi_malloc((unsigned long)SPI_SECT_SIZE);
+
+	if (spibuf == NULL) {
+		return (51);
+	}
+
+	if (spi_flash_manage(pAC, IoC, spibuf, SPI_LSECT_OFF,
+		SPI_SECT_SIZE, SPI_READ)) {
+
+		spi_free(spibuf);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		spibuf[off + i - SPI_LSECT_OFF] = data[i];
+	}
+
+	if (spi_flash_erase(pAC, IoC, SPI_LSECT_OFF, SPI_SECT_SIZE)) {
+
+		spi_free(spibuf);
+		return (7);
+	}
+
+	if (spi_flash_manage(pAC, IoC, spibuf, SPI_LSECT_OFF,
+		SPI_SECT_SIZE, SPI_WRITE)) {
+
+		spi_free(spibuf);
+		return (8);
+	}
+	spi_free(spibuf);
+	return (0);
+}
+
+#endif	/* !SK_SPI_NO_UPDATE */
+
+/*****************************************************************************
+ *
+ * spi_yuk2_write_enable - Enables writing on the SPI EPROM
+ *
+ * Description:
+ *	This function enables writing on the SPI EPROM.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void spi_yuk2_write_enable(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned long spi_ctrl_reg;
+
+	/* execute write enable command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_WEN;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* wait for the SPI to finish command */
+	SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, SPI_TIMER_SET);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_write_disable - Disables writing on the SPI EPROM
+ *
+ * Description:
+ *	This function disables writing on the SPI EPROM.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void spi_yuk2_write_disable(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned long	op2;
+
+	/* Replace Write Enable opcode by Write Disable opcode */
+	SK_IN32(IoC, SPI_Y2_OPCODE_REG2, &op2);
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, (op2 & 0xffffff00) | 
+				(unsigned long)(pAC->spi.pSpiDev->opcodes.op_write_disable));
+
+	spi_yuk2_write_enable(pAC, IoC);
+
+	/* Restore Write Enable opcode */
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, op2);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_write_status - execute the write status register command
+ *
+ * Description:
+ *	This function execute the write status register command
+ *	to protect or unprotect all sectors of the chip.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk2_write_status(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	Val)	/* value to write (0 = unprotect, 0x3c = protect) */
+{
+	unsigned long	spi_ctrl_reg;
+	unsigned long	op;
+#ifdef SK_DIAG
+	unsigned long	RdVal;
+#endif /* SK_DIAG */
+
+	if (!pAC->spi.needs_unprotect) {
+		/* Chip does not need unprotect before write/erase operation. */
+		return (0);
+	}
+
+	/* enable writing */
+	spi_yuk2_write_enable(pAC, IoC);
+
+	if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT &&
+		pAC->spi.pSpiDev->opcodes.op_read_sect_protect != 0) {
+
+		/* write SPI address */
+		SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, 0);
+
+		/* execute the read sector protection registers command */
+		SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+		spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+		spi_ctrl_reg |= SPI_Y2_RDSP;
+		SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+		/* wait for the SPI to finish RD operation */
+		SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+#ifdef SK_DIAG
+		/* read SPI data */
+		SK_IN32(IoC, SPI_Y2_DATA_REG, &RdVal);
+		c_print("Sector 0 protection before write status is %02x.\n",
+			RdVal >> 24);
+#endif /* SK_DIAG */
+	}
+
+	/* write SPI address */
+	SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, Val | Val << 8 | Val << 16 | Val << 24);
+	/* write SPI data */
+	SK_OUT32(IoC, SPI_Y2_DATA_REG, Val | Val << 8 | Val << 16 | Val << 24);
+
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+
+	if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT &&
+		pAC->spi.pSpiDev->opcodes.op_write_status != 0) {
+
+		/* execute the write status register command */
+		spi_ctrl_reg |= SPI_Y2_WST;
+		SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+		/* wait for the SPI to finish RD operation */
+		SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+	}
+	else {
+		/* change command register 2 */
+		SK_IN32(IoC, SPI_Y2_OPCODE_REG2, &op);
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, (op & 0xff00ffff) | 0x00010000);
+
+		/*
+		 * execute the write status register command
+		 * using the sector erase protocol
+		 */
+		spi_ctrl_reg |= SPI_Y2_SERS;
+		SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+		/* wait for the SPI to finish RD operation */
+		SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+		/* restore command register 2 */
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, op);
+	}
+
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+
+	if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT &&
+		pAC->spi.pSpiDev->opcodes.op_read_sect_protect != 0) {
+
+		/* write SPI address */
+		SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, 0);
+
+		/* execute the read sector protection registers command */
+		SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+		spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+		spi_ctrl_reg |= SPI_Y2_RDSP;
+		SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+		/* wait for the SPI to finish RD operation */
+		SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+#ifdef SK_DIAG
+		/* read SPI data */
+		SK_IN32(IoC, SPI_Y2_DATA_REG, &RdVal);
+		c_print("Sector 0 protection after write status is %02x.\n",
+			RdVal >> 24);
+#endif /* SK_DIAG */
+	}
+
+	return (0);
+}	/* spi_yuk2_write_status */
+
+/*****************************************************************************
+ *
+ * spi_yuk2_read_dword - Reads a DWord from the SPI EPROM
+ *
+ * Description:
+ *	This function reads a DWord from the specified address in the SPI EPROM.
+ *
+ * Returns:
+ *	DWord read from given address
+ */
+static unsigned long spi_yuk2_read_dword(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	address)		/* address in the SPI EPROM to read from */
+{
+	unsigned long reg_val;
+	unsigned long spi_ctrl_reg;
+
+	/* write SPI address */
+	SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, address);
+
+	/* execute SPI read command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_RD;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* wait for the SPI to finish RD operation */
+	SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+	/* read the returned data */
+	SK_IN32(IoC, SPI_Y2_DATA_REG, &reg_val);
+
+	return (reg_val);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_write_dword - Writes a DWord to the SPI EPROM
+ *
+ * Description:
+ *	This function writes a DWord to the specified address in the SPI EPROM.
+ *  The target sector should have been erased previously for the access
+ *	to succeed.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Failure
+ */
+static int spi_yuk2_write_dword(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	address,			/* address to write to */
+unsigned long	value)				/* new value to be written */
+{
+	unsigned long spi_ctrl_reg;
+	unsigned long verify_value;
+
+	spi_yuk2_write_enable(pAC, IoC);
+
+	/* write SPI address */
+	SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, address);
+	/* write the new value */
+	SK_OUT32(IoC, SPI_Y2_DATA_REG, value);
+
+	/* execute the SPI write command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_WR;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* wait for write to finish */
+	SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, SPI_TIMER_SET);
+
+	verify_value = spi_yuk2_read_dword(pAC, IoC, address);
+
+	/* verify if write was successful*/
+	if (verify_value != value) {
+		fl_print("\n*** SPI data write error at address 0x%08lx, "
+			"is 0x%08lx, should be 0x%08lx\n", address, verify_value, value);
+		return (1);
+	}
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_sst_write_dword - Writes a DWord to an SST SPI EPROM
+ *
+ * Description:
+ *	This function writes a DWord to the specified address in an SST SPI EPROM.
+ *  The target sector should have been erased previously for the access
+ *	to succeed.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Failure
+ */
+static int spi_yuk2_sst_write_dword(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	address,		/* address to write to */
+unsigned long	value)			/* new value to be written */
+{
+	unsigned long spi_ctrl_reg;
+	unsigned long verify_value;
+	unsigned long i;
+
+	if (pAC->spi.pSpiDev->dev_id == 0x8d) {
+		/* 
+		 * For SST25VF040B we use auto address increment (AAI) mode 
+		 * to program the SPI flash due to a byte program issue with 
+		 * 80MHz type at the Yukon SPI flash interface.
+		 */
+		for (i = 0; i < 4; i+=2) {
+			spi_yuk2_write_enable(pAC, IoC);
+
+			/* write SPI address */
+			SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, address + i);
+			/* write the new value */
+			SK_OUT32(IoC, SPI_Y2_DATA_REG, (value >> i * 8) & 0x0000ffff);
+
+			/* execute the SPI write command */
+			SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+			spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+			spi_ctrl_reg |= SPI_Y2_WR;
+			SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+			/* wait for write to finish */
+			SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, SPI_TIMER_SET);
+
+			spi_yuk2_write_disable(pAC, IoC);
+
+			verify_value = spi_yuk2_read_dword(pAC, IoC, address);
+
+			/* verify if write was successful*/
+			if (((verify_value >> i * 8) & 0x0000ffff) !=
+				((value >> i * 8) & 0x0000ffff)) {
+
+				fl_print("\n*** SPI data write error at address 0x%08lx, "
+					"is 0x%08lx, should be 0x%08lx\n", address + i,
+					((verify_value >> i * 8) & 0x0000ffff),
+					((value >> i * 8) & 0x0000ffff));
+				return (1);
+			}
+		}
+	}
+	else {
+		for (i = 0; i < 4; i++) {
+			spi_yuk2_write_enable(pAC, IoC);
+
+			/* write SPI address */
+			SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, address + i);
+			/* write the new value */
+			SK_OUT32(IoC, SPI_Y2_DATA_REG, (value >> i * 8) & 0x000000ff);
+
+			/* execute the SPI write command */
+			SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+			spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+			spi_ctrl_reg |= SPI_Y2_WR;
+			SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+			/* wait for write to finish */
+			SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, SPI_TIMER_SET);
+
+			verify_value = spi_yuk2_read_dword(pAC, IoC, address);
+
+			/* verify if write was successful*/
+			if (((verify_value >> i * 8) & 0x000000ff) !=
+				((value >> i * 8) & 0x000000ff)) {
+
+				fl_print("\n*** SPI data write error at address 0x%08lx, "
+					"is 0x%08lx, should be 0x%08lx\n", address + i,
+					((verify_value >> i * 8) & 0x000000ff),
+					((value >> i * 8) & 0x000000ff));
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_sst_clear_write_protection - Enables writing on an SST SPI EPROM
+ *
+ * Description:
+ *	This function clears the write protection bits for SST flash types because
+ *  they are set by default.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void spi_yuk2_sst_clear_write_protection(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned long	spi_ctrl_reg;
+	unsigned long	op1;
+	unsigned long	op2;
+	unsigned long	addr;
+	unsigned char	status;
+
+	/* change command registers */
+	SK_IN32(IoC, SPI_Y2_OPCODE_REG1, &op1);
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG1, (op1 & 0xffff00ff) | 0x00000100);
+
+	SK_IN32(IoC, SPI_Y2_OPCODE_REG2, &op2);
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, (op2 & 0xffffff00) | 0x00000050);
+
+	/* execute write status register enable command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_WEN;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* wait for the SPI to finish RD operation */
+	SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	status = (unsigned char)(spi_ctrl_reg & 0xfffffff3);
+	addr = ((unsigned long)status | (unsigned long)(status << 8) |
+		(unsigned long)(status << 16) | (unsigned long)(status << 24));
+
+	/* write SPI address */
+	SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, addr);
+	/* write the new value */
+	SK_OUT32(IoC, SPI_Y2_DATA_REG, addr);
+
+	/* execute the write status register command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_RD;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* wait for the SPI to finish RD operation */
+	SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+
+	/* restore command registers */
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG1, op1);
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, op2);
+}	/* spi_yuk2_sst_clear_write_protection */
+
+/*****************************************************************************
+ *
+ * spi_yuk2_erase_sector - Erases one sector of the SPI EPROM
+ *
+ * Description:
+ *	This function erases one sector of the SPI EPROM.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void spi_yuk2_erase_sector(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	sector_num)		/* sector to be erased */
+{
+	unsigned long spi_ctrl_reg;
+
+	spi_yuk2_write_enable(pAC, IoC);
+
+	/* write sector start address */
+	SK_OUT32(IoC, SPI_Y2_ADDRESS_REG, pAC->spi.pSpiDev->sector_size * sector_num);
+
+	/* execute erase sector command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_SERS;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, SPI_TIMER_SET);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_erase_chip - Erases the SPI EPROM
+ *
+ * Description:
+ *	This function erases the complete SPI EPROM.
+ *	Timeout for chip erase / bulk erase varies widely
+ *	between chips and manufacturers.
+ *
+ * Returns:
+ *	Nothing
+ */
+static void spi_yuk2_erase_chip(
+SK_AC		*pAC,
+SK_IOC		IoC,
+unsigned	Timeout)
+{
+	unsigned long spi_ctrl_reg;
+
+	spi_yuk2_write_enable(pAC, IoC);
+
+	/* execute erase chip command */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+	spi_ctrl_reg &= ~SPI_Y2_CMD_MASK;
+	spi_ctrl_reg |= SPI_Y2_CERS;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	SPI_Y2_WAIT_SE_FINISH_WR(pAC, IoC, Timeout);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_read_chip_id - Reads the SPI vendor and device ID
+ *
+ * Description:
+ *	This function reads the SPI vendor and device ID.
+ *
+ * Returns:
+ *	The lower byte contains the device ID and the upper byte the vendor ID
+ */
+static unsigned long spi_yuk2_read_chip_id(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned long	chip_id;
+	unsigned long	spi_ctrl_reg;
+	unsigned long	opcode_reg1;
+
+	/* Workaround for Yukon-Extreme SPI issue */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+
+	spi_ctrl_reg &= SPI_Y2_CLK_DIV_MASK;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	/* Set read id opcode for currently selected flash */
+	SK_IN32(IoC, SPI_Y2_OPCODE_REG1, &opcode_reg1);
+	opcode_reg1 &= 0xff00ffffL;
+	opcode_reg1 |= (unsigned long)pAC->spi.pSpiDev->opcodes.op_read_id << 16;
+	SK_OUT32(IoC, SPI_Y2_OPCODE_REG1, opcode_reg1);
+
+	/* Read SPI control register */
+	SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+
+	spi_ctrl_reg &=
+		~(SPI_Y2_CMD_MASK | SPI_Y2_ID_BYTE_COUNT_MASK | SPI_Y2_RDID_PROT);
+
+	if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT) {
+		/* Select byte count for chip id readout */
+		spi_ctrl_reg |= pAC->spi.pSpiDev->id_byte_count << 20;
+	}
+
+	/* Select protocol for chip id readout */
+	if (pAC->spi.pSpiDev->set_protocol) {
+		spi_ctrl_reg |= SPI_Y2_RDID_PROT;
+	}
+
+	/* Execute read chip id command */
+	spi_ctrl_reg |= SPI_Y2_RDID;
+	SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+
+	SPI_Y2_WAIT_SE_FINISH_CMD(pAC, IoC, SPI_TIMER_SET);
+
+	SK_IN32(IoC, SPI_Y2_VENDOR_DEVICE_ID_REG, &chip_id);
+
+	return (chip_id);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_set_dev_ptr - Identifies the SPI device and sets a pointer
+ *
+ * Description:
+ *	This function identifies the SPI device and
+ *	sets the pointer to its device table entry.
+ *
+ * Returns:
+ *	pAC->spi.pSpiDev == NULL: unknown or no flash device
+ *	pAC->spi.pSpiDev != NULL: pointer to flash device table entry
+ */
+static void spi_yuk2_set_dev_ptr(
+SK_AC	*pAC,
+SK_IOC	IoC)
+{
+	unsigned long	spi_chip_id;
+	unsigned char	man_id;
+	unsigned char	dev_id;
+	unsigned char	dev_id2 = 0;
+	unsigned long	spi_ctrl_reg;
+	unsigned int	i;
+
+	/* Search for flash in device table. */
+	for (i = 0; i < (sizeof(spi_yuk2_dev_table) / sizeof(SK_SPI_DEVICE)); i++) {
+		if ((pAC->spi.yk_chip_id != CHIP_ID_YUKON_EC_U &&
+			 pAC->spi.yk_chip_id != CHIP_ID_YUKON_EX &&
+			 pAC->spi.yk_chip_id < CHIP_ID_YUKON_SUPR &&
+			 spi_yuk2_dev_table[i].man_id == SPI_MAN_ID_ATMEL) ||
+			(pAC->spi.yk_chip_id < CHIP_ID_YUKON_OPT &&
+			 spi_yuk2_dev_table[i].id_byte_count == 2)) {
+
+			continue;
+		}
+
+		/* Used by e.g. spi_yuk2_read_chip_id(). */
+		pAC->spi.pSpiDev = &spi_yuk2_dev_table[i];
+
+		spi_chip_id = spi_yuk2_read_chip_id(pAC, IoC);
+
+		if (pAC->spi.yk_chip_id < CHIP_ID_YUKON_OPT) {
+			man_id = (unsigned char)((spi_chip_id & SPI_Y2_MAN_ID_MASK) >> 8);
+			dev_id = (unsigned char)(spi_chip_id & SPI_Y2_DEV_ID_MASK);
+		}
+		else {
+			man_id  = (unsigned char)(spi_chip_id & 0xff);
+			dev_id  = (unsigned char)((spi_chip_id >> 8) & 0xff);
+			dev_id2 = 0;
+
+			if (pAC->spi.pSpiDev->id_byte_count != 1) {
+				dev_id2 = (unsigned char)((spi_chip_id >> 16) & 0xff);
+			}
+		}
+
+		if (spi_yuk2_dev_table[i].man_id == man_id &&
+			spi_yuk2_dev_table[i].dev_id == dev_id &&
+			(pAC->spi.yk_chip_id < CHIP_ID_YUKON_OPT ||
+			 spi_yuk2_dev_table[i].dev_id2 == dev_id2)) {
+
+			if (pAC->spi.yk_chip_id < CHIP_ID_YUKON_OPT ||
+				pAC->spi.pSpiDev->id_byte_count == 1) {
+
+				fl_print("\nFlash Device: %s (VID 0x%2.2x, DID 0x%2.2x)\n",
+					spi_yuk2_dev_table[i].dev_name, man_id, dev_id);
+			}
+			else {
+				fl_print("\nFlash Device: %s (VID 0x%2.2x, DID 0x%2.2x, "
+					"DID2 0x%2.2x)\n", spi_yuk2_dev_table[i].dev_name,
+					man_id, dev_id, dev_id2);
+			}
+
+			if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT) {
+				SK_IN32(IoC, SPI_Y2_CONTROL_REG, &spi_ctrl_reg);
+
+				spi_ctrl_reg &= ~SPI_Y2_CLK_DIV_MASK;
+				/* Set SPI clock rate divider. */
+				spi_ctrl_reg |= SPI_Y2_CLK_DIV(pAC->spi.pSpiDev->clk_rate_div);
+				SK_OUT32(IoC, SPI_Y2_CONTROL_REG, spi_ctrl_reg);
+			}
+			return;
+		}
+	}
+
+	pAC->spi.pSpiDev = NULL;
+	return;
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_flash_erase - Erases sectors touched by address range
+ *
+ * Description:
+ *	This function erases all sectors of the flash prom affected by
+ *	the address range denoted by parameters "off" (address offset)
+ *	and "len" (length of address range).
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk2_flash_erase(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	off,	/* start offset in flash eprom for erase */
+unsigned long	len)	/* length in flash eprom for erase */
+{
+	SK_SPI_DEVICE	*pSpiDev;
+	unsigned long	flash_size;
+	unsigned long	i;
+	unsigned long	StartSector;
+	unsigned long	EndSector;
+
+	if (len == 0) {
+		return (0);
+	}
+
+	pSpiDev = pAC->spi.pSpiDev;
+	flash_size = pSpiDev->sector_size * pSpiDev->sector_num;
+
+	/*
+	 * If flash size is smaller than address range
+	 * which should be erased, don't erase flash.
+	 */
+	if ((off + len - 1) > flash_size) {
+		return (1);
+	}
+
+	StartSector = off / pSpiDev->sector_size;
+	EndSector   = (off + len - 1) / pSpiDev->sector_size;
+
+	/* Unprotect if necessary */
+	if (spi_yuk2_write_status(pAC, IoC, 0) != 0) {
+		return (1);
+	}
+
+	if (StartSector == 0 && EndSector == pSpiDev->sector_num - 1) {
+		fl_print("\nAllowing for up to %d seconds\nfor chip erase to complete.\n",
+			pSpiDev->chip_erase_timeout);
+
+		/* Erase complete flash. */
+		spi_yuk2_erase_chip(pAC, IoC, pSpiDev->chip_erase_timeout);
+	}
+	else {
+		/* Erase all affected sectors. */
+		for (i = StartSector; i <= EndSector; i++) {
+			spi_yuk2_erase_sector(pAC, IoC, i);
+		}
+	}
+
+	/* Re-protect if necessary */
+	if (spi_yuk2_write_status(pAC, IoC, 0x3c) != 0) {
+		return (1);
+	}
+
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * spi_yuk2_flash_manage - Reads, verifies, or writes SPI EPROM
+ *
+ * Description:
+ *	This function reads, verifies, or writes the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk2_flash_manage(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom for operation */
+unsigned long	len,	/* length in flash eprom */
+int				flag)	/* action SPI_READ / SPI_VERIFY / SPI_WRITE */
+{
+	unsigned long	addr;
+	unsigned long	spi_data;
+	unsigned long	*spi_data_ptr;
+	unsigned long	progress;
+	unsigned long	last_progress;
+	int				ret = 0;
+	unsigned char	ByteVal;
+
+	len = (len + 3) & ~3;
+
+	if ((off & 3) != 0 || (len & 3) != 0) {
+		return (1);
+	}
+
+	if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_EX &&
+		pAC->spi.yk_chip_rev != CHIP_REV_YU_EX_A0 &&
+		pAC->spi.pSpiDev->sector_size * pAC->spi.pSpiDev->sector_num >=
+			0x40000) {
+
+		SK_IN8(IoC, SPI_CFG, &ByteVal);
+		ByteVal |= SPI_CFG_A17_GATE;
+		SK_OUT8(IoC, SPI_CFG, ByteVal);
+	}
+
+	progress = last_progress = 0;
+
+	for (addr = off, spi_data_ptr = (unsigned long *)data;
+		addr < off + len; addr += 4, spi_data_ptr++) {
+
+		progress = ((addr - off) * 100) / len;
+
+#ifdef MRVL_UEFI
+		if ((progress - last_progress) >= 20) {
+			w_print(".");
+			last_progress += 20;
+		}
+#else	/*  MRVL_UEFI */
+		if ((progress - last_progress) >= 10) {
+			fl_print(".");
+			last_progress += 10;
+		}
+#endif	/*  MRVL_UEFI */
+
+		switch (flag) {
+		case SPI_READ:
+			/* Read a dword from SPI flash */
+			*spi_data_ptr = spi_yuk2_read_dword(pAC, IoC, addr);
+			break;
+
+		case SPI_VERIFY:
+			if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_EX &&
+				pAC->spi.max_faddr == 0x1000 &&
+				(addr >> 12) < 0x80 &&
+				pAC->spi.ModifiedPages[addr >> 12] != 1) {
+				/* Do not compare sector that was skipped when writing. */
+#ifdef XXX
+				if ((addr % 4096) == 0) {
+					fl_print("not comparing sector %d\n", addr >> 12);
+				}
+#endif
+				continue;
+			}
+
+			/* Read and verify dword from SPI flash */
+			spi_data = spi_yuk2_read_dword(pAC, IoC, addr);
+
+			if (spi_data != *spi_data_ptr) {
+				fl_print("\n*** SPI data verify error at address 0x%08lx, "
+					"is 0x%08lx, should be 0x%08lx\n", addr, spi_data, *spi_data_ptr);
+				ret = 1;
+			}
+			break;
+
+		case SPI_WRITE:
+			/*
+			 * Flash-only adapters only support flash sector sizes of 4096 bytes.
+			 */
+			if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_EX &&
+				pAC->spi.max_faddr == 0x1000 &&
+				(addr >> 12) < 0x80 &&
+				pAC->spi.ModifiedPages[addr >> 12] != 1) {
+				/*
+				 * Skip sector when writing. Used for special handling
+				 * of e.g. the Config Sector of flash-only adapters.
+				 */
+#ifdef XXX
+				if ((addr % 4096) == 0) {
+					fl_print("not writing to sector %d\n", addr >> 12);
+				}
+#endif
+				continue;
+			}
+
+			/* Unprotect if necessary */
+			if (spi_yuk2_write_status(pAC, IoC, 0) != 0) {
+				return (1);
+			}
+
+			/* Write a dword to SPI flash */
+			if (pAC->spi.pSpiDev->man_id == SPI_MAN_ID_SST) {
+				ret = spi_yuk2_sst_write_dword(pAC, IoC, addr, *spi_data_ptr);
+			}
+			else {
+				ret = spi_yuk2_write_dword(pAC, IoC, addr, *spi_data_ptr);
+			}
+
+			/* Re-protect if necessary */
+			if (spi_yuk2_write_status(pAC, IoC, 0x3c) != 0) {
+				return (1);
+			}
+			break;
+		}
+
+		if (ret != 0) {
+			break;
+		}
+	}
+
+	fl_print(".");
+	return (ret);
+}
+
+#ifndef SK_SPI_NO_UPDATE
+
+/*****************************************************************************
+ *
+ * spi_yuk2_update_config - Updates part of the config area
+ *
+ * Description:
+ *	This function updates part of the config area.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_yuk2_update_config(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom (config area) for operation */
+unsigned long	len)	/* length of changing data */
+{
+	SK_SPI_DEVICE	*pSpiDev;
+	unsigned char	*spibuf;
+	unsigned long	start_sector;
+	unsigned long	end_sector;
+	unsigned long	i;
+
+	pSpiDev = pAC->spi.pSpiDev;
+
+	/* determine the affected sectors */
+	start_sector = off / pSpiDev->sector_size;
+	end_sector   = (off + len - 1) / pSpiDev->sector_size;
+
+	/*
+	 * allocate the necessary memory for temporary
+	 * save of the affected sectors
+	 */
+	spibuf = spi_malloc((unsigned long)((end_sector - start_sector + 1) *
+		pSpiDev->sector_size));
+
+	if (spibuf == NULL) {
+		return (51);
+	}
+
+	/* read out the affected sectors */
+	if (spi_flash_manage(pAC, IoC, spibuf, start_sector * pSpiDev->sector_size,
+		(end_sector - start_sector + 1) * pSpiDev->sector_size,
+		SPI_READ)) {
+
+		spi_free(spibuf);
+		return (1);
+	}
+
+	/* update the just read out data */
+	for (i = 0; i < len; i++) {
+		spibuf[off + i - SPI_LSECT_OFF] = data[i];
+	}
+
+	/* erase the affected sectors */
+	if (spi_flash_erase(pAC, IoC, start_sector * pSpiDev->sector_size,
+		(end_sector - start_sector + 1) * pSpiDev->sector_size)) {
+
+		spi_free(spibuf);
+		return (7);
+	}
+
+	/* write the updated data back to the flash */
+	if (spi_flash_manage(pAC, IoC, spibuf, start_sector * pSpiDev->sector_size,
+		(end_sector - start_sector + 1) * pSpiDev->sector_size,
+		SPI_WRITE)) {
+
+		spi_free(spibuf);
+		return (8);
+	}
+
+	spi_free(spibuf);
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * spi_update_config - Updates part of the config area (Y1 and Y2)
+ *
+ * Description:
+ *	This function updates part of the config area.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+static int spi_update_config(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom (config area) for operation */
+unsigned long	len)	/* length of changing data */
+{
+	switch (pAC->spi.fl_type) {
+	case FT_SPI:
+		return (spi_yuk_update_config(pAC, IoC, data, off, len));
+	case FT_SPI_Y2:
+		return (spi_yuk2_update_config(pAC, IoC, data, off, len));
+	}
+
+	return (1);
+}
+
+#endif	/* !SK_SPI_NO_UPDATE */
+
+/*****************************************************************************
+ *
+ * flash_check_spi - Determines whether an SPI EPROM is present
+ *
+ * Description:
+ *	This function determines whether an SPI EPROM is present.
+ *
+ * Returns:
+ *	0	No SPI
+ *	1	SPI detected
+ */
+int flash_check_spi(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	*FlashSize)
+{
+	unsigned long	a1,a2;
+	unsigned long	opcodes;
+	int				i;
+
+	*FlashSize = 0;
+
+	SK_IN8(IoC, B2_CHIP_ID, &pAC->spi.yk_chip_id);
+	SK_IN8(IoC, B2_MAC_CFG, &pAC->spi.yk_chip_rev);
+
+	pAC->spi.yk_chip_rev = (pAC->spi.yk_chip_rev & CFG_CHIP_R_MSK) >> 4;
+
+	if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_LITE) {
+
+		/* YUKON-Lite Rev. A1 */
+		pAC->spi.fl_type = FT_SPI;
+		*FlashSize = pAC->spi.max_pages * pAC->spi.max_faddr;
+		fl_print("\nFlash Device\t: SPI\n");
+		return (1);
+	}
+
+	if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_XL &&
+		pAC->spi.yk_chip_id <= CHIP_ID_YUKON_OP_2) {
+
+		/* WA for A17 problem */
+		if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_SUPR &&
+			pAC->spi.yk_chip_rev == CHIP_REV_YU_SU_A0) {
+
+			SK_OUT16(IoC, SPI_CFG, 0x1c1);
+		}
+
+		spi_yuk2_set_dev_ptr(pAC, IoC);
+		if (pAC->spi.pSpiDev == NULL) {
+			/* unknown or no flash */
+			fl_print("\nFlash device\t: none\n");
+			pAC->spi.fl_type = FT_SPI_UNKNOWN;
+			return (0);
+		}
+
+		pAC->spi.fl_type = FT_SPI_Y2;
+		pAC->spi.max_pages = (long)pAC->spi.pSpiDev->sector_num;
+		pAC->spi.max_faddr = (long)pAC->spi.pSpiDev->sector_size;
+		*FlashSize = pAC->spi.max_pages * pAC->spi.max_faddr;
+
+		/* 
+		 * NOTE:
+		 * SPI flash types of max. 1 MB (8 MBit) are currently supported. 
+		 * Thus restrict flash size and sector/page number for bigger
+		 * SPI flash devices.
+		 */
+		if (*FlashSize > MAX_SPI_FLASH_SIZE) {
+			pAC->spi.max_pages = MAX_SPI_FLASH_SIZE / pAC->spi.max_faddr;
+			*FlashSize = pAC->spi.max_pages * pAC->spi.max_faddr;
+		}
+
+		/*
+		 * For flash-only adapters: Do not overwrite
+		 * Config Sector (array is modified by MT-Tool).
+		 */
+		for (i = 0; i < 0x80; i++) {
+			pAC->spi.ModifiedPages[i] = 1;
+		}
+
+		if (pAC->spi.yk_chip_id == CHIP_ID_YUKON_EX &&
+			pAC->spi.max_faddr == 0x1000) {
+			pAC->spi.ModifiedPages[SPI_PIG_OFF >> 12] = 0;
+		}
+
+		/* set the opcodes for the SPI flash found */
+		SK_IN32(IoC, SPI_Y2_OPCODE_REG1, &opcodes);
+		opcodes &= 0x000000ffL;
+		opcodes |=
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_read << 8 |
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_read_id << 16 |
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_read_status << 24;
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG1, opcodes);
+
+		opcodes =
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_write_enable |
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_write << 8 |
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_sector_erase << 16 |
+			(unsigned long)pAC->spi.pSpiDev->opcodes.op_chip_erase << 24;
+		SK_OUT32(IoC, SPI_Y2_OPCODE_REG2, opcodes);
+
+		if (pAC->spi.yk_chip_id >= CHIP_ID_YUKON_OPT) {
+			/* set the opcodes for the SPI flash found */
+			SK_IN32(IoC, SPI_Y2_OPCODE_REG0, &opcodes);
+			opcodes &= 0x0000ffffL;
+			opcodes |=
+				(unsigned long)pAC->spi.pSpiDev->opcodes.op_write_status << 16 |
+				(unsigned long)pAC->spi.pSpiDev->opcodes.op_read_sect_protect << 24;
+			SK_OUT32(IoC, SPI_Y2_OPCODE_REG0, opcodes);
+		}
+
+		pAC->spi.needs_unprotect = SK_FALSE;
+
+		if (pAC->spi.pSpiDev->man_id == SPI_MAN_ID_SST) {
+			/*
+			 * workaround for SST flash types to clear write
+			 * protection bits which are set by default
+			 */
+			spi_yuk2_sst_clear_write_protection(pAC, IoC);
+		}
+		else if (pAC->spi.pSpiDev->man_id == SPI_MAN_ID_ATMEL &&
+				 pAC->spi.pSpiDev->dev_id >= 0x43 &&
+				 pAC->spi.pSpiDev->dev_id <= 0x47) {
+
+#ifndef XXX
+			/* unprotect before / re-protect after erase and write */
+			pAC->spi.needs_unprotect = SK_TRUE;
+#else	/* XXX */
+			/* unprotect here for complete runtime */
+			if (spi_yuk2_write_status(pAC, IoC, 0) != 0) {
+				return (0);
+			}
+#endif	/* XXX */
+		}
+
+		return (1);
+	}
+
+	/* Save Eprom Address Register 1 */
+	SK_IN32(IoC, SPI_ADR_REG1, &a1);
+
+	/* Write SPI pattern */
+	SK_OUT32(IoC, SPI_ADR_REG1, SPI_PATTERN);
+
+	/* Read SPI pattern */
+	SK_IN32(IoC, SPI_ADR_REG1, &a2);
+
+	/* Restore Eprom Address Register 1 */
+	SK_OUT32(IoC, SPI_ADR_REG1, a1);
+
+	/* This is an SPI Eprom if one of bits 31..16 are set */
+	if ((a2 & SPI_COMP_MASK) != 0) {
+		/* YUKON-Lite Rev. A0 */
+		pAC->spi.fl_type = FT_SPI;
+		*FlashSize = pAC->spi.max_pages * pAC->spi.max_faddr;
+		return (1);
+	}
+	return (0);
+}
+
+/*****************************************************************************
+ *
+ * spi_flash_erase - Erases sectors touched by address range (Y1 and Y2)
+ *
+ * Description:
+ *	This function erases all sectors of the flash prom affected by
+ *	the address range denoted by parameters "off" (address offset)
+ *	and "len" (length of address range).
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_flash_erase(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned long	off,	/* start offset in flash eprom for erase */
+unsigned long	len)	/* length in flash eprom for erase */
+{
+	switch (pAC->spi.fl_type) {
+	case FT_SPI:
+		return (spi_yuk_flash_erase(pAC, IoC, off, len));
+	case FT_SPI_Y2:
+		return (spi_yuk2_flash_erase(pAC, IoC, off, len));
+	}
+
+	return (1);
+}
+
+/*****************************************************************************
+ *
+ * spi_flash_manage - Reads, verifies, or writes SPI EPROM (Y1 and Y2)
+ *
+ * Description:
+ *	This function reads, verifies, or writes the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_flash_manage(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	off,	/* start offset in flash eprom for operation */
+unsigned long	len,	/* length in flash eprom */
+int				flag)	/* action SPI_READ / SPI_VERIFY / SPI_WRITE */
+{
+	switch (pAC->spi.fl_type) {
+	case FT_SPI:
+		return (spi_yuk_flash_manage(pAC, IoC, data, off, len, flag));
+	case FT_SPI_Y2:
+		return (spi_yuk2_flash_manage(pAC, IoC, data, off, len, flag));
+	}
+
+	return (1);
+}
+
+/*****************************************************************************
+ *
+ * spi_vpd_transfer - Reads or updates data in VPD area of SPI EPROM
+ *
+ * Description:
+ *	This function reads or updates data in the VPD area of the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_vpd_transfer(
+SK_AC	*pAC,
+SK_IOC	IoC,
+char	*buf,	/* data buffer */
+int		addr,	/* VPD start address */
+int		len,	/* number of bytes to read / to write */
+int		dir)	/* transfer direction may be VPD_READ or VPD_WRITE */
+{
+	if (dir == 0) {
+		return (spi_flash_manage(pAC, IoC, (SK_U8*)buf, SPI_VPD_OFF + addr,
+			len, SPI_READ));
+	}
+#ifndef SK_SPI_NO_UPDATE
+	return (spi_update_config(pAC, IoC, (SK_U8*)buf, SPI_VPD_OFF + addr, len));
+#else	/* SK_SPI_NO_UPDATE */
+	return (1);
+#endif	/* SK_SPI_NO_UPDATE */
+}
+
+/*****************************************************************************
+ *
+ * spi_get_pig - Gets data from PiG area in SPI EPROM
+ *
+ * Description:
+ *	This function gets data from the PiG area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_get_pig(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data wanted */
+{
+	return (spi_flash_manage(pAC, IoC, data, SPI_PIG_OFF, len, SPI_READ));
+}
+
+/*****************************************************************************
+ *
+ * spi_get_noc - Gets data from VPD area in SPI EPROM
+ *
+ * Description:
+ *	This function gets data from the VPD area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_get_noc(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data wanted */
+{
+	return (spi_flash_manage(pAC, IoC, data, SPI_NOC_OFF, len, SPI_READ));
+}
+
+/*****************************************************************************
+ *
+ * spi_get_pet - Gets data from PET area in SPI EPROM
+ *
+ * Description:
+ *	This function gets data from the PET area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_get_pet(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data wanted */
+{
+	return (spi_flash_manage(pAC, IoC, data, SPI_PET_OFF, len, SPI_READ));
+}
+
+#ifndef SK_SPI_NO_UPDATE
+
+/*****************************************************************************
+ *
+ * spi_update_pig - Updates data in PiG area in SPI EPROM
+ *
+ * Description:
+ *	This function updates data in the PiG area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_update_pig(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data to update */
+{
+	return (spi_update_config(pAC, IoC, data, SPI_PIG_OFF, len));
+}
+
+/*****************************************************************************
+ *
+ * spi_update_noc - Updates data in NOC area in SPI EPROM
+ *
+ * Description:
+ *	This function updates data in the NOC area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_update_noc(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data to update */
+{
+	return (spi_update_config(pAC, IoC, data, SPI_NOC_OFF, len));
+}
+
+/*****************************************************************************
+ *
+ * spi_update_pet - Updates data in PET area in SPI EPROM
+ *
+ * Description:
+ *	This function updates data in the PET area in the SPI EPROM.
+ *
+ * Returns:
+ *	0	Success
+ *	1	Timeout
+ */
+int spi_update_pet(
+SK_AC			*pAC,
+SK_IOC			IoC,
+unsigned char	*data,	/* data buffer */
+unsigned long	len)	/* length of data to update */
+{
+	return (spi_update_config(pAC, IoC, data, SPI_PET_OFF, len));
+}
+
+#endif	/* !SK_SPI_NO_UPDATE */
+
+/* End of File */
diff -ruN linux/drivers/net/sk98lin/sktimer.c linux-new/drivers/net/sk98lin/sktimer.c
--- linux/drivers/net/sk98lin/sktimer.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sktimer.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,310 @@
+/******************************************************************************
+ *
+ * Name:	sktimer.c
+ * Project:	Gigabit Ethernet Adapters, Event Scheduler Module
+ * Version:	$Revision: #5 $
+ * Date:	$Date: 2010/11/04 $
+ * Purpose:	High level timer functions.
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * History:
+ *
+ *	$Log: sktimer.c,v $
+ *	Revision 2.4  2007/07/31 13:18:42  rschmidt
+ *	Used SK_BOOL for Restart flag
+ *	Editorial changes
+ *	
+ *	Revision 2.3  2005/12/14 16:11:02  ibrueder
+ *	Added copyright header flags
+ *
+ *	Revision 2.2  2004/05/28 13:44:39  rschmidt
+ *	Changed para Time in SkHwtStart() to units of 1 uS (16 uS before).
+ *	Editorial changes.
+ *
+ *	Revision 2.1  2003/10/27 14:16:09  amock
+ *	Promoted to major revision 2.1
+ *
+ *	Revision 1.1  2003/10/27 14:14:18  amock
+ *	Copied to yukon2 module branch
+ *
+ *	Revision 1.14  2003/09/16 13:46:51  rschmidt
+ *	Added (C) Marvell to SysKonnectFileId
+ *	Editorial changes
+ *
+ *	Revision 1.13  2003/05/13 18:01:01  mkarl
+ *	Editorial changes.
+ *
+ *	Revision 1.12  1999/11/22 13:38:51  cgoos
+ *	Changed license header to GPL.
+ *
+ *	Revision 1.11  1998/12/17 13:24:13  gklug
+ *	fix: restart problem: do NOT destroy timer queue if init 1 is done
+ *
+ *	Revision 1.10  1998/10/15 15:11:36  gklug
+ *	fix: ID_sccs to SysKonnectFileId
+ *
+ *	Revision 1.9  1998/09/15 15:15:04  cgoos
+ *	Changed TRUE/FALSE to SK_TRUE/SK_FALSE
+ *
+ *	Revision 1.8  1998/09/08 08:47:55  gklug
+ *	add: init level handling
+ *
+ *	Revision 1.7  1998/08/19 09:50:53  gklug
+ *	fix: remove struct keyword from c-code (see CCC) add typedefs
+ *
+ *	Revision 1.6  1998/08/17 13:43:13  gklug
+ *	chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
+ *
+ *	Revision 1.5  1998/08/14 07:09:14  gklug
+ *	fix: chg pAc -> pAC
+ *
+ *	Revision 1.4  1998/08/07 12:53:46  gklug
+ *	fix: first compiled version
+ *
+ *	Revision 1.3  1998/08/07 09:31:53  gklug
+ *	fix: delta spelling
+ *
+ *	Revision 1.2  1998/08/07 09:31:02  gklug
+ *	adapt functions to new c coding conventions
+ *	rmv: "fast" handling
+ *	chg: inserting of new timer in queue.
+ *	chg: event queue generation when timer runs out
+ *
+ *	Revision 1.1  1998/08/05 11:27:55  gklug
+ *	first version: adapted from SMT
+ *
+ ******************************************************************************/
+
+/*
+ *	Event queue and dispatcher
+ */
+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
+static const char SysKonnectFileId[] =
+	"@(#) $Id: //Release/Yukon_1G/Shared/schedule/V3/sktimer.c#5 $ (C) Marvell.";
+#endif
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#include "h/skdrv2nd.h"		/* Adapter Control- and Driver specific Def. */
+
+#ifdef __C2MAN__
+/*
+	Event queue management.
+
+	General Description:
+
+ */
+intro()
+{}
+#endif
+
+
+/* Forward declaration */
+static void timer_done(SK_AC *pAC, SK_IOC IoC, SK_BOOL Restart);
+
+
+/*
+ * Inits the software timer
+ *
+ * needs to be called during Init level 1.
+ */
+void SkTimerInit(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Level)		/* Init Level */
+{
+	switch (Level) {
+	case SK_INIT_DATA:
+		pAC->Tim.StQueue = 0;
+		break;
+	case SK_INIT_IO:
+		SkHwtInit(pAC, IoC);
+		SkTimerDone(pAC, IoC);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * Stops a high level timer
+ * - If a timer is not in the queue the function returns normally, too.
+ */
+void SkTimerStop(
+SK_AC		*pAC,		/* Adapter Context */
+SK_IOC		IoC,		/* I/O Context */
+SK_TIMER	*pTimer)	/* Timer Pointer to be stopped */
+{
+	SK_TIMER	**ppTimPrev;
+	SK_TIMER	*pTm;
+
+	/* remove timer from queue */
+	pTimer->TmActive = SK_FALSE;
+
+	if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
+
+		SkHwtStop(pAC, IoC);
+	}
+
+	for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
+		ppTimPrev = &pTm->TmNext ) {
+
+		if (pTm == pTimer) {
+			/*
+			 * Timer found in queue
+			 * - dequeue it
+			 * - correct delta of the next timer
+			 */
+			*ppTimPrev = pTm->TmNext;
+
+			if (pTm->TmNext) {
+				/* correct delta of next timer in queue */
+				pTm->TmNext->TmDelta += pTm->TmDelta;
+			}
+			return;
+		}
+	}
+}
+
+/*
+ * Start a high level software timer
+ */
+void SkTimerStart(
+SK_AC		*pAC,		/* Adapter Context */
+SK_IOC		IoC,		/* I/O Context */
+SK_TIMER	*pTimer,	/* Timer Pointer to be started */
+SK_U32		Time,		/* Time Value (in microsec.) */
+SK_U32		Class,		/* Event Class for this timer */
+SK_U32		Event,		/* Event Value for this timer */
+SK_EVPARA	Para)		/* Event Parameter for this timer */
+{
+	SK_TIMER	**ppTimPrev;
+	SK_TIMER	*pTm;
+	SK_U32		Delta;
+
+	SkTimerStop(pAC, IoC, pTimer);
+
+	pTimer->TmClass = Class;
+	pTimer->TmEvent = Event;
+	pTimer->TmPara = Para;
+	pTimer->TmActive = SK_TRUE;
+
+	if (!pAC->Tim.StQueue) {
+		/* first Timer to be started */
+		pAC->Tim.StQueue = pTimer;
+		pTimer->TmNext = 0;
+		pTimer->TmDelta = Time;
+
+		SkHwtStart(pAC, IoC, Time);
+
+		return;
+	}
+
+	/* timer correction */
+	timer_done(pAC, IoC, SK_FALSE);
+
+	/* find position in queue */
+	Delta = 0;
+	for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
+		ppTimPrev = &pTm->TmNext ) {
+
+		if (Delta + pTm->TmDelta > Time) {
+			/* the timer needs to be inserted here */
+			break;
+		}
+		Delta += pTm->TmDelta;
+	}
+
+	/* insert in queue */
+	*ppTimPrev = pTimer;
+	pTimer->TmNext = pTm;
+	pTimer->TmDelta = Time - Delta;
+
+	if (pTm) {
+		/* there is a next timer:  correct its Delta value */
+		pTm->TmDelta -= pTimer->TmDelta;
+	}
+
+	/* restart with first */
+	SkHwtStart(pAC, IoC, pAC->Tim.StQueue->TmDelta);
+}
+
+
+void SkTimerDone(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC)		/* I/O Context */
+{
+	timer_done(pAC, IoC, SK_TRUE);
+}
+
+
+static void timer_done(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_BOOL	Restart)	/* Do we need to restart the Hardware timer ? */
+{
+	SK_U32		Delta;
+	SK_TIMER	*pTm;
+	SK_TIMER	*pTComp;	/* Timer completed now */
+	SK_TIMER	**ppLast;	/* Next field of Last timer to be deq */
+	int		Done = 0;
+
+	Delta = SkHwtRead(pAC, IoC);
+
+	ppLast = &pAC->Tim.StQueue;
+	pTm = pAC->Tim.StQueue;
+
+	while (pTm && !Done) {
+		if (Delta >= pTm->TmDelta) {
+			/* Timer ran out */
+			pTm->TmActive = SK_FALSE;
+			Delta -= pTm->TmDelta;
+			ppLast = &pTm->TmNext;
+			pTm = pTm->TmNext;
+		}
+		else {
+			/* We found the first timer that did not run out */
+			pTm->TmDelta -= Delta;
+			Delta = 0;
+			Done = 1;
+		}
+	}
+
+	*ppLast = 0;
+	/*
+	 * pTm points to the first Timer that did not run out.
+	 * StQueue points to the first Timer that run out.
+	 */
+
+	for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
+
+		SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
+	}
+
+	/* Set head of timer queue to the first timer that did not run out */
+	pAC->Tim.StQueue = pTm;
+
+	if (Restart && pAC->Tim.StQueue) {
+		/* Restart HW timer */
+		SkHwtStart(pAC, IoC, pAC->Tim.StQueue->TmDelta);
+	}
+}
+
+/* End of file */
diff -ruN linux/drivers/net/sk98lin/sktwsi.c linux-new/drivers/net/sk98lin/sktwsi.c
--- linux/drivers/net/sk98lin/sktwsi.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sktwsi.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1288 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/twsi/V4/sktwsi.c#5 $
+ * Project:	Gigabit Ethernet Adapters, TWSI-Module
+ * Version:	$Revision: #5 $, $Change: 5665 $
+ * Date:	$DateTime: 2011/03/09 10:13:28 $
+ * Purpose:	Functions to access Voltage and Temperature Sensor
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*
+ *	TWSI Protocol
+ */
+
+#include "h/skdrv1st.h"		/* Driver Specific Definitions */
+#include "h/lm80.h"
+#include "h/skdrv2nd.h"		/* Adapter Control- and Driver specific Def. */
+
+/*
+	TWSI protocol implementation.
+
+	General Description:
+
+	The TWSI protocol is used for the temperature sensors and for
+	the serial EEPROM which hold the configuration.
+
+	This file covers functions that allow to read write and do
+	some bulk requests a specified TWSI address.
+
+	The Genesis has 2 TWSI buses. One for the EEPROM which holds
+	the VPD Data and one for temperature and voltage sensor.
+	The following picture shows the TWSI buses, TWSI devices and
+	their control registers.
+
+	Note: The VPD functions are in skvpd.c
+.
+.	PCI Config TWSI Bus for VPD Data:
+.
+.		      +------------+
+.		      | VPD EEPROM |
+.		      +------------+
+.			     |
+.			     | <-- TWSI
+.			     |
+.		 +-----------+-----------+
+.		 |			 |
+.	+-----------------+	+-----------------+
+.	| PCI_VPD_ADR_REG |	| PCI_VPD_DAT_REG |
+.	+-----------------+	+-----------------+
+.
+.
+.	TWSI Bus for LM80 sensor:
+.
+.			+-----------------+
+.			| Temperature and |
+.			| Voltage Sensor  |
+.			|	LM80	  |
+.			+-----------------+
+.				|
+.				|
+.			TWSI --> |
+.				|
+.			     +----+
+.	     +-------------->| OR |<--+
+.	     |		     +----+   |
+.     +------+------+		      |
+.     |		    |		      |
+. +--------+	+--------+	+----------+
+. | B2_I2C |	| B2_I2C |	|  B2_I2C  |
+. | _CTRL  |	| _DATA  |	|   _SW    |
+. +--------+	+--------+	+----------+
+.
+	The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
+	and B2_I2C_DATA registers.
+	For driver software it is recommended to use the TWSI control and
+	data register, because TWSI bus timing is done by the ASIC and
+	an interrupt may be received when the TWSI request is completed.
+
+	Clock Rate Timing:			MIN	MAX	generated by
+		VPD EEPROM:			50 kHz	100 kHz		HW
+		LM80 over TWSI Ctrl/Data reg.	50 kHz	100 kHz		HW
+		LM80 over B2_I2C_SW register	0	400 kHz		SW
+
+	Note:	The clock generated by the hardware is dependend on the
+		PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
+		clock is 50 kHz.
+ */
+
+#ifdef SK_DIAG
+/*
+ * TWSI Fast Mode timing values used by the LM80.
+ * If new devices are added to the TWSI bus the timing values have to be checked.
+ */
+#ifndef I2C_SLOW_TIMING
+#define T_CLK_LOW			1300L	/* clock low time in ns */
+#define T_CLK_HIGH			 600L	/* clock high time in ns */
+#define T_DATA_IN_SETUP		 100L	/* data in Set-up Time */
+#define T_START_HOLD		 600L	/* start condition hold time */
+#define T_START_SETUP		 600L	/* start condition Set-up time */
+#define T_STOP_SETUP		 600L	/* stop condition Set-up time */
+#define T_BUS_IDLE			1300L	/* time the bus must free after Tx */
+#define T_CLK_2_DATA_OUT	 900L	/* max. clock low to data output valid */
+#else	/* I2C_SLOW_TIMING */
+/* TWSI Standard Mode Timing */
+#define T_CLK_LOW			4700L	/* clock low time in ns */
+#define T_CLK_HIGH			4000L	/* clock high time in ns */
+#define T_DATA_IN_SETUP		 250L	/* data in Set-up Time */
+#define T_START_HOLD		4000L	/* start condition hold time */
+#define T_START_SETUP		4700L	/* start condition Set-up time */
+#define T_STOP_SETUP		4000L	/* stop condition Set-up time */
+#define T_BUS_IDLE			4700L	/* time the bus must free after Tx */
+#endif	/* !I2C_SLOW_TIMING */
+
+#define NS2BCLK(x)	(((x)*125)/10000)
+
+/*
+ * TWSI Wire Operations
+ *
+ * About I2C_CLK_LOW():
+ *
+ * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
+ * clock to low, to prevent the ASIC and the TWSI data client from driving the
+ * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client
+ * send an 'ACK'). See also Concentrator Bugreport No. 10192.
+ */
+#define I2C_DATA_HIGH(IoC)	SK_I2C_SET_BIT(IoC, I2C_DATA)
+#define I2C_DATA_LOW(IoC)	SK_I2C_CLR_BIT(IoC, I2C_DATA)
+#define I2C_DATA_OUT(IoC)	SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
+#define I2C_DATA_IN(IoC)	SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
+#define I2C_CLK_HIGH(IoC)	SK_I2C_SET_BIT(IoC, I2C_CLK)
+#define I2C_CLK_LOW(IoC)	SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
+#define I2C_START_COND(IoC)	SK_I2C_CLR_BIT(IoC, I2C_CLK)
+
+#define NS2CLKT(x)	((x*125L)/10000)
+
+/*--------------- TWSI Interface Register Functions --------------- */
+
+/*
+ * sending one bit
+ */
+void SkI2cSndBit(
+SK_IOC	IoC,	/* I/O Context */
+SK_U8	Bit)	/* Bit to send */
+{
+	I2C_DATA_OUT(IoC);
+	if (Bit) {
+		I2C_DATA_HIGH(IoC);
+	}
+	else {
+		I2C_DATA_LOW(IoC);
+	}
+	SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
+	I2C_CLK_HIGH(IoC);
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
+	I2C_CLK_LOW(IoC);
+}	/* SkI2cSndBit*/
+
+
+/*
+ * Signal a start to the TWSI Bus.
+ *
+ * A start is signaled when data goes to low in a high clock cycle.
+ *
+ * Ends with Clock Low.
+ *
+ * Status: not tested
+ */
+void SkI2cStart(
+SK_IOC	IoC)	/* I/O Context */
+{
+	/* Init data and Clock to output lines */
+	/* Set Data high */
+	I2C_DATA_OUT(IoC);
+	I2C_DATA_HIGH(IoC);
+	/* Set Clock high */
+	I2C_CLK_HIGH(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
+
+	/* Set Data Low */
+	I2C_DATA_LOW(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
+
+	/* Clock low without Data to Input */
+	I2C_START_COND(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
+}	/* SkI2cStart */
+
+
+void SkI2cStop(
+SK_IOC	IoC)	/* I/O Context */
+{
+	/* Init data and Clock to output lines */
+	/* Set Data low */
+	I2C_DATA_OUT(IoC);
+	I2C_DATA_LOW(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
+
+	/* Set Clock high */
+	I2C_CLK_HIGH(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
+
+	/*
+	 * Set Data High:	Do it by setting the Data Line to Input.
+	 *			Because of a pull up resistor the Data Line floods to high.
+	 */
+	I2C_DATA_IN(IoC);
+
+	/*
+	 *	When TWSI activity is stopped
+	 *	 o	DATA should be set to input and
+	 *	 o	CLOCK should be set to high!
+	 */
+	SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
+}	/* SkI2cStop */
+
+
+/*
+ * Receive just one bit via the TWSI bus.
+ *
+ * Note:	Clock must be set to LOW before calling this function.
+ *
+ * Returns The received bit.
+ */
+int SkI2cRcvBit(
+SK_IOC	IoC)	/* I/O Context */
+{
+	int	Bit;
+	SK_U8	I2cSwCtrl;
+
+	/* Init data as input line */
+	I2C_DATA_IN(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
+
+	I2C_CLK_HIGH(IoC);
+
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
+
+	SK_I2C_GET_SW(IoC, &I2cSwCtrl);
+
+	Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
+
+	I2C_CLK_LOW(IoC);
+	SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
+
+	return(Bit);
+}	/* SkI2cRcvBit */
+
+
+/*
+ * Receive an ACK.
+ *
+ * returns	0 If acknowledged
+ *		1 in case of an error
+ */
+int SkI2cRcvAck(
+SK_IOC	IoC)	/* I/O Context */
+{
+	/*
+	 * Received bit must be zero.
+	 */
+	return(SkI2cRcvBit(IoC) != 0);
+}	/* SkI2cRcvAck */
+
+
+/*
+ * Send an NACK.
+ */
+void SkI2cSndNAck(
+SK_IOC	IoC)	/* I/O Context */
+{
+	/*
+	 * Received bit must be zero.
+	 */
+	SkI2cSndBit(IoC, 1);
+}	/* SkI2cSndNAck */
+
+
+/*
+ * Send an ACK.
+ */
+void SkI2cSndAck(
+SK_IOC IoC)	/* I/O Context */
+{
+	/*
+	 * Received bit must be zero.
+	 */
+	SkI2cSndBit(IoC, 0);
+}	/* SkI2cSndAck */
+
+
+/*
+ * Send one byte to the TWSI device and wait for ACK.
+ *
+ * Return acknowleged status.
+ */
+int SkI2cSndByte(
+SK_IOC	IoC,	/* I/O Context */
+int		Byte)	/* byte to send */
+{
+	int	i;
+
+	for (i = 0; i < 8; i++) {
+		if (Byte & (1<<(7-i))) {
+			SkI2cSndBit(IoC, 1);
+		}
+		else {
+			SkI2cSndBit(IoC, 0);
+		}
+	}
+
+	return(SkI2cRcvAck(IoC));
+}	/* SkI2cSndByte */
+
+
+/*
+ * Receive one byte and ack it.
+ *
+ * Return byte.
+ */
+int SkI2cRcvByte(
+SK_IOC	IoC,	/* I/O Context */
+int		Last)	/* Last Byte Flag */
+{
+	int	i;
+	int	Byte = 0;
+
+	for (i = 0; i < 8; i++) {
+		Byte <<= 1;
+		Byte |= SkI2cRcvBit(IoC);
+	}
+
+	if (Last) {
+		SkI2cSndNAck(IoC);
+	}
+	else {
+		SkI2cSndAck(IoC);
+	}
+
+	return(Byte);
+}	/* SkI2cRcvByte */
+
+
+/*
+ * Start dialog and send device address
+ *
+ * Return 0 if acknowleged, 1 in case of an error
+ */
+int SkI2cSndDev(
+SK_IOC	IoC,	/* I/O Context */
+int		Addr,	/* Device Address */
+int		Rw)		/* Read / Write Flag */
+{
+	SkI2cStart(IoC);
+	Rw = ~Rw;
+	Rw &= I2C_WRITE;
+	return(SkI2cSndByte(IoC, (Addr << 1) | Rw));
+}	/* SkI2cSndDev */
+
+#endif /* SK_DIAG */
+
+/*----------------- TWSI CTRL Register Functions ----------*/
+
+/*
+ * waits for a completion of a TWSI transfer
+ *
+ * returns	0:	success, transfer completes
+ *			1:	error,	 transfer does not complete, TWSI transfer
+ *						 killed, wait loop terminated.
+ */
+int SkI2cWait(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Event)	/* complete event to wait for (I2C_READ or I2C_WRITE) */
+{
+	SK_U64	StartTime;
+	SK_U64	CurrTime;
+	SK_U32	I2cCtrl;
+
+	StartTime = SkOsGetTime(pAC);
+
+	do {
+		CurrTime = SkOsGetTime(pAC);
+
+		if (CurrTime - StartTime > SK_TICKS_PER_SEC / 8) {
+
+			SK_I2C_STOP(IoC);
+#ifndef SK_DIAG
+			if (pAC->I2c.InitLevel > SK_INIT_DATA) {
+				SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
+			}
+#endif /* !SK_DIAG */
+			return(1);
+		}
+
+		SK_I2C_GET_CTL(IoC, &I2cCtrl);
+
+	} while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
+
+	return(0);
+}	/* SkI2cWait */
+
+
+/*
+ * waits for a completion of a TWSI transfer
+ *
+ * Returns
+ *	Nothing
+ */
+void SkI2cWaitIrq(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SK_SENSOR	*pSen;
+	SK_U64		StartTime;
+	SK_U32		IrqSrc;
+	SK_U32		IsTwsiReadyBit;
+
+	pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+
+	if (pSen->SenState == SK_SEN_IDLE) {
+		return;
+	}
+
+	IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY;
+
+	StartTime = SkOsGetTime(pAC);
+
+	do {
+		if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
+
+			SK_I2C_STOP(IoC);
+#ifndef SK_DIAG
+			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
+#endif /* !SK_DIAG */
+			return;
+		}
+
+		SK_IN32(IoC, B0_ISRC, &IrqSrc);
+
+	} while ((IrqSrc & IsTwsiReadyBit) == 0);
+
+	pSen->SenState = SK_SEN_IDLE;
+	return;
+}	/* SkI2cWaitIrq */
+
+/*
+ * writes a single byte or 4 bytes into the TWSI device
+ *
+ * returns	0:	success
+ *			1:	error
+ */
+int SkI2cWrite(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+SK_U32	I2cData,	/* TWSI Data to write */
+int		I2cDev,		/* TWSI Device Address */
+int		I2cDevSize,	/* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
+int		I2cReg,		/* TWSI Device Register Address */
+int		I2cBurst)	/* TWSI Burst Flag */
+{
+	SK_OUT32(IoC, B2_I2C_DATA, I2cData);
+
+	SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
+
+	return(SkI2cWait(pAC, IoC, I2C_WRITE));
+}	/* SkI2cWrite*/
+
+
+#ifdef SK_DIAG
+/*
+ * reads a single byte or 4 bytes from the TWSI device
+ *
+ * returns	the word read
+ */
+SK_U32 SkI2cRead(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		I2cDev,		/* TWSI Device Address */
+int		I2cDevSize,	/* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
+int		I2cReg,		/* TWSI Device Register Address */
+int		I2cBurst)	/* TWSI Burst Flag */
+{
+	SK_U32	Data;
+
+	SK_OUT32(IoC, B2_I2C_DATA, 0);
+
+	SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
+
+	if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
+		w_print("%s\n", SKERR_I2C_E002MSG);
+	}
+
+	SK_IN32(IoC, B2_I2C_DATA, &Data);
+
+	return(Data);
+}	/* SkI2cRead */
+#endif /* SK_DIAG */
+
+
+/*
+ * read a sensor's value
+ *
+ * This function reads a sensor's value from the TWSI sensor chip. The sensor
+ * is defined by its index into the sensors database in the struct pAC points
+ * to.
+ * Returns
+ *		1 if the read is completed
+ *		0 if the read must be continued (TWSI Bus still allocated)
+ */
+int SkI2cReadSensor(
+SK_AC		*pAC,	/* Adapter Context */
+SK_IOC		IoC,	/* I/O Context */
+SK_SENSOR	*pSen)	/* Sensor to be read */
+{
+	if (pSen->SenRead != NULL) {
+		return((*pSen->SenRead)(pAC, IoC, pSen));
+	}
+
+	return(0); /* no success */
+}	/* SkI2cReadSensor */
+
+/*
+ * Do the Init state 0 initialization
+ */
+static int SkI2cInit0(
+SK_AC	*pAC)	/* Adapter Context */
+{
+	int			i;
+	SK_SENSOR	*pSen;
+
+	/* Begin with first sensor */
+	pAC->I2c.CurrSens = 0;
+
+	/* Begin with timeout control for state machine */
+	pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
+
+	/* Set sensor number to zero */
+	pAC->I2c.MaxSens = 0;
+
+#ifndef SK_DIAG
+	/* Initialize Number of Dummy Reads */
+	pAC->I2c.DummyReads = SK_MAX_SENSORS;
+#endif /* !SK_DIAG */
+
+	for (i = 0; i < SK_MAX_SENSORS; i++) {
+		pSen = &pAC->I2c.SenTable[i];
+
+		pSen->SenDesc = "unknown";
+		pSen->SenType = SK_SEN_UNKNOWN;
+		pSen->SenThreErrHigh = 0;
+		pSen->SenThreErrLow = 0;
+		pSen->SenThreWarnHigh = 0;
+		pSen->SenThreWarnLow = 0;
+		pSen->SenReg = LM80_FAN2_IN;
+		pSen->SenInit = SK_SEN_DYN_INIT_NONE;
+		pSen->SenValue = 0;
+		pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
+		pSen->SenErrCts = 0;
+		pSen->SenBegErrTS = 0;
+		pSen->SenState = SK_SEN_IDLE;
+		pSen->SenRead = NULL;
+		pSen->SenDev = 0;
+	}
+
+	/* Now we are "INIT data"ed */
+	pAC->I2c.InitLevel = SK_INIT_DATA;
+	return(0);
+}	/* SkI2cInit0*/
+
+
+/*
+ * Do the init state 1 initialization
+ *
+ * initialize the following register of the LM80:
+ * Configuration register:
+ * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
+ *
+ * Interrupt Mask Register 1:
+ * - all interrupts are Disabled (0xff)
+ *
+ * Interrupt Mask Register 2:
+ * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
+ *
+ * Fan Divisor/RST_OUT register:
+ * - Divisors set to 1 (bits 00), all others 0s.
+ *
+ * OS# Configuration/Temperature resolution Register:
+ * - all 0s
+ *
+ */
+static int SkI2cInit1(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	int			i;
+	SK_U8		I2cSwCtrl;
+	SK_SENSOR	*pSen;
+
+	if (pAC->I2c.InitLevel != SK_INIT_DATA) {
+		/* Re-init not needed in TWSI module */
+		return(0);
+	}
+
+	pSen = &pAC->I2c.SenTable[0];
+	pSen->SenDesc = "Temperature";
+	pSen->SenType = SK_SEN_TEMP;
+	pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
+	pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
+	pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
+	pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
+
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_EC_U) {
+		/* No sensors on Yukon-EC, -ECU, -EX, -SUP, -FE, -FE+ */
+		if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+			/* use temperature sensor from PHY */
+			pAC->I2c.MaxSens = 1;
+		}
+		return(0);
+	}
+
+	/* Set the Direction of TWSI-Data Pin to IN */
+	SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
+
+	/* Check for 32-Bit Yukon with Low at TWSI-Data Pin */
+	SK_I2C_GET_SW(IoC, &I2cSwCtrl);
+
+	if ((I2cSwCtrl & I2C_DATA) == 0) {
+		/* this is a 32-Bit board */
+		pAC->GIni.GIYukon32Bit = SK_TRUE;
+		return(0);
+	}
+
+	/* Check for 64 Bit Yukon without sensors */
+	if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
+		return(0);
+	}
+
+	(void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
+
+	(void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
+
+	(void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
+
+	(void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
+
+	(void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
+		LM80_CFG, 0);
+
+	/*
+	 * MaxSens has to be updated here, because PhyType is not
+	 * set when performing Init Level 0
+	 */
+	pAC->I2c.MaxSens = 8;
+
+	for (i = 0; i < pAC->I2c.MaxSens; i++) {
+		pSen = &pAC->I2c.SenTable[i];
+		switch (i) {
+		case 0:
+			pSen->SenReg = LM80_TEMP_IN;
+			break;
+		case 1:
+			pSen->SenDesc = "Voltage PCI";
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
+			pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
+			if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
+				pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
+				pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
+			}
+			else {
+				pSen->SenThreWarnLow = 0;
+				pSen->SenThreErrLow = 0;
+			}
+			pSen->SenReg = LM80_VT0_IN;
+			break;
+		case 2:
+			pSen->SenDesc = "Voltage PCI-IO";
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
+			pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
+			if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
+				pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
+				pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
+			}
+			else {
+				pSen->SenThreWarnLow = 0;
+				pSen->SenThreErrLow = 0;
+			}
+			pSen->SenReg = LM80_VT1_IN;
+			pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO;
+			break;
+		case 3:
+			pSen->SenDesc = "Voltage VMAIN";
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
+			pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
+			pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
+			pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR;
+			pSen->SenReg = LM80_VT2_IN;
+			break;
+		case 4:
+			pSen->SenDesc = "Voltage VAUX";
+			pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
+			pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
+			if (pAC->GIni.GIVauxAvail) {
+				pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
+				pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
+			}
+			else {
+				pSen->SenThreErrLow = 0;
+				pSen->SenThreWarnLow = 0;
+			}
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenReg = LM80_VT3_IN;
+			break;
+		case 5:
+			if (CHIP_ID_YUKON_2(pAC)) {
+				if (pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
+					pSen->SenDesc = "Voltage Core 1V3";
+					pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR;
+					pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN;
+					pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN;
+					pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR;
+				}
+				else {
+					pSen->SenDesc = "Voltage Core 1V2";
+					pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR;
+					pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN;
+					pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN;
+					pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR;
+				}
+			}
+			else {
+				pSen->SenDesc = "Voltage Core 1V5";
+				pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
+				pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
+				pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
+				pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
+			}
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenReg = LM80_VT4_IN;
+			break;
+		case 6:
+			if (CHIP_ID_YUKON_2(pAC)) {
+				pSen->SenDesc = "Voltage PHY 1V5";
+				pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
+				pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
+				if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
+					pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
+					pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
+				}
+				else {
+					pSen->SenThreWarnLow = 0;
+					pSen->SenThreErrLow = 0;
+				}
+			}
+			else {
+				pSen->SenDesc = "Voltage PHY 3V3";
+				pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
+				pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
+				pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
+				pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
+			}
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenReg = LM80_VT5_IN;
+			break;
+		case 7:
+			pSen->SenDesc = "Voltage PHY 2V5";
+			pSen->SenType = SK_SEN_VOLT;
+			pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
+			pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
+			pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
+			pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
+			pSen->SenReg = LM80_VT6_IN;
+			break;
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
+				SKERR_I2C_E001, SKERR_I2C_E001MSG);
+			break;
+		}
+
+		pSen->SenValue = 0;
+		pSen->SenErrFlag = SK_SEN_ERR_OK;
+		pSen->SenErrCts = 0;
+		pSen->SenBegErrTS = 0;
+		pSen->SenState = SK_SEN_IDLE;
+		if (pSen->SenThreWarnLow != 0) {
+			pSen->SenRead = SkLm80ReadSensor;
+		}
+		pSen->SenDev = LM80_ADDR;
+	}
+
+#ifndef SK_DIAG
+	pAC->I2c.DummyReads = pAC->I2c.MaxSens;
+#endif /* !SK_DIAG */
+
+	/* Clear TWSI IRQ */
+	SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
+
+	/* Now we are I/O initialized */
+	pAC->I2c.InitLevel = SK_INIT_IO;
+	return(0);
+}	/* SkI2cInit1 */
+
+
+/*
+ * Init level 2: Start first sensor read.
+ */
+static int SkI2cInit2(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	int			ReadComplete;
+	SK_SENSOR	*pSen;
+
+	if (pAC->I2c.InitLevel != SK_INIT_IO) {
+		/* ReInit not needed in TWSI module */
+		/* Init0 and Init2 not permitted */
+		return(0);
+	}
+
+	pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+
+	ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
+
+	if (ReadComplete) {
+		SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
+	}
+
+	/* Now we are correctly initialized */
+	pAC->I2c.InitLevel = SK_INIT_RUN;
+
+	return(0);
+}	/* SkI2cInit2*/
+
+
+/*
+ * Initialize TWSI devices
+ *
+ * Get the first voltage value and discard it.
+ * Go into temperature read mode. A default pointer is not set.
+ *
+ * The things to be done depend on the init level in the parameter list:
+ * Level 0:
+ *	Initialize only the data structures. Do NOT access hardware.
+ * Level 1:
+ *	Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
+ * Level 2:
+ *	Everything is possible. Interrupts may be used from now on.
+ *
+ * return:
+ *	0 = success
+ *	other = error.
+ */
+int SkI2cInit(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context needed in levels 1 and 2 */
+int		Level)	/* Init Level */
+{
+
+	switch (Level) {
+	case SK_INIT_DATA:
+		return(SkI2cInit0(pAC));
+	case SK_INIT_IO:
+		return(SkI2cInit1(pAC, IoC));
+	case SK_INIT_RUN:
+		return(SkI2cInit2(pAC, IoC));
+	default:
+		break;
+	}
+
+	return(0);
+}	/* SkI2cInit */
+
+
+#ifndef SK_DIAG
+/*
+ * Interrupt service function for the TWSI Interface
+ *
+ * Clears the Interrupt source
+ *
+ * Reads the register and check it for sending a trap.
+ *
+ * Starts the timer if necessary.
+ */
+void SkI2cIsr(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC)	/* I/O Context */
+{
+	SK_EVPARA	Para;
+
+	/* Clear TWSI IRQ */
+	SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
+
+	Para.Para64 = 0;
+	SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
+}	/* SkI2cIsr */
+
+
+/*
+ * Check this sensors Value against the threshold and send events.
+ */
+static void SkI2cCheckSensor(
+SK_AC		*pAC,	/* Adapter Context */
+SK_SENSOR	*pSen)
+{
+	SK_EVPARA	ParaLocal;
+	SK_BOOL		TooHigh;	/* Is sensor too high? */
+	SK_BOOL		TooLow;		/* Is sensor too low? */
+	SK_U64		CurrTime;	/* Current Time */
+	SK_BOOL		DoTrapSend;	/* We need to send a trap */
+	SK_BOOL		DoErrLog;	/* We need to log the error */
+	SK_BOOL		IsError;	/* Error occurred */
+
+	/* Check Dummy Reads first */
+	if (pAC->I2c.DummyReads > 0) {
+		pAC->I2c.DummyReads--;
+		return;
+	}
+
+	/* Get the current time */
+	CurrTime = SkOsGetTime(pAC);
+
+	/* Set para to the most useful setting: The current sensor. */
+	ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
+
+	/* Check the Value against the thresholds. First: Error Thresholds */
+	TooHigh = pSen->SenValue > pSen->SenThreErrHigh;
+	TooLow  = pSen->SenValue < pSen->SenThreErrLow;
+
+	IsError = SK_FALSE;
+
+	if (TooHigh || TooLow) {
+		/* Error condition is satisfied */
+		DoTrapSend = SK_TRUE;
+		DoErrLog = SK_TRUE;
+
+		/* Now error condition is satisfied */
+		IsError = SK_TRUE;
+
+		if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
+			/* This state is the former one */
+
+			/* So check first whether we have to send a trap */
+			if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) {
+				/*
+				 * Do NOT send the Trap. The hold back time
+				 * has to run out first.
+				 */
+				DoTrapSend = SK_FALSE;
+			}
+
+			/* Check now whether we have to log an Error */
+			if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) {
+				/*
+				 * Do NOT log the error. The hold back time
+				 * has to run out first.
+				 */
+				DoErrLog = SK_FALSE;
+			}
+		}
+		else {
+			/* We came from a different state -> Set Begin Time Stamp */
+			pSen->SenBegErrTS = CurrTime;
+			pSen->SenErrFlag = SK_SEN_ERR_ERR;
+		}
+
+		if (DoTrapSend) {
+			/* Set current Time */
+			pSen->SenLastErrTrapTS = CurrTime;
+			pSen->SenErrCts++;
+
+#ifndef SK_NO_PNMI
+			/* Queue PNMI Event */
+			SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
+				SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW, ParaLocal);
+#endif /* !SK_NO_PNMI */
+		}
+
+		if (DoErrLog) {
+			/* Set current Time */
+			pSen->SenLastErrLogTS = CurrTime;
+
+			if (pSen->SenType == SK_SEN_TEMP) {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
+			}
+			else if (pSen->SenType == SK_SEN_VOLT) {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
+			}
+			else {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
+			}
+		}
+	}
+
+	/* Check the Value against the thresholds */
+	/* 2nd: Warning thresholds */
+	TooHigh = pSen->SenValue > pSen->SenThreWarnHigh;
+	TooLow  = pSen->SenValue < pSen->SenThreWarnLow;
+
+	if (!IsError && (TooHigh || TooLow)) {
+		/* Error condition is satisfied */
+		DoTrapSend = SK_TRUE;
+		DoErrLog = SK_TRUE;
+
+		if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
+			/* This state is the former one */
+
+			/* So check first whether we have to send a trap */
+			if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
+				/*
+				 * Do NOT send the Trap. The hold back time
+				 * has to run out first.
+				 */
+				DoTrapSend = SK_FALSE;
+			}
+
+			/* Check now whether we have to log an Error */
+			if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
+				/*
+				 * Do NOT log the error. The hold back time
+				 * has to run out first.
+				 */
+				DoErrLog = SK_FALSE;
+			}
+		}
+		else {
+			/* We came from a different state -> Set Begin Time Stamp */
+			pSen->SenBegWarnTS = CurrTime;
+			pSen->SenErrFlag = SK_SEN_ERR_WARN;
+		}
+
+		if (DoTrapSend) {
+			/* Set current Time */
+			pSen->SenLastWarnTrapTS = CurrTime;
+			pSen->SenWarnCts++;
+
+#ifndef SK_NO_PNMI
+			/* Queue PNMI Event */
+			SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
+				SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal);
+#endif /* !SK_NO_PNMI */
+		}
+
+		if (DoErrLog) {
+			/* Set current Time */
+			pSen->SenLastWarnLogTS = CurrTime;
+
+			if (pSen->SenType == SK_SEN_TEMP) {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
+			}
+			else if (pSen->SenType == SK_SEN_VOLT) {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
+			}
+			else {
+				SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
+			}
+		}
+	}
+
+	/* Check for NO error at all */
+	if (!IsError && !TooHigh && !TooLow) {
+		/* Set o.k. Status if no error and no warning condition */
+		pSen->SenErrFlag = SK_SEN_ERR_OK;
+	}
+
+	/* End of check against the thresholds */
+
+	if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
+		/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
+		pSen->SenInit = SK_SEN_DYN_INIT_NONE;
+
+		if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
+			/* 5V PCI-IO Voltage */
+			pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
+			pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
+		}
+		else {
+			/* 3.3V PCI-IO Voltage */
+			pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
+			pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
+		}
+	}
+
+#ifdef TEST_ONLY
+	/* Dynamic thresholds also for VAUX of LM80 sensor */
+	if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
+
+		pSen->SenInit = SK_SEN_DYN_INIT_NONE;
+
+		/* 3.3V VAUX Voltage */
+		if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
+			pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
+			pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
+		}
+		/* 0V VAUX Voltage */
+		else {
+			pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
+			pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
+		}
+	}
+
+	/* Check initialization state: the VIO Thresholds need adaptation */
+	if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
+		 pSen->SenValue > SK_SEN_WARNLOW2C &&
+		 pSen->SenValue < SK_SEN_WARNHIGH2) {
+
+		pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
+		pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
+		pSen->SenInit = SK_TRUE;
+	}
+
+	if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
+		 pSen->SenValue > SK_SEN_WARNLOW2 &&
+		 pSen->SenValue < SK_SEN_WARNHIGH2C) {
+
+		pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
+		pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
+		pSen->SenInit = SK_TRUE;
+	}
+#endif /* TEST_ONLY */
+
+	if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
+		SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
+	}
+}	/* SkI2cCheckSensor */
+
+
+/*
+ * The only Event to be served is the timeout event
+ *
+ */
+int SkI2cEvent(
+SK_AC		*pAC,	/* Adapter Context */
+SK_IOC		IoC,	/* I/O Context */
+SK_U32		Event,	/* Module specific Event */
+SK_EVPARA	Para)	/* Event specific Parameter */
+{
+	int			ReadComplete;
+	SK_SENSOR	*pSen;
+	SK_U32		Time;
+	SK_EVPARA	ParaLocal;
+	int			i;
+
+	/* New case: no sensors */
+	if (pAC->I2c.MaxSens == 0) {
+		return(0);
+	}
+
+	switch (Event) {
+	case SK_I2CEV_IRQ:
+		pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+
+		ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
+
+		if (ReadComplete) {
+			/* Check sensor against defined thresholds */
+			SkI2cCheckSensor(pAC, pSen);
+
+			/* Increment Current sensor and set appropriate Timeout */
+			pAC->I2c.CurrSens++;
+			if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
+				pAC->I2c.CurrSens = 0;
+				Time = SK_I2C_TIM_LONG;
+			}
+			else {
+				Time = SK_I2C_TIM_SHORT;
+			}
+
+			/* Start Timer */
+			ParaLocal.Para64 = (SK_U64)0;
+
+			pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
+
+			SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
+				SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
+		}
+		else {
+			/* Start Timer */
+			ParaLocal.Para64 = (SK_U64)0;
+
+			pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
+
+			SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
+				SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
+		}
+		break;
+	case SK_I2CEV_TIM:
+		if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
+
+			ParaLocal.Para64 = (SK_U64)0;
+			SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
+
+			pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+			ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
+
+			if (ReadComplete) {
+				/* Check sensor against defined thresholds */
+				SkI2cCheckSensor(pAC, pSen);
+
+				/* Increment Current sensor and set appropriate Timeout */
+				pAC->I2c.CurrSens++;
+				if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
+					pAC->I2c.CurrSens = 0;
+					Time = SK_I2C_TIM_LONG;
+				}
+				else {
+					Time = SK_I2C_TIM_SHORT;
+				}
+
+				/* Start Timer */
+				ParaLocal.Para64 = (SK_U64)0;
+
+				pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
+
+				SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
+					SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
+			}
+		}
+		else {
+			pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
+			pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
+			SK_I2C_STOP(IoC);
+
+			/* Increment Current sensor and set appropriate Timeout */
+			pAC->I2c.CurrSens++;
+			if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
+				pAC->I2c.CurrSens = 0;
+				Time = SK_I2C_TIM_LONG;
+			}
+			else {
+				Time = SK_I2C_TIM_SHORT;
+			}
+
+			/* Start Timer */
+			ParaLocal.Para64 = (SK_U64)0;
+
+			pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
+
+			SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
+				SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
+		}
+		break;
+	case SK_I2CEV_CLEAR:
+		for (i = 0; i < SK_MAX_SENSORS; i++) {
+			pSen = &pAC->I2c.SenTable[i];
+
+			pSen->SenErrFlag = SK_SEN_ERR_OK;
+			pSen->SenErrCts = 0;
+			pSen->SenWarnCts = 0;
+			pSen->SenBegErrTS = 0;
+			pSen->SenBegWarnTS = 0;
+			pSen->SenLastErrTrapTS = (SK_U64)0;
+			pSen->SenLastErrLogTS = (SK_U64)0;
+			pSen->SenLastWarnTrapTS = (SK_U64)0;
+			pSen->SenLastWarnLogTS = (SK_U64)0;
+		}
+		break;
+	default:
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
+	}
+
+	return(0);
+}	/* SkI2cEvent*/
+
+#endif /* !SK_DIAG */
+
diff -ruN linux/drivers/net/sk98lin/skvpd.c linux-new/drivers/net/sk98lin/skvpd.c
--- linux/drivers/net/sk98lin/skvpd.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skvpd.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,1564 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/vpd/V4/skvpd.c#4 $
+ * Project:	Gigabit Ethernet Adapters, VPD-Module
+ * Version:	$Revision: #4 $, $Change: 4281 $
+ * Date:	$DateTime: 2010/11/05 11:58:07 $
+ * Purpose:	Shared software to read and write VPD
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/* Please refer skvpd.txt for information how to include this module. */
+
+#include "h/skdrv1st.h"
+#include "h/sktypes.h"
+#include "h/skdebug.h"
+#include "h/skdrv2nd.h"
+
+/*
+ * Static functions
+ */
+#ifndef SK_KR_PROTO
+static SK_VPD_PARA	*vpd_find_para(
+	SK_AC	*pAC,
+	const char	*key,
+	SK_VPD_PARA *p);
+#else	/* SK_KR_PROTO */
+static SK_VPD_PARA	*vpd_find_para();
+#endif	/* SK_KR_PROTO */
+
+/******************************************************************************
+ *
+ *	VpdWait()	- waits for a VPD read/write completion
+ *
+ * Description:
+ *	Waits for a completion of a VPD read/write transfer
+ *	The VPD transfer must complete within SK_TICKS_PER_SEC/16
+ *
+ * returns	0:	success, transfer complete
+ *			1:	error, timeout
+ */
+static int VpdWait(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+int		event)	/* event to wait for VPD_READ / VPD_WRITE completion */
+{
+	SK_U64	start_time;
+	SK_U32	delta_time;
+	SK_U16	state;
+#ifdef xSK_DIAG
+	SK_U32	StartTime;
+	SK_U32	EndTime;
+#endif /* SK_DIAG */
+
+#ifdef XXX		/* Creates too much debug output */
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD wait for %s\n", event ? "Write" : "Read"));
+#endif /* XXX */
+
+	start_time = SkOsGetTime(pAC);
+
+#ifdef xSK_DIAG
+	SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
+#endif /* SK_DIAG */
+
+	do {
+		delta_time = (SK_U32)(SkOsGetTime(pAC) - start_time);
+
+		VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
+
+		/* Error on reading VPD Address Register */
+		if (state == 0xffff) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+				("ERROR: VPD %s status\n", event ? "Write" : "Read"));
+			return(1);
+		}
+
+		if (delta_time > SK_TICKS_PER_SEC / 16 &&
+			(int)(state & PCI_VPD_FLAG) == event) {
+
+			/* Bug fix AF: Thu Mar 28 2002
+			 * Do not call: VPD_STOP(pAC, IoC);
+			 * A pending VPD read cycle can not be aborted by writing VPD_WRITE
+			 * to the PCI_VPD_ADR_REG (VPD address register).
+			 * Although the write threshold in the OUR-register protects VPD RO
+			 * space from being overwritten, this does not protect a VPD read
+			 * from being `converted` into a VPD write operation (on the fly).
+			 * As a consequence the VPD_STOP would delete VPD read only data.
+			 * In case of any problems with the I2C bus we exit the loop here.
+			 * The I2C read operation can not be aborted except by a reset.
+			 */
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+				("ERROR: VPD %s timeout\n", event ? "Write" : "Read"));
+			return(1);
+		}
+
+	} while ((int)(state & PCI_VPD_FLAG) == event);
+
+#ifdef xSK_DIAG
+	SK_IN32(IoC, GMAC_TI_ST_VAL, &EndTime);
+
+	delta_time = HW_TICKS_TO_USEC(pAC, EndTime - StartTime);
+#endif /* SK_DIAG */
+
+#ifdef xSK_DIAG
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD state = 0x%04X, delta = %lu\n", state, delta_time));
+#endif /* SK_DIAG */
+
+	return(0);
+}
+
+#if (!defined(SK_SLIM) || defined(EFI_UNDI)) /* needs to be enabled for ASF w/o EEPROM */
+/******************************************************************************
+ *
+ *	SpiWait()	- waits for a SPI read completion
+ *
+ * Description:
+ *	Waits for a completion of a SPI read transfer
+ *	The SPI transfer must complete within SK_TICKS_PER_SEC/16
+ *
+ * returns	0:	success, transfer completes
+ *			1:	error, timeout
+ */
+static int SpiWait(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC)	/* IO Context */
+{
+	SK_I64	start_time;
+	SK_U32	delta_time;
+	SK_U32	stat;
+
+#ifdef XXX		/* Creates too much debug output */
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("SPI wait\n"));
+#endif /* XXX */
+
+	start_time = (SK_I64)SkOsGetTime(pAC);
+
+	do {
+		delta_time = (SK_U32)(SkOsGetTime(pAC) - start_time);
+
+		if (delta_time > SK_TICKS_PER_SEC / 16) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+				("ERROR: SPI wait timeout\n"));
+			return(1);
+		}
+
+		SK_IN32(IoC, SPI_CTRL, &stat);
+
+	} while ((stat & SPI_CTRL_BSY) != 0);
+
+	return(0);
+}
+#endif /* !SK_SLIM || EFI_UNDI */
+
+#ifdef SK_DIAG
+/*
+ * Read the dword at address 'addr' from the VPD EEPROM.
+ *
+ * Needed Time:	MIN 1,3 ms	MAX 2,6 ms
+ *
+ * Note: The dword is returned in the endianess of the machine
+ *
+ * Returns the data read.
+ */
+SK_U32 VpdReadDWord(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+int		Addr)	/* VPD address */
+{
+	SK_U32	DWord;
+
+	/* start VPD read */
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
+		("VPD read dword at 0x%x: ", Addr));
+
+	Addr &= ~VPD_WRITE;	/* ensure the R/W bit is set to read */
+
+	VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)Addr);
+
+	/* ignore return code here */
+	(void)VpdWait(pAC, IoC, VPD_READ);
+
+	/* get the VPD from data register */
+	VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &DWord);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
+		("data = 0x%x\n", DWord));
+
+	return(DWord);
+}
+#endif /* SK_DIAG */
+
+
+#ifdef XXX
+/*
+	Write the dword 'data' at address 'addr' into the VPD EEPROM, and
+	verify that the data is written.
+
+ Needed Time:
+
+.						MIN		MAX
+. -------------------------------------------------------------------
+. write					1.8 ms	 3.6 ms
+. internal write cyles	0.7 ms	 7.0 ms
+. -------------------------------------------------------------------
+. over all program time	2.5 ms	10.6 ms
+. read					1.3 ms	 2.6 ms
+. -------------------------------------------------------------------
+. over all				3.8 ms	13.2 ms
+.
+ Returns	0:	success
+			1:	error,	I2C transfer does not terminate
+			2:	error,	data verify error
+
+ */
+static int VpdWriteDWord(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+int		Addr,	/* VPD address */
+SK_U32	Data)	/* VPD to write */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD write dword at addr 0x%x, data = 0x%x\n", Addr, Data));
+
+	/* write the VPD into data register */
+	VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, Data);
+
+	/* start VPD write */
+	VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(VPD_WRITE | Addr));
+
+	/* this may take up to 10.6 ms */
+	if (VpdWait(pAC, IoC, VPD_WRITE)) {
+		return(1);
+	}
+
+	/* verify data */
+	if (VpdReadDWord(pAC, IoC, Addr) != Data) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Data Verify Error\n"));
+		return(2);
+	}
+	return(0);
+}	/* VpdWriteDWord */
+
+#endif /* XXX */
+
+
+#ifndef SK_SLIM
+/*
+ *	Read one Stream of 'len' bytes of VPD, starting at 'addr' from
+ *	or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdWriteStream(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* data buffer */
+int		Addr,	/* VPD start address */
+int		Len)	/* number of bytes to read / to write */
+{
+	int		i;
+	int		Rtv;
+	SK_U8	Byte;
+	SK_U32	*pComp;	/* compare pointer */
+	SK_U32	DWord;	/* read data for compare */
+#if defined(SK_DIAG) || defined(DEBUG)
+	SK_U32	StartTime;
+	SK_U32	EndTime;
+	SK_U32	DeltaWr;
+	SK_U32	DeltaRd;
+#endif /* SK_DIAG || DEBUG */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("WriteStream:\n"));
+
+	Addr &= ~VPD_WRITE;	/* ensure the R/W bit is set to read */
+
+	/* Init Compare Pointer */
+	pComp = (SK_U32 *)buf;
+
+	for (i = 0; i < Len; i++) {
+		if ((i % SZ_LONG) == 0) {
+			/*
+			 * At the begin of each cycle read the Data Reg
+			 * So it is initialized even if only a few bytes are written.
+			 */
+			VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)Addr);
+
+			/* Wait for termination */
+			Rtv = VpdWait(pAC, IoC, VPD_READ);
+			if (Rtv != 0) {
+				return(i);
+			}
+		}
+
+		Byte = *(buf + i);
+
+		/* Write current byte */
+		VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), Byte);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+			("0x%02X ", Byte));
+
+		if (((i % SZ_LONG) == 3) || (i == (Len - 1))) {
+			/* New address needs to be written to VPD_ADDR reg */
+			VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(VPD_WRITE | Addr));
+
+#if defined(SK_DIAG) || defined(DEBUG)
+			SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+			/* Wait for termination */
+			Rtv = VpdWait(pAC, IoC, VPD_WRITE);
+			if (Rtv != 0) {
+				return(i - (i % SZ_LONG));
+			}
+
+#if defined(SK_DIAG) || defined(DEBUG)
+			SK_IN32(IoC, GMAC_TI_ST_VAL, &EndTime);
+
+			DeltaWr = HW_TICKS_TO_USEC(pAC, EndTime - StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+			/* Now re-read VPD to verify */
+			VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)Addr);
+
+#if defined(SK_DIAG) || defined(DEBUG)
+			SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+			/* Wait for termination */
+			Rtv = VpdWait(pAC, IoC, VPD_READ);
+			if (Rtv != 0) {
+				return(i - (i % SZ_LONG));
+			}
+
+#if defined(SK_DIAG) || defined(DEBUG)
+			SK_IN32(IoC, GMAC_TI_ST_VAL, &EndTime);
+
+			DeltaRd = HW_TICKS_TO_USEC(pAC, EndTime - StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+			/* get the VPD from data register */
+			VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &DWord);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+				("==> VPD read: 0x%08X, Wr=%u us, Rd=%u us\n",
+				DWord, DeltaWr, DeltaRd));
+
+			if (DWord != *pComp) {
+				/* Verify Error */
+				SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+					("WriteStream Verify Error at address 0x%02X "
+					 "(is 0x%08lX, exp. 0x%08lX)\n", Addr, DWord, *pComp));
+
+				/* Retry reading */
+				VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)Addr);
+
+#if defined(SK_DIAG) || defined(DEBUG)
+				SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+				/* Wait for termination */
+				Rtv = VpdWait(pAC, IoC, VPD_READ);
+				if (Rtv != 0) {
+					return(i - (i % SZ_LONG));
+				}
+
+#if defined(SK_DIAG) || defined(DEBUG)
+				SK_IN32(IoC, GMAC_TI_ST_VAL, &EndTime);
+
+				DeltaRd = HW_TICKS_TO_USEC(pAC, EndTime - StartTime);
+#endif /* SK_DIAG || DEBUG */
+
+				/* get the VPD from data register */
+				VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &DWord);
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+					("Re-read VPD: 0x%08X, Rd=%u us\n", DWord, DeltaRd));
+
+				if (DWord != *pComp) {
+					/* Verify Error */
+					SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+						("Verify Error, is 0x%08lX, exp. 0x%08lX)\n",
+						 DWord, *pComp));
+
+					return(i - (i % SZ_LONG));
+				}
+			}
+
+			Addr += SZ_LONG;
+
+			pComp++;
+		}
+	}
+
+	return(Len);
+}
+#endif /* !SK_SLIM */
+
+/*
+ *	Read one Stream of 'len' bytes of VPD, starting at 'addr' from
+ *	or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdReadStream(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* data buffer */
+int		Addr,	/* VPD start address */
+int		Len)	/* number of bytes to read / to write */
+{
+	int		i;
+	int		Rtv;
+	SK_U32	DWord;
+
+	Addr &= ~VPD_WRITE;	/* ensure the R/W bit is set to read */
+
+	for (i = 0; i < Len; i++) {
+		if ((i % SZ_LONG) == 0) {
+			/* New Address needs to be written to VPD_ADDR reg */
+			VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)Addr);
+
+			/* Wait for termination */
+			Rtv = VpdWait(pAC, IoC, VPD_READ);
+			if (Rtv != 0) {
+				return(i);
+			}
+
+			Addr += SZ_LONG;
+
+			/* get the VPD from data register */
+			VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &DWord);
+		}
+
+#ifdef SK_LITTLE_ENDIAN
+		*(buf + i) = *((char *)&DWord + (i % SZ_LONG));
+#else
+		*(buf + i) = *((char *)&DWord + (3 - (i % SZ_LONG)));
+#endif
+	}
+
+	return(Len);
+}
+
+
+/*
+ *	Read ore writes 'len' bytes of VPD, starting at 'addr' from
+ *	or to the I2C EEPROM.
+ *
+ * Returns number of bytes read / written.
+ */
+static int VpdTransferBlock(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* data buffer */
+int		addr,	/* VPD start address */
+int		len,	/* number of bytes to read / to write */
+int		dir)	/* transfer direction (VPD_READ or VPD_WRITE) */
+{
+	int		Rtv = 0;
+	int		vpd_rom_size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD %s block, addr = 0x%x, len = %d\n",
+		dir ? "write" : "read", addr, len));
+
+	if (len == 0) {
+		return(0);
+	}
+
+	vpd_rom_size = pAC->vpd.rom_size;
+
+	if (addr > vpd_rom_size - 4) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Address error: 0x%x, exp. < 0x%x\n",
+			addr, vpd_rom_size - 4));
+		return(0);
+	}
+
+	if (addr + len > vpd_rom_size) {
+		len = vpd_rom_size - addr;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("Warning: len was cut to %d\n", len));
+	}
+
+	/* WA for dev. #5.18 */
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_FE_P) {
+		SK_TST_MODE_ON(IoC);
+	}
+
+	if (dir == VPD_READ) {
+		Rtv = VpdReadStream(pAC, IoC, buf, addr, len);
+	}
+#ifndef SK_SLIM
+	else {
+		Rtv = VpdWriteStream(pAC, IoC, buf, addr, len);
+	}
+#endif /* !SK_SLIM */
+
+	SK_TST_MODE_OFF(IoC);
+
+	return(Rtv);
+}
+
+#if (!defined(SK_SLIM) || defined(EFI_UNDI)) /* needs to be enabled for ASF w/o EEPROM */
+/******************************************************************************
+ *
+ *	SpiReadBlock()	-	Read VPD from SPI flash
+ *
+ * Description:
+ *	Read 'len' bytes of VPD, starting at 'addr' from the SPI flash.
+ *	If the device doesn't have an EEPROM, the VPD is stored in the
+ *	SPI flash and is read only.
+ *
+ * Returns:
+ *	number of read bytes
+ */
+static int SpiReadBlock(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* data buffer */
+int		addr,	/* VPD start address */
+int		len)	/* number of bytes to read / to write */
+{
+	int		vpd_rom_size;
+	int		i;
+	union {
+		SK_U32	RegVal;
+		SK_U8	Byte[4];
+	} uBuf;
+	SK_U32	SpiCtrlReg;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD SPI read block, addr = 0x%x, len = %d\n", addr, len));
+
+	if (len == 0) {
+		return(0);
+	}
+
+	vpd_rom_size = pAC->vpd.rom_size;
+
+	if (addr > vpd_rom_size - 4) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Address error: 0x%x, exp. < 0x%x\n",
+			addr, vpd_rom_size - 4));
+		return(0);
+	}
+
+	if (addr + len > vpd_rom_size) {
+		len = vpd_rom_size - addr;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("Warning: len was cut to %d\n", len));
+	}
+
+	addr += VPD_SPI_ADDR;
+
+	for (i = 0; i < len; i++, buf++) {
+		if ((i % SZ_LONG) == 0) {
+			/* write SPI address */
+			SK_OUT32(IoC, SPI_ADDR, addr);
+
+			/* execute SPI read command */
+			SK_IN32(IoC, SPI_CTRL, &SpiCtrlReg);
+
+			SpiCtrlReg &= ~SPI_CTRL_INST_MSK;
+			SpiCtrlReg |= (1L << SPI_CTRL_INST_BASE);
+			SpiCtrlReg |= SPI_CTRL_STRT_SPI;
+
+			SK_OUT32(IoC, SPI_CTRL, SpiCtrlReg);
+
+			/* wait for the SPI to finish RD operation */
+			if (SpiWait(pAC, IoC)) {
+				break;
+			}
+
+			/* read the returned data */
+			SK_IN32(IoC, SPI_DATA, &uBuf.RegVal);
+
+			addr += 4;
+		}
+
+		*buf = uBuf.Byte[i % SZ_LONG];
+	}
+
+	return(i);
+}
+#endif /* !SK_SLIM || EFI_UNDI */
+
+/******************************************************************************
+ *
+ *	VpdReadBlock() - Read a block of config data from the EEPROM
+ *
+ * Description:
+ *	Read 'len' bytes of configuration data, starting at 'addr'.
+ *	VpdInit() needs to be run prior calling this function.
+ *
+ * Returns number of bytes read.
+ */
+int VpdReadBlock(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* buffer were the data should be stored */
+int		addr,	/* start reading at the VPD address */
+int		len)	/* number of bytes to read */
+{
+	int n;	/* number of read bytes */
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+	if (pAC->vpd.CfgInSpi) {
+		n = SpiReadBlock(pAC, IoC, buf, addr, len);
+	}
+	else
+#endif /* !SK_SLIM */
+	{
+		n = VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ);
+	}
+
+	return(n);
+}
+
+/******************************************************************************
+ *
+ *	VpdWriteBlock()	- Write a block of config data to the EEPROM
+ *
+ * Description:
+ *	Writes 'len' bytes of *buf to the VPD EEPROM, starting at 'addr'.
+ *	VpdInit() needs to be run prior calling this function.
+ *
+ * Returns number of bytes written.
+ */
+int VpdWriteBlock(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*buf,	/* buffer, holds the data to write */
+int		addr,	/* start writing at the VPD address */
+int		len)	/* number of bytes to write */
+{
+	int n;	/* number of written bytes */
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+	if (pAC->vpd.CfgInSpi) {
+		n = 0;
+	}
+	else
+#endif /* !SK_SLIM */
+	{
+		n = VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE);
+	}
+
+	return(n);
+}
+
+/******************************************************************************
+ *
+ *	VpdInit() - (re)initialize the VPD buffer
+ *
+ * Description:
+ *	Reads the VPD from the EEPROM into the VPD buffer.
+ *	Get the remaining read only and read / write space.
+ *
+ * Returns:
+ *	0:	success
+ *	1:	fatal VPD error
+ */
+int VpdInit(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC)	/* IO Context */
+{
+	SK_VPD_PARA *r, rp;	/* RW or RV */
+	int		i;
+	int		vpd_size;
+	int		vpd_ro_size;
+	SK_U8	byte;
+	SK_U32	our_reg2;
+	SK_U32	vpd_ctrl_add_reg;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... "));
+
+	/* Reset VPD status */
+	pAC->vpd.v.vpd_status = 0;
+
+	if (pAC->GIni.GILevel < SK_INIT_IO) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("Wrong Init Level"));
+		return(1);
+	}
+
+	if (!HW_SUP_VPD(pAC)) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("VPD not supported"));
+		return(1);
+	}
+
+	VPD_IN8(pAC, IoC, PCI_PM_NITEM, &byte);
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+	pAC->vpd.CfgInSpi = (byte != PCI_VPD_CAP_ID) && CHIP_ID_YUKON_2(pAC);
+#endif /* !SK_SLIM */
+
+	VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
+
+	pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
+
+	/*
+	 * this function might get used before the hardware is initialized
+	 * therefore we cannot always trust in GIChipId
+	 */
+
+	/* for Yukon the VPD size is always 256 */
+	vpd_size = VPD_SIZE_YUKON;
+
+	vpd_ro_size = vpd_size / 2;
+
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+		/*
+		 * Supreme: VPD may be in parallel flash or EEPROM
+		 * Ultra 2: VPD only in EEPROM
+		 *
+		 * Read VPD_CTRL_ADD to get length for VPD RO and RW section.
+		 */
+		SK_IN32(IoC, PCI_C2(pAC, IoC, VPD_CTRL_ADD), &vpd_ctrl_add_reg);
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_SUPR ||
+			(pAC->GIni.GIChipId >= CHIP_ID_YUKON_UL_2 &&
+			 (vpd_ctrl_add_reg & VPD_CTRL_ADD_VPD_SEL) != 0)) {
+
+			vpd_size = (int)((vpd_ctrl_add_reg & VPD_CTRL_ADD_VPD_END_MSK) >> 24) + 1;
+			vpd_size -= (int)((vpd_ctrl_add_reg & VPD_CTRL_ADD_VPD_START_MSK) >> 8);
+			vpd_size *= 4;
+
+			vpd_ro_size = (int)((vpd_ctrl_add_reg & VPD_CTRL_ADD_VPD_W_START_MSK) >> 16);
+			vpd_ro_size -= (int)((vpd_ctrl_add_reg & VPD_CTRL_ADD_VPD_START_MSK) >> 8);
+			vpd_ro_size *= 4;
+		}
+		else {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("VPD not supported"));
+			return(1);
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT,
+		("VPD Size = %d, VPD RO Size = %d\n", vpd_size, vpd_ro_size));
+
+	if (vpd_ro_size == 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("Error: VPD R/O size is 0\n"));
+		return(1);
+	}
+
+	if (vpd_size > VPD_SIZE) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("Error: Too much VPD (%u)\n", vpd_size));
+		return(1);
+	}
+
+	/* read the VPD into the VPD buffer */
+	if (VpdReadBlock(pAC, IoC, pAC->vpd.vpd_buf, 0, vpd_size) != vpd_size) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("Block Read Error\n"));
+		return(1);
+	}
+
+	pAC->vpd.vpd_size = vpd_size;
+
+#ifndef SK_SLIM
+	/* Asus K8V Se Deluxe bugfix. Correct VPD content */
+	i = 62;
+	if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8<E", 4)) {
+
+		pAC->vpd.vpd_buf[i + 2] = '8';
+	}
+#endif /* !SK_SLIM */
+
+	/* find the end tag of the RO area */
+	if ((r = vpd_find_para(pAC, VPD_RV, &rp)) == NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Encoding Error: RV Tag not found\n"));
+		return(1);
+	}
+
+	if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_ro_size) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Encoding Error: Invalid VPD struct size\n"));
+		return(1);
+	}
+
+	pAC->vpd.v.vpd_free_ro = r->p_len - 1;
+
+	/* test the checksum */
+	for (i = 0, byte = 0; (unsigned)i <= (unsigned)vpd_ro_size - r->p_len; i++) {
+		byte += pAC->vpd.vpd_buf[i];
+	}
+
+	if (byte != 0) {
+		/* checksum error */
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("VPD Checksum Error\n"));
+		return(1);
+	}
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+	if (pAC->vpd.CfgInSpi) {
+		pAC->vpd.v.vpd_free_rw = 0;
+		pAC->vpd.v.vpd_status |= VPD_NO_RW;
+	}
+	else {
+#endif /* !SK_SLIM */
+		/* find and check the end tag of the RW area */
+		if (!(r = vpd_find_para(pAC, VPD_RW, &rp))) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+				("Encoding Error: RW Tag not found\n"));
+			return(1);
+		}
+
+		if (r->p_val < pAC->vpd.vpd_buf + vpd_ro_size) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+				("Encoding Error: Invalid VPD struct size\n"));
+			return(1);
+		}
+
+		pAC->vpd.v.vpd_free_rw = r->p_len;
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+		if ((pAC->vpd.v.vpd_free_rw < 3) &&
+			(r->p_val == pAC->vpd.vpd_buf + vpd_ro_size + 6)) {
+			pAC->vpd.v.vpd_status |= VPD_NO_RW;
+		}
+	}
+#endif /* !SK_SLIM */
+
+	/* everything seems to be ok */
+	if (pAC->GIni.GIChipId != 0) {
+		pAC->vpd.v.vpd_status |= VPD_VALID;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT,
+		("done. Free RO = %d, Free RW = %d\n",
+		pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw));
+
+	return(0);
+}
+
+
+/*
+ *	find the Keyword 'key' in the VPD buffer and fills the
+ *	parameter struct 'p' with it's values
+ *
+ * returns	*p	success
+ *		0:	parameter was not found or VPD encoding error
+ */
+static SK_VPD_PARA *vpd_find_para(
+SK_AC		*pAC,	/* Adapters Context */
+const char	*key,	/* keyword to find (e.g. "MN") */
+SK_VPD_PARA	*p)		/* parameter description struct */
+{
+	char *v	;	/* points to VPD buffer */
+	int max;	/* Maximum Number of Iterations */
+	int len;
+
+	v = pAC->vpd.vpd_buf;
+	max = 128;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD find para %s .. ", key));
+
+	/* check mandatory resource type ID string (Product Name) */
+	if (*v != (char)RES_ID) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Error: Resource type ID (0x%x) missing\n", RES_ID));
+		return(NULL);
+	}
+
+	len = VPD_GET_RES_LEN(v);
+
+	if (SK_STRCMP(key, VPD_NAME) == 0) {
+		p->p_len = len;
+		p->p_val = VPD_GET_VAL(v);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+			("found, len = %d\n", len));
+		return(p);
+	}
+
+	v += 3 + len + 3;
+
+	for ( ; ; ) {
+		if (key[0] == v[0] && key[1] == v[1]) {
+
+			p->p_len = VPD_GET_VPD_LEN(v);
+			p->p_val = VPD_GET_VAL(v);
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+				("\nfound %s, len = %d\n", key, p->p_len));
+			return(p);
+		}
+
+		/* exit when reaching the "RW" Tag or the maximum of iterations */
+		max--;
+
+		if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) {
+			break;
+		}
+
+		len = 3 + VPD_GET_VPD_LEN(v);
+
+		if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
+			len += 3;					/* skip VPD-W */
+		}
+		v += len;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+			("\nscanning '%c%c' len = %d ", v[0], v[1], v[2]));
+	}
+
+#ifdef DEBUG
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("\nnot found para %s\n", key));
+
+	if (max == 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("key/len encoding error\n"));
+	}
+#endif /* DEBUG */
+	return(NULL);
+}
+
+
+/*
+ *	Move 'n' bytes. Begin with the last byte if 'n' is > 0,
+ *	Start with the last byte if n is < 0.
+ *
+ * returns nothing
+ */
+static void vpd_move_para(
+char	*start,		/* start of memory block */
+char	*end,		/* end of memory block to move */
+int		n)			/* number of bytes the memory block has to be moved */
+{
+	char *p;
+	int i;		/* number of byte copied */
+
+	if (n == 0) {
+		return;
+	}
+
+	i = (int) (end - start + 1);
+	if (n < 0) {
+		p = start + n;
+		while (i != 0) {
+			*p++ = *start++;
+			i--;
+		}
+	}
+	else {
+		p = end + n;
+		while (i != 0) {
+			*p-- = *end--;
+			i--;
+		}
+	}
+}
+
+
+/*
+ *	setup the VPD keyword 'key' at 'ip'.
+ *
+ * returns nothing
+ */
+static void vpd_insert_key(
+const char	*key,	/* keyword to insert */
+const char	*buf,	/* buffer with the keyword value */
+int		len,		/* length of the value string */
+char	*ip)		/* inseration point */
+{
+	SK_VPD_KEY *p;
+
+	p = (SK_VPD_KEY *)ip;
+	p->p_key[0] = key[0];
+	p->p_key[1] = key[1];
+	p->p_len = (unsigned char)len;
+
+	SK_MEMCPY(&p->p_val, buf, len);
+}
+
+
+/*
+ *	Setup the VPD end tag "RV" / "RW".
+ *	Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
+ *
+ * returns	0:	success
+ *		1:	encoding error
+ */
+static int vpd_mod_endtag(
+SK_AC	*pAC,		/* Adapters Context */
+char	*etp)		/* end pointer input position */
+{
+	SK_VPD_KEY	*p;
+	unsigned char	x;
+	int	i;
+	int	vpd_size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD modify endtag at 0x%x = '%c%c'\n", (SK_U32)etp, etp[0], etp[1]));
+
+	vpd_size = pAC->vpd.vpd_size;
+
+	p = (SK_VPD_KEY *)etp;
+
+	if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
+		/* something wrong here, encoding error */
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
+			("Encoding Error: invalid end tag\n"));
+		return(1);
+	}
+
+	if (etp > pAC->vpd.vpd_buf + vpd_size/2) {
+		/* create "RW" tag */
+		p->p_len = (unsigned char)(pAC->vpd.vpd_buf + vpd_size - etp - 4);
+		pAC->vpd.v.vpd_free_rw = (int)p->p_len;
+		i = pAC->vpd.v.vpd_free_rw;
+		etp += 3;
+	}
+	else {
+		/* create "RV" tag */
+		p->p_len = (unsigned char)(pAC->vpd.vpd_buf + vpd_size/2 - etp - 3);
+		pAC->vpd.v.vpd_free_ro = (int) p->p_len - 1;
+
+		/* setup checksum */
+		for (i = 0, x = 0; i < vpd_size/2 - p->p_len; i++) {
+			x += pAC->vpd.vpd_buf[i];
+		}
+		p->p_val = (char)0 - x;
+		i = pAC->vpd.v.vpd_free_ro;
+		etp += 4;
+	}
+
+	while (i) {
+		*etp++ = 0x00;
+		i--;
+	}
+
+	return(0);
+}
+
+
+/*
+ *	Insert a VPD keyword into the VPD buffer.
+ *
+ *	The keyword 'key' is inserted at the position 'ip' in the VPD buffer.
+ *	The keywords behind the input position will be moved.
+ *	The VPD end tag "RV" or "RW" is generated again.
+ *
+ * returns	0:	success
+ *		2:	value string was cut
+ *		4:	VPD full, keyword was not written
+ *		6:	fatal VPD error
+ *
+ */
+int	VpdSetupPara(
+SK_AC	*pAC,		/* Adapters Context */
+const char	*key,	/* keyword to insert */
+const char	*buf,	/* buffer with the keyword value */
+int		len,		/* length of the keyword value */
+int		type,		/* VPD_RO_KEY or VPD_RW_KEY */
+int		op)			/* operation to do: ADD_KEY or OWR_KEY */
+{
+	SK_VPD_PARA vp = { 0, 0 }; /* to make prefast happy */
+	char	*etp;		/* end tag position */
+	char	*ip;		/* input position inside the VPD buffer */
+	int		free_sp;	/* remaining space in selected area */
+	int		rtv;		/* return code */
+	int		head;		/* additional header bytes to move */
+	int		found;		/* additional bytes if the keyword was found */
+	int		vpd_size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("VPD setup para key = %s, val = %s\n", key, buf));
+
+	vpd_size = pAC->vpd.vpd_size;
+
+	rtv = 0;
+	ip = 0;
+	if (type == VPD_RW_KEY) {
+		/* end tag is "RW" */
+		free_sp = pAC->vpd.v.vpd_free_rw;
+		etp = pAC->vpd.vpd_buf + (vpd_size - free_sp - 1 - 3);
+	}
+	else {
+		/* end tag is "RV" */
+		free_sp = pAC->vpd.v.vpd_free_ro;
+		etp = pAC->vpd.vpd_buf + (vpd_size/2 - free_sp - 4);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("Free RO = %d, Free RW = %d\n",
+		pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw));
+
+	head = 0;
+	found = 0;
+	if (op == OWR_KEY) {
+		if (vpd_find_para(pAC, key, &vp)) {
+			found = 3;
+			ip = vp.p_val - 3;
+			free_sp += vp.p_len + 3;
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+				("Overwrite Key\n"));
+		}
+		else {
+			op = ADD_KEY;
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+				("Add Key\n"));
+		}
+	}
+
+	if (op == ADD_KEY) {
+		ip = etp;
+		vp.p_len = 0;
+		head = 3;
+	}
+
+	if (len + 3 > free_sp) {
+		if (free_sp < 7) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD Buffer Overflow, keyword not written\n"));
+			return(4);
+		}
+		/* cut it again */
+		len = free_sp - 3;
+		rtv = 2;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("VPD Buffer Full, Keyword was cut\n"));
+	}
+
+	vpd_move_para(ip + vp.p_len + found, etp + 2, len-vp.p_len + head);
+
+	vpd_insert_key(key, buf, len, ip);
+
+	if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) {
+		pAC->vpd.v.vpd_status &= ~VPD_VALID;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("VPD Encoding Error\n"));
+		return(6);
+	}
+
+	return(rtv);
+}
+
+#if (!defined(SK_SLIM) || defined(EFI_UNDI))
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *
+ * return:	A pointer to the s_vpd_status structure.
+ */
+SK_VPD_STATUS *VpdStat(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC)	/* IO Context */
+{
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		(void)VpdInit(pAC, IoC);
+	}
+	return(&pAC->vpd.v);
+}
+
+
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *	Scan the VPD buffer for VPD keywords and create the VPD keyword list
+ *	by copying the keywords to 'buf', terminated with a '\0'.
+ *
+ * Exceptions:
+ *		o The Resource Type ID String (product name) is called "Name"
+ *		o The VPD end tags 'RV' and 'RW' are not listed
+ *
+ *	The number of copied keywords is counted in 'elements'.
+ *
+ * returns	0:	success
+ *		2:	buffer overflow, one or more keywords are missing
+ *		6:	fatal VPD error
+ *
+ *	example values after returning:
+ *
+ *		buf =	"Name\0PN\0EC\0MN\0SN\0CP\0VF\0VL\0YA\0"
+ *		*len =		30
+ *		*elements =	 9
+ */
+int VpdKeys(
+SK_AC	*pAC,		/* Adapters Context */
+SK_IOC	IoC,		/* IO Context */
+char	*buf,		/* buffer where to copy the keywords */
+int		*len,		/* buffer length */
+int		*elements)	/* number of keywords returned */
+{
+	char *v;
+	int n;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("list VPD keys .. "));
+
+	*elements = 0;
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		if (VpdInit(pAC, IoC) != 0) {
+			*len = 0;
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD Init Error, terminated\n"));
+			return(6);
+		}
+	}
+
+	n = SK_STRLEN(VPD_NAME) + 1;
+
+	if (*len < n) {
+		*len = 0;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("buffer overflow\n"));
+		return(2);
+	}
+
+	SK_STRNCPY(buf, VPD_NAME, n);
+
+	v = pAC->vpd.vpd_buf;
+
+	buf += n;
+	*elements = 1;
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+		("Res.ID: 0x%02X (len: %u), ", (unsigned char)v[0], v[1]));
+
+	v += 3 + VPD_GET_RES_LEN(v) + 3;
+
+	for ( ; ; ) {
+		/* exit when reaching the "RW" Tag */
+		if (SK_MEMCMP(VPD_RW, v, 2) == 0) {
+			break;
+		}
+
+		if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
+			v += 3 + VPD_GET_VPD_LEN(v) + 3;	/* skip VPD-W */
+			continue;
+		}
+
+		if (*len < n + 3) {
+			*len = n;
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("buffer overflow\n"));
+			return(2);
+		}
+
+		SK_MEMCPY(buf, v, 2);
+
+		buf += 2;
+		*buf++ = '\0';
+		n += 3;
+		v += 3 + VPD_GET_VPD_LEN(v);
+		*elements += 1;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
+			("'%c%c' ", v[0], v[1]));
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("\n"));
+	*len = n;
+	return(0);
+}
+#endif /* !SK_SLIM || EFI_UNDI */
+
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *	Search for the VPD keyword 'key' and copy its value to 'buf'.
+ *	Add a terminating '\0'.
+ *	If the value does not fit into the buffer cut it after 'len' - 1 bytes.
+ *
+ * returns	0:	success
+ *		1:	keyword not found
+ *		2:	value string was cut
+ *		3:	VPD transfer timeout
+ *		6:	fatal VPD error
+ */
+int VpdRead(
+SK_AC		*pAC,	/* Adapters Context */
+SK_IOC		IoC,	/* IO Context */
+const char	*key,	/* keyword to read (e.g. "MN") */
+char		*buf,	/* buffer where to copy the keyword value */
+int			*len)	/* buffer length */
+{
+	SK_VPD_PARA *p, vp;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("VPD read %s .. ", key));
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		if (VpdInit(pAC, IoC) != 0) {
+			*len = 0;
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD init error\n"));
+			return(6);
+		}
+	}
+
+	if ((p = vpd_find_para(pAC, key, &vp)) == NULL) {
+		*len = 0;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("not found para %s\n", key));
+		return(1);
+	}
+
+	if (p->p_len > (unsigned)(*len - 1)) {
+		p->p_len = *len - 1;
+	}
+
+	SK_MEMCPY(buf, p->p_val, p->p_len);
+
+	buf[p->p_len] = '\0';
+	*len = p->p_len;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
+		("0x%02X 0x%02X 0x%02X 0x%02X ... '%c%c%c%c...', len = %d\n",
+		 (unsigned char)buf[0], (unsigned char)buf[1],
+		 (unsigned char)buf[2], (unsigned char)buf[3],
+		 buf[0], buf[1], buf[2], buf[3], *len));
+
+	return(0);
+}
+
+#if (!defined(SK_SLIM) || defined(EFI_UNDI))
+/*
+ *	Check whether a given key may be written
+ *
+ * returns
+ *	SK_TRUE		Yes, it may be written
+ *	SK_FALSE	No
+ */
+SK_BOOL VpdMayWrite(
+char	*key)	/* keyword to write (allowed values "Yx", "Vx") */
+{
+	if ((*key != 'Y' && *key != 'V') ||
+		key[1] < '0' || key[1] > 'Z' ||
+		(key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
+
+		return(SK_FALSE);
+	}
+	return(SK_TRUE);
+}
+
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *	Insert/overwrite the keyword 'key' in the VPD buffer.
+ *	Cut the keyword value if it does not fit into the VPD read / write area.
+ *
+ * returns	0:	success
+ *		2:	value string was cut
+ *		3:	VPD transfer timeout
+ *		4:	VPD full, keyword was not written
+ *		5:	keyword cannot be written
+ *		6:	fatal VPD error
+ */
+int VpdWrite(
+SK_AC		*pAC,	/* Adapters Context */
+SK_IOC		IoC,	/* IO Context */
+const char	*key,	/* keyword to write (allowed values "Yx", "Vx") */
+const char	*buf)	/* buffer where the keyword value can be read from */
+{
+	int len;		/* length of the keyword to write */
+	int rtv;		/* return code */
+	int rtv2;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
+		("VPD write %s = %s\n", key, buf));
+
+	if ((*key != 'Y' && *key != 'V') ||
+		key[1] < '0' || key[1] > 'Z' ||
+		(key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("illegal key tag, keyword not written\n"));
+		return(5);
+	}
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		if (VpdInit(pAC, IoC) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD init error\n"));
+			return(6);
+		}
+	}
+
+	rtv = 0;
+	len = SK_STRLEN(buf);
+	if (len > VPD_MAX_LEN) {
+		/* cut it */
+		len = VPD_MAX_LEN;
+		rtv = 2;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("keyword too long, cut after %d bytes\n", VPD_MAX_LEN));
+	}
+
+	if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("VPD write error\n"));
+		return(rtv2);
+	}
+
+	return(rtv);
+}
+
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *	Remove the VPD keyword 'key' from the VPD buffer.
+ *	Only the keywords in the read/write area can be deleted.
+ *	Keywords in the read only area cannot be deleted.
+ *
+ * returns	0:	success, keyword was removed
+ *		1:	keyword not found
+ *		5:	keyword cannot be deleted
+ *		6:	fatal VPD error
+ */
+int VpdDelete(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*key)	/* keyword to read (e.g. "MN") */
+{
+	SK_VPD_PARA *p, vp;
+	char *etp;
+	int	vpd_size;
+
+	vpd_size = pAC->vpd.vpd_size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key));
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		if (VpdInit(pAC, IoC) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD init error\n"));
+			return(6);
+		}
+	}
+
+	if ((p = vpd_find_para(pAC, key, &vp)) == NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("keyword not found\n"));
+		return(1);
+	}
+
+	if (p->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
+		/* try to delete read only keyword */
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("cannot delete RO keyword\n"));
+		return(5);
+	}
+
+	etp = pAC->vpd.vpd_buf + (vpd_size-pAC->vpd.v.vpd_free_rw-1-3);
+
+	vpd_move_para(vp.p_val + vp.p_len, etp + 2,
+		- ((int)(vp.p_len + 3)));
+
+	if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) {
+		pAC->vpd.v.vpd_status &= ~VPD_VALID;
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+			("VPD encoding error\n"));
+		return(6);
+	}
+
+	return(0);
+}
+
+/*
+ *	If the VPD buffer contains valid data write the VPD read/write area
+ *	back to the VPD EEPROM.
+ *
+ * returns	0:	success
+ *		2:	not supported
+ *		3:	VPD transfer timeout
+ */
+int VpdUpdate(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC)	/* IO Context */
+{
+	int vpd_size;
+
+	vpd_size = pAC->vpd.vpd_size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD update .. "));
+
+#ifndef SK_SLIM		/* needs to be enabled for ASF w/o EEPROM */
+	if (pAC->vpd.CfgInSpi) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("not supported"));
+		return(2);
+	}
+#endif /* !SK_SLIM */
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) != 0) {
+		if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf + vpd_size/2,
+			vpd_size/2, vpd_size/2, VPD_WRITE) != vpd_size/2) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("transfer timed out\n"));
+			return(3);
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("done\n"));
+	return(0);
+}
+
+/*
+ *	Copy the content of the VPD EEPROM to the VPD buffer if not already done.
+ *	If the keyword "VF" is not present it will be created and
+ *	the error log message will be stored to this keyword.
+ *	If "VF" is not present the error log message will be stored to the
+ *	keyword "VL". "VL" will created or overwritten if "VF" is present.
+ *	The VPD read/write area is saved to the VPD EEPROM.
+ *
+ * returns nothing, errors will be ignored.
+ */
+void VpdErrLog(
+SK_AC	*pAC,	/* Adapters Context */
+SK_IOC	IoC,	/* IO Context */
+char	*msg)	/* error log message */
+{
+	SK_VPD_PARA vf;
+	int len;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
+		("VPD error log message %s\n", msg));
+
+	if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
+		if (VpdInit(pAC, IoC) != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
+				("VPD init error\n"));
+			return;
+		}
+	}
+
+	len = SK_STRLEN(msg);
+	if (len > VPD_MAX_LEN) {
+		/* cut it */
+		len = VPD_MAX_LEN;
+	}
+
+	if (vpd_find_para(pAC, VPD_VF, &vf) != NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n"));
+		(void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY);
+	}
+	else {
+		SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n"));
+		(void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY);
+	}
+
+	(void)VpdUpdate(pAC, IoC);
+}
+#endif /* !SK_SLIM || EFI_UNDI*/
+
diff -ruN linux/drivers/net/sk98lin/skxmac2.c linux-new/drivers/net/sk98lin/skxmac2.c
--- linux/drivers/net/sk98lin/skxmac2.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/skxmac2.c	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,4125 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/common/V6/skxmac2.c#17 $
+ * Project:	Gigabit Ethernet Adapters, Common Modules
+ * Version:	$Revision: #17 $, $Change: 6262 $
+ * Date:	$DateTime: 2011/05/11 11:41:59 $
+ * Purpose:	Contains functions to initialize the MACs and PHYs
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* local variables ************************************************************/
+
+/* function prototypes *******************************************************/
+static void	SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL);
+static int	SkGmAutoNegDoneMarv(SK_AC*, SK_IOC, int);
+
+#ifndef VCPU
+/* OptimaEEE PHY AFE workaround */
+typedef struct s_PhyHack {
+	SK_U16	PhyReg;		/* PHY register */
+	SK_U16	PhyVal;		/* Value to write */
+} OPT_EEE_HACK;
+
+static OPT_EEE_HACK OptimaEeeAfe[] = {
+ { 0x156, 0x58ce },
+ { 0x153, 0x99eb },
+ { 0x141, 0x8064 },
+/* { 0x155, 0x130b },*/
+ { 0x000, 0x0000 },
+ { 0x151, 0x8433 },
+ { 0x14b, 0x8c44 },
+ { 0x14c, 0x0f90 },
+ { 0x14f, 0x39aa },
+/* { 0x154, 0x2f39 },*/
+ { 0x14d, 0xba33 },
+ { 0x144, 0x0048 },
+ { 0x152, 0x2010 },
+/* { 0x158, 0x1223 },*/
+ { 0x140, 0x4444 },
+ { 0x154, 0x2f3b },
+ { 0x158, 0xb203 },
+ { 0x157, 0x2029 },
+};
+#endif /* !VCPU */
+
+/******************************************************************************
+ *
+ *	SkGmPhyRead() - Read from GPHY register
+ *
+ * Description:	reads a 16-bit word from GPHY through MDIO
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	error during MDIO read
+ *	2	timeout
+ */
+int SkGmPhyRead(
+SK_AC	*pAC,			/* Adapter Context */
+SK_IOC	IoC,			/* I/O Context */
+int		Port,			/* Port Index (MAC_1 + n) */
+int		PhyReg,			/* Register Address (Offset) */
+SK_U16	SK_FAR *pVal)	/* Pointer to Value */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		Word;
+	SK_U16		Ctrl;
+	SK_U32		StartTime;
+	SK_U32		Delta;
+	SK_U32		TimeOut;
+	int			Rtv;
+
+	Rtv = 0;
+
+	*pVal = 0xffff;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* additional check for MDC/MDIO activity */
+	GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
+
+	if ((Ctrl & GM_SMI_CT_BUSY) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("SkGmPhyRead, Port: %d, Reg: %2d, Busy (Ctrl=0x%04X)\n",
+			 Port, PhyReg, Ctrl));
+
+		return(1);
+	}
+
+	/* set PHY-Register offset and 'Read' OpCode (= 1) */
+	Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
+		GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
+
+	GM_OUT16(IoC, Port, GM_SMI_CTRL, Word);
+
+	/* additional check for MDC/MDIO activity */
+	GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
+
+	if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("SkGmPhyRead, Port: %d, Reg: %2d, Error (Ctrl=0x%04X)\n",
+			 Port, PhyReg, Ctrl));
+
+		return(1);
+	}
+
+	Word |= GM_SMI_CT_BUSY;
+
+	/* get current value of timestamp timer */
+	StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+	/* set timeout to 10 ms */
+	TimeOut = HW_MS_TO_TICKS(pAC, 10);
+
+	do {	/* wait until 'Busy' is cleared and 'ReadValid' is set */
+#ifdef VCPU
+		VCPUwaitTime(1000);
+#endif /* VCPU */
+
+		/* get delta value of timestamp timer */
+		Delta = SkHwGetTimeDelta(pAC, IoC, StartTime);
+
+		GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
+
+		/* Error on reading SMI Control Register */
+		if (Ctrl == 0xffff) {
+			return(1);
+		}
+
+		/* check also if 'Busy'-bit is still set */
+		if ((Delta > TimeOut) && (Ctrl & GM_SMI_CT_BUSY) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmPhyRead, Port: %d, Reg: %2d, Timeout (Ctrl=0x%04X)\n",
+				 Port, PhyReg, Ctrl));
+
+			Rtv = 2;
+			break;
+		}
+
+	} while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY));
+
+	GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
+
+	/* dummy read after GM_IN16() */
+	SK_IN32(IoC, B2_TI_VAL, &TimeOut);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmPhyRead, Port: %d, Reg: %2d, Val = 0x%04X\n",
+		 Port, PhyReg, *pVal));
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("Read 0x%04X from PHY reg %u on port %c\n",
+		*pVal, PhyReg, 'A' + Port);
+#endif /* VCPU || SK_DIAG */
+
+	return(Rtv);
+}	/* SkGmPhyRead */
+
+
+/******************************************************************************
+ *
+ *	SkGmPhyWrite() - Write to GPHY register
+ *
+ * Description:	writes a 16-bit word to GPHY through MDIO
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	error during MDIO read
+ *	2	timeout
+ */
+int SkGmPhyWrite(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		PhyReg,		/* Register Address (Offset) */
+SK_U16	Val)		/* Value */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		Ctrl;
+	SK_U32		StartTime;
+	SK_U32		Delta;
+	SK_U32		TimeOut;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmPhyWrite, Port: %d, Reg: %2d, Val = 0x%04X\n",
+		 Port, PhyReg, Val));
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* write the PHY register's value */
+	GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
+
+#ifdef DEBUG
+	/* additional check for MDC/MDIO activity */
+	GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl);
+
+	if (Ctrl != Val) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("PHY write impossible on Port %d (Val=0x%04X)\n", Port, Ctrl));
+
+		return(1);
+	}
+#endif /* DEBUG */
+
+	/* set PHY-Register offset and 'Write' OpCode (= 0) */
+	Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
+		GM_SMI_CT_REG_AD(PhyReg));
+
+	GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl);
+
+	/* get current value of timestamp timer */
+	StartTime = SkHwGetTimeDelta(pAC, IoC, 0);
+
+	/* set timeout to 10 ms */
+	TimeOut = HW_MS_TO_TICKS(pAC, 10);
+
+	do {	/* wait until 'Busy' is cleared */
+#ifdef VCPU
+		VCPUwaitTime(1000);
+#endif /* VCPU */
+
+		/* get delta value of timestamp timer */
+		Delta = SkHwGetTimeDelta(pAC, IoC, StartTime);
+
+		GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
+
+		/* Error on reading SMI Control Register */
+		if (Ctrl == 0xffff) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("PHY write error on Port %d (Ctrl=0x%04X)\n", Port, Ctrl));
+			return(1);
+		}
+
+		/* check also if 'Busy'-bit is still set */
+		if ((Delta > TimeOut) && (Ctrl & GM_SMI_CT_BUSY) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("PHY write timeout on Port %d (Ctrl=0x%04X)\n", Port, Ctrl));
+			return(2);
+		}
+
+	} while ((Ctrl & GM_SMI_CT_BUSY) != 0);
+
+	/* dummy read after GM_IN16() */
+	SK_IN32(IoC, B2_TI_VAL, &TimeOut);
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("Wrote 0x%04X to PHY reg %u on port %c\n",
+		Val, PhyReg, 'A' + Port);
+#endif /* VCPU || SK_DIAG */
+
+	return(0);
+}	/* SkGmPhyWrite */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGmPtpRead() - Read from PTP (Precise Time Protocol) register
+ *
+ * Description:	reads a 16-bit word from PTP through AVB Command Register
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	error during AVB read
+ */
+int SkGmPtpRead(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* AVB Port Index */
+int		PtpReg,		/* Register Address (Offset) */
+SK_U16	*pVal)		/* Pointer to Value */
+{
+	SK_U16	Ctrl;
+	int		Rtv;
+
+	Rtv = 0;
+
+	*pVal = 0xffff;
+
+	/* additional check for AVB activity */
+	SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+	if ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("SkGmPtpRead, Reg: %2d, Busy (Ctrl=0x%04X)\n",
+			 PtpReg, Ctrl));
+
+		return(1);
+	}
+
+	Ctrl = (SK_U16)(PTP_AVB_COMMAND_AVBBUSY |
+		(AVB_READ << PTP_AVB_COMMAND_AVBOP_BASE) |
+		(Port << PTP_AVB_COMMAND_AVBPORT_BASE) |
+		(PtpReg & PTP_AVB_COMMAND_AVBADDR_MSK));
+
+	SK_OUT16(IoC, PTP_AVB_COMMAND, Ctrl);
+
+	do {
+		SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+		/* additional check for AVB activity */
+		if (Ctrl == 0xffff) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmPtpRead, Reg: %2d, Error (Ctrl=0x%04X)\n",
+				 PtpReg, Ctrl));
+
+			return(1);
+		}
+
+	} while ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0);
+
+	SK_IN16(IoC, PTP_AVB_DATA, pVal);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmPtpRead, Reg: %2d, Val = 0x%04X\n",
+		 PtpReg, *pVal));
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("Read 0x%04X from PTP reg %u, Port 0x%X\n",
+		*pVal, PtpReg, Port);
+#endif /* VCPU || SK_DIAG */
+
+	return(Rtv);
+}	/* SkGmPtpRead */
+
+
+/******************************************************************************
+ *
+ *	SkGmPtpReadDbl() - Read from PTP (Precise Time Protocol) register
+ *
+ * Description:	reads 2x 16-bit word from PTP through AVB Command Register
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	error during AVB read
+ */
+int SkGmPtpReadDbl(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* AVB Port Index */
+int		PtpReg,		/* Register Address (Offset) */
+SK_U32	*pVal)		/* Pointer to Value */
+{
+	SK_U16	Ctrl;
+	SK_U16	Word;
+	int		Rtv;
+
+	Rtv = 0;
+
+	*pVal = 0xffff;
+
+	/* additional check for AVB activity */
+	SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+	if ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("SkGmPtpReadDbl, Reg: %2d, Busy (Ctrl=0x%04X)\n",
+			 PtpReg, Ctrl));
+
+		return(1);
+	}
+
+	Ctrl = (SK_U16)(PTP_AVB_COMMAND_AVBBUSY |
+		(AVB_READ_INC << PTP_AVB_COMMAND_AVBOP_BASE) |
+		(Port << PTP_AVB_COMMAND_AVBPORT_BASE) |
+		(PtpReg & PTP_AVB_COMMAND_AVBADDR_MSK));
+
+	SK_OUT16(IoC, PTP_AVB_COMMAND, Ctrl);
+
+	do {
+		SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+		/* additional check for AVB activity */
+		if (Ctrl == 0xffff) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmPtpReadDbl, Reg: %2d, Error (Ctrl=0x%04X)\n",
+				 PtpReg, Ctrl));
+
+			return(1);
+		}
+
+	} while ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0);
+
+	SK_IN16(IoC, PTP_AVB_DATA, &Word);
+
+	*pVal = Word;
+
+	do {
+		SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+		/* additional check for AVB activity */
+		if (Ctrl == 0xffff) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmPtpReadDbl, Reg: %2d, Error (Ctrl=0x%04X)\n",
+				 PtpReg, Ctrl));
+
+			return(1);
+		}
+
+	} while ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0);
+
+	SK_IN16(IoC, PTP_AVB_DATA, &Word);
+
+	*pVal |= (SK_U32)Word << 16;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmPtpReadDbl, Reg: %2d, Val = 0x%08lX\n",
+		 PtpReg, *pVal));
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("Read 0x%08lX from PTP reg %u, Port 0x%X\n",
+		*pVal, PtpReg, Port);
+#endif /* VCPU || SK_DIAG */
+
+	return(Rtv);
+}	/* SkGmPtpReadDbl */
+
+
+/******************************************************************************
+ *
+ *	SkGmPtpWrite() - Write to PTP (Precise Time Protocol) register
+ *
+ * Description:	writes a 16-bit word to PTP through AVB Command Register
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	error during AVB read
+ */
+int SkGmPtpWrite(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* AVB Port Index */
+int		PtpReg,		/* Register Address (Offset) */
+SK_U16	Val)		/* Value */
+{
+	SK_U16	Ctrl;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmPtpWrite, Reg: %2d, Val = 0x%04X\n",
+		 PtpReg, Val));
+
+	/* additional check for AVB activity */
+	SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+	if ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("SkGmPtpWrite, Reg: %2d, Busy (Ctrl=0x%04X)\n",
+			 PtpReg, Ctrl));
+
+		return(1);
+	}
+
+	SK_OUT16(IoC, PTP_AVB_DATA, Val);
+
+	Ctrl = (SK_U16)(PTP_AVB_COMMAND_AVBBUSY |
+		(AVB_WRITE << PTP_AVB_COMMAND_AVBOP_BASE) |
+		(Port << PTP_AVB_COMMAND_AVBPORT_BASE) |
+		(PtpReg & PTP_AVB_COMMAND_AVBADDR_MSK));
+
+	SK_OUT16(IoC, PTP_AVB_COMMAND, Ctrl);
+
+	do {
+		SK_IN16(IoC, PTP_AVB_COMMAND, &Ctrl);
+
+		/* additional check for AVB activity */
+		if (Ctrl == 0xffff) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmPtpWrite, Reg: %2d, Error (Ctrl=0x%04X)\n",
+				 PtpReg, Ctrl));
+
+			return(1);
+		}
+
+	} while ((Ctrl & PTP_AVB_COMMAND_AVBBUSY) != 0);
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("Wrote 0x%04X to PTP reg %u, Port 0x%X\n",
+		Val, PtpReg, Port);
+#endif /* VCPU || SK_DIAG */
+
+	return(0);
+}	/* SkGmPtpWrite */
+#endif /* !SK_SLIM */
+
+
+#ifdef SK_DIAG
+/******************************************************************************
+ *
+ *	SkGePhyRead() - Read from PHY register
+ *
+ * Description:	calls a read PHY routine dep. on adapter type
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGePhyRead(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		PhyReg,		/* Register Address (Offset) */
+SK_U16	*pVal)		/* Pointer to Value */
+{
+	pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal);
+}	/* SkGePhyRead */
+
+
+/******************************************************************************
+ *
+ *	SkGePhyWrite() - Write to PHY register
+ *
+ * Description:	calls a write PHY routine dep. on adapter type
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGePhyWrite(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		PhyReg,		/* Register Address (Offset) */
+SK_U16	Val)		/* Value */
+{
+	pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val);
+}	/* SkGePhyWrite */
+#endif /* SK_DIAG */
+
+
+/******************************************************************************
+ *
+ *	SkMacPromiscMode() - Enable / Disable Promiscuous Mode
+ *
+ * Description:
+ *	enables / disables promiscuous mode by setting Receive Control Register
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacPromiscMode(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+SK_BOOL	Enable)	/* Enable / Disable */
+{
+	SK_U16	RcReg;
+
+	GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
+
+	/* enable or disable unicast and multicast filtering */
+	if (Enable) {
+		RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
+	}
+	else {
+		RcReg |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
+	}
+	/* setup Receive Control Register */
+	GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);
+
+}	/* SkMacPromiscMode*/
+
+
+/******************************************************************************
+ *
+ *	SkMacHashing() - Enable / Disable Hashing
+ *
+ * Description:
+ *	enables / disables hashing by setting Receive Control Register
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacHashing(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+SK_BOOL	Enable)	/* Enable / Disable */
+{
+	SK_U16	RcReg;
+
+	GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
+
+	/* enable or disable multicast filtering */
+	if (Enable) {
+		RcReg |= GM_RXCR_MCF_ENA;
+	}
+	else {
+		RcReg &= ~GM_RXCR_MCF_ENA;
+	}
+	/* setup Receive Control Register */
+	GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);
+
+}	/* SkMacHashing*/
+
+
+#ifdef SK_DIAG
+/******************************************************************************
+ *
+ *	SkGmSetRxCmd() - Modify the value of the GMAC's Rx Control Register
+ *
+ * Description:
+ *	The features
+ *	 - FCS (CRC) stripping,				SK_STRIP_FCS_ON/OFF
+ *	 - don't set GMR_FS_LONG_ERR		SK_BIG_PK_OK_ON/OFF
+ *		for frames > 1514 bytes
+ *	- enable Rx of own packets			SK_SELF_RX_ON/OFF
+ *
+ *	for incoming packets may be enabled/disabled by this function.
+ *	Additional modes may be added later.
+ *	Multiple modes can be enabled/disabled at the same time.
+ *	The new configuration is written to the Rx Command register immediately.
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmSetRxCmd(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		Mode)		/* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
+						SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
+{
+	SK_U16	RxCmd;
+
+	if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
+
+		GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd);
+
+		if ((Mode & SK_STRIP_FCS_ON) != 0) {
+			RxCmd |= GM_RXCR_CRC_DIS;
+		}
+		else {
+			RxCmd &= ~GM_RXCR_CRC_DIS;
+		}
+		/* Write the new mode to the Rx Control register */
+		GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
+	}
+
+	if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
+
+		GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd);
+
+		if ((Mode & SK_BIG_PK_OK_ON) != 0) {
+			RxCmd |= GM_SMOD_JUMBO_ENA;
+		}
+		else {
+			RxCmd &= ~GM_SMOD_JUMBO_ENA;
+		}
+		/* Write the new mode to the Serial Mode register */
+		GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
+	}
+}	/* SkGmSetRxCmd */
+
+
+/******************************************************************************
+ *
+ *	SkMacSetRxCmd() - Modify the value of the MAC's Rx Control Register
+ *
+ * Description:	modifies the MAC's Rx Control register
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacSetRxCmd(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		Mode)		/* Rx Mode */
+{
+	SkGmSetRxCmd(pAC, IoC, Port, Mode);
+
+}	/* SkMacSetRxCmd */
+
+
+/******************************************************************************
+ *
+ *	SkMacCrcGener() - Enable / Disable CRC Generation
+ *
+ * Description:	enables / disables CRC generation
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacCrcGener(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+SK_BOOL	Enable)	/* Enable / Disable */
+{
+	SK_U16	Word;
+
+	GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
+
+	if (Enable) {
+		Word &= ~GM_TXCR_CRC_DIS;
+	}
+	else {
+		Word |= GM_TXCR_CRC_DIS;
+	}
+	/* setup Tx Control Register */
+	GM_OUT16(IoC, Port, GM_TX_CTRL, Word);
+
+}	/* SkMacCrcGener*/
+
+#endif /* SK_DIAG */
+
+
+/******************************************************************************
+ *
+ *	SkGmSoftRst() - Do a GMAC software reset
+ *
+ * Description:
+ *	The PHY registers should not be affected during this kind of software reset.
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmSoftRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_U16	EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
+	SK_U16	RxCtrl;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmSoftRst: Port %d\n", Port));
+
+	/* reset the statistics module */
+	(void)SkGmResetCounter(pAC, IoC, Port);
+
+	/* disable all GMAC IRQs */
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
+
+	if (pAC->GIni.GP[Port].PState != SK_PRT_RESET) {
+		/* disable all PHY IRQs */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
+	}
+
+	/* clear the Hash Register */
+	GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
+
+	/* enable Unicast and Multicast filtering */
+	GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
+
+	GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
+
+}	/* SkGmSoftRst */
+
+
+/******************************************************************************
+ *
+ *	SkGmHardRst() - Do a GMAC hardware reset
+ *
+ * Description:
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmHardRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_U32	DWord;
+#if defined(QUICK_LINK) || defined(SK_DIAG)
+	SK_U8	Byte;
+#endif /* QUICK_LINK || SK_DIAG */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmHardRst: Port %d\n", Port));
+
+#if defined(VCPU) || defined(SK_DIAG)
+	c_print("\nSkGmHardRst: Port %c\n", 'A' + Port);
+#endif /* VCPU || SK_DIAG */
+
+	/* WA code for COMA mode */
+	if (pAC->GIni.GIYukonLite &&
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
+
+		SK_IN32(IoC, B2_GP_IO, &DWord);
+
+		DWord |= (GP_DIR_9 | GP_IO_9);
+
+		/* set PHY reset */
+		SK_OUT32(IoC, B2_GP_IO, DWord);
+	}
+#if defined(QUICK_LINK) || defined(SK_DIAG)
+	else if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_OPT &&
+			 pAC->GIni.GIChipId <= CHIP_ID_YUKON_OP_2) {
+
+		SK_IN8(IoC, PCI_C2(pAC, IoC, PSM_CONFIG_REG4), &Byte);
+
+		Byte &= ~(SK_U8)PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
+
+		/* enable Config Write */
+		SK_TST_MODE_ON(IoC);
+
+		/* release reset for PHY Quick Link Detect */
+		SK_OUT8(IoC, PCI_C2(pAC, IoC, PSM_CONFIG_REG4), Byte);
+
+		/* disable Config Write */
+		SK_TST_MODE_OFF(IoC);
+	}
+#endif /* QUICK_LINK || SK_DIAG */
+
+	/* set GPHY Control reset */
+	SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
+
+	if (!pAC->GIni.GIAsfEnabled) {
+		/* set GMAC Control reset */
+		SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
+	}
+
+}	/* SkGmHardRst */
+
+
+/******************************************************************************
+ *
+ *	SkGmClearRst() - Release the GPHY & GMAC reset
+ *
+ * Description:
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmClearRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_U32	DWord;
+	SK_U16	PhyId0;
+	SK_U16	PhyId1;
+	SK_U16	Word;
+	SK_U8	Byte;
+	int		ChipId;
+	int		i;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmClearRst: Port %d\n", Port));
+
+	ChipId = pAC->GIni.GIChipId;
+
+#ifndef DISABLE_YUKON_I
+	/* WA code for COMA mode */
+	if (pAC->GIni.GIYukonLite &&
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
+
+		SK_IN32(IoC, B2_GP_IO, &DWord);
+
+		DWord |= GP_DIR_9;		/* set to output */
+		DWord &= ~GP_IO_9;		/* clear PHY reset (active high) */
+
+		/* clear PHY reset */
+		SK_OUT32(IoC, B2_GP_IO, DWord);
+	}
+#endif /* !DISABLE_YUKON_I */
+#ifdef VCPU
+	/* set MAC Reset before PHY reset is set */
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
+#endif /* VCPU */
+
+	if (CHIP_ID_YUKON_2(pAC)) {
+
+		Byte = (ChipId == CHIP_ID_YUKON_FE_P) ? (SK_U8)BIT_7S : 0;
+
+		/* set GPHY Control reset */
+		SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), Byte | (SK_U8)GPC_RST_SET);
+
+		/* release GPHY Control reset */
+		SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), Byte | (SK_U8)GPC_RST_CLR);
+
+#ifdef DEBUG
+		/* additional check for PEX */
+		SK_IN8(IoC, MR_ADDR(Port, GPHY_CTRL), &Byte);
+
+		Byte &= GPC_RST_CLR | GPC_RST_SET;
+
+		if (pAC->GIni.GIPciBus == SK_PEX_BUS && Byte != GPC_RST_CLR) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("Error on PEX-bus after GPHY reset (GPHY Ctrl=0x%02X)\n",
+				Byte));
+		}
+#endif /* DEBUG */
+	}
+#ifndef DISABLE_YUKON_I
+	else {
+		/* set HWCFG_MODE */
+		DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
+			GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
+			(pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
+			GPC_HWCFG_GMII_FIB);
+
+		/* set GPHY Control reset */
+		SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
+
+		/* release GPHY Control reset */
+		SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
+	}
+#endif /* !DISABLE_YUKON_I */
+
+	/* dummy read after PHY reset */
+	SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);
+
+#if defined(VCPU) && !defined(HASE)
+	/* wait for internal initialization of GPHY */
+	VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
+	VCpuWait(10000);
+#endif /* VCPU */
+
+	if (ChipId >= CHIP_ID_YUKON_OPT && pAC->GIni.GP[Port].PRevAutoNeg) {
+
+		SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
+
+		DWord &= ~GMC_RST_SET;
+
+		/* enable PHY Reverse Auto-Negotiation */
+		DWord |= MAC_CTRL_PD_REV_ANEG_A;
+	}
+	else {
+		DWord = 0;
+	}
+
+	/* clear GMAC Control reset */
+	SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), DWord | GMC_RST_CLR);
+
+#if defined(VCPU) && !defined(HASE)
+	/* wait for stable GMAC clock */
+	VCpuWait(9000);
+#endif /* VCPU */
+
+#ifdef SK_DIAG
+	if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {
+
+		/* clear GMAC 1 Control reset */
+		SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
+
+		do {
+			/* set GMAC 2 Control reset */
+			SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);
+
+			/* clear GMAC 2 Control reset */
+			SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
+
+			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);
+
+			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);
+
+			SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);
+
+		} while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
+				 PhyId1 != PHY_MARV_ID1_Y2);
+	}
+#endif /* SK_DIAG */
+
+	if (ChipId == CHIP_ID_YUKON_FE_P) {
+
+		for (i = 0; i < 9; ++i) {
+			/* dummy read after PHY reset */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &Word);
+
+			/* check VCT registers after PHY reset */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_VCT_TX, &PhyId0);
+
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_VCT_RX, &PhyId1);
+
+			if (Word == PHY_MARV_ID1_FEP && PhyId0 == 0 && PhyId1 == 0) {
+
+#ifdef xDEBUG
+				SK_TST_MODE_ON(IoC);
+				SK_OUT8(IoC, B2_MAC_3, (SK_U8)i);
+				SK_TST_MODE_OFF(IoC);
+#endif
+				break;
+			}
+
+			/* set GPHY Control reset */
+			SK_OUT8(IoC, GPHY_CTRL, (SK_U8)(BIT_7S | GPC_RST_SET));
+
+			/* dummy read after PHY reset */
+			SK_IN32(IoC, GPHY_CTRL, &DWord);
+
+			/* release GPHY Control reset */
+			SK_OUT8(IoC, GPHY_CTRL, (SK_U8)(BIT_7S | GPC_RST_CLR));
+
+			/* dummy read */
+			SK_IN32(IoC, GPHY_CTRL, &DWord);
+		}
+	}
+
+#if defined(VCPU) && !defined(HASE)
+	VCpuWait(2000);
+
+	SK_IN32(IoC, B0_ISRC, &DWord);
+#endif /* VCPU */
+
+}	/* SkGmClearRst */
+
+
+/******************************************************************************
+ *
+ *	SkMacSoftRst() - Do a MAC software reset
+ *
+ * Description:	calls a MAC software reset routine
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacSoftRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	/* disable receiver and transmitter */
+	SkMacRxTxDisable(pAC, IoC, Port);
+
+	SkGmSoftRst(pAC, IoC, Port);
+
+	pAC->GIni.GP[Port].PState = SK_PRT_STOP;
+
+}	/* SkMacSoftRst */
+
+
+/******************************************************************************
+ *
+ *	SkMacHardRst() - Do a MAC hardware reset
+ *
+ * Description:	calls a MAC hardware reset routine
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacHardRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SkGmHardRst(pAC, IoC, Port);
+
+	pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;
+	pAC->GIni.GP[Port].PPhyQLink = SK_FALSE;
+
+	pAC->GIni.GP[Port].PState = SK_PRT_RESET;
+
+}	/* SkMacHardRst */
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkMacClearRst() - Clear the MAC reset
+ *
+ * Description:	calls a clear MAC reset routine
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacClearRst(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port)	/* Port Index (MAC_1 + n) */
+{
+	SkGmClearRst(pAC, IoC, Port);
+
+}	/* SkMacClearRst */
+#endif /* !SK_SLIM */
+
+/******************************************************************************
+ *
+ *	SkGmInitMac() - Initialize the GMAC
+ *
+ * Description:
+ *	Initialize the GMAC of the specified port.
+ *	The GMAC must be reset or stopped before calling this function.
+ *
+ * Note:
+ *	The GMAC's Rx and Tx state machine is still disabled when returning.
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGmInitMac(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+	int			i;
+	SK_U16		SWord;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("SkGmInitMac: Port %d, PState = %d, PLinkSpeed = %d\n",
+		 Port, pPrt->PState, pPrt->PLinkSpeed));
+
+#ifndef VCPU
+	if (pPrt->PState == SK_PRT_STOP) {
+		/* Verify that the reset bit is cleared */
+		SK_IN16(IoC, MR_ADDR(Port, GMAC_CTRL), &SWord);
+
+		if ((SWord & GMC_RST_SET) != 0) {
+			/* PState does not match HW state */
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmInitMac: PState does not match HW state"));
+			/* Correct it */
+			pPrt->PState = SK_PRT_RESET;
+		}
+		else {
+			/* enable PHY interrupts */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
+				(SK_U16)PHY_M_DEF_MSK);
+		}
+	}
+#endif /* !VCPU */
+
+	if (pPrt->PState == SK_PRT_RESET) {
+
+		SkGmHardRst(pAC, IoC, Port);
+
+		SkGmClearRst(pAC, IoC, Port);
+
+#ifndef SK_SLIM
+		if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
+			pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
+			/* Force Auto-Negotiation */
+			pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
+				SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF;
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("SkGmInitMac: Force Auto-Negotiation, PLinkMode = %d",
+				pPrt->PLinkMode));
+		}
+#endif /* !SK_SLIM */
+
+		SWord = 0;
+
+		/* speed settings */
+		switch (pPrt->PLinkSpeed) {
+		case SK_LSPEED_AUTO:
+		case SK_LSPEED_1000MBPS:
+			/* check for Gigabit adapters */
+			if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+
+				SWord |= GM_GPCR_SPEED_1000;
+			}
+			break;
+		case SK_LSPEED_100MBPS:
+			SWord |= GM_GPCR_SPEED_100;
+			break;
+		case SK_LSPEED_10MBPS:
+			break;
+		}
+
+		/* duplex settings */
+		if (pPrt->PLinkMode != SK_LMODE_HALF) {
+			/* set full duplex */
+			SWord |= GM_GPCR_DUP_FULL;
+		}
+
+		/* flow-control settings */
+		switch (pPrt->PFlowCtrlMode) {
+		case SK_FLOW_MODE_NONE:
+			/* disable Tx & Rx flow-control */
+			SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
+			break;
+		case SK_FLOW_MODE_LOC_SEND:
+			/* disable Rx flow-control */
+			SWord |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
+			break;
+		case SK_FLOW_MODE_SYMMETRIC:
+		case SK_FLOW_MODE_SYM_OR_REM:
+			/* enable Tx & Rx flow-control */
+			break;
+		}
+
+		/* Auto-negotiation disabled */
+		if (pPrt->PLinkMode == SK_LMODE_HALF ||
+			pPrt->PLinkMode == SK_LMODE_FULL) {
+
+			/* disable auto-update for speed, duplex and flow-control */
+			SWord |= GM_GPCR_AU_ALL_DIS;
+		}
+
+		/* setup General Purpose Control Register */
+		GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
+
+		/* dummy read the Interrupt Source Register */
+		SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);
+
+#ifndef VCPU
+		SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
+#endif /* !VCPU */
+	}
+	else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+			 pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+
+		/* Read PHY Copper Specific Control 2 */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &SWord);
+
+		if ((SWord & BIT_0S) != 0) {
+			/* Enable PHY Transmitter (clear bit 26_0.0) */
+			SWord &= ~BIT_0S;
+
+			/* Write PHY changes (SW-reset must follow) */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, SWord);
+		}
+	}
+
+	if (HW_SUP_EEE(pAC)) {
+		/*
+		 * Using SK_IN16 and SK_OUT16. These I/Os are only executed on chips
+		 * that allow GMAC access without additional safety measures.
+		 */
+		if (!HW_FEATURE(pAC, HWF_DO_EEE_ENABLE)) {
+			/* disable LPI signaling */
+			SK_IN16(IoC, GMA(Port, EEE_CONTROL), &SWord);
+			SK_OUT16(IoC, GMA(Port, EEE_CONTROL),
+				(SWord & ~EEE_CONTROL_CAPABLE) | EEE_CONTROL_RESET);
+
+			SK_IN16(IoC, GMA(Port, EEE_CONTROL), &SWord);
+			SK_OUT16(IoC, GMA(Port, EEE_CONTROL),
+				SWord & ~(EEE_CONTROL_CAPABLE | EEE_CONTROL_RESET));
+		}
+	}
+
+#ifndef VCPU	/* saves some time in co-sim */
+	(void)SkGmResetCounter(pAC, IoC, Port);
+#else	/* VCPU */
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_PRM) {
+		/*
+		 * Using SK_IN16 and SK_OUT16. These I/Os are only executed on chips
+		 * that allow GMAC access without additional safety measures.
+		 */
+		SK_IN16(IoC, GMA(Port, EEE_CONTROL), &SWord);
+		SK_OUT16(IoC, GMA(Port, EEE_CONTROL), SWord | EEE_CONTROL_DEBUG_LPI);
+	}
+#endif	/* VCPU */
+
+	/* setup Transmit Control Register */
+#ifndef SK_SLIM
+	GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
+#else
+	GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(TX_COL_DEF));
+#endif
+	/* setup Receive Control Register */
+	SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;
+
+	GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);
+
+	/* setup Transmit Flow-Control Register */
+	GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
+
+	/* setup Transmit Parameter Register */
+#ifdef VCPU
+	GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
+#endif /* VCPU */
+
+#ifndef SK_SLIM
+	SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
+		TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
+		TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
+		TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
+#else
+	SWord = (SK_U16)(TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
+		TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
+		TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
+		TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
+#endif
+
+	GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
+
+	/* configure the Serial Mode Register */
+#ifndef SK_SLIM
+	SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) |
+		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData_1G));
+
+	if (pPrt->PMacLimit4) {
+		/* reset of collision counter after 4 consecutive collisions */
+		SWord |= GM_SMOD_LIMIT_4;
+	}
+#else
+	SWord = (SK_U16)(DATA_BLIND_VAL(DATA_BLIND_DEF) |
+		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000));
+#endif
+
+	if (pPrt->PPortUsage == SK_JUMBO_LINK) {
+		/* enable jumbo mode (Max. Frame Length = 9018) */
+		SWord |= GM_SMOD_JUMBO_ENA;
+	}
+
+	if (HW_FEATURE(pAC, HWF_NEW_FLOW_CONTROL)) {
+		/* enable new Flow-Control */
+		SWord |= GM_NEW_FLOW_CTRL;
+	}
+
+	GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
+
+	if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+		/* adjust Flow-Control Timeout for Gigabit clock (125 MHz) */
+		GM_OUT16(IoC, Port, GM_FC_TIMEOUT, 31250);
+	}
+
+	/*
+	 * configure the GMACs Station Addresses
+	 * in PROM you can find our addresses at:
+	 * B2_MAC_1 = xx xx xx xx xx x0 virtual address
+	 * B2_MAC_2 = xx xx xx xx xx x1 is programmed to GMAC A
+	 * B2_MAC_3 = xx xx xx xx xx x2 is reserved for DualPort
+	 */
+
+	for (i = 0; i < 3; i++) {
+		/*
+		 * The following 2 statements are together endianess independent.
+		 */
+		/* physical address: will be used for pause frames */
+		SK_IN16(IoC, B2_MAC_2 + Port * 8 + i * 2, &SWord);
+
+#ifdef WA_DEV_16
+		/* WA for deviation #16 */
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON && pAC->GIni.GIChipRev == 0) {
+			/* swap the address bytes */
+			SWord = ((SWord & 0xff00) >> 8)	| ((SWord & 0x00ff) << 8);
+
+			/* write to register in reversed order */
+			GM_OUT16(IoC, Port, GM_SRC_ADDR_1L + (2 - i) * 4, SWord);
+		}
+		else {
+			GM_OUT16(IoC, Port, GM_SRC_ADDR_1L + i * 4, SWord);
+		}
+#else
+		GM_OUT16(IoC, Port, GM_SRC_ADDR_1L + i * 4, SWord);
+#endif /* WA_DEV_16 */
+
+		/* virtual address: will be used for data */
+		SK_IN16(IoC, B2_MAC_1 + Port * 8 + i * 2, &SWord);
+
+		GM_OUT16(IoC, Port, GM_SRC_ADDR_2L + i * 4, SWord);
+
+		/* reset Multicast filtering Hash registers 1-3 */
+		GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0);
+	}
+
+	/* reset Multicast filtering Hash register 4 */
+	GM_OUT16(IoC, Port, GM_MC_ADDR_H4, 0);
+
+	/* enable interrupt mask for counter overflows */
+	GM_OUT16(IoC, Port, GM_TX_IRQ_MSK, 0);
+	GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
+	GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
+
+	pPrt->PState = SK_PRT_STOP;
+
+}	/* SkGmInitMac */
+
+
+#ifdef SK_PHY_LP_MODE
+/******************************************************************************
+ *
+ *	SkGmEnterLowPowerMode()
+ *
+ * Description:
+ *	This function sets the Marvell Alaska PHY to the low power mode
+ *	given by parameter mode.
+ *	The following low power modes are available:
+ *
+ *		- COMA Mode (Deep Sleep):
+ *			The PHY cannot wake up on its own.
+ *
+ *		- IEEE 22.2.4.1.5 compatible power down mode
+ *			The PHY cannot wake up on its own.
+ *
+ *		- energy detect mode
+ *			The PHY can wake up on its own by detecting activity
+ *			on the CAT 5 cable.
+ *
+ *		- energy detect plus mode
+ *			The PHY can wake up on its own by detecting activity
+ *			on the CAT 5 cable.
+ *			Connected devices can be woken up by sending normal link
+ *			pulses every second.
+ *
+ * Note:
+ *
+ * Returns:
+ *		0: ok
+ *		1: error
+ */
+int SkGmEnterLowPowerMode(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (e.g. MAC_1) */
+SK_U8	Mode)		/* low power mode */
+{
+	SK_U8	LastMode;
+	SK_U8	Byte;
+	SK_U16	Word;
+	SK_U16	PhySpec;
+	SK_U16	ClkDiv;
+	SK_U32	DWord;
+	SK_U32	PowerDownBit;
+	SK_U32	ClkMask;
+	int		ChipId;
+	int		Ret = 0;
+
+	if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
+
+		return(1);
+	}
+
+	/* save current power mode */
+	LastMode = pAC->GIni.GP[Port].PPhyPowerState;
+	pAC->GIni.GP[Port].PPhyPowerState = Mode;
+
+	ChipId = pAC->GIni.GIChipId;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
+		("SkGmEnterLowPowerMode: %u\n", Mode));
+
+	/* release GPHY Control reset */
+	SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
+
+	/* release GMAC reset */
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
+
+	if (ChipId == CHIP_ID_YUKON_EC_U ||
+		ChipId == CHIP_ID_YUKON_EX ||
+		ChipId >= CHIP_ID_YUKON_SUPR) {
+		/* re-read PEX Link Control */
+		SK_IN16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_CTRL)),
+			&pAC->GIni.GIPexLinkCtrl);
+
+		/* select page 2 to access MAC control register */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+		/* allow GMII Power Down */
+		Word &= ~PHY_M_MAC_GMIF_PUP;
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+
+		/* set page register back to 0 */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+	}
+
+	switch (Mode) {
+	/* COMA mode (deep sleep) */
+	case PHY_PM_DEEP_SLEEP:
+		/* setup General Purpose Control Register */
+		GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS |
+			GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			/* set power down bit */
+			PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
+				PCI_Y2_PHY2_POWD;
+
+			if (ChipId != CHIP_ID_YUKON_EC) {
+
+				if (ChipId == CHIP_ID_YUKON_EC_U) {
+
+					SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhySpec);
+					/* enable Power Down */
+					PhySpec |= PHY_M_PC_POW_D_ENA;
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+				}
+
+				/* set IEEE compatible Power Down Mode (dev. #4.99) */
+				Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
+			}
+		}
+		else {
+			/* apply COMA mode workaround for Yukon-Plus */
+			(void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 31);
+
+			Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3);
+
+			PowerDownBit = PCI_PHY_COMA;
+		}
+
+		/* enable Config Write */
+		SK_TST_MODE_ON(IoC);
+
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &DWord);
+
+		/* set PHY to PowerDown/COMA Mode */
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), DWord | PowerDownBit);
+
+		/* check if this routine was called from a for() loop */
+		if (CHIP_ID_YUKON_2(pAC) &&
+			(pAC->GIni.GIMacsFound == 1 || Port == MAC_2)) {
+
+			if (ChipId == CHIP_ID_YUKON_EC_U ||
+				ChipId == CHIP_ID_YUKON_EX ||
+				ChipId >= CHIP_ID_YUKON_FE_P) {
+				/* set GPHY Control reset */
+				SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Set PHY into reset, Port %d\n", Port));
+
+				/* additional power saving measurements */
+				SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &DWord);
+
+				if (pAC->GIni.GIGotoD3Cold) {
+					/* set gating core clock for LTSSM in DETECT state */
+					DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_DET_STAT) |
+						/* enable Gate Root Core Clock */
+						P_CLK_GATE_ROOT_COR_ENA);
+
+					/* set Mask Register for Release/Gate Clock */
+					SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5),
+						P_REL_MAIN_PWR_AVAIL | P_GAT_MAIN_PWR_N_AVAIL);
+				}
+				else {
+					/* set gating core clock for LTSSM in L1 state */
+					DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
+						/* auto clock gated scheme controlled by CLKREQ */
+						P_ASPM_A1_MODE_SELECT |
+						/* enable Gate Root Core Clock */
+						P_CLK_GATE_ROOT_COR_ENA);
+
+					if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
+						/* enable Clock Power Management (CLKREQ) */
+						if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_CLK_PM_ENA) == 0) {
+
+							pAC->GIni.GIPexLinkCtrl |= PEX_LC_CLK_PM_ENA;
+
+							SK_OUT16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_CTRL)),
+								pAC->GIni.GIPexLinkCtrl);
+						}
+					}
+					else if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_CLK_PM_ENA) == 0) {
+						/* Force CLKREQ Enable and CLKREQn pin low */
+						DWord |= P_ASPM_FORCE_CLKREQ_PIN | P_ASPM_FORCE_CLKREQ_ENA;
+					}
+
+					if (ChipId == CHIP_ID_YUKON_FE_P) {
+						/* set delay-timer value to 2 ms */
+						DWord |= P_TIMER_VALUE_MSK;
+					}
+
+					/* set Mask Register for Release/Gate Clock */
+					SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5),
+						P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
+						P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
+						P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
+				}
+
+				SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), DWord);
+
+				if (!pAC->GIni.GIAsfRunning) {
+					/* stop the watchdog */
+					SK_OUT32(IoC, CPU_WDOG, 0);
+
+					/* put CPU into reset state */
+					SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)HCU_CCSR_ASF_RESET);
+
+					if (!HW_FEATURE(pAC, HWF_WA_DEV_542)) {
+						/* put CPU into halt state */
+						SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)HCU_CCSR_ASF_HALTED);
+					}
+
+					/* stop the watchdog */
+					SK_OUT32(IoC, CPU_WDOG, 0);
+				}
+			}
+			else {
+				/* ASF system clock stopped */
+				SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT);
+			}
+
+			if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) {
+				/* divide clock by 4 only for Yukon-EC */
+				ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0;
+
+				/* on Yukon-2 clock select value is 31 */
+				DWord = (ChipId == CHIP_ID_YUKON_XL) ?
+					(Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) :
+					 Y2_CLK_DIV_VAL(ClkDiv);
+
+				/* check for Yukon-2 dual port PCI-Express adapter */
+				if (!(pAC->GIni.GIMacsFound == 2 &&
+					  pAC->GIni.GIPciBus == SK_PEX_BUS)) {
+					/* enable Core Clock Division */
+					DWord |= Y2_CLK_DIV_ENA;
+				}
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Set Core Clock: 0x%08lX\n", DWord));
+
+				/* reduce Core Clock Frequency */
+				SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord);
+			}
+
+			if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) {
+				/* check for Yukon-2 Rev. A2 */
+				if (ChipId == CHIP_ID_YUKON_XL &&
+					pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
+					/* enable bits are inverted */
+					Byte = 0;
+				}
+				else {
+					Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+						Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+						Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
+				}
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Set Clock Gating: 0x%02X\n", Byte));
+
+				/* disable MAC/PHY, PCI and Core Clock for both Links */
+				SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
+			}
+
+			if (pAC->GIni.GILevel != SK_INIT_IO &&
+				pAC->GIni.GIMacsFound == 1 &&
+				pAC->GIni.GIPciBus == SK_PEX_BUS) {
+
+				if (ChipId == CHIP_ID_YUKON_EC_U ||
+					ChipId == CHIP_ID_YUKON_EX ||
+					ChipId >= CHIP_ID_YUKON_FE_P) {
+
+#ifdef PCI_E_L1_STATE
+					SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &Word);
+					/* force to PCIe L1 */
+					Word |= (SK_U16)PCI_FORCE_PEX_L1;
+					SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), Word);
+#else /* !PCI_E_L1_STATE */
+
+#ifdef DEEP_SLEEP_D1
+					/* check if ASPM L1 enabled */
+					if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_ASPM_LC_L1) != 0) {
+						break;
+					}
+#else
+					break;
+#endif /* !DEEP_SLEEP_D1 */
+
+#endif /* !PCI_E_L1_STATE */
+				}
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+					("Switch to D1 state\n"));
+
+				/* switch to D1 state */
+				SK_OUT8(IoC, PCI_C2(pAC, IoC, PCI_PM_CTL_STS), PCI_PM_STATE_D1);
+			}
+		}
+
+		break;
+
+	/* IEEE 22.2.4.1.5 compatible power down mode */
+	case PHY_PM_IEEE_POWER_DOWN:
+
+		if (!CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIYukonLite) {
+
+			Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhySpec);
+
+			/* disable MAC 125 MHz clock */
+			PhySpec |= PHY_M_PC_DIS_125CLK;
+			PhySpec &= ~PHY_M_PC_MAC_POW_UP;
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+
+			/* these register changes must be followed by a software reset */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET);
+		}
+
+		/* switch IEEE compatible power down mode on */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
+
+#ifdef DEBUG
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+#endif /* DEBUG */
+		break;
+
+	/* energy detect and energy detect plus mode */
+	case PHY_PM_ENERGY_DETECT:
+	case PHY_PM_ENERGY_DETECT_PLUS:
+
+		Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhySpec);
+
+		if (!CHIP_ID_YUKON_2(pAC)) {
+			/* disable MAC 125 MHz clock */
+			PhySpec |= PHY_M_PC_DIS_125CLK;
+		}
+
+		if (ChipId == CHIP_ID_YUKON_FE || ChipId == CHIP_ID_YUKON_FE_P) {
+			/* enable Energy Detect (sense & pulse) */
+			PhySpec |= PHY_M_PC_ENA_ENE_DT;
+		}
+		else {
+			/* clear energy detect mode bits */
+			PhySpec &= ~PHY_M_PC_EN_DET_MSK;
+
+			PhySpec |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET :
+				PHY_M_PC_EN_DET_PLUS;
+		}
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+
+		/* these register changes must be followed by a software reset */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+		Word |= PHY_CT_RESET;
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
+
+		if (ChipId == CHIP_ID_YUKON_FE_P) {
+			/* Re-enable Link Partner Next Page */
+			PhySpec |= PHY_M_PC_ENA_LIP_NP;
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+		}
+
+		if (ChipId == CHIP_ID_YUKON_EC_U ||
+			ChipId == CHIP_ID_YUKON_EX ||
+			ChipId >= CHIP_ID_YUKON_FE_P) {
+			/* additional power saving measurements */
+			SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &DWord);
+
+			if (pAC->GIni.GIGotoD3Cold) {
+				/* set gating core clock for LTSSM in DETECT state */
+				DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_DET_STAT) |
+					/* enable Gate Root Core Clock */
+					P_CLK_GATE_ROOT_COR_ENA);
+
+				/* set Mask Register for Release/Gate Clock */
+				SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5),
+					P_REL_MAIN_PWR_AVAIL | P_GAT_MAIN_PWR_N_AVAIL);
+			}
+			else {
+				/* set gating core clock for LTSSM in L1 state */
+				DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
+					/* auto clock gated scheme controlled by CLKREQ */
+					P_ASPM_A1_MODE_SELECT |
+					/* enable Gate Root Core Clock */
+					P_CLK_GATE_ROOT_COR_ENA);
+
+				if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
+					/* enable Clock Power Management (CLKREQ) */
+					if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_CLK_PM_ENA) == 0) {
+
+						pAC->GIni.GIPexLinkCtrl |= PEX_LC_CLK_PM_ENA;
+
+						SK_OUT16(IoC, PCI_C2(pAC, IoC, PEX_CAP_REGS(PEX_LNK_CTRL)),
+							pAC->GIni.GIPexLinkCtrl);
+					}
+				}
+				else if ((pAC->GIni.GIPexLinkCtrl & PEX_LC_CLK_PM_ENA) == 0) {
+					/* Force CLKREQ Enable and CLKREQn pin low */
+					DWord |= P_ASPM_FORCE_CLKREQ_PIN | P_ASPM_FORCE_CLKREQ_ENA;
+				}
+
+				if (ChipId == CHIP_ID_YUKON_FE_P) {
+					/* set delay-timer value to 2 ms */
+					DWord |= P_TIMER_VALUE_MSK;
+				}
+
+				ClkMask = P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
+						P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
+						P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN;
+
+				if (pAC->GIni.GIAsfEnabled) {
+					ClkMask |= P_REL_CPU_TO_SLEEP | P_GAT_CPU_TO_SLEEP;
+				}
+
+				/* set Mask Register for Release/Gate Clock */
+				SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5), ClkMask);
+			}
+
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), DWord);
+
+#ifdef PCI_E_L1_STATE
+			SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &Word);
+			/* enable PCIe L1 on GPHY link down */
+			Word |= (SK_U16)PCI_ENA_GPHY_LNK;
+			SK_OUT16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), Word);
+#endif /* PCI_E_L1_STATE */
+		}
+
+		pAC->GIni.GP[Port].PState = SK_PRT_STOP;
+		break;
+
+	/* don't change current power mode */
+	default:
+		pAC->GIni.GP[Port].PPhyPowerState = LastMode;
+		Ret = 1;
+	}
+
+	return(Ret);
+
+}	/* SkGmEnterLowPowerMode */
+
+/******************************************************************************
+ *
+ *	SkGmLeaveLowPowerMode()
+ *
+ * Description:
+ *	Leave the current low power mode and switch to normal mode
+ *
+ * Note:
+ *
+ * Returns:
+ *		0:	ok
+ *		1:	error
+ */
+int SkGmLeaveLowPowerMode(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (e.g. MAC_1) */
+{
+	SK_GEPORT	*pPrt;
+	SK_U32		DWord;
+	SK_U32		PowerDownBit;
+	SK_U16		Word;
+	SK_U8		LastMode;
+	int			ChipId;
+	int			Ret = 0;
+
+	if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
+
+		return(1);
+	}
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* save current power mode */
+	LastMode = pPrt->PPhyPowerState;
+	pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
+
+	ChipId = pAC->GIni.GIChipId;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
+		("SkGmLeaveLowPowerMode: %u\n", LastMode));
+
+	switch (LastMode) {
+	/* COMA mode (deep sleep) */
+	case PHY_PM_DEEP_SLEEP:
+
+		if (ChipId == CHIP_ID_YUKON_EC_U ||
+			ChipId == CHIP_ID_YUKON_EX ||
+			ChipId >= CHIP_ID_YUKON_FE_P) {
+
+#ifdef PCI_E_L1_STATE
+			SkPciReadCfgWord(pAC, PCI_C1(pAC, PCI_OUR_REG_1), &Word);
+
+			/* set the default value into bits 6 & 5 */
+			Word &= ~(SK_U16)(PCI_ENA_GPHY_LNK | PCI_FORCE_PEX_L1);
+
+			SkPciWriteCfgWord(pAC, PCI_C1(pAC, PCI_OUR_REG_1), Word);
+#endif /* PCI_E_L1_STATE */
+
+			SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &DWord);
+
+			DWord &= P_ASPM_CONTROL_MSK;
+			/* set all bits to 0 except bits 15..12 and 8 */
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), DWord);
+
+			/* set to default value */
+			SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_5), 0);
+		}
+
+		SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word);
+
+		if ((Word & PCI_PM_STATE_MSK) != 0) {
+			/* switch to D0 state */
+			SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word & ~PCI_PM_STATE_MSK);
+		}
+
+		/* enable Config Write */
+		SK_TST_MODE_ON(IoC);
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+			/* disable Core Clock Division */
+			SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
+
+			/* set power down bit */
+			PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
+				PCI_Y2_PHY2_POWD;
+		}
+		else {
+			PowerDownBit = PCI_PHY_COMA;
+		}
+
+		SK_IN32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), &DWord);
+
+		/* Release PHY from PowerDown/COMA Mode */
+		SK_OUT32(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_1), DWord & ~PowerDownBit);
+
+		/* disable Config Write */
+		SK_TST_MODE_OFF(IoC);
+
+		if (CHIP_ID_YUKON_2(pAC)) {
+
+			if (ChipId == CHIP_ID_YUKON_FE) {
+				/* release IEEE compatible Power Down Mode */
+				Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE);
+			}
+			else if (ChipId == CHIP_ID_YUKON_EC_U ||
+					 ChipId == CHIP_ID_YUKON_EX ||
+					 ChipId >= CHIP_ID_YUKON_FE_P) {
+				/* release GPHY Control reset */
+				SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
+			}
+		}
+		else {
+			SK_IN32(IoC, B2_GP_IO, &DWord);
+
+			/* set to output */
+			DWord |= (GP_DIR_9 | GP_IO_9);
+
+			/* set PHY reset */
+			SK_OUT32(IoC, B2_GP_IO, DWord);
+
+			DWord &= ~GP_IO_9;	/* clear PHY reset (active high) */
+
+			/* clear PHY reset */
+			SK_OUT32(IoC, B2_GP_IO, DWord);
+		}
+
+		break;
+
+	/* IEEE 22.2.4.1.5 compatible power down mode */
+	case PHY_PM_IEEE_POWER_DOWN:
+
+		if (ChipId != CHIP_ID_YUKON_XL) {
+
+			Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+			Word &= ~PHY_M_PC_DIS_125CLK;	/* enable MAC 125 MHz clock */
+			Word |= PHY_M_PC_MAC_POW_UP;	/* set MAC power up */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+
+			/* these register changes must be followed by a software reset */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+			Word |= PHY_CT_RESET;
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
+		}
+
+		/* switch IEEE compatible power down mode off */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+		Word &= ~PHY_CT_PDOWN;
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
+
+		break;
+
+	/* energy detect and energy detect plus mode */
+	case PHY_PM_ENERGY_DETECT:
+	case PHY_PM_ENERGY_DETECT_PLUS:
+
+		if (ChipId != CHIP_ID_YUKON_XL && !pPrt->PEnDetMode) {
+
+			Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+
+			if (ChipId == CHIP_ID_YUKON_FE || ChipId == CHIP_ID_YUKON_FE_P) {
+				/* disable Energy Detect */
+				Word &= ~PHY_M_PC_ENA_ENE_DT;
+			}
+			else {
+				/* disable energy detect mode & enable MAC 125 MHz clock */
+				Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK);
+			}
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+
+			/* these register changes must be followed by a software reset */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
+			Word |= PHY_CT_RESET;
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
+		}
+		break;
+
+	/* don't change current power mode */
+	default:
+		pAC->GIni.GP[Port].PPhyPowerState = LastMode;
+		Ret = 1;
+	}
+
+	return(Ret);
+
+}	/* SkGmLeaveLowPowerMode */
+#endif /* SK_PHY_LP_MODE */
+
+/******************************************************************************
+ *
+ *	SkGmInitPhyMarv() - Initialize the Marvell PHY registers
+ *
+ * Description:	initializes all the Marvell PHY registers
+ *
+ * Note:
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmInitPhyMarv(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL	DoLoop)		/* Should a PHY LoopBack be set-up? */
+{
+	SK_GEPORT	*pPrt;
+	SK_BOOL		AutoNeg;
+	SK_BOOL		NewPhyType;
+	SK_U16		PhyCtrl;
+	SK_U16		C1000BaseT;
+	SK_U16		AutoNegAdv;
+	SK_U8		PauseMode;
+	int			ChipId;
+	int			ChipRev;
+#ifndef SK_SLIM
+	int			MacCtrl;
+	SK_U16		LoopSpeed;
+#endif /* !SK_SLIM */
+	SK_U16		Word;
+	SK_U16		PageReg;
+#ifndef VCPU
+	int			i;
+	SK_U16		PhySpec;
+	SK_U16		ExtPhyCtrl;
+	SK_U16		BlinkCtrl;
+	SK_U16		LedCtrl;
+	SK_U16		LedConf;
+	SK_U16		LedOver;
+	int			Mode;
+#if !defined(SK_DIAG) && !defined(SK_SLIM)
+	SK_EVPARA	Para;
+#endif /* !SK_DIAG && !SK_SLIM */
+#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
+	SK_U16		PhyStat;
+	SK_U16		PhyStat1;
+	SK_U16		PhySpecStat;
+#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
+#endif /* !VCPU */
+
+	/* set Pause On */
+	PauseMode = (SK_U8)GMC_PAUSE_ON;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	ChipId = pAC->GIni.GIChipId;
+
+	ChipRev = pAC->GIni.GIChipRev;
+
+	NewPhyType = HW_HAS_NEWER_PHY(pAC);
+
+	/* Auto-negotiation ? */
+	AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
+			  pPrt->PLinkMode != SK_LMODE_FULL;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n",
+		 Port, AutoNeg ? "ON" : "OFF",
+		 pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode));
+
+#ifndef VCPU
+	ExtPhyCtrl = 0;
+
+	/* read Id from PHY */
+	if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) {
+
+#if !defined(SK_DIAG) && !defined(SK_SLIM)
+		Para.Para64 = Port;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
+#endif /* !SK_DIAG && !SK_SLIM */
+
+		return;
+	}
+#endif /* !VCPU */
+
+	/* check for Gigabit adapters */
+	if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+
+#ifndef SK_SLIM
+		if (DoLoop) {
+			/* special setup for newer PHYs */
+			if (NewPhyType) {
+
+				LoopSpeed = pPrt->PLinkSpeed;
+
+				if (LoopSpeed == SK_LSPEED_AUTO) {
+					/* force 1000 Mbps */
+					LoopSpeed = SK_LSPEED_1000MBPS;
+				}
+				LoopSpeed += 2;
+
+#ifdef VCPU
+				if (CHIP_ID_YUKON_PRM == ChipId || CHIP_ID_YUKON_OP_2 == ChipId) {
+					/*
+					 * from task phy_init in sim_tasks_pcix.inc, 20100609
+					 * needed for simulation with REAL_PHY
+					 */
+					SkGmPhyWrite(pAC, IoC, Port, 22, 0x4000);
+					SkGmPhyWrite(pAC, IoC, Port, 22, 0x40fa);
+					SkGmPhyWrite(pAC, IoC, Port,  0, 0x0200);
+					SkGmPhyWrite(pAC, IoC, Port, 16, 0x0040);
+					SkGmPhyWrite(pAC, IoC, Port,  1, 0x0010);
+					if (SK_LSPEED_100MBPS == pPrt->PLinkSpeed) {
+						SkGmPhyWrite(pAC, IoC, Port, 22, 0x4002);
+						SkGmPhyWrite(pAC, IoC, Port, 16, 0x9000);
+						SkGmPhyWrite(pAC, IoC, Port, 21, 0x0001);
+					}
+					else if (SK_LSPEED_10MBPS == pPrt->PLinkSpeed) {
+						SkGmPhyWrite(pAC, IoC, Port, 22, 0x4002);
+						SkGmPhyWrite(pAC, IoC, Port, 16, 0x9000);
+						SkGmPhyWrite(pAC, IoC, Port, 21, 0x0000);
+					}
+					SkGmPhyWrite(pAC, IoC, Port, 22, 0x4000);
+				}
+#endif	/* VCPU */
+
+				/* save page register */
+				SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
+
+				/* select page 2 to access MAC control register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
+
+				if (ChipId == CHIP_ID_YUKON_XL) {
+					/* set PHY reg 0, page 2, field [6:4] */
+					MacCtrl = PHY_MARV_CTRL;
+					LoopSpeed <<= 4;
+				}
+				else {	/*
+						 * CHIP_ID_YUKON_EC_U || CHIP_ID_YUKON_EX ||
+						 * >= CHIP_ID_YUKON_SUPR
+						 */
+					/* set PHY reg 21, page 2, field [2:0] */
+					MacCtrl = PHY_MARV_MAC_CTRL;
+				}
+
+				/* set MAC interface speed */
+				SkGmPhyWrite(pAC, IoC, Port, MacCtrl, LoopSpeed);
+
+				/* restore page register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
+
+				/* disable link pulses */
+				Word = PHY_M_PC_DIS_LINK_P;
+			}
+#ifndef VCPU
+			else {
+				/* set 'MAC Power up'-bit, set Manual MDI configuration */
+				Word = PHY_M_PC_MAC_POW_UP;
+			}
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+#endif /* !VCPU */
+		}
+#ifndef VCPU
+		else
+#endif /* !VCPU */
+#endif /* !SK_SLIM */
+#ifndef VCPU
+		if (!NewPhyType && AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
+			/* check for Gigabit adapters */
+			(pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+			/* Read Ext. PHY Specific Control */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
+
+			ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
+				PHY_M_EC_MAC_S_MSK);
+
+			ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
+
+			/* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
+			if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) {
+				/* set downshift counter to 3x and enable downshift */
+				ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
+			}
+			else {
+				/* set master & slave downshift counter to 1x */
+				ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
+			}
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
+		}
+#endif /* !VCPU */
+	}
+
+#ifndef VCPU
+	if (CHIP_ID_YUKON_2(pAC)) {
+		/* Read PHY Specific Control */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhySpec);
+
+		if (!DoLoop && pAC->GIni.GICopperType) {
+
+			if (ChipId == CHIP_ID_YUKON_FE || ChipId == CHIP_ID_YUKON_FE_P) {
+				/* enable Automatic Crossover (!!! Bits 5..4) */
+				PhySpec |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1);
+
+				if (ChipId == CHIP_ID_YUKON_FE_P && ChipRev == CHIP_REV_YU_FE2_A0) {
+					/* Enable Class A driver for FE+ A0 */
+					SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &Word);
+					Word |= PHY_M_FESC_SEL_CL_A;
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, Word);
+				}
+			}
+			else {
+#ifndef SK_SLIM
+				/* Read PHY Copper Specific Control 2 */
+				SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &Word);
+
+				if (HW_FEATURE(pAC, HWF_PHY_CLASS_A_100BT)) {
+					/* Enable Class A driver for 100Base-T */
+					Word |= BIT_12S;
+				}
+
+				if (ChipId >= CHIP_ID_YUKON_OPT && pPrt->PRevAutoNeg) {
+					/* enable PHY Reverse Auto-Negotiation */
+					Word |= BIT_13S;
+				}
+
+				if ((Word & (BIT_13S | BIT_12S)) != 0) {
+					/* Write PHY changes (SW-reset must follow) */
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, Word);
+				}
+#endif /* !SK_SLIM */
+
+				/* set Transformer-less mode for PHY group A */
+				if (HW_FEATURE(pAC, HWF_TRAFO_LESS_ENABLE)) {
+					/* connect internal MDI termination to AVDD */
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 3);
+
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x0002);
+
+					/* apply fixes in PHY AFE */
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00ff);
+
+					/* enable half amplitude mode */
+					SkGmPhyWrite(pAC, IoC, Port, 24, 0xa104);
+					SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
+
+					if (HW_FEATURE(pAC, HWF_PHY_SET_SLAVE_MDIX)) {
+						/* set manual slave */
+						pPrt->PMSMode = SK_MS_MODE_SLAVE;
+
+						/* set manual MDIX */
+						PhySpec &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_MDIX_MSK);
+
+						PhySpec |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_MAN_MDIX);
+					}
+
+					SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+				}
+				else {
+					if (!pPrt->PEnDetMode) {
+						/* disable Energy Detect Mode */
+						PhySpec &= ~PHY_M_PC_EN_DET_MSK;
+					}
+
+					/* enable Automatic Crossover */
+					PhySpec |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
+
+					/* downshift on PHY 88E1112 and 88E1149 is changed */
+					if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
+						NewPhyType) {
+						/* set downshift counter to 3x and enable downshift */
+						PhySpec &= ~PHY_M_PC_DSC_MSK;
+						PhySpec |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
+					}
+				}
+			}
+		}
+		/* workaround for deviation #4.88 (CRC errors) */
+		else {
+			/* disable Automatic Crossover */
+			PhySpec &= ~PHY_M_PC_MDIX_MSK;
+		}
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Set PHY Spec Reg. = 0x%04X\n", PhySpec));
+	}
+
+	/* special setup for PHY 88E1112 Fiber */
+	if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) {
+		/* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+
+		Word &= ~PHY_M_MAC_MD_MSK;
+		Word |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+
+		/* select page 1 to access Fiber registers */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
+
+		if (pAC->GIni.GIPmdTyp == 'P') {
+			/* for SFP-module set SIGDET polarity to low */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+
+			Word |= PHY_M_FIB_SIGD_POL;
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+		}
+		/* !!! don't set page register back to 0 !!! */
+	}
+#endif /* !VCPU */
+
+#ifdef XXX
+	/* Read PHY Control */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
+
+	if (!AutoNeg) {
+		/* disable Auto-negotiation */
+		PhyCtrl &= ~PHY_CT_ANE;
+	}
+
+	/* assert software reset */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl | PHY_CT_RESET);
+#endif /* XXX */
+
+	PhyCtrl = 0;
+	C1000BaseT = 0;
+	AutoNegAdv = PHY_SEL_TYPE;
+
+#ifndef SK_SLIM
+	/* manually Master/Slave ? */
+	if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
+		/* enable Manual Master/Slave */
+		C1000BaseT |= PHY_M_1000C_MSE;
+
+		if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
+			C1000BaseT |= PHY_M_1000C_MSC;	/* set it to Master */
+		}
+	}
+#endif /* !SK_SLIM */
+
+	/* Auto-negotiation ? */
+	if (!AutoNeg) {
+
+		if (pPrt->PLinkMode == SK_LMODE_FULL) {
+			/* set Full Duplex Mode */
+			PhyCtrl |= PHY_CT_DUP_MD;
+		}
+
+#ifndef SK_SLIM
+		/* set Master/Slave manually if not already done */
+		if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
+			C1000BaseT |= PHY_M_1000C_MSE;	/* set it to Slave */
+		}
+#endif /* !SK_SLIM */
+
+		/* set Speed */
+		switch (pPrt->PLinkSpeed) {
+		case SK_LSPEED_AUTO:
+		case SK_LSPEED_1000MBPS:
+			PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
+						PHY_CT_SP1000 : PHY_CT_SP100);
+			break;
+		case SK_LSPEED_100MBPS:
+			PhyCtrl |= PHY_CT_SP100;
+			break;
+		case SK_LSPEED_10MBPS:
+			break;
+		default:
+			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
+				SKERR_HWI_E019MSG);
+		}
+
+		if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) ||
+			/* disable Pause also for 10/100 Mbps in half duplex mode */
+			(!(ChipId == CHIP_ID_YUKON_EC_U ||
+			   ChipId == CHIP_ID_YUKON_EX ||
+			   ChipId >= CHIP_ID_YUKON_SUPR) &&
+			(pPrt->PLinkMode == SK_LMODE_HALF) &&
+			 ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) ||
+			  (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) {
+
+			/* set Pause Off */
+			PauseMode = (SK_U8)GMC_PAUSE_OFF;
+		}
+
+		SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
+
+#ifdef XXX
+		if (!DoLoop) {
+			/* assert software reset */
+			PhyCtrl |= PHY_CT_RESET;
+		}
+#endif /* XXX */
+	}
+	else {
+		/* set Auto-negotiation advertisement */
+
+		if (pAC->GIni.GICopperType) {
+			/* set Speed capabilities */
+			switch (pPrt->PLinkSpeed) {
+			case SK_LSPEED_AUTO:
+				/* check for Gigabit adapters */
+				if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+					C1000BaseT |= PHY_M_1000C_AFD | PHY_M_1000C_AHD;
+				}
+				AutoNegAdv |= PHY_M_AN_100_FD_HD | PHY_M_AN_10_FD_HD;
+				break;
+			case SK_LSPEED_1000MBPS:
+				/* check for Gigabit adapters */
+				if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+					C1000BaseT |= PHY_M_1000C_AFD | PHY_M_1000C_AHD;
+				}
+				break;
+			case SK_LSPEED_100MBPS:
+				AutoNegAdv |= PHY_M_AN_100_FD_HD;
+
+				if (!(HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
+						/* only in case of 100FD */
+						pPrt->PLinkModeConf < SK_LMODE_AUTOHALF)) {
+					/* advertise 10Base-T also */
+					AutoNegAdv |= PHY_M_AN_10_FD_HD;
+				}
+				break;
+			case SK_LSPEED_10MBPS:
+				AutoNegAdv |= PHY_M_AN_10_FD_HD;
+				break;
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
+					SKERR_HWI_E019MSG);
+			}
+
+			/* set Full/half duplex capabilities */
+			switch (pPrt->PLinkMode) {
+			case SK_LMODE_AUTOHALF:
+				C1000BaseT &= ~PHY_M_1000C_AFD;
+				AutoNegAdv &= ~(PHY_M_AN_100_FD | PHY_M_AN_10_FD);
+				break;
+			case SK_LMODE_AUTOFULL:
+				C1000BaseT &= ~PHY_M_1000C_AHD;
+				AutoNegAdv &= ~(PHY_M_AN_100_HD | PHY_M_AN_10_HD);
+				break;
+			case SK_LMODE_AUTOBOTH:
+				break;
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
+					SKERR_HWI_E015MSG);
+			}
+
+			/* set Flow-control capabilities */
+			switch (pPrt->PFlowCtrlMode) {
+			case SK_FLOW_MODE_NONE:
+				AutoNegAdv |= PHY_B_P_NO_PAUSE;
+				break;
+			case SK_FLOW_MODE_LOC_SEND:
+				AutoNegAdv |= PHY_B_P_ASYM_MD;
+				break;
+			case SK_FLOW_MODE_SYMMETRIC:
+				AutoNegAdv |= PHY_B_P_SYM_MD;
+				break;
+			case SK_FLOW_MODE_SYM_OR_REM:
+				AutoNegAdv |= PHY_B_P_BOTH_MD;
+				break;
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
+					SKERR_HWI_E016MSG);
+			}
+		}
+		else {	/* special defines for FIBER (88E1040S only) */
+
+			/* set Full/half duplex capabilities */
+			switch (pPrt->PLinkMode) {
+			case SK_LMODE_AUTOHALF:
+				AutoNegAdv |= PHY_M_AN_1000X_AHD;
+				break;
+			case SK_LMODE_AUTOFULL:
+				AutoNegAdv |= PHY_M_AN_1000X_AFD;
+				break;
+			case SK_LMODE_AUTOBOTH:
+				AutoNegAdv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
+				break;
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
+					SKERR_HWI_E015MSG);
+			}
+
+			/* set Flow-control capabilities */
+			switch (pPrt->PFlowCtrlMode) {
+			case SK_FLOW_MODE_NONE:
+				AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
+				break;
+			case SK_FLOW_MODE_LOC_SEND:
+				AutoNegAdv |= PHY_M_P_ASYM_MD_X;
+				break;
+			case SK_FLOW_MODE_SYMMETRIC:
+				AutoNegAdv |= PHY_M_P_SYM_MD_X;
+				break;
+			case SK_FLOW_MODE_SYM_OR_REM:
+				AutoNegAdv |= PHY_M_P_BOTH_MD_X;
+				break;
+			default:
+				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
+					SKERR_HWI_E016MSG);
+			}
+		}
+
+		if (!DoLoop) {
+			/* Restart Auto-negotiation */
+			PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
+		}
+	}
+
+#ifdef VCPU
+	if (ChipId == CHIP_ID_YUKON_PRM || ChipId == CHIP_ID_YUKON_OP_2) {
+		/* email from Gu Lin 2010-05-03 */
+
+		if (pPrt->PLinkSpeed == SK_LSPEED_1000MBPS) {
+			/* Program PHY register 30 as 16'h0708 for simulation speed up */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x0700 /* 0x0708 */);
+
+			VCpuWait(2000);
+		}
+	}
+	else {
+		/* email from Gu Lin (08-03-2002) */
+
+		/* Program PHY register 30 as 16'h0708 for simulation speed up */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x0700 /* 0x0708 */);
+
+		VCpuWait(2000);
+	}
+#else /* !VCPU */
+	if (ChipId != CHIP_ID_YUKON_FE && ChipId != CHIP_ID_YUKON_FE_P) {
+		/* Write 1000Base-T Control Register */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Set 1000B-T Ctrl  = 0x%04X\n", C1000BaseT));
+	}
+
+	/* Write AutoNeg Advertisement Register */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
+#endif /* !VCPU */
+
+	/* Write to the PHY Control register with SW reset */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl | PHY_CT_RESET);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
+
+#ifndef SK_SLIM
+	if (DoLoop) {
+		/* set the PHY Loopback bit */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl | PHY_CT_LOOP);
+	}
+#endif /* !SK_SLIM */
+
+#ifdef VCPU
+#ifndef HASE
+	VCpuWait(2000);
+#endif /* HASE */
+#else /* !VCPU */
+
+	LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS);
+
+	LedOver = 0;
+
+	BlinkCtrl = pAC->GIni.GILedBlinkCtrl;
+
+	if ((BlinkCtrl & SK_ACT_LED_BLINK) != 0) {
+
+		if (ChipId == CHIP_ID_YUKON_FE) {
+			/* on 88E3082 these bits are at 11..9 (shifted left) */
+			LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
+
+			Word = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_LINK) |
+				   /* change ACT LED control to LINK/ACT or blink mode */
+				   PHY_M_FELP_LED1_CTRL(
+					((BlinkCtrl & SK_LED_COMB_ACT_LNK) != 0) ?
+					LED_PAR_CTRL_LNK_AC : LED_PAR_CTRL_ACT_BL) |
+				   PHY_M_FELP_LED0_CTRL(
+					/* check for LINK_LED mux */
+					((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) ?
+					LED_PAR_CTRL_LINK : LED_PAR_CTRL_SPEED);
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word);
+		}
+		else if (ChipId == CHIP_ID_YUKON_FE_P) {
+			/* Read PHY Specific Control */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhySpec);
+
+			/* Enable Link Partner Next Page */
+			PhySpec |= PHY_M_PC_ENA_LIP_NP;
+
+			/* disable Energy Detect and enable scrambler */
+			PhySpec &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhySpec);
+
+			/* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
+			Word = PHY_M_FELP_LED2_CTRL(
+					((BlinkCtrl & SK_LED_COMB_ACT_LNK) != 0) ?
+					LED_PAR_CTRL_LNK_AC : LED_PAR_CTRL_ACT_BL) |
+				   PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
+				   PHY_M_FELP_LED0_CTRL(
+					/* check for LINK_LED mux */
+					((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) ?
+					LED_PAR_CTRL_LINK : LED_PAR_CTRL_SPEED);
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word);
+		}
+		else if (NewPhyType) {
+			/* save page register */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
+
+			/* select page 3 to access LED control register */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3);
+
+			/* LINK/ACT (Yukon-2 only) */
+			LedConf = PHY_M_LEDC_LOS_CTRL(LC_LNK_ON_ACT_BL) |
+					  PHY_M_LEDC_STA1_CTRL(LC_LINK_ON) |	/* 100 Mbps */
+					  PHY_M_LEDC_STA0_CTRL(LC_LINK_ON);		/* 1000 Mbps */
+
+			Mode = LC_LINK_ON;		/* 10 Mbps: On */
+
+			if (ChipId == CHIP_ID_YUKON_XL) {
+				/* set Polarity Control register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16)
+					(PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) |
+					 PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) |
+					 PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2)));
+			}
+			else if (ChipId == CHIP_ID_YUKON_EC_U ||
+					 ChipId == CHIP_ID_YUKON_EX ||
+					 ChipId >= CHIP_ID_YUKON_SUPR) {
+				/* check for LINK_LED mux */
+				if ((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) {
+
+					/* LED scheme #2 */
+					SK_IN16(IoC, GPHY_CTRL, &Word);
+
+					Word |= GPC_LED_CONF_VAL(4);
+
+					/* set GPHY LED Config */
+					SK_OUT16(IoC, GPHY_CTRL, Word);
+				}
+				else {
+					/* check for LED config bit 8 in PCI Our4 */
+					SK_IN16(IoC, PCI_C2(pAC, IoC, PCI_OUR_REG_4), &Word);
+
+					if ((Word & P_PIN63_LINK_LED_ENA) == 0) {
+						if ((BlinkCtrl & SK_LED_COMB_ACT_LNK) == 0) {
+							/* LED scheme #1 */
+							Mode = LC_FORCE_OFF;	/* 10 Mbps: forced Off */
+						}
+						/* else LED scheme #5 */
+
+						if ((BlinkCtrl & SK_ACT_LED_NOTR_OFF) == 0) {
+							/* set LED[5:4] Function Control and Polarity */
+							SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_STAT,
+								(SK_U16)
+								/* LED_ACT to Link/Act. */
+								(PHY_M_LEDC_STA1_CTRL(LC_LNK_ON_ACT_BL) |
+								/* LED_DUP to Duplex */
+								PHY_M_LEDC_STA0_CTRL(LC_DUPLEX_ON)));
+						}
+					}
+					/* LED scheme #3 if P_PIN63_LINK_LED_ENA is set */
+				}
+
+				/* set Blink Rate in LED Timer Control Register */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
+					LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS));
+			}
+
+			LedConf |= PHY_M_LEDC_INIT_CTRL(Mode);
+
+			/* set LED Function Control register */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, LedConf);
+
+#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
+			/* select page 6 to access Packet Generation register */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
+
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
+
+			Word |= BIT_4S;			/* enable CRC checker */
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
+
+			/* enable temperature sensor */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, BIT_5S);
+#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
+
+			/* restore page register */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
+		}
+		else {
+			/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
+			LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
+
+			/* on PHY 88E1111 there is a change for LED control */
+			if (ChipId == CHIP_ID_YUKON_EC &&
+				(BlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) {
+				/* Yukon-EC needs setting of 2 bits: 0,6=11) */
+				LedCtrl |= PHY_M_LEDC_TX_C_LSB;
+			}
+			/* turn off the Rx LED (LED_RX) */
+			LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF);
+		}
+	}
+
+	if ((BlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
+		/* disable blink mode (LED_DUPLEX) on collisions */
+		LedCtrl |= PHY_M_LEDC_DP_CTRL;
+	}
+
+	if (ChipId == CHIP_ID_YUKON_EC_U || ChipId == CHIP_ID_YUKON_UL_2) {
+		/* apply fixes in PHY AFE */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00ff);
+
+		/* increase differential signal amplitude in 10BASE-T */
+		SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99);
+		SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011);
+
+		if (ChipId == CHIP_ID_YUKON_EC_U) {
+			/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
+			SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204);
+			SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
+		}
+
+		/* set page register back to 0 */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+	}
+	else if (ChipId == CHIP_ID_YUKON_FE_P && ChipRev == CHIP_REV_YU_FE2_A0) {
+		/* apply workaround for integrated resistors calibration */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 17);
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x3f60);
+	}
+	else if (ChipId == CHIP_ID_YUKON_OPT && ChipRev == 0) {
+		/* apply fixes in PHY AFE */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00ff);
+
+		/* apply RDAC termination workaround */
+		SkGmPhyWrite(pAC, IoC, Port, 24, 0x2800);
+		SkGmPhyWrite(pAC, IoC, Port, 23, 0x2001);
+
+		/* set page register back to 0 */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+	}
+	else if (ChipId != CHIP_ID_YUKON_EX && ChipId < CHIP_ID_YUKON_SUPR) {
+		/* no effect on Yukon-XL */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
+
+#ifndef SK_SLIM
+		if ((BlinkCtrl & SK_LED_LINK100_ON) != 0) {
+			/* only in forced 100 Mbps mode */
+			if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
+				/* turn on 100 Mbps LED (LED_LINK100) */
+				LedOver |= PHY_M_LED_MO_100(MO_LED_ON);
+			}
+		}
+#endif /* !SK_SLIM */
+
+		if (LedOver != 0) {
+			/* set Manual LED Override */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver);
+		}
+	}
+	else if (ChipId == CHIP_ID_YUKON_PRM && pAC->GIni.GIChipCap == 0x7) {
+		/* Start Workaround for OptimaEEE Rev.Z0 */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00fb);
+
+		SkGmPhyWrite(pAC, IoC, Port,  1, 0x4099);
+		SkGmPhyWrite(pAC, IoC, Port,  3, 0x1120);
+		SkGmPhyWrite(pAC, IoC, Port, 11, 0x113c);
+		SkGmPhyWrite(pAC, IoC, Port, 14, 0x8100);
+		SkGmPhyWrite(pAC, IoC, Port, 15, 0x112a);
+		SkGmPhyWrite(pAC, IoC, Port, 17, 0x1008);
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00fc);
+
+		SkGmPhyWrite(pAC, IoC, Port,  1, 0x20b0);
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0x00ff);
+
+		for (i = 0; i < (int)(sizeof(OptimaEeeAfe) / sizeof(OPT_EEE_HACK)); i++) {
+			/* apply AFE settings */
+			SkGmPhyWrite(pAC, IoC, Port, 17, OptimaEeeAfe[i].PhyVal);
+			SkGmPhyWrite(pAC, IoC, Port, 16, OptimaEeeAfe[i].PhyReg | BIT_13S);
+		}
+
+		/* End Workaround for OptimaEEE */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+
+		if (HW_FEATURE(pAC, HWF_DO_EEE_ENABLE)) {
+			/* Enable 10Base-Te (EEE) */
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &Word);
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
+				Word | PHY_M_10B_TE_ENABLE);
+		}
+	}
+
+#ifdef SK_DIAG
+	c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl);
+	c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT);
+	c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv);
+	c_print("Set PHY Spec = 0x%04X\n", PhySpec);
+	c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl);
+#endif /* SK_DIAG */
+
+#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
+	/* Read PHY Control */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
+
+	/* Read AutoNeg Advertisement Register */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
+
+	if (ChipId != CHIP_ID_YUKON_FE && ChipId != CHIP_ID_YUKON_FE_P) {
+		/* Read 1000Base-T Control Register */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("1000B-T Ctrl  = 0x%04X\n", C1000BaseT));
+
+		/* Read Ext. PHY Specific Control */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
+	}
+
+	/* Read PHY Status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PHY Stat Reg. = 0x%04X\n", PhyStat));
+
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PHY Stat Reg. = 0x%04X\n", PhyStat1));
+
+	/* Read PHY Specific Status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PHY Spec Stat = 0x%04X\n", PhySpecStat));
+
+	pAC->GIni.GIPhyInitTime = (SK_U32)SkOsGetTime(pAC);
+
+#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
+
+#ifdef SK_DIAG
+	c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl);
+	c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT);
+	c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv);
+	c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl);
+	c_print("PHY Stat Reg = 0x%04X\n", PhyStat);
+	c_print("PHY Stat Reg = 0x%04X\n", PhyStat1);
+	c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat);
+#endif /* SK_DIAG */
+
+	/* clear PHY IRQ status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &Word);
+
+	/* enable PHY interrupts */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK);
+#endif /* !VCPU */
+
+}	/* SkGmInitPhyMarv */
+
+
+/******************************************************************************
+ *
+ *	SkMacInitPhy() - Initialize the PHY registers
+ *
+ * Description:	calls the Init PHY routines
+ *
+ * Note:
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacInitPhy(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL	DoLoop)		/* Should a PHY LoopBack be set-up? */
+{
+	SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
+
+}	/* SkMacInitPhy */
+
+
+/******************************************************************************
+ *
+ *	SkGmAutoNegDoneMarv() - Auto-negotiation handling
+ *
+ * Description:
+ *	This function handles the auto-negotiation if the Done bit is set.
+ *
+ * Returns:
+ *	SK_AND_OK	o.k.
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
+ */
+static int SkGmAutoNegDoneMarv(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		ResAb;		/* Resolved Ability */
+	SK_U16		AuxStat;	/* Auxiliary Status */
+	SK_U16		Word;
+	SK_U8		PauseMode;	/* Pause Mode */
+#ifndef SK_SLIM
+	SK_U16		LinkPartAb;	/* Link Partner Ability */
+#ifndef SK_DIAG
+	SK_EVPARA	Para;
+#endif /* !SK_DIAG */
+#endif /* !SK_SLIM */
+
+	/* set Pause On */
+	PauseMode = (SK_U8)GMC_PAUSE_ON;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("AutoNegDoneMarv, Port %d\n", Port));
+
+	pPrt = &pAC->GIni.GP[Port];
+
+#ifndef SK_SLIM
+	/* Get PHY parameters */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("Link P.Abil. = 0x%04X\n", LinkPartAb));
+
+	if ((LinkPartAb & PHY_M_AN_RF) != 0) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("AutoNegFail: Remote fault bit set Port %d\n", Port));
+		pPrt->PAutoNegFail = SK_TRUE;
+
+		return(SK_AND_OTHER);
+	}
+
+	if (pAC->GIni.GICopperType) {
+
+		if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
+			/* #979 remove workaround for 100M Link */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0);
+		}
+
+		/* Read PHY Auto-Negotiation Expansion */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word);
+
+		if ((Word & PHY_ANE_LP_CAP) == 0) {
+
+			pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
+
+#ifndef SK_DIAG
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
+				Word));
+
+#ifndef NDIS_MINIPORT_DRIVER
+			SK_ERR_LOG(pAC, SK_ERRCL_INFO, SKERR_HWI_E025, SKERR_HWI_E025MSG);
+#endif
+			Para.Para64 = Port;
+			SkEventQueue(pAC, SKGE_DRV, SK_DRV_LIPA_NOT_AN_ABLE, Para);
+#else
+			c_print("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
+				Word);
+#endif /* !SK_DIAG */
+
+			if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
+				pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
+				/* set used link speed */
+				pPrt->PLinkSpeedUsed = pPrt->PLinkSpeed;
+
+				/* Set Link Mode Status */
+				pPrt->PLinkModeStatus = (SK_U8)
+					(pPrt->PLinkModeConf == SK_LMODE_FULL) ?
+					SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF;
+
+				return(SK_AND_OK);
+			}
+		}
+		else {
+			/* check for fake auto-negotiation from link partner */
+			if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
+				/* only in case of 100FD */
+				pPrt->PLinkModeConf == SK_LMODE_FULL &&
+				pPrt->PLinkSpeed == SK_LSPEED_100MBPS &&
+				/* check if only 100HD is advertised */
+				(LinkPartAb & PHY_M_AN_100_FD_HD) == PHY_M_AN_100_HD) {
+
+				pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
+
+				/* set used link speed */
+				pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
+
+				/* Set Link Mode Status */
+				pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_FULL;
+
+				return(SK_AND_OK);
+			}
+
+			pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+
+			/* save Link Partner Ability */
+			pPrt->PLipaAbil = LinkPartAb;
+		}
+	}
+#endif /* !SK_SLIM */
+
+	/* check for Gigabit adapters */
+	if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
+
+#if defined(DEBUG) && !defined(SK_SLIM)
+		if ((ResAb & PHY_B_1000S_LP_FD) == 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+				("Link Partner is not capable of 1000FD, Phy1000BT: 0x%04X\n",
+				 ResAb));
+		}
+#endif /* DEBUG && !SK_SLIM */
+
+		/* Check Master/Slave resolution */
+		if ((ResAb & PHY_B_1000S_MSF) != 0) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("Master/Slave Fault Port %d\n", Port));
+
+			pPrt->PAutoNegFail = SK_TRUE;
+			pPrt->PMSStatus = SK_MS_STAT_FAULT;
+
+			return(SK_AND_OTHER);
+		}
+
+		pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
+			(SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
+	}
+
+	/* Read PHY Specific Status */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
+
+	/* Check Speed & Duplex resolved */
+	if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port));
+
+		pPrt->PAutoNegFail = SK_TRUE;
+		pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
+
+		return(SK_AND_DUP_CAP);
+	}
+
+	if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
+		pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
+			SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF);
+	}
+	else {
+		pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
+			SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF);
+	}
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE ||
+		pAC->GIni.GIChipId == CHIP_ID_YUKON_FE_P) {
+		/* set used link speed */
+		pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ?
+			SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS);
+
+		/* Yukon-FE PHYs don't report the Flow-Control resolution */
+		AuxStat = 0;
+
+		/* read MAC General Purpose Status */
+		GM_IN16(IoC, Port, GM_GP_STAT, &Word);
+
+		/* get the negotiated Flow-Control resolution from GPSR */
+		if ((Word & GM_GPSR_FC_RX_DIS) == 0) {
+			AuxStat |= PHY_M_PS_RX_P_EN;
+		}
+
+		if ((Word & GM_GPSR_FC_TX_DIS) == 0) {
+			AuxStat |= PHY_M_PS_TX_P_EN;
+		}
+	}
+	else {
+		/* Flow-Control Timeout for Fast Ethernet clock (50 MHz) */
+		Word = 12500;
+
+		/* set used link speed */
+		switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
+		case (unsigned)PHY_M_PS_SPEED_1000:
+			pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
+			/* adjust Flow-Control Timeout for Gigabit clock (125 MHz) */
+			Word = 31250;
+			break;
+		case PHY_M_PS_SPEED_100:
+			pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
+			break;
+		default:
+			pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
+		}
+
+		if (pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) {
+			/* adjust Flow-Control Timeout */
+			GM_OUT16(IoC, Port, GM_FC_TIMEOUT, Word);
+		}
+
+		if (HW_HAS_NEWER_PHY(pAC)) {
+			/* Tx & Rx Pause Enabled bits are at 9..8 */
+			AuxStat >>= 6;
+
+			if (!pAC->GIni.GICopperType) {
+				/* always 1000 Mbps on fiber */
+				pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
+			}
+		}
+
+		AuxStat &= PHY_M_PS_PAUSE_MSK;
+	}
+
+	/* We are using IEEE 802.3z/D5.0 Table 37-4 */
+	if (AuxStat == PHY_M_PS_PAUSE_MSK) {
+		/* Symmetric PAUSE */
+		pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
+	}
+	else if (AuxStat == PHY_M_PS_RX_P_EN) {
+		/* enable PAUSE receive, disable PAUSE transmit */
+		pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
+	}
+	else if (AuxStat == PHY_M_PS_TX_P_EN) {
+		/* disable PAUSE receive, enable PAUSE transmit */
+		pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
+	}
+	else {
+		/* PAUSE mismatch -> no PAUSE */
+		pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("LinkSpeedUsed = %d\n", pPrt->PLinkSpeedUsed));
+
+	if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) ||
+		/* disable Pause also for 10/100 Mbps in half duplex mode */
+		(!(pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U ||
+		   pAC->GIni.GIChipId == CHIP_ID_YUKON_EX ||
+		   pAC->GIni.GIChipId >= CHIP_ID_YUKON_SUPR) &&
+		(pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) &&
+		 pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) {
+
+		/* set Pause Off */
+		PauseMode = (SK_U8)GMC_PAUSE_OFF;
+	}
+
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
+
+	return(SK_AND_OK);
+}	/* SkGmAutoNegDoneMarv */
+
+
+/******************************************************************************
+ *
+ *	SkMacAutoNegDone() - Auto-negotiation handling
+ *
+ * Description:	calls the auto-negotiation done routine and enables Rx/Tx
+ *
+ * Returns:
+ *	SK_AND_OK	o.k.
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
+ */
+int SkMacAutoNegDone(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+	int			Rtv;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
+
+	if (Rtv != SK_AND_OK) {
+		return(Rtv);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("AutoNeg done Port %d\n", Port));
+
+	/* We checked everything and may now enable the link */
+	pPrt->PAutoNegFail = SK_FALSE;
+
+	/* enable receiver/transmitter */
+	SkMacRxTxEnable(pAC, IoC, Port);
+
+	return(SK_AND_OK);
+}	/* SkMacAutoNegDone */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC
+ *
+ * Description:
+ *  sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg.
+ *  enables Rx/Tx
+ *
+ * Returns: N/A
+ */
+static void SkGmSetRxTxEn(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		Para)		/* Parameter to set: MAC LoopBack, Duplex Mode */
+{
+	SK_U16	Ctrl;
+
+	GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
+
+	switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
+	case SK_MAC_LOOPB_ON:
+		Ctrl |= GM_GPCR_LOOP_ENA;
+		break;
+	case SK_MAC_LOOPB_OFF:
+		Ctrl &= ~GM_GPCR_LOOP_ENA;
+		break;
+	}
+
+	switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
+	case SK_PHY_FULLD_ON:
+		Ctrl |= GM_GPCR_DUP_FULL;
+		break;
+	case SK_PHY_FULLD_OFF:
+		Ctrl &= ~GM_GPCR_DUP_FULL;
+		break;
+	}
+
+	GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+
+}	/* SkGmSetRxTxEn */
+
+
+/******************************************************************************
+ *
+ *	SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
+ *
+ * Description:	calls the Special Set Rx/Tx Enable routines
+ *
+ * Returns: N/A
+ */
+void SkMacSetRxTxEn(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+int		Para)		/* Parameter to set: MAC LoopBack, Duplex Mode */
+{
+	SkGmSetRxTxEn(pAC, IoC, Port, Para);
+
+}	/* SkMacSetRxTxEn */
+#endif /* !SK_SLIM */
+
+
+/******************************************************************************
+ *
+ *	SkMacRxTxEnable() - Enable Rx/Tx activity if port is up
+ *
+ * Description:	enables Rx/Tx activity in the MAC
+ *
+ * Returns:
+ *	0	o.k.
+ *	!= 0	Error happened
+ */
+int SkMacRxTxEnable(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+	SK_U16		Reg;		/* 16-bit register value */
+	SK_U16		IntMask;	/* MAC interrupt mask */
+#ifndef SK_SLIM
+	SK_U16		SWord;
+#endif /* !SK_SLIM */
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (!pPrt->PHWLinkUp) {
+		/* The Hardware link is NOT up */
+		return(0);
+	}
+
+	if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
+		 pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
+		 pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
+		 pPrt->PAutoNegFail) {
+		/* Auto-negotiation is not done or failed */
+		return(0);
+	}
+
+	/*
+	 * Initialize the Interrupt Mask Register. Default IRQs are...
+	 *	- Rx Counter Event Overflow
+	 *	- Tx Counter Event Overflow
+	 *	- Transmit FIFO Underrun
+	 */
+	IntMask = GMAC_DEF_MSK;
+
+#if (defined(DEBUG) || defined(YUK2)) && !defined(SK_SLIM)
+	/* add IRQ for Receive FIFO Overrun */
+	IntMask |= GM_IS_RX_FF_OR;
+#endif
+
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask);
+
+	/* get General Purpose Control */
+	GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
+
+	if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
+		pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
+		/* set to Full Duplex */
+		Reg |= GM_GPCR_DUP_FULL;
+
+#ifndef SK_SLIM
+		if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
+			pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
+			/* disable auto-update for speed, duplex and flow-control */
+			Reg |= GM_GPCR_AU_ALL_DIS;
+		}
+#endif /* !SK_SLIM */
+	}
+
+	/* WA for dev. #4.209 */
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+		pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
+		/* enable/disable Store & Forward mode for TX */
+		SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
+			pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ?
+			TX_STFW_ENA : TX_STFW_DIS);
+	}
+
+#ifndef SK_SLIM
+	/* configure IPG according to used link speed */
+	GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
+
+	SWord &= ~GM_SMOD_IPG_MSK;
+
+	SWord |= IPG_DATA_VAL((pPrt->PLinkSpeedUsed == SK_LSPEED_STAT_1000MBPS) ?
+		pPrt->PMacIpgData_1G : pPrt->PMacIpgData_FE);
+
+	GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
+#endif /* SK_SLIM */
+
+	/* enable Rx/Tx */
+	GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+
+	pAC->GIni.GP[Port].PState = SK_PRT_RUN;
+
+	return(0);
+
+}	/* SkMacRxTxEnable */
+
+
+/******************************************************************************
+ *
+ *	SkMacRxTxDisable() - Disable Receiver and Transmitter
+ *
+ * Description:	disables Rx/Tx in the MAC
+ *
+ * Returns: N/A
+ */
+void SkMacRxTxDisable(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_U16	Word;
+
+	GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
+
+	Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+
+	GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
+
+}	/* SkMacRxTxDisable */
+
+
+/******************************************************************************
+ *
+ *	SkMacIrqDisable() - Disable IRQ from MAC
+ *
+ * Description:	sets the IRQ-mask to disable IRQ
+ *
+ * Returns: N/A
+ */
+void SkMacIrqDisable(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_GEPORT	*pPrt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	/* disable all GMAC IRQs */
+	SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
+
+#ifndef VCPU
+	if (pPrt->PState != SK_PRT_RESET) {
+		/* disable all PHY IRQs */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
+	}
+#endif /* !VCPU */
+
+}	/* SkMacIrqDisable */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkMacTimeStamp() - Enable / Disable Time Stamp
+ *
+ * Description:	enable / disable Time Stamp generation for Rx packets
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacTimeStamp(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+SK_BOOL	Enable)	/* Enable / Disable */
+{
+	SK_U8	TimeCtrl;
+
+	if (Enable) {
+		TimeCtrl = GMT_ST_START | GMT_ST_CLR_IRQ;
+	}
+	else {
+		TimeCtrl = GMT_ST_STOP | GMT_ST_CLR_IRQ;
+	}
+	/* Start/Stop Time Stamp Timer */
+	SK_OUT8(IoC, GMAC_TI_ST_CTRL, TimeCtrl);
+
+}	/* SkMacTimeStamp*/
+#endif /* !SK_SLIM */
+
+#ifdef SK_DIAG
+/******************************************************************************
+ *
+ *	SkGmSendCont() - Enable / Disable Send Continuous Mode
+ *
+ * Description:	enable / disable Packet Generation on GPHY
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGmSendCont(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+SK_BOOL	Enable)	/* Enable / Disable */
+{
+	SK_U16	Reg;
+	SK_U16	PageReg;
+
+	if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
+		/* select page 18 */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18);
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg);
+
+		Reg &= ~0x003c;			/* clear bits 5..2 */
+
+		if (Enable) {
+			/* enable packet generation, 1518 byte length */
+			Reg |= (BIT_5S | BIT_3S);
+		}
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg);
+	}
+	else if (HW_HAS_NEWER_PHY(pAC)) {
+		/* save page register */
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
+
+		/* select page 6 to access Packet Generation register */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
+
+		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg);
+
+		Reg &= ~0x003f;			/* clear bits 5..0 */
+
+		if (Enable) {
+			/* enable packet generation, 1518 byte length */
+			Reg |= (BIT_3S | BIT_1S);
+		}
+
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg);
+
+		/* restore page register */
+		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
+	}
+
+}	/* SkGmSendCont */
+
+/******************************************************************************
+ *
+ *	SkGmReadPhyTempSensor() - Read PHY's Temperature Sensor
+ *
+ * Description:	gets the Temperature from PHY's sensor
+ *
+ * Returns:
+ *	0	o.k.
+ *	1	PHY in reset
+ */
+int SkGmReadPhyTempSensor(
+SK_AC	*pAC,	/* Adapter Context */
+SK_IOC	IoC,	/* I/O Context */
+int		Port,	/* Port Index (MAC_1 + n) */
+int		*pVal)	/* Pointer to Value */
+{
+	SK_U16	Word;
+	SK_U16	Page;
+
+	/* additional check for PHY reset */
+	SK_IN16(IoC, MR_ADDR(Port, GPHY_CTRL), &Word);
+
+	if ((Word & GPC_RST_CLR) == 0) {
+		/* use old value */
+		return(1);
+	}
+
+	/* save page register */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Page);
+
+	/* select page to access temperature sensor */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
+
+	/* read temperature */
+	SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &Word);
+
+	/* restore page register */
+	SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Page);
+
+	*pVal = (Word & 0x1f) * 5;
+
+	switch (pAC->GIni.GIChipId) {
+	case CHIP_ID_YUKON_SUPR:
+	case CHIP_ID_YUKON_UL_2:
+		*pVal -= 25;
+		break;
+	case CHIP_ID_YUKON_OPT:
+		*pVal -= 5;
+		break;
+	case CHIP_ID_YUKON_PRM:
+		*pVal -= 15;
+		break;
+	}
+
+	return(0);
+
+}	/* SkGmReadPhyTempSensor */
+
+#else /* !SK_DIAG */
+
+/******************************************************************************
+ *
+ *	SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg
+ *
+ *	This function analyses the PHY status word.
+ *  If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable
+ *	is set true.
+ */
+void SkMacAutoNegLipaPhy(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_U16	PhyStat)	/* PHY Status word to analyse */
+{
+	SK_GEPORT	*pPrt;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
+		(PhyStat & PHY_ST_AN_OVER) != 0) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+			("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n",
+			Port, PhyStat));
+
+		pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
+	}
+}	/* SkMacAutoNegLipaPhy */
+
+
+/******************************************************************************
+ *
+ *	SkGmIrq() - Interrupt Service Routine
+ *
+ * Description:	services an Interrupt Request of the GMAC
+ *
+ * Note:
+ *
+ * Returns:
+ *	nothing
+ */
+static void SkGmIrq(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	SK_U8		IStatus;	/* Interrupt status */
+#if defined(SK_SLIM) || defined(SK_NO_PNMI)
+	SK_U64		OverflowStatus;
+#endif /* SK_SLIM || SK_NO_PNMI */
+#ifndef SK_SLIM
+	SK_GEPORT	*pPrt;
+	SK_EVPARA	Para;
+
+	pPrt = &pAC->GIni.GP[Port];
+#endif /* !SK_SLIM */
+
+	SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
+		("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus));
+
+	/* Combined Tx & Rx Counter Overflow SIRQ Event */
+	if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
+		/* these IRQs will be cleared by reading GMACs register */
+#if defined(SK_SLIM) || defined(SK_NO_PNMI)
+		SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus);
+#else /* !SK_SLIM && !SK_NO_PNMI */
+		Para.Para32[0] = (SK_U32)Port;
+		Para.Para32[1] = (SK_U32)IStatus;
+		SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
+#endif /* !SK_SLIM && !SK_NO_PNMI */
+	}
+
+#ifndef SK_SLIM
+	if (IStatus & GM_IS_RX_FF_OR) {
+		/* clear GMAC Rx FIFO Overrun IRQ */
+		SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
+
+		Para.Para64 = Port;
+		SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para);
+
+#ifdef DEBUG
+		pPrt->PRxOverCnt++;
+#endif /* DEBUG */
+	}
+#endif /* !SK_SLIM */
+
+	if (IStatus & GM_IS_TX_FF_UR) {
+		/* clear GMAC Tx FIFO Underrun IRQ */
+		SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FU);
+
+#ifndef SK_SLIM
+		if (HW_FEATURE(pAC, HWF_WA_DEV_511)) {
+			Para.Para32[0] = (SK_U32)Port;
+			Para.Para32[1] = 0;
+			SkEventQueue(pAC, SKGE_DRV, SK_DRV_TX_UNDERRUN, Para);
+		}
+		else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
+			pPrt->PPortUsage == SK_JUMBO_LINK) {
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("%s\n", SKERR_SIRQ_E020MSG));
+		}
+		else {
+			/* may NOT happen -> error log */
+			SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG);
+		}
+#endif /* !SK_SLIM */
+	}
+
+#ifndef SK_SLIM
+	if (IStatus & GM_IS_TX_COMPL) {
+		/* Clear GMAC Frame Transmission Complete IRQ */
+		SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
+	}
+
+	if (IStatus & GM_IS_RX_COMPL) {
+		/* Clear GMAC Frame Reception Complete IRQ */
+		SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
+	}
+#endif /* !SK_SLIM */
+}	/* SkGmIrq */
+
+
+/******************************************************************************
+ *
+ *	SkMacIrq() - Interrupt Service Routine for MAC
+ *
+ * Description:	calls the Interrupt Service Routine
+ *
+ * Returns:
+ *	nothing
+ */
+void SkMacIrq(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port)		/* Port Index (MAC_1 + n) */
+{
+	/* IRQ from GMAC */
+	SkGmIrq(pAC, IoC, Port);
+
+}	/* SkMacIrq */
+
+#endif /* !SK_DIAG */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGmUpdateStats() - Force the GMAC to output the current statistic
+ *
+ * Description:
+ *	Empty function for GMAC. Statistic data is accessible in direct way.
+ *
+ * Returns:
+ *	0:  success
+ *	1:  something went wrong
+ */
+int SkGmUpdateStats(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+unsigned int Port)	/* Port Index (MAC_1 + n) */
+{
+	return(0);
+}
+#endif /* !SK_SLIM */
+
+
+/******************************************************************************
+ *
+ *	SkGmMacStatistic() - Get GMAC counter value
+ *
+ * Description:
+ *	Gets the 32bit counter value. Except for the octet counters
+ *	the lower 32bit are counted in hardware and the upper 32bit
+ *	must be counted in software by monitoring counter overflow interrupts.
+ *
+ * Returns:
+ *	0:  success
+ *	1:  something went wrong
+ */
+int SkGmMacStatistic(
+SK_AC	*pAC,			/* Adapter Context */
+SK_IOC	IoC,			/* I/O Context */
+unsigned int Port,		/* Port Index (MAC_1 + n) */
+SK_U16	StatAddr,		/* MIB counter base address */
+SK_U32	SK_FAR *pVal)	/* Pointer to return statistic value */
+{
+
+	if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
+
+		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
+		return(1);
+	}
+
+	GM_IN32(IoC, Port, StatAddr, pVal);
+
+	return(0);
+}	/* SkGmMacStatistic */
+
+
+/******************************************************************************
+ *
+ *	SkGmResetCounter() - Clear MAC statistic counter
+ *
+ * Description:
+ *	Force GMAC to clear its statistic counter.
+ *
+ * Returns:
+ *	0:  success
+ *	1:  something went wrong
+ */
+int SkGmResetCounter(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+unsigned int Port)	/* Port Index (MAC_1 + n) */
+{
+	SK_U16	Reg;	/* PHY Address Register */
+	SK_U16	LoWord;
+	SK_U16	HiWord;
+	int		i;
+	int		Addr;
+
+	GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg);
+
+	/* set MIB Clear Counter Mode */
+	GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
+
+	/* read all MIB Counters with Clear Mode set */
+	for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
+
+		Addr = GM_MIB_CNT_BASE + 8 * i;
+
+		/* the reset is performed only when the lower 16 bits are read */
+		GM_IN16(IoC, Port, Addr, &LoWord);
+
+		/* check if MIB was cleared */
+		GM_IN16(IoC, Port, Addr, &LoWord);
+		GM_IN16(IoC, Port, Addr + 2, &HiWord);
+
+		if (LoWord != 0 || HiWord != 0) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("SkGmResetCounter: MIB counter not cleared (0x%04X)\n", Addr));
+		}
+	}
+
+	/* clear MIB Clear Counter Mode */
+	GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
+
+	return(0);
+}	/* SkGmResetCounter */
+
+
+/******************************************************************************
+ *
+ *	SkGmOverflowStatus() - Gets the status of counter overflow interrupt
+ *
+ * Description:
+ *	Checks the source causing an counter overflow interrupt. On success the
+ *	resulting counter overflow status is written to <pStatus>, whereas the
+ *	the following bit coding is used:
+ *	63:56 - unused
+ *	55:48 - TxRx interrupt register bit 7:0
+ *	47:32 - Rx interrupt register
+ *	31:24 - unused
+ *	23:16 - TxRx interrupt register bit 15:8
+ *	15: 0 - Tx interrupt register
+ *
+ * Returns:
+ *	0:  success
+ *	1:  something went wrong
+ */
+int SkGmOverflowStatus(
+SK_AC	*pAC,				/* Adapter Context */
+SK_IOC	IoC,				/* I/O Context */
+unsigned int Port,			/* Port Index (MAC_1 + n) */
+SK_U16	IStatus,			/* Interrupt Status from MAC */
+SK_U64	SK_FAR *pStatus)	/* Pointer for return overflow status value */
+{
+	SK_U16	RegVal;
+	SK_U64	Status;		/* Overflow status */
+
+	Status = 0;
+
+	if ((IStatus & GM_IS_RX_CO_OV) != 0) {
+		/* this register is self-clearing after read */
+		GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
+
+		Status |= (SK_U64)RegVal << 32;
+	}
+
+	if ((IStatus & GM_IS_TX_CO_OV) != 0) {
+		/* this register is self-clearing after read */
+		GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
+
+		Status |= (SK_U64)RegVal;
+	}
+
+	/* this register is self-clearing after read */
+	GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
+
+	/* Rx overflow interrupt register bits (LoByte) */
+	Status |= (SK_U64)((SK_U8)RegVal) << 48;
+	/* Tx overflow interrupt register bits (HiByte) */
+	Status |= (SK_U64)(RegVal >> 8) << 16;
+
+	*pStatus = Status;
+
+	return(0);
+}	/* SkGmOverflowStatus */
+
+
+#ifndef SK_SLIM
+/******************************************************************************
+ *
+ *	SkGmCableDiagStatus() - Starts / Gets status of cable diagnostic test
+ *
+ * Description:
+ *  starts the cable diagnostic test if 'StartTest' is true
+ *  gets the results if 'StartTest' is true
+ *
+ * NOTE:	this test is meaningful only when link is down
+ *
+ * Returns:
+ *	0:  success
+ *	1:  no YUKON copper
+ *	2:  test in progress
+ *	3:  PHY read error
+ */
+int SkGmCableDiagStatus(
+SK_AC	*pAC,		/* Adapter Context */
+SK_IOC	IoC,		/* I/O Context */
+int		Port,		/* Port Index (MAC_1 + n) */
+SK_BOOL	StartTest)	/* flag for start / get result */
+{
+	SK_GEPORT	*pPrt;
+	int			i;
+	int			CableDiagOffs;
+	int			MdiPairs;
+	int			ChipId;
+	int			Rtv;
+	SK_BOOL		FastEthernet;
+	SK_BOOL		NewPhyType;
+	SK_BOOL		AdvancedVct;
+	SK_U16		Ctrl;
+	SK_U16		RegVal;
+
+	pPrt = &pAC->GIni.GP[Port];
+
+	if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
+
+		return(1);
+	}
+
+	ChipId = pAC->GIni.GIChipId;
+
+	NewPhyType = HW_HAS_NEWER_PHY(pAC);
+
+	AdvancedVct = ChipId == CHIP_ID_YUKON_EX || ChipId >= CHIP_ID_YUKON_SUPR;
+
+	if (ChipId == CHIP_ID_YUKON_FE || ChipId == CHIP_ID_YUKON_FE_P) {
+
+		CableDiagOffs = PHY_MARV_FE_VCT_TX;
+		FastEthernet = SK_TRUE;
+		MdiPairs = 2;
+	}
+	else {
+		CableDiagOffs = AdvancedVct ? PHY_MARV_ADV_VCT_C :
+			NewPhyType ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG;
+
+		FastEthernet = SK_FALSE;
+		MdiPairs = 4;
+	}
+
+	if (StartTest) {
+		/* set to RESET to avoid PortCheckUp */
+		pPrt->PState = SK_PRT_RESET;
+
+		/* only start the cable test */
+		if (!FastEthernet) {
+			/* check for PHY model 2, rev. < 4 */
+			if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) &&
+				 ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) {
+				/* apply TDR workaround */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 30);
+
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00);
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800);
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400);
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000);
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100);
+			}
+
+#ifdef YUKON_DBG
+			if (ChipId == CHIP_ID_YUKON_EC) {
+				/* select page 1 */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
+
+				/* disable waiting period */
+				SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs,
+					PHY_M_CABD_DIS_WAIT);
+			}
+#endif
+			if (NewPhyType) {
+				/* select page 5 */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
+
+#ifdef xYUKON_DBG
+				/* disable waiting period */
+				SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1,
+					PHY_M_CABD_DIS_WAIT);
+#endif
+			}
+			else {
+				/* select page 0 for MDI[0] */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
+			}
+		}
+		else {
+			RegVal = PHY_CT_RESET | PHY_CT_SP100;
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal);
+
+#ifdef xYUKON_DBG
+			SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal);
+			/* disable waiting period */
+			RegVal |= PHY_M_FESC_DIS_WAIT;
+
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal);
+#endif
+		}
+
+		Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
+
+		if (Rtv != 0) {
+			/* PHY read error */
+			return(3);
+		}
+
+		/* enable Cable Diagnostic Test */
+		RegVal |= PHY_M_CABD_ENA_TEST;
+
+		if (AdvancedVct) {
+
+			if (ChipId == CHIP_ID_YUKON_EX &&
+				pAC->GIni.GIChipRev == CHIP_REV_YU_EX_A0) {
+				/* apply TDR workaround */
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 13);
+
+				SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0x4c32);
+			}
+
+			RegVal &= ~PHY_M_CABD_MODE_MSK;
+
+			/* select first peak above threshold */
+			RegVal |= PHY_M_CABD_TEST_MODE(1);
+
+			/* read Transmit Pulse Reg */
+			SkGmPhyRead(pAC, IoC, Port, CableDiagOffs + 5, &Ctrl);
+
+			Ctrl &= ~PHY_M_CABD_PWID_MSK;
+
+			/* select 1/2 pulse width (64ns) */
+			Ctrl |= PHY_M_CABD_PULS_WIDT(2);
+
+			SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 5, Ctrl);
+		}
+
+		/* start Cable Diagnostic Test */
+		SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, RegVal);
+
+		return(0);
+	}
+
+	/* read Cable Diagnostic Reg */
+	Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
+
+	if (Rtv != 0) {
+		/* PHY read error */
+		return(3);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
+		("PHY Cable Diag. = 0x%04X\n", RegVal));
+
+	if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
+		/* test is running */
+		return(2);
+	}
+
+	if (AdvancedVct) {
+		/* additional check */
+		if ((RegVal & PHY_M_CABD_COMPLETE) == 0) {
+			/* test not completed */
+			return(2);
+		}
+
+		CableDiagOffs = PHY_MARV_PHY_CTRL;
+	}
+
+	/* get the test results */
+	for (i = 0; i < MdiPairs; i++) {
+
+		if (!FastEthernet && !NewPhyType) {
+			/* set address to i for MDI[i] */
+			SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
+		}
+
+		/* get Cable Diagnostic values */
+		SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
+
+		pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
+
+		pPrt->PMdiPairSts[i] = (SK_U8)(AdvancedVct ?
+			(RegVal >> 8) : ((RegVal & PHY_M_CABD_STAT_MSK) >> 13));
+
+		if (FastEthernet || NewPhyType) {
+			/* get next register */
+			CableDiagOffs++;
+		}
+	}
+
+	return(0);
+}	/* SkGmCableDiagStatus */
+#endif /* !SK_SLIM */
+
+/* End of file */
+
diff -ruN linux/drivers/net/sk98lin/sky2.c linux-new/drivers/net/sk98lin/sky2.c
--- linux/drivers/net/sk98lin/sky2.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sky2.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,2877 @@
+/******************************************************************************
+ *
+ * Name:        sky2.c
+ * Project:     Yukon2 specific functions and implementations
+ * Purpose:     The main driver source module
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ *	    (C)Copyright 1998-2002 SysKonnect GmbH.
+ *	    (C)Copyright 2002-2011 Marvell.
+ *
+ *	    Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
+ *      Server Adapters.
+ *
+ *	    Address all question to: support@marvell.com
+ *
+ *      LICENSE:
+ *      (C)Copyright Marvell.
+ *      
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *      
+ *      The information in this file is provided "AS IS" without warranty.
+ *      /LICENSE
+ *
+ *****************************************************************************/
+
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+#include <linux/tcp.h>
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)
+#include <linux/ip.h>
+#endif
+/******************************************************************************
+ *
+ * Local Function Prototypes
+ *
+ *****************************************************************************/
+
+static void InitPacketQueues(SK_AC *pAC,int Port);
+static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port);
+static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket);
+#ifdef SK_EXTREME
+static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan, SK_U32 Rss, SK_U32 ExtremeCsumResult);
+#else
+static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan, SK_U32 Rss);
+#endif
+static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done);
+static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort);
+static SK_BOOL AllocateAndInitLETables(SK_AC *pAC);
+static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC);
+static void FreeLETables(SK_AC *pAC);
+static void FreePacketBuffers(SK_AC *pAC);
+static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port);
+#ifdef CONFIG_SK98LIN_NAPI
+static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo);
+#else
+static SK_BOOL HandleStatusLEs(SK_AC *pAC);
+#endif
+
+extern void	SkGeCheckTimer		(DEV_NET *pNet);
+extern void	SkLocalEventQueue(	SK_AC *pAC,
+					SK_U32 Class,
+					SK_U32 Event,
+					SK_U32 Param1,
+					SK_U32 Param2,
+					SK_BOOL Flag);
+extern void	SkLocalEventQueue64(	SK_AC *pAC,
+					SK_U32 Class,
+					SK_U32 Event,
+					SK_U64 Param,
+					SK_BOOL Flag);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,19)
+/* Need way to schedule device 0 even when it's offline. */
+static inline int __netif_rx_schedule_prep(struct net_device *dev)
+{
+	return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
+}
+#endif
+#endif
+
+
+/******************************************************************************
+ *
+ * Local Variables
+ *
+ *****************************************************************************/
+
+#define MAX_NBR_RX_BUFFERS_IN_HW	0x15
+static SK_U8 NbrRxBuffersInHW;
+#define FLUSH_OPC(le)
+
+/******************************************************************************
+ *
+ * Global Functions
+ *
+ *****************************************************************************/
+
+int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev);
+void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
+
+/*****************************************************************************
+ *
+ * 	SkY2RestartStatusUnit - restarts teh status unit
+ *
+ * Description:
+ *	Reenables the status unit after any De-Init (e.g. when altering
+ *	the sie of the MTU via 'ifconfig a.b.c.d mtu xxx')
+ *
+ * Returns:	N/A
+ */
+void SkY2RestartStatusUnit(
+SK_AC  *pAC)  /* pointer to adapter control context */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2RestartStatusUnit\n"));
+
+	/*
+	** It might be that the TX timer is not started. Therefore
+	** it is initialized here -> to be more investigated!
+	*/
+	SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
+
+	pAC->StatusLETable.Done  = 0;
+	pAC->StatusLETable.Put   = 0;
+	pAC->StatusLETable.HwPut = 0;
+	SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2RestartStatusUnit\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2AllocateResources - Allocates all required resources for Yukon2
+ *
+ * Description:
+ *	This function allocates all memory needed for the Yukon2.
+ *	It maps also RX buffers to the LETables and initializes the
+ *	status list element table.
+ *
+ * Returns:
+ *	SK_TRUE, if all resources could be allocated and setup succeeded
+ *	SK_FALSE, if an error
+ */
+SK_BOOL SkY2AllocateResources (
+SK_AC  *pAC)  /* pointer to adapter control context */
+{
+	int CurrMac;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("==> SkY2AllocateResources\n"));
+
+	/*
+	** Initialize the packet queue variables first
+	*/
+	for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
+		InitPacketQueues(pAC, CurrMac);
+	}
+
+	/*
+	** Get sufficient memory for the LETables
+	*/
+	if (!AllocateAndInitLETables(pAC)) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
+			("No memory for LETable.\n"));
+		return(SK_FALSE);
+	}
+
+	/*
+	** Allocate and intialize memory for both RX and TX
+	** packet and fragment buffers. On an error, free
+	** previously allocated LETable memory and quit.
+	*/
+	if (!AllocatePacketBuffersYukon2(pAC)) {
+		FreeLETables(pAC);
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
+			("No memory for Packetbuffers.\n"));
+		return(SK_FALSE);
+	}
+
+	/*
+	** Rx and Tx LE tables will be initialized in SkGeOpen()
+	**
+	** It might be that the TX timer is not started. Therefore
+	** it is initialized here -> to be more investigated!
+	*/
+	SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
+	pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("<== SkY2AllocateResources\n"));
+
+	return (SK_TRUE);
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2FreeResources - Frees previously allocated resources of Yukon2
+ *
+ * Description:
+ *	This function frees all previously allocated memory of the Yukon2.
+ *
+ * Returns: N/A
+ */
+void SkY2FreeResources (
+SK_AC  *pAC)  /* pointer to adapter control context */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2FreeResources\n"));
+
+	FreeLETables(pAC);
+	FreePacketBuffers(pAC);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2FreeResources\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2AllocateRxBuffers - Allocates the receive buffers for a port
+ *
+ * Description:
+ *	This function allocated all the RX buffers of the Yukon2.
+ *
+ * Returns: N/A
+ */
+void SkY2AllocateRxBuffers (
+SK_AC    *pAC,   /* pointer to adapter control context */
+SK_IOC    IoC,	 /* I/O control context                */
+int       Port)	 /* port index of RX                   */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("==> SkY2AllocateRxBuffers (Port %c)\n", Port));
+
+	FillReceiveTableYukon2(pAC, IoC, Port);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("<== SkY2AllocateRxBuffers\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2FreeRxBuffers - Free's all allocates RX buffers of
+ *
+ * Description:
+ *	This function frees all RX buffers of the Yukon2 for a single port
+ *
+ * Returns: N/A
+ */
+void SkY2FreeRxBuffers (
+SK_AC    *pAC,   /* pointer to adapter control context */
+SK_IOC    IoC,	 /* I/O control context                */
+int       Port)	 /* port index of RX                   */
+{
+	SK_PACKET     *pSkPacket;
+	unsigned long  Flags;   /* for POP/PUSH macros */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2FreeRxBuffers (Port %c)\n", Port));
+
+	if (pAC->RxPort[Port].ReceivePacketTable   != NULL) {
+		POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
+		while (pSkPacket != NULL) {
+			if ((pSkPacket->pFrag) != NULL) {
+				pci_unmap_page(pAC->PciDev,
+				(dma_addr_t) pSkPacket->pFrag->pPhys,
+				pSkPacket->pFrag->FragLen - 2,
+				PCI_DMA_FROMDEVICE);
+
+				/* wipe out any rubbish data that may interfere */
+				skb_shinfo(pSkPacket->pMBuf)->nr_frags = 0;
+				skb_shinfo(pSkPacket->pMBuf)->frag_list = NULL;
+				DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
+				pSkPacket->pMBuf        = NULL;
+				pSkPacket->pFrag->pPhys = (SK_U64) 0;
+				pSkPacket->pFrag->pVirt = NULL;
+			}
+			PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
+			POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2FreeRxBuffers\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2FreeTxBuffers - Free's any currently maintained Tx buffer
+ *
+ * Description:
+ *	This function frees the TX buffers of the Yukon2 for a single port
+ *	which might be in use by a transmit action
+ *
+ * Returns: N/A
+ */
+void SkY2FreeTxBuffers (
+SK_AC    *pAC,   /* pointer to adapter control context */
+SK_IOC    IoC,	 /* I/O control context                */
+int       Port)	 /* port index of TX                   */
+{
+	SK_PACKET      *pSkPacket;
+	SK_FRAG        *pSkFrag;
+	unsigned long   Flags;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2FreeTxBuffers (Port %c)\n", Port));
+
+	if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) {
+		POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
+		while (pSkPacket != NULL) {
+			if ((pSkFrag = pSkPacket->pFrag) != NULL) {
+				UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
+			}
+			PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
+			POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
+		}
+#ifdef USE_SYNC_TX_QUEUE
+		POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
+		while (pSkPacket != NULL) {
+			if ((pSkFrag = pSkPacket->pFrag) != NULL) {
+				UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
+			}
+			PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
+			POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
+		}
+#endif
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2FreeTxBuffers\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	SkY2Isr - handle a receive IRQ for all yukon2 cards
+ *
+ * Description:
+ *	This function is called when a receive IRQ is set. (only for yukon2)
+ *	HandleReceives does the deferred processing of all outstanding
+ *	interrupt operations.
+ *
+ * Returns:	N/A
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,19)
+SkIsrRetVar SkY2Isr (
+int              irq,     /* the irq we have received (might be shared!) */
+void            *dev_id)  /* current device id                           */
+#else
+SkIsrRetVar SkY2Isr (
+int              irq,     /* the irq we have received (might be shared!) */
+void            *dev_id,  /* current device id                           */
+struct  pt_regs *ptregs)  /* not used by our driver                      */
+#endif
+{
+	struct SK_NET_DEVICE  *dev  = (struct SK_NET_DEVICE *)dev_id;
+	DEV_NET               *pNet = PPRIV;
+	SK_AC                 *pAC  = pNet->pAC;
+#ifndef CONFIG_SK98LIN_NAPI
+	SK_BOOL                handledStatLE	= SK_FALSE;
+	unsigned long          Flags;
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	SK_U32                TmpVal32;
+#endif
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+		("==> SkY2Isr\n"));
+
+	SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &pAC->InterruptSource);
+
+	if ((pAC->InterruptSource == 0) && (!pNet->NetConsoleMode)){
+		SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+			("No Interrupt\n ==> SkY2Isr\n"));
+		return SkIsrRetNone;
+	}
+
+#ifdef Y2_RECOVERY
+	if (pNet->InRecover) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+			("Already in recover\n ==> SkY2Isr\n"));
+		SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
+		return SkIsrRetNone;
+	}
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+	/* Since both boards share one irq, they share one poll routine */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	napi_schedule(&pNet->napi);
+#else
+	if (__netif_rx_schedule_prep(pAC->dev[0])) {
+		__netif_rx_schedule(pAC->dev[0]);
+	}
+#endif
+#else
+
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
+#endif
+	/* Handle the status BMU */
+	handledStatLE = HandleStatusLEs(pAC);
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
+#endif
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	/* FW interrupt handler */
+	if (pAC->InterruptSource & GLB_ISRC_CPU_HOST) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+		printk("SkY2Isr: H FWISR: 0x%x\n", pAC->InterruptSource);
+#endif
+		/* Clear the interrupt */
+		SK_IN32(pAC->IoBase, B28_Y2_ASF_STAT_CMD, &TmpVal32);
+		TmpVal32 |= BIT_17;
+		SK_OUT32(pAC->IoBase, B28_Y2_ASF_STAT_CMD, TmpVal32);
+		SkFwIsr(pAC, pAC->IoBase);
+
+		pAC->InterruptSource = pAC->InterruptSource & ~GLB_ISRC_CPU_HOST;
+	}
+#endif
+
+	/*
+	** Check for Special Interrupts
+	*/
+	if ((pAC->InterruptSource & ~Y2_IS_STAT_BMU) || pAC->CheckQueue 
+#ifdef Y2_RECOVERY
+		|| pNet->TimerExpired
+#endif
+		) {
+		pAC->CheckQueue = SK_FALSE;
+		spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
+		SkGeSirqIsr(pAC, pAC->IoBase, pAC->InterruptSource);
+		SkEventDispatcher(pAC, pAC->IoBase);
+		spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
+	}
+
+	/* Speed enhancement for a2 chipsets */
+	if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
+		spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
+		SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
+		SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
+		spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
+	}
+
+	/*
+	** Reenable interrupts and signal end of ISR
+	*/
+	SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
+
+	/*
+	** Stop and restart TX timer in case a Status LE was handled
+	*/
+	if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
+		SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
+		SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
+	}
+	if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
+		GiveTxBufferToHw(pAC, pAC->IoBase, 0);
+	}
+	if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
+		GiveTxBufferToHw(pAC, pAC->IoBase, 1);
+	}
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+		("<== SkY2Isr\n"));
+
+	return SkIsrRetHandled;
+} /* SkY2Isr */
+
+/*****************************************************************************
+ *
+ *	SkY2Xmit - Linux frame transmit function for Yukon2
+ *
+ * Description:
+ *	The system calls this function to send frames onto the wire.
+ *	It puts the frame in the tx descriptor ring. If the ring is
+ *	full then, the 'tbusy' flag is set.
+ *
+ * Returns:
+ *	0, if everything is ok
+ *	!=0, on error
+ *
+ * WARNING:
+ *	returning 1 in 'tbusy' case caused system crashes (double
+ *	allocated skb's) !!!
+ */
+int SkY2Xmit(
+struct sk_buff       *skb,  /* socket buffer to be sent */
+struct SK_NET_DEVICE *dev)  /* via which device?        */
+{
+	DEV_NET         *pNet = PPRIV;
+	SK_AC           *pAC     = pNet->pAC;
+	SK_U8            FragIdx = 0;
+	SK_PACKET       *pSkPacket;
+	SK_FRAG         *PrevFrag;
+	SK_FRAG         *CurrFrag;
+	SK_PKT_QUEUE    *pWorkQueue;  /* corresponding TX queue */
+	SK_PKT_QUEUE    *pWaitQueue;
+	SK_PKT_QUEUE    *pFreeQueue;
+	SK_LE_TABLE     *pLETab;      /* corresponding LETable  */
+	skb_frag_t      *sk_frag;
+	SK_U64           PhysAddr;
+	unsigned long    Flags;
+	unsigned int     Port;
+	int              CurrFragCtr;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("==> SkY2Xmit\n"));
+
+	/*
+	** Get port and return if no free packet is available
+	*/
+	if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
+		Port = skb_shinfo(skb)->nr_frags - (2*MAX_SKB_FRAGS);
+		skb_shinfo(skb)->nr_frags = 0;
+	} else {
+		Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort;
+	}
+
+	if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+			("Not free packets available for send\n"));
+		netif_stop_queue(dev);
+		return NETDEV_TX_BUSY;/* zero bytes sent! */
+	}
+
+	/*
+	** Put any new packet to be sent in the waiting queue and
+	** handle also any possible fragment of that packet.
+	*/
+	pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
+	pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
+	pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free);
+	pLETab     = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
+
+	/*
+	** Normal send operations require only one fragment, because
+	** only one sk_buff data area is passed.
+	** In contradiction to this, scatter-gather (zerocopy) send
+	** operations might pass one or more additional fragments
+	** where each fragment needs a separate fragment info packet.
+	*/
+	if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) >
+					NUM_FREE_LE_IN_TABLE(pLETab)) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+			("Not enough LE available for send\n"));
+		netif_stop_queue(dev);
+		return NETDEV_TX_BUSY;/* zero bytes sent! */
+	}
+
+	if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+			("Not even one fragment available for send\n"));
+		netif_stop_queue(dev);
+		return NETDEV_TX_BUSY;/* zero bytes sent! */
+	}
+
+	/*
+	** Get first packet from free packet queue
+	*/
+	POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket);
+	if(pSkPacket == NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+			("Could not obtain free packet used for xmit\n"));
+		netif_stop_queue(dev);
+		return NETDEV_TX_BUSY;/* zero bytes sent! */
+	}
+
+	pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]);
+
+	/*
+	** map the sk_buff to be available for the adapter
+	*/
+	PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+			virt_to_page(skb->data),
+			((unsigned long) skb->data & ~PAGE_MASK),
+			skb_headlen(skb),
+			PCI_DMA_TODEVICE);
+	pSkPacket->pMBuf	  = skb;
+	pSkPacket->pFrag->pPhys   = PhysAddr;
+	pSkPacket->pFrag->FragLen = skb_headlen(skb);
+	pSkPacket->pFrag->pNext   = NULL; /* initial has no next default */
+	pSkPacket->NumFrags	  = skb_shinfo(skb)->nr_frags + 1;
+
+	PrevFrag = pSkPacket->pFrag;
+
+	/*
+	** Each scatter-gather fragment need to be mapped...
+	*/
+	for (	CurrFragCtr = 0;
+		CurrFragCtr < skb_shinfo(skb)->nr_frags;
+		CurrFragCtr++) {
+		FragIdx++;
+		sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr];
+		CurrFrag = &(pSkPacket->FragArray[FragIdx]);
+
+		/*
+		** map the sk_buff to be available for the adapter
+		*/
+		PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+				sk_frag->page,
+				sk_frag->page_offset,
+				sk_frag->size,
+				PCI_DMA_TODEVICE);
+
+		CurrFrag->pPhys   = PhysAddr;
+		CurrFrag->FragLen = sk_frag->size;
+		CurrFrag->pNext   = NULL;
+
+		/*
+		** Add the new fragment to the list of fragments
+		*/
+		PrevFrag->pNext = CurrFrag;
+		PrevFrag = CurrFrag;
+	}
+
+	/*
+	** Add packet to waiting packets queue
+	*/
+	PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket);
+	GiveTxBufferToHw(pAC, pAC->IoBase, Port);
+	dev->trans_start = jiffies;
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("<== SkY2Xmit(return 0)\n"));
+
+	return NETDEV_TX_OK;
+} /* SkY2Xmit */
+
+#ifdef CONFIG_SK98LIN_NAPI
+/*****************************************************************************
+ *
+ *	SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets
+ *
+ * Description:
+ *	Called by the Linux system in case NAPI polling is activated
+ *
+ * Returns
+ *	The number of work data still to be handled
+ *
+ * Notes
+ *	The slowpath lock needs to be set because HW accesses may
+ *	interfere with slowpath events (e.g. TWSI)
+ */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+int SkY2Poll(struct napi_struct *napi, int WorkToDo) {
+#else
+int SkY2Poll(struct net_device *dev, int *budget) {
+#endif
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	SK_U32                TmpVal32;
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	DEV_NET	*pNet		= container_of(napi, DEV_NET, napi);
+	SK_AC	*pAC		= pNet->pAC;
+#else
+	DEV_NET *pNet = PPRIV;
+	SK_AC	*pAC		= pNet->pAC;
+	int	WorkToDo	= min(*budget, dev->quota);
+#endif
+	int	WorkDone	= 0;
+	SK_BOOL	handledStatLE	= SK_FALSE;
+
+	/* Handle the status BMU */
+	handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo);
+
+#ifdef MV_INCLUDE_SDK_SUPPORT
+	/* FW interrupt handler */
+	if (pAC->InterruptSource & GLB_ISRC_CPU_HOST) {
+#ifdef VERBOSE_ASF_FIFO_DBUG_RPINTS
+		printk("SkY2Isr: H FWISR: 0x%x\n", pAC->InterruptSource);
+#endif
+		/* Clear the interrupt */
+		SK_IN32(pAC->IoBase, B28_Y2_ASF_STAT_CMD, &TmpVal32);
+		TmpVal32 |= BIT_17;
+		SK_OUT32(pAC->IoBase, B28_Y2_ASF_STAT_CMD, TmpVal32);
+		SkFwIsr(pAC, pAC->IoBase);
+
+		pAC->InterruptSource = pAC->InterruptSource & ~GLB_ISRC_CPU_HOST;
+	}
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+	*budget -= WorkDone;
+	dev->quota -= WorkDone;
+#endif
+
+	/*
+	** Check for Special Interrupts
+	*/
+	if ((pAC->InterruptSource & ~Y2_IS_STAT_BMU) || pAC->CheckQueue 
+#ifdef Y2_RECOVERY
+		|| pNet->TimerExpired
+#endif
+		) {
+		pAC->CheckQueue = SK_FALSE;
+		spin_lock(&pAC->SlowPathLock);
+		SkGeSirqIsr(pAC, pAC->IoBase, pAC->InterruptSource);
+		SkEventDispatcher(pAC, pAC->IoBase);
+		spin_unlock(&pAC->SlowPathLock);
+	}
+
+	/* Speed enhancement for a2 chipsets */
+	if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
+		spin_lock(&pAC->SlowPathLock);
+		SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
+		SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
+		spin_unlock(&pAC->SlowPathLock);
+	}
+
+	if(WorkDone < WorkToDo) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+		netif_rx_complete(dev);
+#endif
+		/*
+		** Stop and restart TX timer in case a Status LE was handled
+		*/
+		if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
+			SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
+			SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
+		}
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+		napi_complete(napi);
+#endif
+
+		/*
+		** Reenable interrupts
+		*/
+		SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
+
+		if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
+			GiveTxBufferToHw(pAC, pAC->IoBase, 0);
+		}
+		if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
+			GiveTxBufferToHw(pAC, pAC->IoBase, 1);
+		}
+	}
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
+	return (WorkDone);
+#else
+	return (WorkDone >= WorkToDo);
+#endif
+
+} /* SkY2Poll */
+#endif
+
+/******************************************************************************
+ *
+ *	SkY2PortStop - stop a port on Yukon2
+ *
+ * Description:
+ *	This function stops a port of the Yukon2 chip. This stop
+ *	stop needs to be performed in a specific order:
+ *
+ *	a) Stop the Prefetch unit
+ *	b) Stop the Port (MAC, PHY etc.)
+ *
+ * Returns: N/A
+ */
+void SkY2PortStop(
+SK_AC   *pAC,      /* adapter control context                             */
+SK_IOC   IoC,      /* I/O control context (address of adapter registers)  */
+int      Port,     /* port to stop (MAC_1 + n)                            */
+int      Dir,      /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
+int      RstMode)  /* Reset Mode (SK_SOFT_RST, SK_HARD_RST)               */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2PortStop (Port %c)\n", 'A' + Port));
+
+	/*
+	** Stop the HW
+	*/
+	SkGeStopPort(pAC, IoC, Port, Dir, RstMode);
+
+	/*
+	** Move any TX packet from work queues into the free queue again
+	** and initialize the TX LETable variables
+	*/
+	SkY2FreeTxBuffers(pAC, pAC->IoBase, Port);
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp    = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr       = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done              = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put               = 0;
+#ifndef MV_INCLUDE_SDK_SUPPORT
+	pAC->GIni.GP[Port].PState = SK_PRT_STOP;
+#endif
+	/*
+	** Move any RX packet from work queue into the waiting queue
+	** and initialize the RX LETable variables
+	*/
+	SkY2FreeRxBuffers(pAC, pAC->IoBase, Port);
+	pAC->RxPort[Port].RxLET.BufHighAddr = 0;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2PortStop()\n"));
+}
+
+/******************************************************************************
+ *
+ *	SkY2PortStart - start a port on Yukon2
+ *
+ * Description:
+ *	This function starts a port of the Yukon2 chip. This start
+ *	action needs to be performed in a specific order:
+ *
+ *	a) Initialize the LET indices (PUT/GET to 0)
+ *	b) Initialize the LET in HW (enables also prefetch unit)
+ *	c) Move all RX buffers from waiting queue to working queue
+ *	   which involves also setting up of RX list elements
+ *	d) Initialize the FIFO settings of Yukon2 (Watermark etc.)
+ *	e) Initialize the Port (MAC, PHY etc.)
+ *	f) Initialize the MC addresses
+ *
+ * Returns:	N/A
+ */
+void SkY2PortStart(
+SK_AC   *pAC,   /* adapter control context                            */
+SK_IOC   IoC,   /* I/O control context (address of adapter registers) */
+int      Port)  /* port to start                                      */
+{
+	SK_HWLE   *pLE;
+	SK_U32     DWord;
+	SK_U16     PrefetchReg; /* register for Put index */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> SkY2PortStart (Port %c)\n", 'A' + Port));
+
+	/*
+	** Initialize the LET indices
+	*/
+	pAC->RxPort[Port].RxLET.Done                = 0;
+	pAC->RxPort[Port].RxLET.Put                 = 0;
+	pAC->RxPort[Port].RxLET.HwPut               = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done  = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put   = 0;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0;
+	if (HW_SYNC_TX_SUPPORTED(pAC)) {
+		pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done  = 0;
+		pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put   = 0;
+		pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0;
+	}
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
+		/*
+		** It might be that we have to limit the RX buffers
+		** effectively passed to HW. Initialize the start
+		** value in that case...
+		*/
+		NbrRxBuffersInHW = 0;
+	}
+
+	/*
+	** TODO on dual net adapters we need to check if
+	** StatusLETable need to be set...
+	**
+	** pAC->StatusLETable.Done  = 0;
+	** pAC->StatusLETable.Put   = 0;
+	** pAC->StatusLETable.HwPut = 0;
+	** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable);
+	*/
+
+	/*
+	** Initialize the LET in HW (enables also prefetch unit)
+	*/
+	SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2,
+			&pAC->RxPort[Port].RxLET);
+	SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2,
+			&pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
+	if (HW_SYNC_TX_SUPPORTED(pAC)) {
+		SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2,
+				&pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET);
+	}
+
+	/*
+	** Using new values for the watermarks and the timer for
+	** low latency optimization
+	*/
+	if (pAC->LowLatency) {
+		SK_OUT8(IoC, STAT_FIFO_WM, 1);
+		SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1);
+		SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50);
+		SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10);
+	}
+
+	/*
+	** Initialize the Port (MAC, PHY etc.)
+	*/
+	if (SkGeInitPort(pAC, IoC, Port)) {
+		if (Port == 0) {
+			printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name);
+		} else {
+			printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name);
+		}
+	}
+
+	if (IS_GMAC(pAC)) {
+		/* disable Rx GMAC FIFO Flush Mode */
+		SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF);
+	}
+
+	/*
+	** Initialize the MC addresses
+	*/
+	SkAddrMcUpdate(pAC,IoC, Port);
+	SkMacRxTxEnable(pAC, IoC,Port);
+	SkGeRxCsum(pAC, IoC, Port, SK_TRUE);
+
+	GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET);
+	RXLE_SET_STACS1(pLE, pAC->CsOfs1);
+	RXLE_SET_STACS2(pLE, pAC->CsOfs2);
+	RXLE_SET_CTRL(pLE, 0);
+
+	RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER);
+	FLUSH_OPC(pLE);
+	if (Port == 0) {
+		PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG);
+	} else {
+		PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG);
+	}
+	DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET);
+	SK_OUT16(IoC, PrefetchReg, (SK_U16)DWord);
+	UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET);
+
+	pAC->GIni.GP[Port].PState = SK_PRT_RUN;
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== SkY2PortStart()\n"));
+}
+
+/******************************************************************************
+ *
+ * Local Functions
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *
+ *	InitPacketQueues - initialize SW settings of packet queues
+ *
+ * Description:
+ *	This function will initialize the packet queues for a port.
+ *
+ * Returns: N/A
+ */
+static void InitPacketQueues(
+SK_AC  *pAC,   /* pointer to adapter control context */
+int     Port)  /* index of port to be initialized    */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("==> InitPacketQueues(Port %c)\n", 'A' + Port));
+
+	pAC->RxPort[Port].RxQ_working.pHead = NULL;
+	pAC->RxPort[Port].RxQ_working.pTail = NULL;
+	spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock);
+
+	pAC->RxPort[Port].RxQ_waiting.pHead = NULL;
+	pAC->RxPort[Port].RxQ_waiting.pTail = NULL;
+	spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock);
+
+	pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL;
+	spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock);
+
+	pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL;
+	spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock);
+
+	pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL;
+	spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock);
+
+#ifdef USE_SYNC_TX_QUEUE
+	pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL;
+	spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock);
+
+	pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL;
+	pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL;
+	spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock);
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("<== InitPacketQueues(Port %c)\n", 'A' + Port));
+} /* InitPacketQueues */
+
+/*****************************************************************************
+ *
+ *	GiveTxBufferToHw - commits a previously allocated DMA area to HW
+ *
+ * Description:
+ *	This functions gives transmit buffers to HW. If no list elements
+ *	are available the buffers will be queued.
+ *
+ * Notes:
+ *       This function can run only once in a system at one time.
+ *
+ * Returns: N/A
+ */
+static void GiveTxBufferToHw(
+SK_AC   *pAC,   /* pointer to adapter control context         */
+SK_IOC   IoC,   /* I/O control context (address of registers) */
+int      Port)  /* port index for which the buffer is used    */
+{
+	SK_HWLE         *pLE;
+	SK_PACKET       *pSkPacket;
+	SK_FRAG         *pFrag;
+	SK_PKT_QUEUE    *pWorkQueue;   /* corresponding TX queue */
+	SK_PKT_QUEUE    *pWaitQueue;
+	SK_LE_TABLE     *pLETab;       /* corresponding LETable  */
+	SK_BOOL          SetOpcodePacketFlag;
+	SK_U32           HighAddress;
+	SK_U32           LowAddress;
+	SK_U16           TcpSumStart = 0;
+	SK_U16           TcpSumWrite = 0;
+	SK_U8            OpCode;
+	SK_U8            Ctrl;
+	unsigned long    Flags;
+	unsigned long    LockFlag;
+	int              Protocol;
+#ifdef NETIF_F_TSO
+	SK_U16           Mss;
+	int              TcpOptLen;
+	int              IpTcpLen;
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("==> GiveTxBufferToHw\n"));
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_510)) {
+		SK_OUT32(pAC->IoBase, TBMU_TEST, TBMU_TEST_BMU_TX_CHK_AUTO_OFF);
+	}
+
+	if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
+		return;
+	}
+
+	spin_lock_irqsave(&pAC->TxQueueLock, LockFlag);
+
+	/*
+	** Initialize queue settings
+	*/
+	pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
+	pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
+	pLETab     = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
+
+	POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
+	while (pSkPacket != NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("\tWe have a packet to send %p\n", pSkPacket));
+
+		/*
+		** the first frag of a packet gets opcode OP_PACKET
+		*/
+		SetOpcodePacketFlag	= SK_TRUE;
+		pFrag			= pSkPacket->pFrag;
+
+		/*
+		** fill list elements with data from fragments
+		*/
+		while (pFrag != NULL) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("\tGet LE\n"));
+#ifdef NETIF_F_TSO
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)
+			Mss = skb_shinfo(pSkPacket->pMBuf)->gso_size;
+#else
+			Mss = skb_shinfo(pSkPacket->pMBuf)->tso_size;
+#endif
+
+			if (Mss) {
+#ifdef SK_EXTREME
+				if (!HW_IS_EXT_LE_FORMAT(pAC)) {
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
+					struct iphdr *iph = ip_hdr(pSkPacket->pMBuf);
+					struct tcphdr *tcph = tcp_hdr(pSkPacket->pMBuf);
+
+					TcpOptLen = ((tcph->doff - 5) * 4);
+					IpTcpLen  = ((iph->ihl * 4) + sizeof(struct tcphdr));
+#else
+					TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4);
+					IpTcpLen  = ((pSkPacket->pMBuf->nh.iph->ihl * 4) +
+						sizeof(struct tcphdr));
+#endif
+					Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER);
+#ifdef SK_EXTREME
+				}
+#endif
+			}
+			if (pLETab->Bmu.RxTx.MssValue != Mss) {
+				pLETab->Bmu.RxTx.MssValue = Mss;
+				/* Take a new LE for TSO from the table */
+				GET_TX_LE(pLE, pLETab);
+
+#ifdef SK_EXTREME
+				if (HW_IS_EXT_LE_FORMAT(pAC)) {
+					TXLE_SET_OPC(pLE, OP_MSS | HW_OWNER);
+					TXLE_SET_MSSVAL(pLE, pLETab->Bmu.RxTx.MssValue);
+				} else {
+#endif
+					TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER);
+					TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue);
+#ifdef SK_EXTREME
+				}
+#endif
+
+				FLUSH_OPC(pLE) ;
+			}
+#endif
+			GET_TX_LE(pLE, pLETab);
+			Ctrl = 0;
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab)));
+
+			SK_DBG_DUMP_TX_LE(pLE);
+
+			LowAddress  = (SK_U32) (pFrag->pPhys & 0xffffffff);
+			HighAddress = (SK_U32) (pFrag->pPhys >> 32);
+
+			if (HighAddress != pLETab->BufHighAddr) {
+				/* set opcode high part of the address in one LE */
+				OpCode = OP_ADDR64 | HW_OWNER;
+
+				/* Set now the 32 high bits of the address */
+				TXLE_SET_ADDR( pLE, HighAddress);
+
+				/* Set the opcode into the LE */
+				TXLE_SET_OPC(pLE, OpCode);
+
+				/* Flush the LE to memory */
+				FLUSH_OPC(pLE);
+
+				/* remember the HighAddress we gave to the Hardware */
+				pLETab->BufHighAddr = HighAddress;
+
+				/* get a new LE because we filled one with high address */
+				GET_TX_LE(pLE, pLETab);
+			}
+
+			/*
+			** TCP checksum offload
+			*/
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+			if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_PARTIAL) &&
+#else
+			if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_HW) &&
+#endif
+			    (SetOpcodePacketFlag         == SK_TRUE)) {
+				Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff);
+				/* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */
+
+				// Yukon Extreme B0
+				if (HW_FEATURE(pAC, HWF_WA_DEV_510)) {
+					if (Protocol & C_PROTO_ID_TCP) {
+						Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
+						/* TCP Checksum Calculation Start Position */
+						TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
+						/* TCP Checksum Write Position */
+						TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
+					} else {
+						Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
+						/* TCP Checksum Calculation Start Position */
+						TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
+						/* UDP Checksum Write Position */
+						TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
+					}
+				}
+				// Yukon 2, Yukon Extreme besides B0
+				else {
+					if (Protocol & C_PROTO_ID_TCP) {
+#ifdef SK_EXTREME
+						if (!HW_IS_EXT_LE_FORMAT(pAC)) {
+#endif
+							Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
+							/* TCP Checksum Calculation Start Position */
+							TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
+							/* TCP Checksum Write Position */
+							TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
+#ifdef SK_EXTREME
+						} else {
+							Ctrl = CALSUM;
+						}
+#endif
+					} else {
+#ifdef SK_EXTREME
+						if (!HW_IS_EXT_LE_FORMAT(pAC)) {
+#endif
+							Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
+							/* TCP Checksum Calculation Start Position */
+							TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
+							/* UDP Checksum Write Position */
+							TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
+#ifdef SK_EXTREME
+						} else {
+							Ctrl = CALSUM;
+						}
+#endif
+					}
+				}
+
+				if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) {
+					/* Update the last value of the write position */
+					pLETab->Bmu.RxTx.TcpWp = TcpSumWrite;
+
+					/* Set the Lock field for this LE: */
+					/* Checksum calculation for one packet only */
+					TXLE_SET_LCKCS(pLE, 1);
+
+					/* Set the start position for checksum. */
+					TXLE_SET_STACS(pLE, TcpSumStart);
+
+					/* Set the position where the checksum will be writen */
+					TXLE_SET_WRICS(pLE, TcpSumWrite);
+
+					/* Set the initial value for checksum */
+					/* PseudoHeader CS passed from Linux -> 0! */
+					TXLE_SET_INICS(pLE, 0);
+
+					/* Set the opcode for tcp checksum */
+					TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER);
+
+					/* Flush the LE to memory */
+					FLUSH_OPC(pLE);
+
+					/* get a new LE because we filled one with data for checksum */
+					GET_TX_LE(pLE, pLETab);
+				}
+			} /* end TCP offload handling */
+
+			TXLE_SET_ADDR(pLE, LowAddress);
+			TXLE_SET_LEN(pLE, pFrag->FragLen);
+
+			if (SetOpcodePacketFlag){
+#ifdef NETIF_F_TSO
+				if (Mss) {
+					OpCode = OP_LARGESEND | HW_OWNER;
+				} else {
+#endif
+					OpCode = OP_PACKET | HW_OWNER;
+#ifdef NETIF_F_TSO
+				}
+#endif
+				SetOpcodePacketFlag = SK_FALSE;
+			} else {
+				/* Follow packet in a sequence has always OP_BUFFER */
+				OpCode = OP_BUFFER | HW_OWNER;
+			}
+
+			/* Check if the low address is near the upper limit. */
+			CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen);
+
+			pFrag = pFrag->pNext;
+			if (pFrag == NULL) {
+				/* mark last fragment */
+				Ctrl |= EOP;
+			}
+			TXLE_SET_CTRL(pLE, Ctrl);
+			TXLE_SET_OPC(pLE, OpCode);
+			FLUSH_OPC(pLE);
+
+			SK_DBG_DUMP_TX_LE(pLE);
+		}
+
+		/*
+		** Remember next LE for tx complete
+		*/
+		pSkPacket->NextLE = GET_PUT_IDX(pLETab);
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE));
+
+		/*
+		** Add packet to working packets queue
+		*/
+		PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket);
+
+		/*
+		** give transmit start command
+		*/
+		if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
+			spin_lock(&pAC->SetPutIndexLock);
+			SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
+			spin_unlock(&pAC->SetPutIndexLock);
+		} else {
+			/* write put index */
+			if (Port == 0) {
+				SK_OUT16(pAC->IoBase,
+					Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG),
+					(SK_U16)GET_PUT_IDX(&pAC->TxPort[0][0].TxALET));
+				UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET);
+			} else {
+				SK_OUT16(pAC->IoBase,
+					Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG),
+					(SK_U16)GET_PUT_IDX(&pAC->TxPort[1][0].TxALET));
+				UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET);
+			}
+		}
+
+		spin_lock_irqsave(&pWaitQueue->QueueLock, Flags);
+		if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
+			spin_unlock_irqrestore(&pWaitQueue->QueueLock, Flags);
+			break; /* get out of while */
+		}
+		spin_unlock_irqrestore(&pWaitQueue->QueueLock, Flags);
+		POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
+	} /* while (pSkPacket != NULL) */
+
+	spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("<== GiveTxBufferToHw\n"));
+	return;
+} /* GiveTxBufferToHw */
+
+/***********************************************************************
+ *
+ *	GiveRxBufferToHw - commits a previously allocated DMA area to HW
+ *
+ * Description:
+ *	This functions gives receive buffers to HW. If no list elements
+ *	are available the buffers will be queued.
+ *
+ * Notes:
+ *       This function can run only once in a system at one time.
+ *
+ * Returns: N/A
+ */
+static void GiveRxBufferToHw(
+SK_AC      *pAC,      /* pointer to adapter control context         */
+SK_IOC      IoC,      /* I/O control context (address of registers) */
+int         Port,     /* port index for which the buffer is used    */
+SK_PACKET  *pPacket)  /* receive buffer(s)                          */
+{
+	SK_HWLE         *pLE;
+	SK_LE_TABLE     *pLETab;
+	SK_BOOL         Done = SK_FALSE;  /* at least on LE changed? */
+	SK_U32          LowAddress;
+	SK_U32          HighAddress;
+	SK_U16          PrefetchReg;      /* register for Put index  */
+	unsigned        NumFree;
+	unsigned        Required;
+	unsigned long   Flags;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+	("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket));
+
+	pLETab	= &pAC->RxPort[Port].RxLET;
+
+	if (Port == 0) {
+		PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG);
+	} else {
+		PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG);
+	}
+
+	if (pPacket != NULL) {
+		/*
+		** For the time being, we have only one packet passed
+		** to this function which might be changed in future!
+		*/
+		PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+	}
+
+	/*
+	** now pPacket contains the very first waiting packet
+	*/
+	POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+	while (pPacket != NULL) {
+		if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
+			if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) {
+				PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+					("<== GiveRxBufferToHw()\n"));
+				return;
+			}
+			NbrRxBuffersInHW++;
+		}
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("Try to add packet %p\n", pPacket));
+
+		/*
+		** Check whether we have enough listelements:
+		**
+		** we have to take into account that each fragment
+		** may need an additional list element for the high
+		** part of the address here I simplified it by
+		** using MAX_FRAG_OVERHEAD maybe it's worth to split
+		** this constant for Rx and Tx or to calculate the
+		** real number of needed LE's
+		*/
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("\tNum %d Put %d Done %d Free %d %d\n",
+			pLETab->Num, pLETab->Put, pLETab->Done,
+			NUM_FREE_LE_IN_TABLE(pLETab),
+			(NUM_FREE_LE_IN_TABLE(pLETab))));
+
+		Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD;
+		NumFree = NUM_FREE_LE_IN_TABLE(pLETab);
+		if (NumFree) {
+			NumFree--;
+		}
+
+		if (Required > NumFree ) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+				("\tOut of LEs have %d need %d\n",
+				NumFree, Required));
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+				("\tWaitQueue starts with packet %p\n", pPacket));
+			PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+			if (Done) {
+				/*
+				** write Put index to BMU or Polling Unit and make the LE's
+				** available for the hardware
+				*/
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+					("\tWrite new Put Idx\n"));
+
+				SK_OUT16(IoC, PrefetchReg, (SK_U16)GET_PUT_IDX(pLETab));
+				UPDATE_HWPUT_IDX(pLETab);
+			}
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+				("<== GiveRxBufferToHw()\n"));
+			return;
+		} else {
+			if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) {
+				/*
+				** Failure while allocating sk_buff might
+				** be due to temporary short of resources
+				** Maybe next time buffers are available.
+				** Until this, the packet remains in the
+				** RX waiting queue...
+				*/
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+					SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+					("Failed to allocate Rx buffer\n"));
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+					("WaitQueue starts with packet %p\n", pPacket));
+				PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+				if (Done) {
+					/*
+					** write Put index to BMU or Polling
+					** Unit and make the LE's
+					** available for the hardware
+					*/
+					SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+						("\tWrite new Put Idx\n"));
+
+					SK_OUT16(IoC, PrefetchReg, (SK_U16)GET_PUT_IDX(pLETab));
+					UPDATE_HWPUT_IDX(pLETab);
+				}
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+					("<== GiveRxBufferToHw()\n"));
+				return;
+			}
+		}
+		Done = SK_TRUE;
+
+		LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff);
+		HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32);
+		if (HighAddress != pLETab->BufHighAddr) {
+			/* get a new LE for high address */
+			GET_RX_LE(pLE, pLETab);
+
+			/* Set now the 32 high bits of the address */
+			RXLE_SET_ADDR(pLE, HighAddress);
+
+			/* Set the control bits of the address */
+			RXLE_SET_CTRL(pLE, 0);
+
+			/* Set the opcode into the LE */
+			RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER));
+
+			/* Flush the LE to memory */
+			FLUSH_OPC(pLE);
+
+			/* remember the HighAddress we gave to the Hardware */
+			pLETab->BufHighAddr = HighAddress;
+		}
+
+		/*
+		** Fill data into listelement
+		*/
+		GET_RX_LE(pLE, pLETab);
+		RXLE_SET_ADDR(pLE, LowAddress);
+		RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen);
+		RXLE_SET_CTRL(pLE, 0);
+		RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER));
+		FLUSH_OPC(pLE);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("=== LE filled\n"));
+
+		SK_DBG_DUMP_RX_LE(pLE);
+
+		/*
+		** Remember next LE for rx complete
+		*/
+		pPacket->NextLE = GET_PUT_IDX(pLETab);
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("\tPackets Next LE is %d\n", pPacket->NextLE));
+
+		/*
+		** Add packet to working receive buffer queue and get
+		** any next packet out of the waiting queue
+		*/
+		PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket);
+		if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) {
+			break; /* get out of while processing */
+		}
+		POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("\tWaitQueue is empty\n"));
+
+	if (Done) {
+		/*
+		** write Put index to BMU or Polling Unit and make the LE's
+		** available for the hardware
+		*/
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("\tWrite new Put Idx\n"));
+
+		/* Speed enhancement for a2 chipsets */
+		if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
+			spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
+			SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab);
+			spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
+		} else {
+			/* write put index */
+			if (Port == 0) {
+				SK_OUT16(IoC,
+					Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG),
+					(SK_U16)GET_PUT_IDX(pLETab));
+			} else {
+				SK_OUT16(IoC,
+					Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG),
+					(SK_U16)GET_PUT_IDX(pLETab));
+			}
+
+			/* Update put index */
+			UPDATE_HWPUT_IDX(pLETab);
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("<== GiveRxBufferToHw()\n"));
+} /* GiveRxBufferToHw */
+
+/***********************************************************************
+ *
+ *	FillReceiveTableYukon2 - map any waiting RX buffers to HW
+ *
+ * Description:
+ *	If the list element table contains more empty elements than
+ *	specified this function tries to refill them.
+ *
+ * Notes:
+ *       This function can run only once per port in a system at one time.
+ *
+ * Returns: N/A
+ */
+void FillReceiveTableYukon2(
+SK_AC   *pAC,   /* pointer to adapter control context */
+SK_IOC   IoC,   /* I/O control context                */
+int      Port)  /* port index of RX                   */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port));
+
+	if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >
+		pAC->MaxUnusedRxLeWorking) {
+
+		/*
+		** Give alle waiting receive buffers down
+		** The queue holds all RX packets that
+		** need a fresh allocation of the sk_buff.
+		*/
+		if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("Waiting queue is not empty -> give it to HW"));
+			GiveRxBufferToHw(pAC, IoC, Port, NULL);
+		}
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("<== FillReceiveTableYukon2 ()\n"));
+} /* FillReceiveTableYukon2 */
+
+
+/******************************************************************************
+ *
+ *
+ *	HandleReceives - will pass any ready RX packet to kernel
+ *
+ * Description:
+ *	This functions handles a received packet. It checks wether it is
+ *	valid, updates the receive list element table and gives the receive
+ *	buffer to Linux
+ *
+ * Notes:
+ *	This function can run only once per port at one time in the system.
+ *
+ * Returns: N/A
+ */
+static SK_BOOL HandleReceives(
+SK_AC  *pAC,          /* adapter control context                     */
+int     Port,         /* port on which a packet has been received    */
+SK_U16  FrameLength,  /* number of bytes which was actually received */
+SK_U32  FrameStatus,  /* MAC frame status word                       */
+SK_U16  Tcp1,         /* first hw checksum                           */
+SK_U16  Tcp2,         /* second hw checksum                          */
+SK_U32  Tist,         /* timestamp                                   */
+SK_U16  Vlan,         /* Vlan Id                                     */
+SK_U32  RssHash       /* RSS hash value                              */
+#ifdef SK_EXTREME
+, SK_U32  ExtremeCsumResult
+#endif
+)
+{
+	SK_PACKET       *pSkPacket;
+	SK_LE_TABLE     *pLETab;
+	struct sk_buff  *pMsg;       /* ptr to message holding frame */
+#ifdef __ia64__
+	struct sk_buff  *pNewMsg;    /* used when IP aligning        */
+#endif
+	SK_BOOL         IsGoodPkt;
+	SK_I16          LenToFree;   /* must be signed integer       */
+	unsigned long   Flags;       /* for spin lock                */
+	unsigned short  Type;
+	int             IpFrameLength;
+	int             HeaderLength;
+	int             Result;
+	SK_U16          HighVal;
+	SK_BOOL         CheckBcMc = SK_FALSE;
+#ifdef Y2_SYNC_CHECK
+	SK_U16          MyTcp;
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("==> HandleReceives (Port %c)\n", 'A' + Port));
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_521)) {
+		HighVal = (SK_U16)(((FrameStatus) & GMR_FS_LEN_MSK) >> GMR_FS_LEN_SHIFT);
+
+		if (FrameStatus == 0x7ffc0001) {
+			FrameStatus = 0;
+		}
+		else if (HighVal != FrameLength) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+				("521: We take pkt len %x stat: %x\n", FrameLength, FrameStatus));
+
+			/*
+			** Try to recover the status word. The multicast and broadcast bits
+			** from status word are set when we have a valid packet header.
+			*/
+			FrameStatus = 0;
+
+			/* Set the ReceiveOK bit. */
+			FrameStatus |= GMR_FS_RX_OK;
+
+			/* Set now the length into the status word */
+			FrameStatus |= (FrameLength << GMR_FS_LEN_SHIFT);
+
+			/* Insure that bit 31 is reset */
+			FrameStatus &= ~GMR_FS_LKUP_BIT2;
+			CheckBcMc = SK_TRUE;
+		}
+	}
+
+	/*
+	** Check whether we want to receive this packet
+	*/
+	SK_Y2_RXSTAT_CHECK_PKT(FrameLength, FrameStatus, IsGoodPkt);
+
+	/*
+	** Take first receive buffer out of working queue
+	*/
+	POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
+	if (pSkPacket == NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_ERROR,
+			("Packet not available. NULL pointer.\n"));
+		return(SK_TRUE);
+	}
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
+		NbrRxBuffersInHW--;
+	}
+
+	/*
+	** Verify the received length of the frame! Note that having
+	** multiple RxBuffers being aware of one single receive packet
+	** (one packet spread over multiple RxBuffers) is not supported
+	** by this driver!
+	*/
+	if ((FrameLength > pAC->RxPort[Port].RxBufSize) ||
+		(FrameLength > (SK_U16) pSkPacket->PacketLen)) {
+		IsGoodPkt = SK_FALSE;
+	}
+
+	/*
+	** Initialize vars for selected port
+	*/
+	pLETab = &pAC->RxPort[Port].RxLET;
+
+	/*
+	** Reset own bit in LE's between old and new Done index
+	** This is not really necessary but makes debugging easier
+	*/
+	CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
+
+	/*
+	** Free the list elements for new Rx buffers
+	*/
+	SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
+	pMsg = pSkPacket->pMBuf;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("Received frame of length %d on port %d\n",FrameLength, Port));
+
+	if (!IsGoodPkt) {
+		/*
+		** release the DMA mapping
+		*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
+		pci_dma_sync_single(pAC->PciDev,
+				(dma_addr_t) pSkPacket->pFrag->pPhys,
+				pSkPacket->pFrag->FragLen,
+				PCI_DMA_FROMDEVICE);
+
+#else
+		pci_dma_sync_single_for_cpu(pAC->PciDev,
+				(dma_addr_t) pSkPacket->pFrag->pPhys,
+				pSkPacket->pFrag->FragLen,
+				PCI_DMA_FROMDEVICE);
+#endif
+
+		DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
+		PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+			("<== HandleReceives (Port %c)\n", 'A' + Port));
+
+		/*
+		** Sanity check for RxBuffer overruns...
+		*/
+		LenToFree = FrameLength - (pSkPacket->pFrag->FragLen);
+		while (LenToFree > 0) {
+			POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
+			if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
+				NbrRxBuffersInHW--;
+			}
+			CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
+			SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
+			pci_dma_sync_single(pAC->PciDev,
+					(dma_addr_t) pSkPacket->pFrag->pPhys,
+					pSkPacket->pFrag->FragLen,
+					PCI_DMA_FROMDEVICE);
+#else
+			pci_dma_sync_single_for_device(pAC->PciDev,
+					(dma_addr_t) pSkPacket->pFrag->pPhys,
+					pSkPacket->pFrag->FragLen,
+					PCI_DMA_FROMDEVICE);
+#endif
+
+			DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
+			PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
+			LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen));
+
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+				("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port));
+		}
+		return(SK_TRUE);
+	} else {
+		/*
+		** Release the DMA mapping
+		*/
+		pci_unmap_single(pAC->PciDev,
+				 pSkPacket->pFrag->pPhys,
+				 pAC->RxPort[Port].RxBufSize,
+				 PCI_DMA_FROMDEVICE);
+
+		skb_put(pMsg, FrameLength);		/* set message len */
+		pMsg->ip_summed = CHECKSUM_NONE;	/* initial default */
+
+#ifdef Y2_SYNC_CHECK
+		pAC->FramesWithoutSyncCheck++;
+		if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) {
+			if ((Tcp1 != 1) || (Tcp2 != 0)) {
+				pAC->FramesWithoutSyncCheck = 0;
+				MyTcp = (SK_U16) SkCsCalculateChecksum(
+						&pMsg->data[14],
+						FrameLength - 14);
+				if (MyTcp != Tcp1) {
+					/* Queue port reset event */
+					SkLocalEventQueue(pAC, SKGE_DRV,
+					SK_DRV_RECOVER,Port,-1,SK_FALSE);
+				}
+			}
+		}
+#endif
+
+		if (pAC->RxPort[Port].UseRxCsum) {
+#ifdef SK_EXTREME
+			if (HW_IS_EXT_LE_FORMAT(pAC)) {
+				/* Checksum calculation for Yukon Extreme */
+				pMsg->ip_summed = CHECKSUM_NONE;
+				if (CSS_IS_IPV4(ExtremeCsumResult) && CSS_IPV4_CSUM_OK(ExtremeCsumResult)) {
+					/* TCP && UDP checksum check */
+					if ((CSS_IS_TCP(ExtremeCsumResult)) || (CSS_IS_UDP(ExtremeCsumResult))) {
+						if (CSS_TCPUDP_CSUM_OK(ExtremeCsumResult))
+							pMsg->ip_summed = CHECKSUM_UNNECESSARY;
+					}
+				}
+			} else {
+#endif
+				Type = ntohs(*((short*)&pMsg->data[12]));
+				if (Type == 0x800) {
+					*((char *)&(IpFrameLength)) = pMsg->data[16];
+					*(((char *)&(IpFrameLength))+1) = pMsg->data[17];
+					IpFrameLength = ntohs(IpFrameLength);
+					HeaderLength  = FrameLength - IpFrameLength;
+					if (HeaderLength == 0xe) {
+						Result =
+						    SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port, IpFrameLength);
+						if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
+						    (Result == SKCS_STATUS_IP_CSUM_OK)  ||
+						    (Result == SKCS_STATUS_TCP_CSUM_OK) ||
+						    (Result == SKCS_STATUS_UDP_CSUM_OK)) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
+							pMsg->ip_summed = CHECKSUM_COMPLETE;
+							pMsg->csum = Tcp1 & 0xffff;
+#else
+							pMsg->ip_summed = CHECKSUM_UNNECESSARY;
+#endif
+						} else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR)    ||
+						           (Result == SKCS_STATUS_UDP_CSUM_ERROR)    ||
+						           (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
+						           (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
+						           (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
+							SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+								SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+								("skge: CRC error. Frame dropped!\n"));
+							DEV_KFREE_SKB_ANY(pMsg);
+							PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
+							SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS,
+								("<==HandleReceives(Port %c)\n",'A'+Port));
+							return(SK_TRUE);
+						} else {
+							pMsg->ip_summed = CHECKSUM_NONE;
+						}
+					} /* end if (HeaderLength == valid) */
+				} /* end if (Type == 0x800) -> IP frame */
+#ifdef SK_EXTREME
+			} /* if (HW_IS_EXT_LE_FORMAT(pAC)) */
+#endif
+		} /* end if (pRxPort->UseRxCsum) */
+
+		if (CheckBcMc == SK_TRUE) {
+
+			/* Check if this is a broadcast packet */
+			if (SK_ADDR_EQUAL(pMsg->data, "\xFF\xFF\xFF\xFF\xFF\xFF")) {
+
+				/* Broadcast packet */
+				FrameStatus |= GMR_FS_BC;
+			}
+			else if (pMsg->data[0] & 0x01) {
+
+				/* Multicast packet */
+				FrameStatus |= GMR_FS_MC;
+			}
+		}
+
+		/* Send up only frames from active port */
+		if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS,("U"));
+#ifdef xDEBUG
+			DumpMsg(pMsg, "Rx");
+#endif
+			SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
+				FrameLength, Port);
+#ifdef __ia64__
+			pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
+			skb_reserve(pNewMsg, 2); /* to align IP */
+			SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
+			pNewMsg->ip_summed = pMsg->ip_summed;
+			skb_put(pNewMsg, pMsg->len);
+			DEV_KFREE_SKB_ANY(pMsg);
+			pMsg = pNewMsg;
+#endif
+			pMsg->dev = pAC->dev[Port];
+			pMsg->protocol = eth_type_trans(pMsg,
+				pAC->dev[Port]);
+
+#ifdef USE_SK_RSS_SUPPORT
+			pMsg->rxhash = le32_to_cpu(pAC->StatusLETable.Bmu.Stat.RssHashValue);
+#endif
+
+#ifdef CONFIG_SK98LIN_NAPI
+			netif_receive_skb(pMsg);
+#else
+			netif_rx(pMsg);
+#endif
+			pAC->dev[Port]->last_rx = jiffies;
+		} else { /* drop frame */
+			SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
+				SK_DBGCAT_DRV_RX_PROGRESS,("D"));
+			DEV_KFREE_SKB_ANY(pMsg);
+		}
+		PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
+	} /* end if-else (IsGoodPkt) */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("<== HandleReceives (Port %c)\n", 'A' + Port));
+	return(SK_TRUE);
+
+} /* HandleReceives */
+
+
+/***********************************************************************
+ *
+ * 	CheckForSendComplete - Frees any freeable Tx bufffer
+ *
+ * Description:
+ *	This function checks the queues of a port for completed send
+ *	packets and returns these packets back to the OS.
+ *
+ * Notes:
+ *	This function can run simultaneously for both ports if
+ *	the OS function OSReturnPacket() can handle this,
+ *
+ *	Such a send complete does not mean, that the packet is really
+ *	out on the wire. We just know that the adapter has copied it
+ *	into its internal memory and the buffer in the systems memory
+ *	is no longer needed.
+ *
+ * Returns: N/A
+ */
+static void CheckForSendComplete(
+SK_AC         *pAC,     /* pointer to adapter control context  */
+SK_IOC         IoC,     /* I/O control context                 */
+int            Port,    /* port index                          */
+SK_PKT_QUEUE  *pPQ,     /* tx working packet queue to check    */
+SK_LE_TABLE   *pLETab,  /* corresponding list element table    */
+unsigned int   Done)    /* done index reported for this LET    */
+{
+	SK_PACKET       *pSkPacket;
+	SK_PKT_QUEUE     SendCmplPktQ = { NULL, NULL, SPIN_LOCK_UNLOCKED };
+	SK_BOOL          DoWakeQueue  = SK_FALSE;
+	unsigned long    Flags;
+	unsigned         Put;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("==> CheckForSendComplete(Port %c)\n", 'A' + Port));
+
+	/*
+	** Reset own bit in LE's between old and new Done index
+	** This is not really necessairy but makes debugging easier
+	*/
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("Clear Own Bits in TxTable from %d to %d\n",
+		pLETab->Done, (Done == 0) ?
+		NUM_LE_IN_TABLE(pLETab) :
+		(Done - 1)));
+
+	spin_lock_irqsave(&(pPQ->QueueLock), Flags);
+
+	CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done);
+
+	Put = GET_PUT_IDX(pLETab);
+
+	/*
+	** Check whether some packets have been completed
+	*/
+	PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
+	while (pSkPacket != NULL) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("Check Completion of Tx packet %p\n", pSkPacket));
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+			("Put %d NewDone %d NextLe of Packet %d\n", Put, Done,
+			pSkPacket->NextLE));
+
+		if ((Put > Done) &&
+			((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) {
+			PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("Packet finished (a)\n"));
+		} else if ((Done > Put) &&
+			(pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) {
+			PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("Packet finished (b)\n"));
+		} else if ((Done == NUMBER_OF_TX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) {
+			PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("Packet finished (b)\n"));
+			DoWakeQueue = SK_TRUE;
+		} else if (Done == Put) {
+			/* all packets have been sent */
+			PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("Packet finished (c)\n"));
+		} else {
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+				("Packet not yet finished\n"));
+			PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket);
+			break;
+		}
+		PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
+	}
+	spin_unlock_irqrestore(&(pPQ->QueueLock), Flags);
+
+	/*
+	** Set new done index in list element table
+	*/
+	SET_DONE_INDEX(pLETab, Done);
+
+	/*
+	** All TX packets that are send complete should be added to
+	** the free queue again for new sents to come
+	*/
+	pSkPacket = SendCmplPktQ.pHead;
+	while (pSkPacket != NULL) {
+		while (pSkPacket->pFrag != NULL) {
+			pci_unmap_page(pAC->PciDev,
+					(dma_addr_t) pSkPacket->pFrag->pPhys,
+					pSkPacket->pFrag->FragLen,
+					PCI_DMA_FROMDEVICE);
+			pSkPacket->pFrag = pSkPacket->pFrag->pNext;
+		}
+
+		DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
+		pSkPacket->pMBuf	= NULL;
+		pSkPacket = pSkPacket->pNext; /* get next packet */
+	}
+
+	/*
+	** Append the available TX packets back to free queue
+	*/
+	if (SendCmplPktQ.pHead != NULL) {
+		spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags);
+		if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) {
+			pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead;
+			pAC->TxPort[Port][0].TxQ_free.pTail        = SendCmplPktQ.pTail;
+			if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) {
+				netif_wake_queue(pAC->dev[Port]);
+			}
+		} else {
+			pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead;
+			pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
+			netif_wake_queue(pAC->dev[Port]);
+		}
+		if (Done == Put) {
+			netif_wake_queue(pAC->dev[Port]);
+		}
+		if (DoWakeQueue) {
+			netif_wake_queue(pAC->dev[Port]);
+			DoWakeQueue = SK_FALSE;
+		}
+		spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("<== CheckForSendComplete()\n"));
+
+	return;
+} /* CheckForSendComplete */
+
+/*****************************************************************************
+ *
+ *	UnmapAndFreeTxPktBuffer
+ *
+ * Description:
+ *      This function free any allocated space of receive buffers
+ *
+ * Arguments:
+ *      pAC - A pointer to the adapter context struct.
+ *
+ */
+static void UnmapAndFreeTxPktBuffer(
+SK_AC       *pAC,       /* pointer to adapter context             */
+SK_PACKET   *pSkPacket,	/* pointer to port struct of ring to fill */
+int          TxPort)    /* TX port index                          */
+{
+	SK_FRAG	 *pFrag = pSkPacket->pFrag;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("--> UnmapAndFreeTxPktBuffer\n"));
+
+	while (pFrag != NULL) {
+		pci_unmap_page(pAC->PciDev,
+				(dma_addr_t) pFrag->pPhys,
+				pFrag->FragLen,
+				PCI_DMA_FROMDEVICE);
+		pFrag = pFrag->pNext;
+	}
+
+	DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
+	pSkPacket->pMBuf	= NULL;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
+		("<-- UnmapAndFreeTxPktBuffer\n"));
+}
+
+/*****************************************************************************
+ *
+ * 	HandleStatusLEs
+ *
+ * Description:
+ *	This function checks for any new status LEs that may have been
+  *	received. Those status LEs may either be Rx or Tx ones.
+ *
+ * Returns:	N/A
+ */
+static SK_BOOL HandleStatusLEs(
+#ifdef CONFIG_SK98LIN_NAPI
+SK_AC *pAC,       /* pointer to adapter context   */
+int   *WorkDone,  /* Done counter needed for NAPI */
+int    WorkToDo)  /* ToDo counter for NAPI        */
+#else
+SK_AC *pAC)       /* pointer to adapter context   */
+#endif
+{
+	int       DoneTxA[SK_MAX_MACS];
+	int       DoneTxS[SK_MAX_MACS];
+	int       Port;
+	SK_BOOL   handledStatLE = SK_FALSE;
+	SK_BOOL   NewDone       = SK_FALSE;
+	SK_HWLE  *pLE;
+	SK_U16    HighVal;
+	SK_U32    LowVal;
+	SK_U32    IntSrc;
+	SK_U8     OpCode;
+#ifdef USE_TIST_FOR_RESET
+	int       i;
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+		("==> HandleStatusLEs\n"));
+
+	do {
+		if (OWN_OF_FIRST_LE(&pAC->StatusLETable) != HW_OWNER)
+			break;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+			("Check next Own Bit of ST-LE[%d]: 0x%li \n",
+			(pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable),
+			 OWN_OF_FIRST_LE(&pAC->StatusLETable)));
+
+		while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) {
+			GET_ST_LE(pLE, &pAC->StatusLETable);
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+				("Working on finished status LE[%d]:\n",
+				GET_DONE_INDEX(&pAC->StatusLETable)));
+#if 0
+			SK_DBG_DUMP_ST_LE(pLE);
+#endif
+			handledStatLE = SK_TRUE;
+			OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
+			Port = STLE_GET_LINK(pLE);
+
+#ifdef USE_TIST_FOR_RESET
+			if (!HW_IS_EXT_LE_FORMAT(pAC) && SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
+				/* do we just have a tist LE ? */
+				if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {
+					for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
+						if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) {
+							/* if a port is waiting for any tist it is done */
+							SK_CLR_STATE_FOR_PORT(pAC, i);
+							SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+								("Got any Tist on port %c (now 0x%X!!!)\n",
+								'A' + i, pAC->AdapterResetState));
+						}
+						if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) {
+							Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal);
+							if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) ||
+								(pAC->MinTistLo < LowVal)) {
+								/* time is up now */
+								SK_CLR_STATE_FOR_PORT(pAC, i);
+								SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+									("Got expected Tist on Port %c (now 0x%X)!!!\n",
+									'A' + i, pAC->AdapterResetState));
+#ifdef Y2_SYNC_CHECK
+								pAC->FramesWithoutSyncCheck =
+								Y2_RESYNC_WATERMARK;
+#endif
+							} else {
+								SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+									("Got Tist %l:%l on Port %c but still waiting\n",
+									pAC->GIni.GITimeStampCnt, pAC->MinTistLo,
+									'A' + i));
+							}
+						}
+					}
+#ifndef Y2_RECOVERY
+					if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
+						/* nobody needs tist anymore - turn it off */
+						SK_Y2_TIST_LE_DIS(pAC->IoBase);
+						SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+						("Turn off Tist !!!\n"));
+					}
+#endif
+				} else if (OpCode == OP_TXINDEXLE) {
+					/*
+					 * change OpCode to notify the folowing code
+					 * to ignore the done index from this LE
+					 * unfortunately tist LEs will be generated only
+					 * for RxStat LEs
+					 * so in order to get a safe Done index for a
+					 * port currently waiting for a tist we have to
+					 * get the done index directly from the BMU
+					 */
+					OpCode = OP_MOD_TXINDEX;
+					SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+						("Mark unusable TX_INDEX LE!!!\n"));
+				} else {
+					if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) {
+						SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+							("Ignore LE 0x%X on Port %c!!!\n",
+							OpCode, 'A' + Port));
+						OpCode = OP_MOD_LE;
+#ifdef Y2_LE_CHECK
+						/* mark entries invalid */
+						pAC->LastOpc = 0xFF;
+						pAC->LastPort = 3;
+#endif
+					}
+				}
+			} /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */
+#endif
+
+#ifdef Y2_LE_CHECK
+			if (!HW_IS_EXT_LE_FORMAT(pAC) && pAC->LastOpc != 0xFF) {
+				/* last opc is valid
+				 * check if current opcode follows last opcode
+				 */
+				if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) ||
+				    (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) ||
+				    ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) {
+
+					/* opcode sequence broken
+					 * current LE is invalid
+					 */
+
+					if (pAC->LastOpc == OP_RXTIMESTAMP) {
+						/* force invalid checksum */
+						pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1;
+						pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0;
+						OpCode = pAC->LastOpc = OP_RXCHKS;
+						Port = pAC->LastPort;
+					} else if (pAC->LastOpc == OP_RXCHKS) {
+						/* force invalid frame */
+						Port = pAC->LastPort;
+						pLE->St.Stat.BufLen = 64;
+						pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR;
+						OpCode = pAC->LastOpc = OP_RXSTAT;
+#ifdef Y2_SYNC_CHECK
+						/* force rx sync check */
+						pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK;
+#endif
+					} else if (pAC->LastOpc == OP_RXSTAT) {
+						/* create dont care tist */
+						pLE->St.StUn.StRxTimeStamp = 0;
+						OpCode = pAC->LastOpc = OP_RXTIMESTAMP;
+						/* dont know the port yet */
+					} else {
+#ifdef DEBUG
+						SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+							("Unknown LastOpc %X for Timestamp on port %c.\n",
+							pAC->LastOpc, Port));
+#endif
+					}
+				}
+			}
+#endif
+
+			switch (OpCode) {
+			case OP_RXSTAT:
+#ifdef Y2_RECOVERY
+				pAC->LastOpc = OP_RXSTAT;
+#endif
+				/*
+				** This is always the last Status LE belonging
+				** to a received packet -> handle it...
+				*/
+
+				HandleReceives(
+					pAC,
+#ifdef SK_EXTREME
+					CSS_GET_PORT(Port),
+#else
+					Port,
+#endif
+					STLE_GET_LEN(pLE),
+					STLE_GET_FRSTATUS(pLE),
+					pAC->StatusLETable.Bmu.Stat.TcpSum1,
+					pAC->StatusLETable.Bmu.Stat.TcpSum2,
+					pAC->StatusLETable.Bmu.Stat.RxTimeStamp,
+					pAC->StatusLETable.Bmu.Stat.VlanId,
+					pAC->StatusLETable.Bmu.Stat.RssHashValue
+#ifdef SK_EXTREME
+					,Port
+#endif
+				);
+#ifdef CONFIG_SK98LIN_NAPI
+				if (*WorkDone >= WorkToDo) {
+					break;
+				}
+				(*WorkDone)++;
+#endif
+				break;
+			case OP_RXVLAN:
+				/* this value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
+				break;
+			case OP_RXTIMEVLAN:
+				/* this value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
+				/* fall through */
+			case OP_RXTIMESTAMP:
+				/* this value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE);
+#ifdef Y2_RECOVERY
+				pAC->LastOpc = OP_RXTIMESTAMP;
+				pAC->LastPort = Port;
+#endif
+				break;
+			case OP_RXCHKSVLAN:
+				/* this value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
+				/* fall through */
+			case OP_RXCHKS:
+				/* this value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE);
+				pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE);
+#ifdef Y2_RECOVERY
+				pAC->LastPort = Port;
+				pAC->LastOpc = OP_RXCHKS;
+#endif
+				break;
+			case OP_RSS_HASH:
+#ifdef USE_SK_RSS_SUPPORT
+				/* This value will be used for next RXSTAT */
+				pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE);
+#endif
+				break;
+			case OP_TXINDEXLE:
+				/*
+				** :;:; TODO
+				** it would be possible to check for which queues
+				** the index has been changed and call
+				** CheckForSendComplete() only for such queues
+				*/
+				STLE_GET_DONE_IDX(pLE,LowVal,HighVal);
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+					("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal));
+
+				/*
+				** It would be possible to check whether we really
+				** need the values for second port or sync queue,
+				** but I think checking whether we need them is
+				** more expensive than the calculation
+				*/
+				DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal);
+				DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal);
+				DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal);
+				DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal);
+
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+					("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n",
+					DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1]));
+
+				NewDone = SK_TRUE;
+				break;
+#ifdef USE_TIST_FOR_RESET
+			case OP_MOD_TXINDEX:
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+					("OP_MOD_TXINDEX\n"));
+				SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]);
+				if (pAC->GIni.GIMacsFound > 1) {
+					SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]);
+				}
+				NewDone = SK_TRUE;
+				break;
+			case OP_MOD_LE:
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
+				("Ignore marked LE on port in Reset\n"));
+				break;
+#endif
+			default:
+				/*
+				** Have to handle the illegal Opcode in Status LE
+				*/
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+					("Unexpected OpCode\n"));
+				break;
+			}
+
+#ifdef Y2_RECOVERY
+			OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
+			STLE_SET_OPC(pLE, OpCode);
+#else
+			/*
+			** Reset own bit we have to do this in order to detect a overflow
+			*/
+			STLE_SET_OPC(pLE, SW_OWNER);
+#endif
+		} /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */
+
+		/*
+		** Now handle any new transmit complete
+		*/
+		if (NewDone) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+				("Done Index for Tx BMU has been changed\n"));
+			for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
+				/*
+				** Do we have a new Done idx ?
+				*/
+				if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) {
+					SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+						("Check TxA%d\n", Port + 1));
+					CheckForSendComplete(pAC, pAC->IoBase, Port,
+						&(pAC->TxPort[Port][0].TxAQ_working),
+						&pAC->TxPort[Port][0].TxALET,
+						DoneTxA[Port]);
+				} else {
+					SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+						("No changes for TxA%d\n", Port + 1));
+				}
+#ifdef USE_SYNC_TX_QUEUE
+				if (HW_SYNC_TX_SUPPORTED(pAC)) {
+					/*
+					** Do we have a new Done idx ?
+					*/
+					if (DoneTxS[Port] !=
+						GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) {
+						SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+							SK_DBGCAT_DRV_INT_SRC,
+							("Check TxS%d\n", Port));
+						CheckForSendComplete(pAC, pAC->IoBase, Port,
+							&(pAC->TxPort[Port][0].TxSQ_working),
+							&pAC->TxPort[Port][0].TxSLET,
+							DoneTxS[Port]);
+					} else {
+						SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+							SK_DBGCAT_DRV_INT_SRC,
+							("No changes for TxS%d\n", Port));
+					}
+				}
+#endif
+			}
+		}
+		NewDone = SK_FALSE;
+
+		/*
+		** Check whether we have to refill our RX table
+		*/
+		if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
+			if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) {
+				for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
+					SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+						("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
+					FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
+				}
+			}
+		} else {
+			for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
+				SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
+					("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
+				if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) {
+					FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
+				}
+			}
+		}
+#ifdef CONFIG_SK98LIN_NAPI
+		if (*WorkDone >= WorkToDo) {
+			break;
+		}
+#endif
+	} while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER);
+
+	/*
+	** Clear status BMU
+	*/
+	if (handledStatLE) {
+		SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ);
+
+		/* Reread interrupt source */
+		SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
+	}
+
+	return(handledStatLE);
+} /* HandleStatusLEs */
+
+/*****************************************************************************
+ *
+ *	AllocateAndInitLETables - allocate memory for the LETable and init
+ *
+ * Description:
+ *	This function will allocate space for the LETable and will also
+ *	initialize them. The size of the tables must have been specified
+ *	before.
+ *
+ * Arguments:
+ *	pAC - A pointer to the adapter context struct.
+ *
+ * Returns:
+ *	SK_TRUE  - all LETables initialized
+ *	SK_FALSE - failed
+ */
+static SK_BOOL AllocateAndInitLETables(
+SK_AC *pAC)  /* pointer to adapter context */
+{
+	char           *pVirtMemAddr;
+	char           *pAddr;
+	dma_addr_t     pPhysMemAddr = 0;
+	dma_addr_t     pPhysOrgMemAddr = 0;
+	SK_U32         CurrMac;
+	unsigned       Size;
+	unsigned       Aligned;
+	unsigned       Alignment;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("==> AllocateAndInitLETables()\n"));
+
+	/*
+	** Determine how much memory we need with respect to alignment
+	*/
+	Alignment = (SK_U32) LE_TAB_SIZE(NUMBER_OF_ST_LE);
+	Size = 0;
+	for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
+		SK_ALIGN_SIZE(LE_TAB_SIZE(NUMBER_OF_RX_LE), Alignment, Aligned);
+		Size += Aligned;
+		SK_ALIGN_SIZE(LE_TAB_SIZE(NUMBER_OF_TX_LE), Alignment, Aligned);
+		Size += Aligned;
+		SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
+		Size += Aligned;
+	}
+	SK_ALIGN_SIZE(LE_TAB_SIZE(NUMBER_OF_ST_LE), Alignment, Aligned);
+	Size += Aligned;
+	Size += Alignment;
+	pAC->SizeOfAlignedLETables = Size;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+			("Need %08x bytes in total\n", Size));
+
+	/*
+	** Allocate the memory
+	*/
+	pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr);
+	pAC->pVirtMemAddr = pVirtMemAddr;
+
+	if (pVirtMemAddr == NULL) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
+			SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
+			("AllocateAndInitLETables: kernel malloc failed!\n"));
+		return (SK_FALSE);
+	}
+
+	/*
+	** Initialize the memory
+	*/
+	SK_MEMSET(pVirtMemAddr, 0, Size);
+	pPhysOrgMemAddr = pPhysMemAddr;
+#ifdef CONFIG_64BIT
+	pAddr = (void *) pPhysMemAddr;
+	ALIGN_ADDR(pAddr, Alignment); /* Macro defined in skgew.h */
+	pPhysMemAddr = (dma_addr_t) pAddr;
+#else
+	pAddr = (void *) (SK_U32) pPhysMemAddr;
+	ALIGN_ADDR(pAddr, Alignment); /* Macro defined in skgew.h */
+	pPhysMemAddr = (dma_addr_t) (SK_U32) pAddr;
+#endif
+	pVirtMemAddr += pPhysMemAddr - pPhysOrgMemAddr;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("Virtual address of LETab is %8p!\n", pVirtMemAddr));
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr));
+
+	for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+			("RxLeTable for Port %c", 'A' + CurrMac));
+		SkGeY2InitSingleLETable(
+			pAC,
+			&pAC->RxPort[CurrMac].RxLET,
+			NUMBER_OF_RX_LE,
+			pVirtMemAddr,
+			(SK_U32) (pPhysMemAddr & 0xffffffff),
+			(SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
+
+		SK_ALIGN_SIZE(LE_TAB_SIZE(NUMBER_OF_RX_LE), Alignment, Aligned);
+		pVirtMemAddr += Aligned;
+		pPhysMemAddr += Aligned;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+			("TxALeTable for Port %c", 'A' + CurrMac));
+		SkGeY2InitSingleLETable(
+			pAC,
+			&pAC->TxPort[CurrMac][0].TxALET,
+			NUMBER_OF_TX_LE,
+			pVirtMemAddr,
+			(SK_U32) (pPhysMemAddr & 0xffffffff),
+			(SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
+
+		SK_ALIGN_SIZE(LE_TAB_SIZE(NUMBER_OF_TX_LE), Alignment, Aligned);
+		pVirtMemAddr += Aligned;
+		pPhysMemAddr += Aligned;
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+			("TxSLeTable for Port %c", 'A' + CurrMac));
+		SkGeY2InitSingleLETable(
+			pAC,
+			&pAC->TxPort[CurrMac][0].TxSLET,
+			TXS_MAX_LE,
+			pVirtMemAddr,
+			(SK_U32) (pPhysMemAddr & 0xffffffff),
+			(SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
+
+		SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
+		pVirtMemAddr += Aligned;
+		pPhysMemAddr += Aligned;
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable"));
+
+	SkGeY2InitSingleLETable(
+		pAC,
+		&pAC->StatusLETable,
+		NUMBER_OF_ST_LE,
+		pVirtMemAddr,
+		(SK_U32) (pPhysMemAddr & 0xffffffff),
+		(SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("<== AllocateAndInitLETables(OK)\n"));
+	return(SK_TRUE);
+} /* AllocateAndInitLETables */
+
+/*****************************************************************************
+ *
+ *	AllocatePacketBuffersYukon2 - allocate packet and fragment buffers
+ *
+ * Description:
+ *      This function will allocate space for the packets and fragments
+ *
+ * Arguments:
+ *      pAC - A pointer to the adapter context struct.
+ *
+ * Returns:
+ *      SK_TRUE  - Memory was allocated correctly
+ *      SK_FALSE - An error occured
+ */
+static SK_BOOL AllocatePacketBuffersYukon2(
+SK_AC *pAC)  /* pointer to adapter context */
+{
+	SK_PACKET       *pRxPacket;
+	SK_PACKET       *pTxPacket;
+	SK_U32           CurrBuff;
+	SK_U32           CurrMac;
+	unsigned long    Flags; /* needed for POP/PUSH functions */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("==> AllocatePacketBuffersYukon2()"));
+
+	for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
+		/*
+		** Allocate RX packet space, initialize the packets and
+		** add them to the RX waiting queue. Waiting queue means
+		** that packet and fragment are initialized, but no sk_buff
+		** has been assigned to it yet.
+		*/
+		pAC->RxPort[CurrMac].ReceivePacketTable =
+			kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
+
+		if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
+				("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac));
+			break;
+		} else {
+			SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0,
+				(RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
+
+			pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable;
+
+			for (CurrBuff=0;CurrBuff<RX_MAX_NBR_BUFFERS;CurrBuff++) {
+				pRxPacket->pFrag = &(pRxPacket->FragArray[0]);
+				pRxPacket->NumFrags = 1;
+				PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket);
+				pRxPacket++;
+			}
+		}
+
+		/*
+		** Allocate TX packet space, initialize the packets and
+		** add them to the TX free queue. Free queue means that
+		** packet is available and initialized, but no fragment
+		** has been assigned to it. (Must be done at TX side)
+		*/
+		pAC->TxPort[CurrMac][0].TransmitPacketTable =
+			kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
+
+		if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) {
+			SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
+				("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac));
+			kfree(pAC->RxPort[CurrMac].ReceivePacketTable);
+			return(SK_FALSE);
+		} else {
+			SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0,
+				(TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
+
+			pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable;
+
+			for (CurrBuff=0;CurrBuff<TX_MAX_NBR_BUFFERS;CurrBuff++) {
+				PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[CurrMac][0].TxQ_free, pTxPacket);
+				pTxPacket++;
+			}
+		}
+	} /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
+		("<== AllocatePacketBuffersYukon2 (OK)\n"));
+	return(SK_TRUE);
+
+} /* AllocatePacketBuffersYukon2 */
+
+/*****************************************************************************
+ *
+ *	FreeLETables - release allocated memory of LETables
+ *
+ * Description:
+ *      This function will free all resources of the LETables
+ *
+ * Arguments:
+ *      pAC - A pointer to the adapter context struct.
+ *
+ * Returns: N/A
+ */
+static void FreeLETables(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	dma_addr_t	pPhysMemAddr;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> FreeLETables()\n"));
+
+	/*
+	** The RxLETable is the first of all LET.
+	** Therefore we can use its address for the input
+	** of the free function.
+	*/
+	pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) |
+			((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow));
+
+	/* free continuous memory */
+	pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables,
+			    pAC->pVirtMemAddr, pPhysMemAddr);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== FreeLETables()\n"));
+} /* FreeLETables */
+
+/*****************************************************************************
+ *
+ *	FreePacketBuffers - free's all packet buffers of an adapter
+ *
+ * Description:
+ *      This function will free all previously allocated memory of the
+ *	packet buffers.
+ *
+ * Arguments:
+ *      pAC - A pointer to the adapter context struct.
+ *
+ * Returns: N/A
+ */
+static void FreePacketBuffers(
+SK_AC *pAC)  /* pointer to adapter control context */
+{
+	int Port;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("==> FreePacketBuffers()\n"));
+
+	for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
+		kfree(pAC->RxPort[Port].ReceivePacketTable);
+		kfree(pAC->TxPort[Port][0].TransmitPacketTable);
+	}
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
+		("<== FreePacketBuffers()\n"));
+} /* FreePacketBuffers */
+
+/*****************************************************************************
+ *
+ * 	AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment
+ *
+ * Description:
+ *	The function allocates a new receive buffer and assigns it to the
+ *	the passed receive packet/fragment
+ *
+ * Returns:
+ *	SK_TRUE - a buffer was allocated and assigned
+ *	SK_FALSE - a buffer could not be added
+ */
+static SK_BOOL AllocAndMapRxBuffer(
+SK_AC      *pAC,        /* pointer to the adapter control context */
+SK_PACKET  *pSkPacket,  /* pointer to packet that is to fill      */
+int         Port)       /* port the packet belongs to             */
+{
+	struct sk_buff *pMsgBlock;  /* pointer to a new message block  */
+	SK_U64          PhysAddr;   /* physical address of a rx buffer */
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("--> AllocAndMapRxBuffer (Port: %i)\n", Port));
+
+	pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC);
+	if (pMsgBlock == NULL) {
+		SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+			SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
+			("%s: Allocation of rx buffer failed !\n",
+			pAC->dev[Port]->name));
+		SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex);
+		return(SK_FALSE);
+	}
+	skb_reserve(pMsgBlock, 8);
+
+	PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
+		virt_to_page(pMsgBlock->data),
+		((unsigned long) pMsgBlock->data &
+		~PAGE_MASK),
+		pAC->RxPort[Port].RxBufSize,
+		PCI_DMA_FROMDEVICE);
+
+	pSkPacket->pFrag->pVirt   = pMsgBlock->data;
+	pSkPacket->pFrag->pPhys   = PhysAddr;
+	pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */
+	pSkPacket->pMBuf          = pMsgBlock;
+	pSkPacket->PacketLen      = pAC->RxPort[Port].RxBufSize;
+
+	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
+		("<-- AllocAndMapRxBuffer\n"));
+
+	return (SK_TRUE);
+} /* AllocAndMapRxBuffer */
+
+/*******************************************************************************
+ *
+ * End of file
+ *
+ ******************************************************************************/
diff -ruN linux/drivers/net/sk98lin/sky2le.c linux-new/drivers/net/sk98lin/sky2le.c
--- linux/drivers/net/sk98lin/sky2le.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sky2le.c	2011-05-16 06:45:54.000000000 -0700
@@ -0,0 +1,509 @@
+/*****************************************************************************
+ *
+ *	Name:		$Id: //Release/Yukon_1G/Shared/common/V6/sky2le.c#7 $
+ *	Project:	Gigabit Ethernet Adapters, Common Modules
+ *	Version:	$Revision: #7 $, $Change: 4376 $
+ *	Date:		$DateTime: 2010/11/10 18:08:48 $
+ *	Purpose:	Functions for handling List Element Tables
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+/*****************************************************************************
+ *
+ * Description:
+ *
+ * This module contains the code necessary for handling List Elements.
+ *
+ * Supported Gigabit Ethernet Chipsets:
+ *	Yukon-2 (PCI, PCI-X, PCI-Express)
+ *
+ * Include File Hierarchy:
+ *
+ *****************************************************************************/
+#include "h/skdrv1st.h"
+#include "h/skdrv2nd.h"
+
+/* defines *******************************************************************/
+/* typedefs ******************************************************************/
+/* global variables **********************************************************/
+/* local variables ***********************************************************/
+/* function prototypes *******************************************************/
+
+/*****************************************************************************
+ *
+ * SkGeY2InitSingleLETable() - Initialize a List Element Table
+ *
+ * Description:
+ *	This function will initialize the selected list element table.
+ *	Should be called once during DriverInit. No InitLevel required.
+ *
+ * Arguments:
+ *	pAC			- pointer to the adapter context
+ *	pLETab		- pointer to list element table structure
+ *	NumLE		- number of list elements in this table
+ *	pVMem		- virtual address of memory allocated for this LE table
+ *	PMemLowAddr	- physical address of memory to be used for the LE table
+ *	PMemHighAddr
+ *
+ * Returns:
+ *	nothing
+ */
+void SkGeY2InitSingleLETable(
+SK_AC	*pAC,			/* pointer to adapter context */
+SK_LE_TABLE	*pLETab,	/* pointer to list element table to be initialized */
+unsigned int NumLE,		/* number of list elements to be filled in tab */
+void	*pVMem,			/* virtual address of memory used for list elements */
+SK_U32	PMemLowAddr,	/* physical address of memory used for LE */
+SK_U32	PMemHighAddr)
+{
+	unsigned int i;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("==> SkGeY2InitSingleLETable()\n"));
+
+#ifdef DEBUG
+	if (NumLE != 2) {	/* not table for polling unit */
+		if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("ERROR: Illegal number of list elements %d\n", NumLE));
+		}
+	}
+#endif /* DEBUG */
+
+	/* special case: unused list element table */
+	if (NumLE == 0) {
+		PMemLowAddr = 0;
+		PMemHighAddr = 0;
+		pVMem = 0;
+	}
+
+	/*
+	 * in order to get the best possible performance,
+	 * the macros to access list elements use & instead of %
+	 * this requires the length of LE tables to be a power of 2
+	 */
+
+	/*
+	 * this code guarantees that we use the next power of 2 below the
+	 * value specified for NumLe - this way some LEs in the table may
+	 * not be used but the macros work correctly
+	 * this code does not check for bad values below 128 because in such a
+	 * case we cannot do anything here
+	 */
+
+	if (NumLE != 2 && NumLE != 0) {
+		/* no check for polling unit and unused sync Tx */
+		i = MIN_LEN_OF_LE_TAB;
+		while (NumLE > i) {
+			i *= 2;
+			if (i > MAX_LEN_OF_LE_TAB) {
+				break;
+			}
+		}
+		if (NumLE != i) {
+			SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+				("ERROR: Illegal number of list elements %d adjusted to %d\n",
+				NumLE, (i / 2)));
+			NumLE = i / 2;
+		}
+	}
+
+	/* set addresses */
+	pLETab->pPhyLETABLow = PMemLowAddr;
+	pLETab->pPhyLETABHigh = PMemHighAddr;
+	pLETab->pLETab = pVMem;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("contains %d LEs", NumLE));
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		(" and starts at virt %08p and phys %08lx:%08lx\n",
+		pVMem, PMemHighAddr, PMemLowAddr));
+
+	/* initialize indexes */
+	pLETab->Done = 0;
+	pLETab->Put = 0;
+	pLETab->HwPut = 0;
+	/* initialize size */
+	pLETab->Num = NumLE;
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("<== SkGeY2InitSingleLETable()\n"));
+}	/* SkGeY2InitSingleLETable */
+
+/*****************************************************************************
+ *
+ * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit
+ *
+ * Description:
+ *	Calling this function requires an already configured list element table.
+ *	The prefetch unit to be configured is specified in the parameter 'Queue'.
+ *	The function is able to initialize the prefetch units of the following
+ *	queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2.
+ *	The function should be called before SkGeInitPort().
+ *
+ * Arguments:
+ *	pAC - pointer to the adapter context
+ *	IoC - I/O context
+ *	Queue - I/O offset of queue e.g. Q_XA1
+ *	pLETab - pointer to list element table to be initialized
+ *
+ * Returns: N/A
+ */
+void SkGeY2InitPrefetchUnit(
+SK_AC	*pAC,			/* pointer to adapter context */
+SK_IOC	IoC,			/* I/O context */
+unsigned int Queue,		/* Queue offset for finding the right registers */
+SK_LE_TABLE	*pLETab)	/* pointer to list element table to be initialized */
+{
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("==> SkGeY2InitPrefetchUnit()\n"));
+
+#ifdef DEBUG
+	if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 &&
+		Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) {
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
+			("ERROR: Illegal queue identifier %x\n", Queue));
+	}
+#endif /* DEBUG */
+
+	/* disable the prefetch unit */
+	SK_OUT8(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
+	SK_OUT8(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh,
+		pLETab->pPhyLETABLow));
+
+	/* Set the list base address  high part*/
+	SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG),
+		pLETab->pPhyLETABHigh);
+
+	/* Set the list base address low part */
+	SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG),
+		pLETab->pPhyLETABLow);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Last index: %d\n", pLETab->Num-1));
+
+	/* Set the list last index */
+	SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG),
+		(SK_U16)pLETab->Num - 1);
+
+	/* turn on prefetch unit */
+	SK_OUT8(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("<== SkGeY2InitPrefetchUnit()\n"));
+}	/* SkGeY2InitPrefetchUnit */
+
+
+/*****************************************************************************
+ *
+ * SkGeY2InitStatBmu() - Initialize the Status BMU
+ *
+ * Description:
+ *	Calling this function requires an already configured list element table.
+ *	Ensure the status BMU is only initialized once during DriverInit -
+ *	InitLevel2 required.
+ *
+ * Arguments:
+ *	pAC - pointer to the adapter context
+ *	IoC - I/O context
+ *	pLETab - pointer to status LE table to be initialized
+ *
+ * Returns: N/A
+ */
+void SkGeY2InitStatBmu(
+SK_AC	*pAC,			/* pointer to adapter context */
+SK_IOC	IoC,			/* I/O context */
+SK_LE_TABLE	*pLETab)	/* pointer to status LE table */
+{
+#ifdef DEBUG
+	SK_U32 Dummy;
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("==> SkGeY2InitStatBmu()\n"));
+
+	/* enable the status unit */
+	SK_OUT8(IoC, STAT_CTRL, SC_STAT_RST_SET);
+	SK_OUT8(IoC, STAT_CTRL, SC_STAT_RST_CLR);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
+
+	/* Set the LE base address */
+	SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow);
+
+#ifdef DEBUG
+	SK_IN32(IoC, STAT_LIST_ADDR_LO, &Dummy);
+#endif
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
+
+	SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Last index: %d\n", pLETab->Num - 1));
+
+	/* Set the list last index */
+	SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)pLETab->Num - 1);
+
+#ifdef DEBUG
+	SK_IN32(IoC, STAT_LAST_IDX, &Dummy);
+#endif
+
+	if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) {
+
+		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+			("Set Tx index threshold\n"));
+		/* WA for dev. #4.3 */
+		SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
+
+		/* set Status-FIFO watermark */
+		SK_OUT8(IoC, STAT_FIFO_WM, 0x21);		/* WA for dev. #4.18 */
+
+		/* set Status-FIFO ISR watermark */
+		SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07);	/* WA for dev. #4.18 */
+
+		/* WA for dev. #4.3 and #4.18 */
+		/* set Status-FIFO Tx timer init value */
+		SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10));
+	}
+	else {
+		/*
+		 * Further settings may be added if required...
+		 * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM)
+		 * 2) Status-FIFO timer values (STAT_TX_TIMER_INI,
+		 *		STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI)
+		 * but tests shows that the default values give the best results,
+		 * therefore the defaults are used.
+		 */
+#ifndef SK_SLIM
+		SK_OUT16(IoC, STAT_TX_IDX_TH, (SK_U16)pAC->GIni.GITxIdxRepThres);
+#else
+		SK_OUT16(IoC, STAT_TX_IDX_TH, 10);
+#endif
+		/* set Status-FIFO watermark */
+		SK_OUT8(IoC, STAT_FIFO_WM, 0x10);
+
+		/* set Status-FIFO ISR watermark */
+		SK_OUT8(IoC, STAT_FIFO_ISR_WM,
+			HW_FEATURE(pAC, HWF_WA_DEV_4109) ? 0x10 : 0x04);
+
+		/* set ISR Timer Init Value to 400 (3.2 us on Yukon-EC) */
+		SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190);
+	}
+
+#ifdef DEBUG
+	SK_IN32(IoC, STAT_ISR_TIMER_INI, &Dummy);
+#endif
+	/* enable the prefetch unit */
+	/* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */
+	SK_OUT8(IoC, STAT_CTRL, SC_STAT_OP_ON);
+
+	/* start Status-FIFO timer */
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Start Status FIFO timer\n"));
+
+	SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START);
+	SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START);
+	SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("<== SkGeY2InitStatBmu()\n"));
+}	/* SkGeY2InitStatBmu */
+
+#ifdef USE_POLLING_UNIT
+/*****************************************************************************
+ *
+ * SkGeY2InitPollUnit() - Initialize the Polling Unit
+ *
+ * Description:
+ *	This function will write the data of one polling LE table into the adapter.
+ *
+ * Arguments:
+ *	pAC - pointer to the adapter context
+ *	IoC - I/O contex.
+ *	pLETab - pointer to polling LE table to be initialized
+ *
+ * Returns: N/A
+ */
+void SkGeY2InitPollUnit(
+SK_AC	*pAC,			/* pointer to adapter context */
+SK_IOC	IoC,			/* I/O context */
+SK_LE_TABLE	*pLETab)	/* pointer to polling LE table */
+{
+	SK_HWLE	*pLE;
+
+#ifdef VCPU
+	int	i;
+
+	VCPU_VARS();
+#endif /* VCPU */
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("==> SkGeY2InitPollUnit()\n"));
+
+#ifdef VCPU
+	for (i = 0; i < SK_MAX_MACS; i++) {
+		GET_PO_LE(pLE, pLETab, i);
+		VCPU_START_AND_COPY_LE();
+		/* initialize polling LE but leave indexes invalid */
+		POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER);
+		POLE_SET_LINK(pLE, i);
+		POLE_SET_RXIDX(pLE, 0);
+		POLE_SET_TXAIDX(pLE, 0);
+		POLE_SET_TXSIDX(pLE, 0);
+		VCPU_WRITE_LE();
+		SK_DBG_DUMP_PO_LE(pLE);
+	}
+#endif /* VCPU */
+
+	/* disable the polling unit */
+	SK_OUT8(IoC, POLL_CTRL, PC_POLL_RST_SET);
+	SK_OUT8(IoC, POLL_CTRL, PC_POLL_RST_CLR);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
+
+	/* Set the list base address */
+	SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
+
+	SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
+
+	/* we don't need to write the last index - it is hardwired to 1 */
+
+	/* enable the prefetch unit */
+	SK_OUT8(IoC, POLL_CTRL, PC_POLL_OP_ON);
+
+	/*
+	 * now we have to start the descriptor poll timer because it triggers
+	 * the polling unit
+	 */
+
+	/*
+	 * still playing with the value (timer runs at 125 MHz)
+	 * descriptor poll timer is enabled by GeInit
+	 */
+	SK_OUT32(IoC, B28_DPT_INI,
+		(SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100));
+
+	SK_OUT8(IoC, B28_DPT_CTRL, TIM_START);
+
+	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
+		("<== SkGeY2InitPollUnit()\n"));
+}	/* SkGeY2InitPollUnit */
+#endif /* USE_POLLING_UNIT */
+
+
+/******************************************************************************
+ *
+ * SkGeY2SetPutIndex
+ *
+ * Description:
+ *	This function writes the Done index of a list element table.
+ *
+ * Notes:
+ *	Dev. Issue 4.2
+ *
+ * Returns: N/A
+ */
+void SkGeY2SetPutIndex(
+SK_AC	*pAC,					/* pointer to adapter context */
+SK_IOC	IoC,					/* I/O context */
+unsigned int StartAddrPrefUnit,	/* start address of the prefetch unit */
+SK_LE_TABLE	*pLETab)			/* list element table to work with */
+{
+	unsigned int Put;
+	unsigned int PrefUnitPutIdxReg;
+	SK_U16 EndOfListIndex;
+	SK_U16 HwGetIndex;
+	SK_U16 HwPutIndex;
+
+	PrefUnitPutIdxReg = StartAddrPrefUnit + PREF_UNIT_PUT_IDX_REG;
+
+	/* set put index we would like to write */
+	Put = GET_PUT_IDX(pLETab);
+
+	/*
+	 * in this case we wrap around
+	 * new put is lower than last put given to HW
+	 */
+	if (Put < pLETab->HwPut) {
+
+		/* set put index = last index of list */
+		EndOfListIndex = NUM_LE_IN_TABLE(pLETab) - 1;
+
+		/* read get index of HW prefetch unit */
+		SK_IN16(IoC, StartAddrPrefUnit + PREF_UNIT_GET_IDX_REG, &HwGetIndex);
+
+		/* read put index of HW prefetch unit */
+		SK_IN16(IoC, PrefUnitPutIdxReg, &HwPutIndex);
+
+		/* prefetch unit reached end of list */
+		/* prefetch unit reached first list element */
+		if (HwGetIndex == 0) {
+			/* restore watermark */
+			SK_OUT8(IoC, StartAddrPrefUnit + PREF_UNIT_FIFO_WM_REG, 0xe0);
+
+			/* write put index */
+			SK_OUT16(IoC, PrefUnitPutIdxReg, (SK_U16)Put);
+
+			/* remember put index written to HW */
+			pLETab->HwPut = Put;
+		}
+		else if (HwGetIndex == EndOfListIndex) {
+			/* set watermark to one list element */
+			SK_OUT8(IoC, StartAddrPrefUnit + PREF_UNIT_FIFO_WM_REG, 8);
+
+			/* set put index to first list element */
+			SK_OUT16(IoC, PrefUnitPutIdxReg, 0);
+		}
+		/* prefetch unit did not reach end of list yet */
+		/* and we did not write put index to end of list yet */
+		else if (HwPutIndex != EndOfListIndex &&
+				 HwGetIndex != EndOfListIndex) {
+			/* write put index */
+			SK_OUT16(IoC, PrefUnitPutIdxReg, EndOfListIndex);
+		}
+		else {
+			/* do nothing */
+		}
+	}
+	else {
+#ifdef XXX	/* leads in to problems in the Windows Driver */
+		if (Put != pLETab->HwPut) {
+			/* write put index */
+			SK_OUT16(IoC, PrefUnitPutIdxReg, (SK_U16)Put);
+			/* update put index */
+			UPDATE_HWPUT_IDX(pLETab);
+		}
+#else
+		/* write put index */
+		SK_OUT16(IoC, PrefUnitPutIdxReg, (SK_U16)Put);
+		/* update put index */
+		UPDATE_HWPUT_IDX(pLETab);
+#endif
+	}
+}	/* SkGeY2SetPutIndex */
+
diff -ruN linux/drivers/net/sk98lin/vpdcheck.c linux-new/drivers/net/sk98lin/vpdcheck.c
--- linux/drivers/net/sk98lin/vpdcheck.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/vpdcheck.c	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,419 @@
+/******************************************************************************
+ *
+ * Name:	$Id: //Release/Yukon_1G/Shared/vpd/V4/vpdcheck.c#4 $
+ * Project:	Gigabit Ethernet Adapters, Diagnostic Tool
+ * Version:	$Revision: #4 $, $Change: 4281 $
+ * Date:	$DateTime: 2010/11/05 11:58:07 $
+ * Purpose:	VPD content structure check
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ *	LICENSE:
+ *	(C)Copyright Marvell.
+ *	
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *	
+ *	The information in this file is provided "AS IS" without warranty.
+ *	/LICENSE
+ *
+ ******************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <ctype.h>
+
+#ifdef SK_DIAG
+#include "h/skdrv1st.h"
+#include "h/lm80.h"
+#include "h/skdrv2nd.h"
+#else
+#define w_print	printf
+#define FALSE	0
+#define TRUE	(!FALSE)
+#endif
+
+#define VPD_LARGE_ITEM_TYPE 1
+#define VPD_SMALL_ITEM_TYPE 0
+
+#define VPD_ITEM_TYPE(pVR) (((pVR)->type_name_len & 0x80)>>7)
+
+#define VPD_RESOURCE_NAME(pVR)								\
+	((VPD_ITEM_TYPE(pVR) == VPD_LARGE_ITEM_TYPE) ?			\
+		VPD_LARGE_ITEM_NAME(pVR) : VPD_SMALL_ITEM_NAME(pVR))
+
+#define VPD_RESOURCE_SIZE(pVR)								\
+	((VPD_ITEM_TYPE(pVR) == VPD_LARGE_ITEM_TYPE) ?			\
+		VPD_LARGE_ITEM_SIZE(pVR) : VPD_SMALL_ITEM_SIZE(pVR))
+
+#define VPD_RESOURCE_DATA(pVR)								\
+	((VPD_ITEM_TYPE(pVR) == VPD_LARGE_ITEM_TYPE) ?			\
+		(pVR)->large_item.data : (pVR)->small_item.data)
+
+#define VPD_RESOURCE_HDR_SIZE(pVR)	((VPD_ITEM_TYPE(pVR) == VPD_LARGE_ITEM_TYPE) ? 3 : 1)
+#define VPD_LARGE_ITEM_SIZE(pVR)	((pVR)->large_item.lsb+(pVR)->large_item.msb*256)
+#define VPD_LARGE_ITEM_NAME(pVR)	((pVR)->type_name_len & 0x7F)
+
+#define VPD_SMALL_ITEM_SIZE(pVR)	((pVR)->type_name_len & 0x07)
+#define VPD_SMALL_ITEM_NAME(pVR)	(((pVR)->type_name_len & 0x78)>>3)
+
+#define ID_STR	0x02
+#define VPD_R	0x10
+#define VPD_W	0x11
+#define END_TAG	0x0F
+
+#pragma pack(1)
+
+typedef struct {
+	unsigned char type_name_len;
+	union {
+		struct {
+			unsigned char data[7];
+		} small_item;
+		struct {
+			unsigned char lsb;
+			unsigned char msb;
+			unsigned char data[65536];
+		} large_item;
+	};
+} VPD_RESOURCE;
+
+typedef struct {
+	unsigned short keyword;
+	unsigned char length;
+	unsigned char data[255];
+} VPD_HEADER;
+
+#pragma pack()
+
+int is_resource_name_ok(unsigned char res_name)
+{
+	const unsigned char DEFINED_ITEM_NAMES[]={ ID_STR, VPD_R, VPD_W, END_TAG };
+	unsigned int i;
+
+	for (i = 0; i < sizeof(DEFINED_ITEM_NAMES); i++) {
+		if (res_name == DEFINED_ITEM_NAMES[i]) {
+			return (TRUE);
+		}
+	}
+	return (FALSE);
+}
+
+unsigned char compute_chksum(unsigned char *data, int len, unsigned char chksum)
+{
+	while (len--) {
+		chksum += *data++;
+	}
+	return (chksum);
+}
+
+int is_vpd_kw_ok(VPD_HEADER **pvph, int ro, unsigned char *chksum, int *last_kw)
+{
+	unsigned char *KEYWORDS_RO[] = {
+		(unsigned char *)"PN",
+		(unsigned char *)"EC",
+		(unsigned char *)"FG",
+		(unsigned char *)"LC",
+		(unsigned char *)"MN",
+		(unsigned char *)"PG",
+		(unsigned char *)"SN",
+		(unsigned char *)"Vx",
+		(unsigned char *)"CP",
+		(unsigned char *)"RV",
+		(unsigned char *)0
+	};
+	unsigned char *KEYWORDS_RW[] = {
+		(unsigned char *)"Vx",
+		(unsigned char *)"Yx",
+		(unsigned char *)"YA",
+		(unsigned char *)"RW",
+		(unsigned char *)0
+	};
+	unsigned char **p;
+	int i = 0, kwok = FALSE;
+
+	*last_kw = FALSE;
+	p = KEYWORDS_RO;
+
+	if (!ro) {
+		p=KEYWORDS_RW;
+	}
+
+	while (p[i]) {
+		if (*(unsigned short *)p[i]==(*pvph)->keyword) {
+			kwok = TRUE;
+			break;
+		}
+		if (p[i][1]=='x' && p[i][0]==((unsigned char *)&((*pvph)->keyword))[0]) {
+			if (isalnum(((unsigned char *)&((*pvph)->keyword))[1])) {
+				kwok = TRUE;
+				break;
+			}
+		}
+		i++;
+	}
+
+	if (!kwok) {
+		w_print("\nUknown VPD KEYWORD \"%c%c\" (0x%01x 0x%01x) found!\n",
+			((unsigned char *)&((*pvph)->keyword))[0],
+			((unsigned char *)&((*pvph)->keyword))[1],
+			((unsigned char *)&((*pvph)->keyword))[0],
+			((unsigned char *)&((*pvph)->keyword))[1]);
+		return (FALSE);
+	}
+
+	switch ((*pvph)->keyword) {
+	case 'C' + 256 * 'P':
+		*chksum = compute_chksum((unsigned char *)(*pvph), (*pvph)->length + 3,
+			*chksum);
+		break;
+	case 'R' + 256 * 'V':
+		*chksum = compute_chksum((unsigned char *)(*pvph), 4, *chksum);
+		if (*chksum!=0) {
+			w_print("\nVPD computed checksum 0x%02x different "
+				"from exp. checksum 0x00!\n", *chksum);
+			return (FALSE);
+		}
+		*last_kw = TRUE;
+		break;
+	case 'R' + 256 * 'W':
+		*last_kw = TRUE;
+		break;
+	default:
+		for (i = 0; i < (*pvph)->length; i++) {
+			if (!isalnum((*pvph)->data[i]) && !isspace((*pvph)->data[i]) &&
+				!ispunct((*pvph)->data[i])) {
+
+				w_print("\nKEYWORD \"%c%c\" data is not 100%% alpha-numeric!\n",
+					((unsigned char *)&((*pvph)->keyword))[0],
+					((unsigned char *)&((*pvph)->keyword))[1]);
+				return (FALSE);
+			}
+		}
+		*chksum = compute_chksum((unsigned char *)(*pvph), (*pvph)->length + 3,
+			*chksum);
+		break;
+	}
+
+	(*pvph) = (VPD_HEADER *)((unsigned char *)*pvph + (*pvph)->length + 3);
+	return (TRUE);
+}
+
+int is_vpd_r_content_ok(unsigned char *res_data, int len, unsigned char *chksum)
+{
+	VPD_HEADER *vph = (VPD_HEADER *)res_data;
+	int last_kw = 0;
+
+	while ((unsigned char *)vph - res_data < len) {
+		if (last_kw==TRUE) {
+			w_print("\nOne of the VPD_R resource size or the 'RV' "
+				"keyword length is incorrect!\n");
+			return (FALSE);
+		}
+
+		if (!is_vpd_kw_ok(&vph, 1, chksum, &last_kw)) {
+			return (FALSE);
+		}
+	}
+
+	if ((unsigned char *)vph - res_data != len) {
+		w_print("\n'RV' keyword not found!\n");
+		w_print("\nSum of VPD keywords lengths %d is different from VPD_R "
+			"resource length %d!\n", (unsigned char *)vph - res_data, len);
+			return (FALSE);
+	}
+	return (TRUE);
+}
+
+int is_vpd_w_content_ok(unsigned char *res_data, int len)
+{
+	VPD_HEADER *vph = (VPD_HEADER *)res_data;
+	int last_kw = 0;
+	unsigned char unused_chksum;
+
+	while ((unsigned char *)vph - res_data < len) {
+		if (last_kw==TRUE) {
+			w_print("\nOne of the VPD_W resource size or the 'RW' "
+				"keyword length is incorrect!\n");
+			return (FALSE);
+		}
+
+		if (!is_vpd_kw_ok(&vph,0,&unused_chksum,&last_kw)) {
+			return (FALSE);
+		}
+	}
+
+	if ((unsigned char *)vph - res_data != len) {
+		w_print("\n'RW' keyword not found!\n");
+		w_print("\nSum of VPD keywords lengths %d is different from VPD_W "
+			"resource length %d!\n", (unsigned char *)vph - res_data, len);
+		return (FALSE);
+	}
+	return (TRUE);
+}
+
+int is_resource_content_ok(VPD_RESOURCE *pvr, unsigned char *chksum)
+{
+	switch (VPD_RESOURCE_NAME(pvr)) {
+	case ID_STR:
+		*chksum = compute_chksum((unsigned char *)pvr, VPD_RESOURCE_SIZE(pvr) +
+			VPD_RESOURCE_HDR_SIZE(pvr), *chksum);
+		/*Nothing to check*/
+		return (TRUE);
+	case VPD_R:
+		*chksum = compute_chksum((unsigned char *)pvr,
+			VPD_RESOURCE_HDR_SIZE(pvr), *chksum);
+		return (is_vpd_r_content_ok(VPD_RESOURCE_DATA(pvr),
+			VPD_RESOURCE_SIZE(pvr), chksum));
+	case VPD_W:
+		return (is_vpd_w_content_ok(VPD_RESOURCE_DATA(pvr),
+			VPD_RESOURCE_SIZE(pvr)));
+	case END_TAG:
+		if (VPD_RESOURCE_SIZE(pvr)!=0) {
+		w_print("\nEND TAG resource size is not 0!\n");
+			return (FALSE);
+		}
+		return (TRUE);
+	default:
+		w_print("\nUnexpected resource name 0x%x!\n", VPD_RESOURCE_NAME(pvr));
+	}
+	return (FALSE);
+}
+
+int is_resource_ok(VPD_RESOURCE **ppvr, unsigned char *chksum)
+{
+	VPD_RESOURCE *pvr=(VPD_RESOURCE *)*ppvr;
+
+	if (!is_resource_name_ok(VPD_RESOURCE_NAME(pvr))) {
+		w_print("\nWrong resource name 0x%x found!\n",VPD_RESOURCE_NAME(pvr));
+		return (FALSE);
+	}
+
+	if (!is_resource_content_ok(pvr,chksum)) {
+		w_print("\nWrong resource content detected!\n");
+		return (FALSE);
+	}
+
+	if (VPD_RESOURCE_NAME(*ppvr) == END_TAG) {
+		*ppvr = 0;
+	}
+	else {
+		*ppvr = (VPD_RESOURCE *)((unsigned char *)pvr +
+			VPD_RESOURCE_SIZE(pvr) + VPD_RESOURCE_HDR_SIZE(pvr));
+	}
+	return (TRUE);
+}
+
+unsigned char *load_file(char *fn, unsigned long *size)
+{
+	unsigned char *vpdr = 0;
+	FILE *f;
+
+	*size = 0;
+
+	f = fopen(fn, "rb");
+
+	if (f) {
+		fseek(f, 0, SEEK_END);
+		*size = ftell(f);
+		fseek(f, 0, SEEK_SET);
+
+		vpdr = (unsigned char *)malloc(*size);
+		if (vpdr) {
+			fread(vpdr, *size, 1, f);
+		}
+		fclose(f);
+	}
+	else {
+		w_print("Can not open file \"%s\": ", fn);
+		perror("");
+	}
+	return (vpdr);
+}
+
+VPD_RESOURCE *find_vpd_data(unsigned char *buf, unsigned long len)
+{
+	VPD_RESOURCE *vpdr = (VPD_RESOURCE *)buf;
+
+	while (len) {
+		if (is_resource_name_ok(VPD_RESOURCE_NAME(vpdr))) {
+			unsigned long vpdr_size = VPD_RESOURCE_SIZE(vpdr) +
+				VPD_RESOURCE_HDR_SIZE(vpdr);
+
+			if (vpdr_size < len) {
+				VPD_RESOURCE *next_vpdr =
+					(VPD_RESOURCE *)(((unsigned char *)vpdr) + vpdr_size);
+
+				if (is_resource_name_ok(VPD_RESOURCE_NAME(next_vpdr))) {
+					/* we might have found the VPD */
+					return (vpdr);
+				}
+			}
+		}
+		vpdr = (VPD_RESOURCE *)(((unsigned char *)vpdr)+1);
+		len--;
+	}
+	return (0);
+}
+
+int vpd_data_valid(VPD_RESOURCE *vpdr)
+{
+	unsigned char chksum = 0;
+
+	while (vpdr) {
+		if (!is_resource_ok(&vpdr,&chksum)) {
+			return (FALSE);
+		}
+	}
+	return (TRUE);
+}
+
+int check_vpd_buffer(unsigned char *file_buf, unsigned long len)
+{
+	VPD_RESOURCE *vpdr = 0;
+
+	vpdr = find_vpd_data(file_buf, len);
+
+	if (!vpdr) {
+		w_print("\nUnable to find valid VPD!\n");
+		return (1);
+	}
+
+	if (!vpd_data_valid(vpdr)) {
+		return (2);
+	}
+	return (0);
+}
+
+int check_vpd_file(char *fn)
+{
+	unsigned char *file_buf = 0;
+	unsigned long len = 0;
+	int ret = 0;
+
+	file_buf = load_file(fn, &len);
+
+	if (file_buf) {
+		ret = check_vpd_buffer(file_buf, len);
+	}
+	else {
+		return (3);
+	}
+
+	free(file_buf);
+	return (ret);
+}
+
+#ifdef TEST
+int main(int argc, char **args)
+{
+	if (argc!=2) {
+		printf("Usage: %s <raw vpd file>\n", args[0]);
+	}
+	return (check_vpd_file(args[1]));
+}
+#endif
diff -ruN linux/Documentation/networking/sk98lin.txt linux-new/Documentation/networking/sk98lin.txt
--- linux/Documentation/networking/sk98lin.txt	1969-12-31 16:00:00.000000000 -0800
+++ linux-new/drivers/net/sk98lin/sk98lin.txt	2011-05-16 06:45:55.000000000 -0700
@@ -0,0 +1,543 @@
+(C)Copyright 1999-2011 Marvell(R).
+All rights reserved.
+================================================================================
+
+sk98lin.txt created 16-May-2011
+
+Readme File for sk98lin v10.88.3.3
+Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter driver for LINUX
+
+This file contains
+ 1  Overview
+ 2  Supported Functions
+ 3  Required Files
+ 4  Installation
+ 5  Driver Parameters
+    5.1  Port Parameters
+    5.2  Network Controller Parameters
+ 6  Ethtool Support
+ 7  Large Frame Support
+ 8  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
+ 9  Wake on Lan Support
+10  Troubleshooting
+
+================================================================================
+
+
+1  Overview
+===========
+
+The sk98lin driver supports Marvell Yukon Ethernet Network Controllers
+on Linux.
+
+It has been tested with Linux on Intel x86 (32-bit) and x86 (64-bit) systems
+and on PowerPC (PPC) 32-bit and 64-bit systems.
+
+For PowerPC systems, use the "generate patch" option in the installation script
+install.sh. For details on using the "generate patch" option, see chapter 6
+"Patch Generation and Recompilation of the Kernel" in the README file.
+***
+
+2  Supported Functions
+======================
+
+NOTE: The hardware support depends on the used network controller.
+
+The following functions are supported by the driver:
+
+- RX/TX HW Checksum
+- Hardware interrupt moderation (static/dynamic)
+- Transmit poll
+- Zerocopy/Scatter-Gather
+- Ethtool support
+- Wake on Lan (Magic Packet only)
+- DualNet
+- 
+ 
+
+3  Required Files
+=================
+
+The Linux kernel source.
+No additional files required.
+***
+
+
+4  Installation
+===============
+
+It is recommended to download the latest version of the driver from our 
+website. For details on the installation of the driver, refer to the 
+README file.
+***
+
+
+5  Driver Parameters
+====================
+
+The driver parameters can be set at the command line after the module has been 
+loaded with the command 'modprobe'.
+The configuration tools of some distributions are able to pass parameters
+to the driver module.
+
+If the kernel module loader is used, the parameters can be set
+in the file /etc/modprobe.conf (or old name: /etc/modules.conf).
+
+To set the driver parameters in this file:
+
+1. Insert a line similar to the following:
+
+   options sk98lin <parameter>=value1 [value2, etc]
+
+   where value1 refers to the first network controller, value2 to the 
+   second, etc.
+
+2. To activate the new parameters, reboot your system.
+
+To set the paramters from the command line:
+ 
+1.  Unload the driver.
+
+2.  Reload the driver by executing the following command:
+    modprobe sk98lin parameter=value1[,value2[,value3...]]
+
+    where value1 refers to the first network controller, value2 to the 
+    second, etc.
+
+NOTE: All parameters are case sensitive. Write them exactly as shown 
+      below.
+
+Example: You have two network controllers and want to set auto-negotiation
+         to 'On' for the first network controller and to 'Off' for the second
+         network controller. Also, you want to set DuplexCapabilities to 'Full'
+         for the first network controller and to 'Half' for the second
+         network controller.
+
+         Enter: modprobe sk98lin AutoNeg_A=On,Off DupCap_A=Full,Half
+
+NOTE: The number of network controllers that can be configured is limited 
+      in the driver (file skge.c, constant SK_MAX_CARD_PARAM). The current 
+      limit is 16. If you have more network controllers installed, adjust 
+      the parameter in the skge.c file and recompile.
+
+
+5.1  Port Parameters
+--------------------
+
+These settings are available for each port on the network controller (if 
+available).
+In the following description, '?' stands for the port for which you set 
+the parameter (A or B).
+
+Auto-Negotiation
+----------------
+Parameter:    AutoNeg_?
+Values:       On, Off, Sense
+Default:      On
+  
+With auto-negotiation, two connected network devices can negotiate common
+transmission parameters, such as speed and duplex mode. If the value 'Sense' is
+configured, the network controller automatically detects whether the link partner 
+supports auto-negotiation or not.
+
+Speed
+-----
+Parameter:    Speed_?
+Values:       10, 100, 1000, Auto
+Default:      Auto
+
+This parameter is only applicable if auto-negotiation for this port is set 
+to 'Sense'. It is used to set the speed capabilities. Usually, the speed is 
+negotiated between the two ports during link establishment. If this fails, 
+a port can be forced to a specific speed with this parameter.
+
+
+Duplex Capabilities
+-------------------
+Parameter:    DupCap_?
+Values:       Half, Full, Both
+Default:      Both
+
+This parameters is only applicable if auto-negotiation for this port is 
+not set to 'Sense'. If auto-negotiation is set to 'On', all three values
+are possible. If it is set to 'Off', only 'Full' and 'Half' are allowed.
+
+NOTE: The combination of Speed 1000 and Half Duplex is not possible. Please
+      use 100HD or 1000FD instead.
+
+Flow Control
+------------
+Parameter:    FlowCtrl_?
+Values:       Sym, SymOrRem, LocSend, None
+Default:      SymOrRem
+
+This parameter can be used to set the flow control capabilities the port 
+reports during auto-negotiation. It can be set for each port individually.
+
+Possible modes:
+   -- Sym      = Symmetric: both link partners are allowed to send PAUSE frames
+   -- SymOrRem = SymmetricOrRemote: both or only the remote partner are allowed 
+                 to send PAUSE frames
+   -- LocSend  = LocalSend: only local link partner is allowed to send PAUSE frames
+   -- None     = no link partner is allowed to send PAUSE frames
+  
+NOTE: If auto-negotiation is set to 'Off', Flow Control is ignored .
+
+Role in Master-Slave-Negotiation (1000Base-T only)
+--------------------------------------------------
+Parameter:    Role_?
+Values:       Auto, Master, Slave
+Default:      Auto
+
+For two 1000Base-T ports to communicate, one must take the role of the
+master (providing timing information), while the other must be the slave. 
+Usually, this is negotiated between the two ports during link establishment. 
+If this fails, a port can be forced to a specific role with this parameter.
+
+
+5.2  Network Controller Parameters
+----------------------------------
+
+Connection Type (for copper network controllers only)
+---------------
+Parameter:    ConType
+Values:       Auto, 1000FD, 100FD, 100HD, 10FD, 10HD
+Default:      Auto
+
+This parameter is a combination of port parameters. This simplifies the 
+configuration of both ports of a network controller! The different values 
+of this variable reflect the most important combinations of port parameters.
+
+The following table shows the values for 'ConType' and the corresponding
+combinations for the port parameters:
+
+    ConType   |  DupCap   AutoNeg   FlowCtrl   Role             Speed
+    ----------+------------------------------------------------------
+    Auto      |  Both     On        SymOrRem   Auto             Auto
+    1000FD    |  Full     Off       None       Auto (ignored)   1000
+    100FD     |  Full     Off       None       Auto (ignored)   100
+    100HD     |  Half     Off       None       Auto (ignored)   100
+    10FD      |  Full     Off       None       Auto (ignored)   10
+    10HD      |  Half     Off       None       Auto (ignored)   10
+
+The port parameters (e.g., Speed_A) have a higher priority than the parameter
+'ConType'. Therefore, setting any other port parameter together with the 'ConType' 
+parameter will result in a merged configuration.
+
+NOTE: This parameter is always used on both ports of the network controller.
+
+
+Wake on Lan Type (for copper network controllers only)
+---------------
+Parameter:    WolType
+Values:       Auto, 100FD, 100HD, 10FD, 10HD
+Default:      Auto
+
+This parameter is a combination of port parameters. This simplifies the 
+configuration of the WOL speed. To support WOL you must have a computer
+with Motherboard that supports WOL. The WOL process is done through
+sending a special packet (aka "Magic Packet") to the remote computer.
+
+The following table shows the values for 'WolType' and the corresponding
+combinations for the port parameters:
+
+    WolType   |  DupCap   AutoNeg   FlowCtrl   Role             Speed
+    ----------+------------------------------------------------------
+    Auto      |  Both     On        SymOrRem   Auto             Auto
+    100FD     |  Full     Off       None       Auto (ignored)   100
+    100HD     |  Half     Off       None       Auto (ignored)   100
+    10FD      |  Full     Off       None       Auto (ignored)   10
+    10HD      |  Half     Off       None       Auto (ignored)   10
+
+NOTE: This parameter is always used on both ports of the network controller.
+
+
+Transmit Moderation
+--------------------
+Parameter:    TxModeration
+Values:       1...4095
+Default:      10
+
+With transmit moderation, the maximum number of transmit complete interrupts 
+the driver must serve can be limited. That is, one or more interrupts (which 
+indicate any transmit packet to be processed) are queued until the driver 
+processes them. When TxModeration is set to '1', all transmit complete interrupts 
+will be generated immediately. When set to '10', the network controller will 
+generate one transmit complete interrupt every ten served packets.
+
+NOTE: This parameter is only used on Yukon Extreme network controllers.
+
+
+Interrupt Moderation
+--------------------
+Parameter:    Moderation
+Values:       None, Static, Dynamic
+Default:      None
+
+With interrupt moderation, the maximum number of interrupts the driver must 
+serve can be limited. That is, one or more interrupts (which indicate any 
+transmit or receive packet to be processed) are queued until the driver processes 
+them. When queued interrupts are to be served is determined by the IntsPerSec 
+parameter (see section "Interrupts per Second").
+
+Possible modes:
+
+   -- None - each transmit or receive interrupt is served immediately as soon as 
+      it appears on the interrupt line of the network controller.
+
+   -- Static - all transmit and receive interrupts are queued until a complete 
+      moderation interval ends. If such a moderation interval ends, all queued 
+      interrupts are processed at once without any delay. 'Static' means that 
+      interrupt moderation is always enabled, regardless how much network load 
+      is currently passing via a particular interface. In addition, the duration
+      of the moderation interval has a fixed length that never changes while 
+      the driver is operational.
+
+   -- Dynamic - Interrupt moderation might be enabled for the network 
+      controller, depending on the system load. If the driver detects that the 
+      system load is too high, it enables interrupt moderation. If, at a later 
+      time, the system load decreases (or if the network load is negligible), 
+      interrupt moderation will automatically be disabled.
+
+Interrupt moderation should be used when the driver must handle one or more
+interfaces with a high network load, which also leads to a high CPU utilization. 
+When interrupt moderation is applied in such high network load situations, 
+CPU load might be reduced by 20-30%.
+
+NOTE: The drawback of using interrupt moderation is an increase of the Round-
+      Trip Time (RTT), due to the queueing and serving of interrupts at 
+      dedicated moderation times.
+
+Interrupts per Second
+---------------------
+Parameter:    IntsPerSec
+Values:       30...40000 (interrupts per second)
+Default:      2000
+
+The number of interrupts per second determines the length of any interrupt 
+moderation interval. This parameter is only applicable if either static or 
+dynamic interrupt moderation is enabled for the network controller. Otherwise, 
+it will be ignored.
+
+Example: Assuming that static interrupt moderation is to be used, an 'IntsPerSec' 
+         parameter value of 2000 will lead to an interrupt moderation interval 
+         of 500 microseconds. 
+
+NOTE: The duration of the moderation interval must be selected with care. A long 
+      interval (e.g., only 100 interrupts/s) results in a significantly increased
+      packet processing delay. But, selecting a very short interval might 
+      compensate the benefits of any moderation applied. 
+
+LowLatency 
+----------
+Parameter:    LowLatency
+Values:       On, Off
+Default:      Off
+
+This parameter is used to reduce the packet latency time of the network 
+controller. Setting the LowLatency parameter to 'On' forces the network 
+controller to pass any received packet immediately to upper network layers and 
+to send out any transmit packet as fast as possible. 
+
+NOTE 1: The system load increases if LowLatency is set to 'On', and a large 
+        number of data packets is transmitted and received.
+
+NOTE 2: This parameter is only used for network controllers which are based on 
+        PCI Express compatible chipsets.
+
+
+Message-Signaled Interrupts
+----------
+Parameter:    MsiIrq
+Values:       On, Off
+Default:      On
+
+Message Signaled Interrupts, in PCI Express, are an alternative way of 
+generating an interrupt. MSI increases the number of interrupts that are 
+possible. There is also a slight performance advantage.
+
+
+Receive-Side Scaling (RSS) 
+----------
+Parameter:    RSS
+Values:       On, Off
+Default:      Off
+
+Receive-Side Scaling (RSS) resolves the single-processor bottleneck by allowing 
+the receive side network load from a network adapter to be shared across multiple 
+processors. RSS enables packet receive-processing to scale with the number of 
+available processors. This allows the subsystem to take advantage of multi-core 
+and many core processor architectures.
+
+NOTE 1: Receive-Side Scaling is supported only for kernel versions >= 2.6.35
+***
+
+
+6  Ethtool Support
+==================
+
+The sk98lin driver provides the built-in ethtool support. Ethtool can 
+be used to display or modify interface-specific configurations.
+Ethtool is used with either a query command or a set command, followed by a 
+number of parameters (optional). With the query command, information about a 
+parameter is displayed. With the set command, the specified parameter is set.
+It is not the intention of this section to explain the ethtool command line 
+tool and all its options. For further information, refer to the man page of 
+ethtool. This section only describes the ethtool parameters supported by the 
+sk98lin driver.
+
+Pause Parameters
+----------------
+Query command:  -a
+Set command:    -A [autoneg on|off] [rx on|off] [tx on|off]
+Example:        ethtool -A eth0 rx off tx off
+
+Coalescing Parameters
+---------------------
+Query command:  -c
+Set command:    -C [sample-interval I]
+                   [rx-usecs N] [tx-usecs N]
+                   [rx-usecs-low N] [tx-usecs-low N]
+                   [rx-usecs-high N] [tx-usecs-high N]
+Parameter:      I = Length of sample interval, in seconds
+                    (supported values range from 1...10)
+                N = Length of coalescing interval, in microseconds
+                    (supported values range from 25...33,333)
+Example:        ethtool -C eth2 rx-usecs 500 tx-usecs 500
+
+NOTE: The sk98lin driver does not support different settings for the 
+      Rx and Tx interrupt coalescing parameters.
+
+Driver Information
+------------------
+Query command:  -i
+Example:        ethtool -i eth1
+
+Checksumming Parameters
+-----------------------
+Query command:  -k
+Set command:    -K [rx on|off] [tx on|off] [sg on|off] [tso on|off]
+Example:        ethtool -K eth0 sg off
+
+Locate NIC Command
+------------------
+Query command:  -p [N]
+Parameter:      N = Amount of time to perform locate NIC command, in seconds
+Example:        ethtool -p 10 eth1
+
+Driver-specific Statistics
+--------------------------
+Query command:  -S
+Example:        ethtool -S eth0
+
+Setting Parameters
+------------------
+Set command:    -s [speed 10|100|1000] [duplex half|full] 
+                   [autoneg on|off] [wol gd]
+Example:        ethtool -s eth2 wol d
+Example:        ethtool -s eth2 autoneg off speed 100 duplex full
+
+NOTE: If the cable is disconnected, set the speed and duplex mode if you 
+      disable/enable autonegotiation.
+ 
+NOTE: To set this parameter back to the default value, use the 'autoneg on'
+      command.
+      Example:    ethtool -s eth2 autoneg on
+***
+
+
+7  Large Frame Support
+======================
+
+The sk98lin supports large frames (also called jumbo frames). Using jumbo
+frames can result in an improved throughput when transferring large amounts 
+of data.
+To enable large frames, set the Maximum Transfer Unit (MTU) of the interface 
+to 9000, execute the following command:
+
+         ifconfig eth0 mtu 9000
+
+This will only work if two network controllers are connected back-to-back or if 
+a switch is used that supports large frames. When using a switch, it must be 
+configured to allow large frames. The setting must be configured for all network 
+controllers that can be reached by the large frames. If one network controller 
+is not set to receive large frames, it will simply drop them.
+
+To switch back to the standard Ethernet frame size, execute the following 
+command:
+         ifconfig eth0 mtu 1500
+
+To permanently configure this setting, add a script including this command 
+to the system startup sequence (named "S99sk98lin" in the directory
+/etc/rc.d/rc2.d).
+***
+
+8  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
+==================================================================
+
+The Marvell Yukon Linux drivers support VLAN and Link Aggregation 
+according to IEEE standards 802.1, 802.1q, and 802.3ad. 
+
+9  Wake on Lan Support
+======================
+
+The sk98lin supports wake up from suspend mode with MagicPacket.
+Wake on Lan support is enabled by default. To disable it, use the ethtool.
+
+NOTE 1: WOL support has to be enabled in the BIOS and in the kernel.
+
+NOTE 2: Refer to the kernel documentation for additional requirements 
+        regarding WOL support.
+
+
+10  Troubleshooting
+===================
+
+If any problems occur during the installation process, check the 
+following list:
+
+
+Problem:  Programs such as 'ifconfig' and 'route' cannot be found, or the 
+          error message 'Operation not permitted' is displayed.
+Reason:   You are not logged in as user 'root'.
+Solution: Logout and login as 'root' or change to 'root' via 'su'.
+
+
+Problem:  The driver can be started, but if an IP address is assigned
+          to a network controller, no link up indication is displayed although
+          it is connected to the network. It is also not possible to receive
+          or transmit any packets, e.g., 'ping' does not work.
+Reason:   The network controller does not receive any interrupts from the Linux 
+          system. This can occur when using the Advanced Programmable Interrupt 
+          Controller (APIC) of a Symmetric Multi-Processor (SMP) compiled kernel 
+          in a Uni-Processor (UP) environment. 
+Solution: Use the Linux kernel parameters 'noapic' or 'nolapic' when booting the
+          kernel. To do this, add these parameters to the boot manager kernel 
+          selection menu: (either /boot/grub/menu.lst  for GRUB or /etc/lilo.conf 
+          for LILO).
+          When you build a kernel, deselect the option CONFIG_X86_LOCAL_APIC.
+
+
+Problem:  The driver can be started, the network controller is connected to the 
+          network and a link up indication is displayed, but it is not possible 
+          to receive or transmit any packets, e.g., 'ping' does not work.
+Reason:   There is an incorrect route in your routing table or the remote host 
+          is unreachable.
+Solution: Check the routing table using the command 'route' and read the 
+          manual help pages dealing with routes (enter 'man route'). Check the 
+          connection to the remote host system.
+
+
+If your problem is not listed here, please contact Marvell technical support 
+for help (MSGG-linux@marvell.com).
+When contacting our technical support, have the following information available:
+--------------------------------------------------------------------------------
+- 'install.log' file created by the install script 'install.sh'
+- System Manufacturer and hardware information (e.g., CPU, Memory... )
+- PCI-Boards in your system
+- Linux distribution
+- Linux kernel version
+- driver version
+***
+
+***End of Readme File***
diff -ruN linux/drivers/net/Kconfig linux-new/drivers/net/Kconfig
--- linux/drivers/net/Kconfig	2011-01-04 16:50:19.000000000 -0800
+++ linux-new/drivers/net/Kconfig	2011-07-07 21:13:32.000000000 -0700
@@ -2277,6 +2277,35 @@
 	  To compile this driver as a module, choose M here: the module
 	  will be called sis190.  This is recommended.
 
+
+config SK98LIN
+	tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
+	depends on PCI
+	---help---
+	  Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
+	  compliant Gigabit Ethernet Adapter.
+	  
+	  The adapters support Jumbo Frames.
+	  The dual link adapters support link-failover and dual port features.
+	  Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support 
+	  the scatter-gather functionality with sendfile(). Please refer to 
+	  Documentation/networking/sk98lin.txt for more information about
+	  optional driver parameters.
+	  Questions concerning this driver may be addressed to:
+	      linux@syskonnect.de
+	  
+	  If you want to compile this driver as a module ( = code which can be
+	  inserted in and removed from the running kernel whenever you want),
+	  say M here and read Documentation/modules.txt. This is recommended.
+	  The module will be called sk98lin. This is recommended.
+
+config SK98LIN_NAPI
+	bool "Use Rx polling (NAPI)"
+	depends on SK98LIN
+	help
+	  NAPI is a new driver API designed to reduce CPU and interrupt load
+	  when the driver is receiving lots of packets from the card.
+
 config SKGE
 	tristate "New SysKonnect GigaEthernet support"
 	depends on PCI
diff -ruN linux/drivers/net/Makefile linux-new/drivers/net/Makefile
--- linux/drivers/net/Makefile	2011-01-04 16:50:19.000000000 -0800
+++ linux-new/drivers/net/Makefile	2011-07-07 21:13:32.000000000 -0700
@@ -96,6 +96,7 @@
 obj-$(CONFIG_TC35815) += tc35815.o
 obj-$(CONFIG_SKGE) += skge.o
 obj-$(CONFIG_SKY2) += sky2.o
+obj-$(CONFIG_SK98LIN) += sk98lin/
 obj-$(CONFIG_SKFP) += skfp/
 obj-$(CONFIG_KS8842)	+= ks8842.o
 obj-$(CONFIG_KS8851)	+= ks8851.o
